Semiconductor memory device, semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of forming a suitable pad.SOLUTION: According to one embodiment, a semiconductor device comprises a first pad provided in a first insulation film and including a first layer provided on a side surface and a lower surface of the first insulation film, and a second layer provided on the side surface and the lower surface of the first insulation film via the first layer. In addition, the device comprises a second pad provided on the first pad in a second insulation film provided on the first insulation film and including a third layer provided a side surface and an upper surface of the second insulation film and a fourth layer provided on the side surface and the upper surface of the second insulation film via the third layer. Furthermore, the device comprises a first portion provided between the upper surface of the first pad and the lower surface of the second insulation film or between a lower surface of the second pad and an upper surface of the first insulation film and including a same metal element as the metal element contained in the first layer or the third layer.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] When manufacturing a semiconductor device by bonding a metal pad and an insulating film on one substrate to a metal pad and an insulating film on another substrate, the surface of the metal pad on one substrate may be exposed to the surface of the insulating film on the other substrate. In this case, problems such as diffusion of metal atoms (e.g., copper atoms) from the surface of the metal pad exposed to the surface of the insulating film may occur. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-79901 A [Patent Document 2] JP 2020-43120 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of forming a suitable pad and a manufacturing method thereof are provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a first insulating film and a first pad provided in the first insulating film, the first pad including a first layer provided on a side surface and a lower surface of the first insulating film and a second layer provided on the side surface and the lower surface of the first insulating film via the first layer. The device further includes a second insulating film provided on the first insulating film and a second pad provided in the second insulating film on the first pad, the second pad including a third layer provided on a side surface and an upper surface of the second insulating film and a fourth layer provided on the side surface and the upper surface of the second insulating film via the third layer. The device further includes a first portion provided between the upper surface of the first pad and the lower surface of the second insulating film or between the lower surface of the second pad and the upper surface of the first insulating film, the first portion including the same metal element as the metal element included in the first layer or the third layer. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a cross-sectional view showing the structure of a columnar portion CL of the first embodiment. FIG. [Diagram 3] 4 is a cross-sectional view (1 / 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4 is a cross-sectional view (2 / 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] 4 is a cross-sectional view showing a structure of a semiconductor device of a comparative example to the first embodiment. FIG. [Figure 6] 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment. [Figure 7] 5 is a cross-sectional view (1 / 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 5 is a cross-sectional view (2 / 5) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 9] 5 is a cross-sectional view (3 / 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 4 is a cross-sectional view (4 / 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 5 is a cross-sectional view (5 / 5) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 12] FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. [Figure 13] 11 is a cross-sectional view (1 / 4) showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 14] 11 is a cross-sectional view (2 / 4) showing the method for manufacturing the semiconductor device according to the second embodiment. [Figure 15] 11 is a cross-sectional view (3 / 4) illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 16] 11 is a cross-sectional view (4 / 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 17] FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. [Figure 18] FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment. [Figure 19] FIG. 13 is a cross-sectional view showing the structure of a semiconductor device according to a fifth embodiment. [Figure 20] FIG. 13 is a cross-sectional view showing the structure of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In Fig. 1 to Fig. 20, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0008] (First embodiment) Fig. 1 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment. The semiconductor device in Fig. 1 is a three-dimensional memory in which an array chip 1 and a circuit chip 2 are bonded together.

[0009] The array chip 1 includes a memory cell array 11 including a plurality of memory cells, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 below the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 13 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film. The interlayer insulating film 13 is an example of a second insulating film.

[0010] The circuit chip 2 is provided under the array chip 1. The reference character S indicates the bonding surface between the array chip 1 and the circuit chip 2. The circuit chip 2 includes an interlayer insulating film 14 and a substrate 15 under the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film, or a laminated film including a silicon oxide film and another insulating film. The interlayer insulating film 14 is an example of a first insulating film. The substrate 15 is, for example, a semiconductor substrate such as a silicon substrate.

[0011] 1 shows an X direction and a Y direction parallel to and perpendicular to the surface of the substrate 15, and a Z direction perpendicular to the surface of the substrate 15. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0012] The array chip 1 includes a plurality of word lines WL and source lines SL as a plurality of electrode layers in a memory cell array 11. FIG. 1 shows a staircase structure portion 21 of the memory cell array 11. Each word line WL is electrically connected to a word wiring layer 23 via a contact plug 22. Each columnar portion CL penetrating the plurality of word lines WL is electrically connected to a bit line BL via a via plug 24, and is also electrically connected to a source line SL. The source line SL includes a first layer SL1 which is a semiconductor layer, and a second layer SL2 which is a metal layer.

[0013] The circuit chip 2 includes a plurality of transistors 31. Each of the transistors 31 includes a gate electrode 32 provided on the substrate 15 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate 15. The circuit chip 2 also includes a plurality of contact plugs 33 provided on the gate electrodes 32, the source diffusion layer, or the drain diffusion layer of each of the transistors 31, a wiring layer 34 provided on the contact plugs 33 and including a plurality of wirings, and a wiring layer 35 provided on the wiring layer 34 and including a plurality of wirings.

[0014] The circuit chip 2 further includes a wiring layer 36 provided on the wiring layer 35 and including a plurality of wirings, a plurality of via plugs 37 provided on the wiring layer 36, and a plurality of metal pads 38 provided on these via plugs 37. The metal pads 38 are, for example, a metal layer including a Cu (copper) layer. The metal pads 38 are an example of a first pad, and the via plugs 37 are an example of a first plug. The circuit chip 2 functions as a control circuit (logic circuit) that controls the operation of the array chip 1. This control circuit is composed of transistors 31 and the like, and is electrically connected to the metal pads 38.

[0015] The array chip 1 includes a plurality of metal pads 41 provided on the metal pads 38, and a plurality of via plugs 42 provided on the metal pads 41. The array chip 1 also includes a wiring layer 43 provided on the via plugs 42 and including a plurality of wirings, and a wiring layer 44 provided on the wiring layer 43 and including a plurality of wirings. The metal pads 41 are, for example, a metal layer including a Cu layer. The metal pads 41 are an example of a second pad, and the via plugs 42 are an example of a second plug. The bit lines BL described above are included in the wiring layer 44. The control circuit is electrically connected to the memory cell array 11 via the metal pads 41, 38, etc., and controls the operation of the memory cell array 11 via the metal pads 41, 38, etc.

[0016] The array chip 1 further includes a plurality of via plugs 45 provided on the wiring layer 44, metal pads 46 provided on the via plugs 45 and on the insulating film 12, and a passivation film 47 provided on the metal pads 46 and on the insulating film 12. The metal pads 46 are, for example, a metal layer including a Cu layer, and function as external connection pads (bonding pads) of the semiconductor device of FIG. 1. The passivation film 47 is, for example, an insulating film such as a silicon oxide film, and has an opening P that exposes the upper surface of the metal pads 46. The metal pads 46 can be connected to a mounting board or other devices via the opening P by a bonding wire, a solder ball, a metal bump, or the like.

[0017] FIG. 2 is a cross-sectional view showing the structure of the columnar portion CL of the first embodiment.

[0018] 2, the memory cell array 11 includes a plurality of word lines WL and a plurality of insulating layers 51 alternately stacked on the interlayer insulating film 13 (FIG. 1). The word lines WL are, for example, W (tungsten) layers. The insulating layers 51 are, for example, silicon oxide films.

[0019] The columnar portion CL includes a block insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56, in that order. The charge storage layer 53 is, for example, a silicon nitride film, and is formed on the side surface of the word line WL and the insulating layer 51 via the block insulating film 52. The charge storage layer 53 may be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 55 is, for example, a polysilicon layer, and is formed on the side surface of the charge storage layer 53 via the tunnel insulating film 54. The block insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, a silicon oxide film or a metal insulating film.

[0020] 3 and 4 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0021] 3 shows an array wafer W1 including a plurality of array chips 1 and a circuit wafer W2 including a plurality of circuit chips 2. The array wafer W1 is also called a "memory wafer" and the circuit wafer W2 is also called a "CMOS wafer."

[0022] It should be noted that the orientation of the array wafer W1 in Fig. 3 is opposite to that of the array chip 1 in Fig. 1. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2 together. Fig. 3 shows the array wafer W1 before it is inverted for bonding, and Fig. 1 shows the array chip 1 after it has been inverted for bonding, bonded, and diced.

[0023] 3, reference symbol S1 indicates the upper surface of the array wafer W1, and reference symbol S2 indicates the upper surface of the circuit wafer W2. It should be noted that the array wafer W1 includes a substrate 16 provided under an insulating film 12. The substrate 16 is, for example, a semiconductor substrate such as a silicon substrate.

[0024] In this embodiment, first, as shown in FIG. 3, the memory cell array 11, the insulating film 12, the interlayer insulating film 13, the staircase structure 21, the metal pad 41, etc. are formed on the substrate 16 of the array wafer W1, and the interlayer insulating film 14, the transistor 31, the metal pad 38, etc. are formed on the substrate 15 of the circuit wafer W2. For example, the via plug 45, the wiring layer 44, the wiring layer 43, the via plug 42, and the metal pad 41 are formed in this order on the substrate 16. In addition, the contact plug 33, the wiring layer 34, the wiring layer 35, the wiring layer 36, the via plug 37, and the metal pad 38 are formed in this order on the substrate 15. Next, as shown in FIG. 4, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure. As a result, the interlayer insulating film 13 and the interlayer insulating film 14 are bonded. Next, the array wafer W1 and the circuit wafer W2 are annealed at 400° C. As a result, the metal pad 41 and the metal pad 38 are bonded.

[0025] Thereafter, the substrate 15 is thinned by CMP (Chemical Mechanical Polishing), the substrate 16 is removed by CMP, and the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. In this manner, the semiconductor device of FIG. 1 is manufactured. FIG. 1 shows a circuit chip 2 including a metal pad 38 and an interlayer insulating film 14, and an array chip 1 including a metal pad 41 and an interlayer insulating film 13 disposed on the metal pad 38 and the interlayer insulating film 14, respectively. Note that the metal pad 46 and the passivation film 47 are formed on the insulating film 12, for example, after the substrate 15 is thinned and the substrate 16 is removed.

[0026] In this embodiment, the array wafer W1 and the circuit wafer W2 are bonded together, but instead, array wafers W1 may be bonded together. The contents described above with reference to Figures 1 to 4 and the contents described below with reference to Figures 5 to 20 are also applicable to bonding array wafers W1 together.

[0027] 1 shows the boundary surface between the interlayer insulating film 13 and the interlayer insulating film 14 and the boundary surface between the metal pad 41 and the metal pad 38, but these boundaries generally cannot be observed after the above-mentioned annealing. However, the positions of these boundaries can be estimated by detecting, for example, the inclination of the side surface of the metal pad 41 or the side surface of the metal pad 38, or the positional deviation between the side surface of the metal pad 41 and the metal pad 38.

[0028] Furthermore, the semiconductor device of this embodiment may be traded in the state shown in FIG. 1 after being cut into a plurality of chips, or in the state shown in FIG. 4 before being cut into a plurality of chips. FIG. 1 shows the semiconductor device in the form of a chip, and FIG. 4 shows the semiconductor device in the form of a wafer. In this embodiment, a plurality of chip-shaped semiconductor devices (FIG. 1) are manufactured from one wafer-shaped semiconductor device (FIG. 4).

[0029] Fig. 5 is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the first embodiment. Fig. 6 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. The difference between the semiconductor device shown in Fig. 5 and the semiconductor device shown in Fig. 6 is, for example, the presence or absence of a metal layer 61. The metal layer 61 is an example of a first portion.

[0030] Hereinafter, the structure of the semiconductor device of this embodiment will be described with reference to FIG. 6, and then the semiconductor device of this embodiment will be compared with a semiconductor device of a comparative example with reference to FIGS.

[0031] In this embodiment (FIG. 6), the interlayer insulating film 14 includes insulating films 14e, 14d, 14c, 14b, and 14a provided in order below the bonding surface S, and the interlayer insulating film 13 includes insulating films 13e, 13d, 13c, 13b, and 13a provided in order on the bonding surface S. Furthermore, the metal pad 38 includes a barrier metal layer 38a and a pad material layer 38b provided in order in the interlayer insulating film 14, and the metal pad 41 includes a barrier metal layer 41a and a pad material layer 41b provided in order in the interlayer insulating film 13. The semiconductor device of this embodiment further includes the above-mentioned metal layer 61.

[0032] The insulating films 14a, 14c, 14e, 13a, 13c, and 13e are, for example, SiO2 films (silicon oxide films). The insulating films 14b and 13b are, for example, SiN films (silicon nitride films). The insulating films 14b and 13b of this embodiment are used as etching stoppers when forming holes for embedding the metal pads 38 and 41 in the interlayer insulating films 14 and 13 by etching. The insulating films 14d and 13d are, for example, SiCN films (silicon carbonitride films). The insulating films 14d and 13d of this embodiment are formed to prevent Cu atoms in the metal pads 38 and 41 from diffusing into the interlayer insulating films 14 and 13. The insulating films 14d and 13d are examples of the third film and the fourth film, respectively. The insulating films 14e and 13e are examples of the first film and the second film, respectively.

[0033] The insulating films 14e and 13e of this embodiment are natural oxide films formed by natural oxidation of the insulating films 14d and 13d, respectively, before the array wafer W1 and the circuit wafer W2 are bonded together. Therefore, the lower surface of the insulating film 14e of this embodiment is in contact with the upper surface of the insulating film 14d, and the upper surface of the insulating film 13e of this embodiment is in contact with the lower surface of the insulating film 13e. Also, the upper surface of the insulating film 14e of this embodiment is in contact with the lower surface of the insulating film 13e. Note that the insulating films 14e and 13e may be formed by a cause other than natural oxidation, and may be formed, for example, by CMP or plasma treatment of the surfaces of the interlayer insulating films 14 and 13.

[0034] The barrier metal layer 38a is formed on the side and lower surface (bottom surface) of the interlayer insulating film 14, and is in contact with the side and lower surface of the interlayer insulating film 14. The pad material layer 38b is formed on the side and lower surface of the interlayer insulating film 14 via the barrier metal layer 38a. Similarly, the barrier metal layer 41a is formed on the side and upper surface (bottom surface) of the interlayer insulating film 13, and is in contact with the side and upper surface of the interlayer insulating film 13. The pad material layer 41b is formed on the side and upper surface of the interlayer insulating film 13 via the barrier metal layer 41a. The barrier metal layers 38a and 41a are examples of the first layer and the third layer, respectively. The pad material layers 38b and 41b are examples of the second layer and the fourth layer, respectively.

[0035] The barrier metal layers 38a and 41a are, for example, metal layers containing Ti (titanium), Al (aluminum), or Mn (manganese), and are Ti layers here. The barrier metal layers 38a and 41a in this embodiment are formed, for example, to prevent Cu atoms in the metal pads 38 and 41 from diffusing into the interlayer insulating films 14 and 13, respectively. The barrier metal layers 38a and 41a may be metal compound layers containing metal elements and nonmetal elements, and may be, for example, metal oxide films or metal nitride films. The barrier metal layers 38a and 41a may also be alloy layers containing two or more kinds of metal elements. The pad material layers 38b and 41b are, for example, metal layers containing Cu, and are Cu layers here. The pad material layers 38b and 41b may be metal layers other than Cu layers.

[0036] The metal pads 38 and 41 of this embodiment have the same planar shape. Here, these planar shapes are squares or rectangles having two sides extending in the X direction and two sides extending in the Y direction. Therefore, the widths in the X direction and the Y direction of the metal pad 41 of this embodiment are the same as the widths in the X direction and the Y direction of the metal pad 38, respectively.

[0037] Therefore, if metal pad 41 is disposed directly above metal pad 38, the bottom surface of metal pad 41 will only be in contact with the top surface of metal pad 38, and will not be in contact with the top surfaces of layers other than metal pad 38. Similarly, the bottom surface of metal pad 38 will only be in contact with the bottom surface of metal pad 41, and will not be in contact with the bottom surfaces of layers other than metal pad 41.

[0038] However, the metal pad 41 of this embodiment is not disposed directly above the metal pad 38. Therefore, the lower surface of the metal pad 41 of this embodiment is not only in contact with the upper surface of the metal pad 38, but is also provided on the upper surface of the interlayer insulating film 14. Similarly, the upper surface of the metal pad 38 of this embodiment is not only in contact with the lower surface of the metal pad 38, but is also provided below the lower surface of the interlayer insulating film 13. In this embodiment, the metal layer 61 is formed between the upper surface of the metal pad 38 and the lower surface of the interlayer insulating film 13, and between the lower surface of the metal pad 41 and the upper surface of the interlayer insulating film 14.

[0039] The metal layer 61 contains, for example, the same metal element as the metal element contained in the barrier metal layers 38a and 41a. The metal element is, for example, Ti, Al, or Mn. The metal layer 61 may further contain oxygen. In this embodiment, the barrier metal layers 38a and 41a are Ti layers, and the metal layer 61 is TiO x (titanium oxide) layer.

[0040] The metal layer 61 of this embodiment is formed by diffusing Ti atoms in the barrier metal layers 38a and 41a into the interface between the pad material layer 38b and the insulating film 13e and the interface between the pad material layer 41b and the insulating film 14e, and is formed in a self-aligned manner at the positions of these interfaces. The metal layer 61 of this embodiment is a TiO x Therefore, the lower surface of the metal layer 61 in this embodiment is in contact with the upper surface of the insulating film 14e and the upper surface of the pad material layer 38b, and the upper surface of the metal layer 61 in this embodiment is in contact with the lower surface of the insulating film 13e and the lower surface of the pad material layer 41b.

[0041] The metal layer 61 may contain the same metal element as the metal element contained in only one of the barrier metal layers 38a and 41a. For example, if only the barrier metal layer 38a of the barrier metal layers 38a and 41a contains Ti atoms and the metal layer 61 is formed by Ti atoms diffused from the barrier metal layer 38a, the barrier metal layer 38a and the metal layer 61 contain Ti, and the barrier metal layer 41a does not contain Ti.

[0042] Furthermore, the metal layer 61 of this embodiment may be formed between the metal pad 38 and the interlayer insulating film 13, or between the metal pad 41 and the interlayer insulating film 14, with a thickness or size so small that it cannot be called a layer. Further details of the process of forming the metal layer 61 of this embodiment will be described later.

[0043] Next, the semiconductor device of this embodiment will be compared with the semiconductor device of the comparative example with reference to FIGS.

[0044] In the comparative example (FIG. 5), the barrier metal layers 38a and 41a are Ta (tantalum) layers instead of Ti layers. Ta atoms are less likely to diffuse than Ti atoms. Therefore, in the comparative example, the metal layer 61 is not formed between the metal pad 38 and the interlayer insulating film 13 or between the metal pad 41 and the interlayer insulating film 14.

[0045] In the comparative example, the insulating films 14e and 13e (SiO2 films) are formed between the insulating films 14d and 13d (SiCN films) in the same manner as in the present embodiment. The SiO2 film has a smaller effect of preventing the diffusion of Cu atoms than the SiCN film. Therefore, in the comparative example, the Cu atoms in the metal pads 38 and 41 diffuse into the interlayer insulating films 14 and 13 through the insulating films 14e and 13e. The diffusion of Cu atoms may occur, for example, during an annealing process when manufacturing a semiconductor device. The Cu atoms diffused into the interlayer insulating films 14 and 13 may cause leakage currents between the metal pads 38, between the metal pads 41, between the metal pads 38 and 41, and between the metal pads 38 and 41, for example.

[0046] The diffusion of Cu atoms into the interlayer insulating films 14 and 13 is almost no problem if the metal pads 38 and 41 have the same planar shape and the metal pad 41 is disposed directly above the metal pad 38. In this case, the bottom surface of the metal pad 41 contacts only the top surface of the metal pad 38, and the top surface of the metal pad 38 contacts only the bottom surface of the metal pad 41.

[0047] However, when the array wafer W1 and the circuit wafer W2 are bonded together, an error may occur in the alignment between the metal pad 38 and the metal pad 41. In this case, the metal pad 41 is not disposed directly above the metal pad 38, and the lower surface of the metal pad 41 also contacts the upper surface of the interlayer insulating film 14, and the upper surface of the metal pad 38 also contacts the lower surface of the interlayer insulating film 13.

[0048] Even in this case, if the upper surface of the interlayer insulating film 14 is formed of the insulating film 14d (SiCN film) and the lower surface of the interlayer insulating film 13 is formed of the insulating film 13d (SiCN film), the diffusion of Cu atoms into the interlayer insulating films 14 and 13 can be suppressed. This is because the SiCN film has a large effect of preventing the diffusion of Cu atoms. However, if the interlayer insulating films 14 and 13 contain the insulating films 14e and 13e (SiO2 films) due to natural oxidation or the like, the Cu atoms in the metal pads 38 and 41 will diffuse into the interlayer insulating films 14 and 13 via the insulating films 14e and 13e.

[0049] On the other hand, in this embodiment (FIG. 6), the barrier metal layers 38a and 41a are Ti layers. Ti atoms are more easily diffused than Ta atoms. Therefore, in this embodiment, a metal layer 61 is formed between the metal pad 38 and the interlayer insulating film 13 and between the metal pad 41 and the interlayer insulating film 14. Therefore, according to this embodiment, even if the metal pad 41 is not disposed directly above the metal pad 38 and the interlayer insulating films 14 and 13 contain insulating films 14e and 13e (SiO2 films) due to natural oxidation or the like, the metal layer 61 can suppress the diffusion of Cu atoms from the metal pads 38 and 41 to the interlayer insulating films 14 and 13. The diffusion of Ti atoms that causes the metal layer 61 occurs, for example, during an annealing process when manufacturing a semiconductor device.

[0050] The use of Ti layers as the barrier metal layers 38a and 41a has the following advantages: x The advantages are that the barrier properties of the Ti layer (metal layer 61) are high and that the cost of forming the Ti layer is low. x When forming a layer, or when using an Mn layer, MnO x This can also be achieved when forming layers.

[0051] In addition, the structure in this embodiment in which metal pad 41 is not directly above metal pad 38 may occur due to an error in alignment between metal pad 38 and metal pad 41, or may be created intentionally when manufacturing the semiconductor device.

[0052] 7 to 11 are cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment. The method shown in Figs. 7 to 11 corresponds to a specific example of the method shown in Figs.

[0053] First, the array wafer W1 and the circuit wafer W2 are processed into the structure shown in FIG. 7. Specifically, an insulating film 13a is formed above the substrate 16 (see FIG. 3), a via plug 42 is formed in the insulating film 13a, insulating films 13b, 13c, and 13d are formed in order on the insulating film 13a and the via plug 42, and a barrier metal layer 41a and a pad material layer 41b are formed in order in the insulating films 13b, 13c, and 13d. Similarly, an insulating film 14a is formed above the substrate 15 (see FIG. 3), a via plug 37 is formed in the insulating film 14a, insulating films 14b, 14c, and 14d are formed in order on the insulating film 14a and the via plug 37, and a barrier metal layer 38a and a pad material layer 38b are formed in order in the insulating films 14b, 14c, and 14d. As a result, metal pads 41 and 38 are formed in the interlayer insulating films 13 and 14, respectively.

[0054] Next, the insulating films 13e and 14e are formed on the surfaces of the insulating films 13d and 14d by oxidation, respectively (FIG. 8). The insulating films 13e and 14e are formed by, for example, natural oxidation.

[0055] Next, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure so that the metal pad 41 is placed on the metal pad 38 and the interlayer insulating film 13 is placed on the interlayer insulating film 14 (FIG. 9). This bonds the interlayer insulating film 13 and the interlayer insulating film 14 together. In FIG. 9, an error has occurred in the alignment of the metal pad 38 and the metal pad 41, and part of the upper surface of the metal pad 38 and part of the lower surface of the metal pad 41 are in contact with each other.

[0056] Next, the array wafer W1 and the circuit wafer W2 are annealed (FIG. 10). This bonds the metal pads 41 and 38. FIG. 10 further shows grain boundaries α between crystal grains in the pad material layers 38b and 41b, and Ti atom groups β diffusing along the grain boundaries α and the bonding surface S. In this embodiment, Ti atoms diffuse from the barrier metal layers 38a and 41a due to the annealing in the process shown in FIG.

[0057] As a result, Ti atoms in the barrier metal layers 38a and 41a are diffused to the interface between the pad material layer 38b and the insulating film 13e and the interface between the pad material layer 41b and the insulating film 14e, and a metal layer 61 is formed in a self-aligned manner at the interface (FIG. 11). Specifically, the Ti atoms diffused from the barrier metal layers 38a and 41a to these interfaces react with O atoms in the insulating films 14e and 13e to form the metal layer 61 as TiO x Therefore, according to this embodiment, the diffusion of Cu atoms from the metal pads 38 and 41 to the interlayer insulating films 14 and 13 can be suppressed by the metal layer 61.

[0058] In this manner, the semiconductor device in Fig. 6 is manufactured. After that, the substrate 15 is thinned by CMP, and the substrate 16 is removed by CMP, and then the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. In this manner, the semiconductor device in Fig. 1 is manufactured.

[0059] As described above, the semiconductor device of this embodiment includes the metal layer 61 containing the same metal element as the metal element contained in the barrier metal layers 38a, 41a between the upper surface of the metal pad 38 and the lower surface of the interlayer insulating film 13, and between the lower surface of the metal pad 41 and the upper surface of the interlayer insulating film 14. Therefore, according to this embodiment, it is possible to form suitable metal pads 38, 41, for example, by suppressing diffusion of metal atoms (e.g., Cu atoms) from the pad material layers 38b, 41b to the insulating films 14e, 13e.

[0060] Second embodiment FIG. 12 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0061] The interlayer insulating films 13 and 14 of this embodiment do not include insulating films 13d and 14d (SiCN films), and as a result, do not include insulating films 13e and 14e (SiO2 films). In this embodiment, the insulating film 13c (SiO2 film) in the interlayer insulating film 13 and the insulating film 14c (SiO2 film) in the interlayer insulating film 14 are in contact with each other at the bonding surface S.

[0062] The semiconductor device of this embodiment also includes a metal layer 61. The metal layer 61 of this embodiment is formed when Ti atoms diffused from the barrier metal layers 38a and 41a react with O atoms in the insulating films 14c and 13c.

[0063] According to this embodiment, it is possible to omit the step of forming the insulating films 13d and 14d. Moreover, according to this embodiment, since the insulating films 13d and 14d are not present near the surfaces of the interlayer insulating films 13 and 14, it is possible to easily planarize the surfaces of the interlayer insulating films 13 and 14 by CMP. On the other hand, according to the first embodiment, the diffusion of Cu atoms can be suppressed not only by the metal layer 61 but also by the insulating films 13d and 14d.

[0064] 13 to 16 are cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment. The method shown in Figs. 13 to 16 corresponds to a specific example of the method shown in Figs.

[0065] First, the array wafer W1 and the circuit wafer W2 are processed into the structure shown in FIG. 13. Specifically, an insulating film 13a is formed above the substrate 16 (see FIG. 3), a via plug 42 is formed in the insulating film 13a, insulating films 13b and 13c are formed in order on the insulating film 13a and the via plug 42, and a barrier metal layer 41a and a pad material layer 41b are formed in order in the insulating films 13b and 13c. Similarly, an insulating film 14a is formed above the substrate 15 (see FIG. 3), a via plug 37 is formed in the insulating film 14a, insulating films 14b and 14c are formed in order on the insulating film 14a and the via plug 37, and a barrier metal layer 38a and a pad material layer 38b are formed in order in the insulating films 14b and 14c. As a result, metal pads 41 and 38 are formed in the interlayer insulating films 13 and 14, respectively.

[0066] Next, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure so that the metal pad 41 is placed on the metal pad 38 and the interlayer insulating film 13 is placed on the interlayer insulating film 14 (FIG. 14). This bonds the interlayer insulating film 13 and the interlayer insulating film 14 together. In FIG. 14, an error has occurred in the alignment of the metal pad 38 and the metal pad 41, and part of the upper surface of the metal pad 38 and part of the lower surface of the metal pad 41 are in contact with each other.

[0067] Next, the array wafer W1 and the circuit wafer W2 are annealed (FIG. 15). This bonds the metal pads 41 and 38. FIG. 15 further shows grain boundaries α between crystal grains in the pad material layers 38b and 41b, and Ti atom groups β diffusing along the grain boundaries α and the bonding surface S. In this embodiment, Ti atoms diffuse from the barrier metal layers 38a and 41a due to the annealing in the process shown in FIG.

[0068] As a result, Ti atoms in the barrier metal layers 38a and 41a are diffused to the interface between the pad material layer 38b and the insulating film 13c and the interface between the pad material layer 41b and the insulating film 14c, and a metal layer 61 is formed in a self-aligned manner at the interface (FIG. 16). Specifically, the Ti atoms diffused from the barrier metal layers 38a and 41a to these interfaces react with O atoms in the insulating films 14c and 13c to form the metal layer 61 as TiO x Therefore, according to this embodiment, the diffusion of Cu atoms from the metal pads 38 and 41 to the interlayer insulating films 14 and 13 can be suppressed by the metal layer 61.

[0069] In this manner, the semiconductor device in Fig. 12 is manufactured. After that, the substrate 15 is thinned by CMP, and the substrate 16 is removed by CMP, and then the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. In this manner, the semiconductor device in Fig. 1 is manufactured.

[0070] As described above, the semiconductor device of this embodiment includes the metal layer 61 containing the same metal element as the metal element contained in the barrier metal layers 38a, 41a between the upper surface of the metal pad 38 and the lower surface of the interlayer insulating film 13, and between the lower surface of the metal pad 41 and the upper surface of the interlayer insulating film 14. Therefore, according to this embodiment, it is possible to form suitable metal pads 38, 41, for example, by suppressing diffusion of metal atoms (e.g., Cu atoms) from the pad material layers 38b, 41b to the insulating films 14c, 13c.

[0071] Third embodiment FIG. 17 is a cross-sectional view showing the structure of the semiconductor device of the third embodiment.

[0072] The interlayer insulating film 13 of this embodiment does not include the insulating film 13d (SiCN film), and as a result, does not include the insulating film 13e (SiO2 film). On the other hand, the interlayer insulating film 14 of this embodiment includes the insulating film 14d (SiCN film), and as a result, also includes the insulating film 14e (SiO2 film). In this embodiment, the insulating film 13c (SiO2 film) in the interlayer insulating film 13 and the insulating film 14e (SiO2 film) in the interlayer insulating film 14 are in contact with each other at the bonding surface S.

[0073] The semiconductor device of this embodiment also includes a metal layer 61. The metal layer 61 of this embodiment is formed when Ti atoms diffused from the barrier metal layers 38a and 41a react with O atoms in the insulating films 14e and 13c.

[0074] According to this embodiment, it is possible to obtain the same advantages as in the first embodiment for the interlayer insulating film 14, and the same advantages as in the second embodiment for the interlayer insulating film 13. The semiconductor device of this embodiment can be manufactured, for example, by applying the method shown in Figures 13 to 16 to the array wafer W1, and by applying the method shown in Figures 7 to 11 to the circuit wafer W2.

[0075] In the semiconductor device of this embodiment, the interlayer insulating film 13 may include the insulating films 13d and 13e, and the interlayer insulating film 14 may not include the insulating films 14d and 14e.

[0076] (Fourth embodiment) FIG. 18 is a cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment.

[0077] The metal pad 38 and the via plug 37 in the first to third embodiments are single damascene wiring, whereas the metal pad 38 and the via plug 37 in this embodiment are dual damascene wiring. Therefore, the barrier metal layer 37a and the plug material layer 37b in the via plug 37 in this embodiment are the same as the barrier metal layer 38a and the pad material layer 38b in the metal pad 38, respectively, and the plug material layer 37b in the via plug 37 is in contact with the pad material layer 38b in the metal pad 38. In other words, the barrier metal layers 38a and 37b are not provided at the interface between the pad material layer 38b and the plug material layer 37b. The barrier metal layer 38a and the barrier metal layer 37b are examples of the first layer, and the pad material layer 38b and the plug material layer 37b are examples of the second layer.

[0078] Similarly, the metal pad 41 and the via plug 42 in the first to third embodiments are single damascene wiring, whereas the metal pad 41 and the via plug 42 in this embodiment are dual damascene wiring. Therefore, the barrier metal layer 42a and the plug material layer 42b in the via plug 42 in this embodiment are the same as the barrier metal layer 41a and the pad material layer 41b in the metal pad 41, respectively, and the plug material layer 42b in the via plug 42 is in contact with the pad material layer 41b in the metal pad 41. In other words, the barrier metal layers 41a and 42b are not provided at the interface between the pad material layer 41b and the plug material layer 42b. The barrier metal layer 41a and the barrier metal layer 42b are examples of the third layer, and the pad material layer 41b and the plug material layer 42b are examples of the fourth layer.

[0079] According to this embodiment, it is possible to form the metal pad 38 and the via plug 37 in fewer steps, and it is possible to form the metal pad 41 and the via plug 42 in fewer steps. The semiconductor device of this embodiment can be manufactured, for example, by using a dual damascene method instead of a single damascene method in the steps of FIG. 7 when applying the method shown in FIG. 7 to FIG. 11.

[0080] Fifth embodiment FIG. 19 is a cross-sectional view showing the structure of the semiconductor device according to the fifth embodiment.

[0081] The metal pad 38 and the metal pad 41 of this embodiment have different planar shapes. The planar shapes of the metal pad 38 and the metal pad 41 of this embodiment are both square or rectangular, but the width in the X direction of the metal pad 41 is different from the width in the X direction of the metal pad 38, and the width in the Y direction of the metal pad 41 is different from the width in the Y direction of the metal pad 38. For example, the width in the X direction of the metal pad 41 is shorter than the width in the X direction of the metal pad 38, the width in the Y direction of the metal pad 41 is shorter than the width in the Y direction of the metal pad 38, and the entire lower surface of the metal pad 41 is in contact with a part of the upper surface of the metal pad 38.

[0082] The semiconductor device of this embodiment also includes a metal layer 61. The metal layer 61 of this embodiment is formed by reaction of Ti atoms diffused from the barrier metal layers 38a and 41a with O atoms mainly in the insulating film 13e.

[0083] In the first to fourth embodiments, if an error occurs in the alignment between the metal pads 38 and 41, the contact area between the metal pads 38 and 41 changes, and the contact resistance between the metal pads 38 and 41 changes. On the other hand, in this embodiment, even if a small error occurs in the alignment between the metal pads 38 and 41, the contact area between the metal pads 38 and 41 does not change, and the contact resistance between the metal pads 38 and 41 does not change. Therefore, according to this embodiment, it is possible to suppress problems associated with errors in the alignment between the metal pads 38 and 41.

[0084] In this embodiment, since the metal pad 38 and the metal pad 41 have different planar shapes, even if no error occurs in the alignment between the metal pad 38 and the metal pad 41, there will be a portion where the upper surface of the metal pad 38 is located below the lower surface of the interlayer insulating film 13, or a portion where the lower surface of the metal pad 41 is located above the upper surface of the interlayer insulating film 14. In this embodiment, the metal layer 61 can be formed in such portions. Therefore, according to this embodiment, it is possible to suppress the disadvantages of the metal pad 38 and the metal pad 41 having different planar shapes while enjoying the advantages of the metal pad 38 and the metal pad 41 having different planar shapes.

[0085] 7 to 11, the semiconductor device of this embodiment can be manufactured by making the planar shape of the metal pad 38 and the planar shape of the metal pad 41 different in the process of Fig. 7. Note that in this embodiment, a single damascene method may be used instead of the dual damascene method.

[0086] Sixth embodiment FIG. 20 is a cross-sectional view showing the structure of the semiconductor device according to the sixth embodiment.

[0087] The semiconductor device of this embodiment includes not only the metal pads 38, 41 that are in contact with each other (see FIG. 1, etc.), but also the metal pads 38, 41 that are not in contact with each other as shown in FIG. 20. Such metal pads 38, 41 are formed, for example, as dummy pads that are not used to electrically connect the array wafer W1 and the circuit wafer W2. The dummy pads are formed, for example, to adjust the density of the metal pads 38, 41 on the bonding surface S.

[0088] The semiconductor device of this embodiment also includes a metal layer 61. The metal layer 61 on the metal pad 38 of this embodiment is formed by Ti atoms diffused from the barrier metal layer 38a reacting mainly with O atoms in the insulating film 13e. On the other hand, the metal layer 61 below the metal pad 41 of this embodiment is formed by Ti atoms diffused from the barrier metal layer 41a reacting mainly with O atoms in the insulating film 14e.

[0089] The semiconductor device of this embodiment can be manufactured, for example, by applying the method shown in Figures 7 to 11, by bonding the array wafer W1 and the circuit wafer W2 in the process of Figure 9 so that the metal pads 38 and 41 shown in Figure 20 do not come into contact with each other.

[0090] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel device and method described in this specification can be implemented in various other forms. In addition, various omissions, substitutions, and modifications can be made to the forms of the device and method described in this specification without departing from the spirit of the invention. The appended claims and their equivalents are intended to include such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0091] 1: array chip, 2: circuit chip, 11: memory cell array, 12: insulating film, 13: interlayer insulating film, 13a: insulating film, 13b: insulating film, 13c: insulating film, 13d: insulating film, 13e: insulating film, 14: interlayer insulating film, 14a: insulating film, 14b: insulating film, 14c: insulating film, 14d: insulating film, 14e: insulating film, 15: substrate, 16: substrate, 21: staircase structure portion; 22: contact plug; 23: word wiring layer, 24: via plug, 31: transistor; 32: gate electrode; 33: contact plug; 34: wiring layer, 35: wiring layer, 36: wiring layer, 37: via plug, 37a: barrier metal layer, 37b: plug material layer, 38: metal pad, 38a: barrier metal layer, 38b: pad material layer, 41: metal pad, 41a: barrier metal layer, 41b: pad material layer, 42: via plug, 42a: barrier metal layer, 42b: plug material layer, 43: wiring layer, 44: wiring layer, 45: via plug, 46: metal pad, 47: passivation film, 51: insulating layer, 52: block insulating film, 53: charge storage layer, 54: tunnel insulating film, 55: channel semiconductor layer, 56: core insulating film, 61: metal layer

Claims

1. A first insulating film; a first pad provided in the first insulating film, the first pad including a first layer provided on a side surface and a bottom surface of the first insulating film and in contact with the side surface and the bottom surface of the first insulating film, and a second layer provided on the side surface and the bottom surface of the first insulating film via the first layer, the second layer being a Cu (copper) layer; A second insulating film provided on the first insulating film; a second pad provided on the first pad within the second insulating film, the second pad including a third layer provided on a side surface and an upper surface of the second insulating film and in contact with the side surface and the upper surface of the second insulating film, and a fourth layer, which is a Cu layer, provided on the side surface and the upper surface of the second insulating film via the third layer; a first portion provided between an upper surface of the first pad and a lower surface of the second insulating film, or between a lower surface of the second pad and an upper surface of the first insulating film, the first portion including the same metal element as the metal element included in the first layer or the third layer; a memory cell array provided in the second insulating film, the memory cell array including a plurality of word lines, a columnar portion penetrating the plurality of word lines, and a source line provided above the plurality of word lines and electrically connected to the columnar portion; a bit line provided in the second insulating film below the memory cell array and electrically connected to the columnar portion; a control circuit provided in the first insulating film and controlling the memory cell array via the first pad and the second pad; Equipped with the first pad is provided on a first plug including the first layer and the second layer, and the second layer in the first plug is in contact with the second layer in the first pad; or the second pad is provided under a second plug including the third layer and the fourth layer, the fourth layer in the second plug being in contact with the fourth layer in the second pad; and, The first insulating film includes an 11th film containing oxygen and in contact with a lower surface of the first portion, a 12th film containing nitrogen and in contact with a lower surface of the 11th film and a side surface of the first pad, and a 13th film containing oxygen and in contact with a lower surface of the 12th film and a side surface of the first plug, or the second insulating film includes a 14th film containing oxygen and in contact with an upper surface of the first portion, a 15th film containing nitrogen and in contact with an upper surface of the 14th film and a side surface of the second pad, and a 16th film containing oxygen and in contact with an upper surface of the 12th film and a side surface of the second plug; Semiconductor memory device.

2. 2. The semiconductor memory device according to claim 1, wherein said first portion contains said metal element and oxygen.

3. 3. The semiconductor memory device according to claim 1, wherein the metal element includes titanium, aluminum, or manganese.

4. 4. The semiconductor memory device according to claim 1, wherein the first layer or the third layer is a simple metal layer containing the metal element, or a metal compound layer containing the metal element and a nonmetal element.

5. A first insulating film; a first pad provided in the first insulating film, the first pad including a first layer provided on a side surface and a bottom surface of the first insulating film and in contact with the side surface and the bottom surface of the first insulating film, and a second layer provided on the side surface and the bottom surface of the first insulating film via the first layer, the second layer being a Cu (copper) layer; A second insulating film provided on the first insulating film; a second pad provided on the first pad within the second insulating film, the second pad including a third layer provided on a side surface and an upper surface of the second insulating film and in contact with the side surface and the upper surface of the second insulating film, and a fourth layer, which is a Cu layer, provided on the side surface and the upper surface of the second insulating film via the third layer; a first portion provided between an upper surface of the first pad and a lower surface of the second insulating film, or between a lower surface of the second pad and an upper surface of the first insulating film, the first portion including the same metal element as the metal element included in the first layer or the third layer; Equipped with the first insulating film includes a first film containing oxygen and in contact with a lower surface of the first portion, and a third film containing carbon and nitrogen and in contact with a lower surface of the first film, the first film being a native oxide film of the third film, or the second insulating film includes a second film containing oxygen and in contact with an upper surface of the first portion, and a fourth film containing carbon and nitrogen and in contact with an upper surface of the second film, the second film being a native oxide film of the fourth film; Semiconductor device.

6. The first insulating film includes a plurality of fifth films that contain oxygen and are in contact with the side surface of the first pad, a sixth film that contains nitrogen and is in contact with the side surface of the first pad, and a seventh film that contains carbon and nitrogen and is in contact with the side surface of the first pad, or the second insulating film includes a plurality of eighth films containing oxygen and in contact with a side surface of the second pad, a ninth film containing nitrogen and in contact with a side surface of the second pad, and a tenth film containing carbon and nitrogen and in contact with a side surface of the second pad; The semiconductor device according to claim 5 .

7. 7. The semiconductor device according to claim 5, wherein the first pad and the second pad have the same width.

8. 7. The semiconductor device according to claim 5, wherein the first pad and the second pad have different widths.

9. forming a first pad in a first insulating film, the first pad including a first layer provided on a side surface and a bottom surface of the first insulating film and in contact with the side surface and the bottom surface of the first insulating film, and a second layer, which is a Cu (copper) layer, provided on the side surface and the bottom surface of the first insulating film via the first layer; forming a second pad in a second insulating film, the second pad including a third layer provided on a side surface and a bottom surface of the second insulating film and in contact with the side surface and the bottom surface of the second insulating film, and a fourth layer, which is a Cu layer, provided on the side surface and the bottom surface of the second insulating film via the third layer; disposing the second insulating film on the first insulating film and disposing the second pad on the first pad; forming a first portion containing the same metal element as the metal element contained in the first layer or the third layer between an upper surface of the first pad and a lower surface of the second insulating film, or between the lower surface of the second pad and an upper surface of the first insulating film; Including, The method for manufacturing a semiconductor device, wherein the first portion is formed by the metal element diffused from the first layer or the third layer.

Images