Die-level product modeling without die-level input data

Abstract

A machine learning model for each die to attribute process control parameters at the die is based on wafer sort parametric measurements at multiple test sites across the wafer, as well as wafer yield results, allowing for better analysis of outlier spatial patterns that lead to improved yield results.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 62 / 916,163, filed October 16, 2019, entitled “Die Level Semiconductor Product Modeling without Die Level Input Data,” which is incorporated by reference in its entirety.

[0002] This application relates to modeling of semiconductor wafers, and more particularly, to modeling of die-level parameters. [Background technology]

[0003] Predicting the die-level yield of semiconductor products is very difficult for a variety of reasons. In previous generations, product yields were often defect-limited, and extensive optical defect data was required to model the die-level yield. Most efforts to model the spatial patterns of yield or wafer-sort parametric measurements using process control monitor (PCM) measurements focus on interpolating or extrapolating the PCM measurements to try and predict the PCM measurements on each wafer. To do this, electrical measurements of test structures on a few wafers are made as representative of a much larger set of wafers, and then used to create a fixed parameter map. These efforts have generally been unsuccessful, as they have failed to account for the variations in spatial patterns that often result in bad wafers.

[0004] Furthermore, mainly due to cost limitations, only a small percentage of wafers can be measured at each layer, making die-level prediction virtually impossible for most wafers.Yields in more recent generations are more often driven by parametric variations rather than defects, offering the opportunity to model yields directly from parametric measurements that can be performed on each die.

[0005] However, even here, cost is an obstacle. Initial parametric measurements of scribe line structures, often known as PCM or WAT (wafer acceptance test) data, are typically performed on a limited number of sites on each wafer, often only 5-10 sites. Using PCM data to predict wafer sort yield or wafer sort parameters on each die is valuable, especially when the importance of each variable on each wafer can be specified. Because PCM measurements are well known to generally correlate to parametric yield loss and wafer sort parameters, many wafer-level models have been successfully created using them to predict both wafer yield and the average values ​​of the parameters for each wafer. However, as mentioned above, predicting yield at the die level is particularly difficult, since PCM measurements are typically only available for a small number of sites on a wafer. To predict die-level yield, the most common approach is to impute values ​​of the PCM parameters at each die, either by interpolation or by fitting an assumed model form to the available PCM data. This has been only marginally successful due to the limited number of available sites and uncertainty in the model form for each PCM parameter.

[0006] It is therefore desirable to predict die yield or die-level wafer sort parameters directly from PCM parameters without the errors associated with explicitly attributing PCM parameters for each die. Summary of the Invention

[0007] A machine learning model is created for each die of a semiconductor wafer. Test data is obtained from multiple test sites distributed across the wafer. A die-level map of the wafer is obtained. Based on the test data and the die-level map, each model is configured to predict a yield for a respective die and to attribute process control parameters for the die. [Brief description of the drawings]

[0008] [Figure 1] 1 is a graphical plot illustrating wafer-level correlation between predicted and actual yields for multiple wafer samples. [Diagram 2] 2 is a graphical plot illustrating lot-level correlation between predicted and actual yields for the multiple wafer samples of FIG. 1. [Diagram 3] 1 is a series of graphical plots illustrating die-level correlation between predicted and actual yields for multiple wafer lots. [Figure 4] 4 is a series of heat maps illustrating predicted spatial patterns for the wafer lots shown in FIG. 3. [Diagram 5] 5 is a series of heat maps illustrating the actual spatial pattern of the wafer lots shown in FIG. 3 and predicted in FIG. 4. [Figure 6] 1 is a flow chart of a general process for determining die-level values ​​of process control parameters. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A wafer is a thin slice of semiconductor material used in the manufacture of integrated circuits. Typically, many identical circuits are formed on individual dies on a wafer, and once manufacturing is complete, the dies are sliced ​​at scribe lines to separate the individual circuits for packaging. Any structures close to the scribe lines are destroyed during this process, rendering the area useless for creating product circuits. However, these scribe line spaces are ideal for creating test structures that are measured before the dies are sliced.

[0010] Before slicing the dies, test protocols such as Wafer Acceptance Test (WAT) or Process Control Monitoring (PCM) are performed on scribe-line test structures formed at various test sites on the wafer. In one example, nine test sites are measured on the wafer. Ideally, some of the test sites are located near the edge of the wafer to understand the variations across the wafer. However, it is usually preferable to place the test sites away from the edge of the wafer to improve the quality of the measurements.

[0011] To improve die-level yield prediction, a separate processor-based model can be built for each die on a wafer, using test data acquired from each test site as separate input variables to the model. Additionally, models can be built per site, per die, per wafer, and / or per lot. Modern machine learning techniques can be used to construct algorithm-based software models that learn complex nonlinear relationships, initially from a training set of data and updated from newly acquired data, to continuously learn about the relationships between parameters to yield performance. For example, neural networks are one example of an implementation of a machine learning model, and XGBoost is another machine learning model based on an extremely complex tree model.

[0012] The complex data relationships between process parameters and variables can be univariate or multivariate, or both. By providing an analytical framework to better evaluate the various parameters and variables as representative of die-level performance, consistently better yield performance can be obtained overall. From the complex data relationships, the relevant input parameters for each die may be implicitly imputed by a model specific to that die.

[0013] Processor-based models can be desktop-based, i.e., standalone, or part of a network system, but given the heavy load of information to be processed and displayed with some interactivity, the processor capabilities (CPU, RAM, etc.) should be state-of-the-art to maximize efficiency. In a semiconductor foundry environment, the Exensio® analysis platform is a useful option for building GUI templates. In one embodiment, coding of processing routines can be done using Spotfire® analysis software version 7.11 or higher, which is compatible with the Python object-oriented programming language, which is primarily used for coding machine language models.

[0014] The key is to learn and understand the complex nonlinear relationships required to implicitly impute each PCM parameter for each die. Because there is insufficient PCM data to explicitly predict each PCM value, the imputation is driven by the die yield so that the imputed PCM values ​​can be implicitly predicted. Regardless of whether an implicit or explicit imputation form is selected for the model, the accuracy is clearly demonstrated by the correlation between predicted and actual yield at the lot, wafer, and die level, as shown in the figure.

[0015] 1 is a wafer-level scatter plot 100 of predicted versus actual yield for a number of wafers across multiple lots, with the linear correlation between predicted and actual yield shown as line 120. The linear correlation between predicted and actual yield has a cross-validated r-squared value of 0.561, indicating an average correlation across all wafers of approximately 56% of predicted yield to actual yield.

[0016] Several individual wafers, labeled 101-109, are specifically referenced herein and in the drawings for illustrative purposes. For example, according to the wafer level correlations shown in Figure 1, wafer 103 has a relatively low correlation between predicted and actual yield, while wafers 102 and 109 have a relatively high correlation between predicted and actual yield.

[0017] Referring to FIG. 2, a lot-level scatter plot 200 of the same wafer is useful for drilling down and providing additional input to the die-level model, showing additional variance at the lot level.

[0018] Since yield is a binary variable with a value of 0 for a failed die and a value of 1 for a passing die, and prediction is a number between 0 and 1 indicating the probability that the die will produce a yield, it is more useful to compare the predicted yield to the average actual yield of each die and its immediately adjacent dies. This is called smoothing, and the actual and predicted yields in all figures have been smoothed using this method.

[0019] Die level correlations of predicted smoothed yield versus actual smoothed yield are shown in a series of plots in Figure 3 corresponding to nine sample wafers 101-109. For example, the die correlation for wafer 109 has an average r-squared value of 0.757, indicating approximately 76% correlation between the predicted and actual yield of the die on this wafer, the die correlation for wafer 108 has an average r-squared value of 0.580, indicating approximately 58% correlation between the predicted and actual yield of the die on this wafer, the die correlation for wafer 107 has an average r-squared value of 0.057, indicating approximately 6% correlation between the predicted and actual yield of the die on this wafer, the die correlation for wafer 106 has an average r-squared value of 0.714, indicating approximately 71% correlation between the predicted and actual yield of the die on this wafer, and the die correlation for wafer 105 has an average r-squared value of 0.293, indicating approximately 75% correlation between the predicted and actual yield of the die on this wafer. The die correlation for wafer 104 has an average r-squared value of 0.755, indicating approximately 76% correlation between the predicted and actual yield of the die on this wafer; the die correlation for wafer 103 has an average r-squared value of 0.430, indicating approximately 43% correlation between the predicted and actual yield of the die on this wafer; the die correlation for wafer 102 has an average r-squared value of 0.495, indicating approximately 50% correlation between the predicted and actual yield of the die on this wafer; and finally, the die correlation for wafer 101 has an average r-squared value of 0.331, indicating approximately 33% correlation between the predicted and actual yield of the die on this wafer.

[0020] These conclusions can be further confirmed by examining the spatial correlation for the die model, as shown for wafers 101-109 in the predicted heat map of Figure 4 and the actual heat map of Figure 5. Even when the yield results are lower, the model predicts the final map fairly well. The visual similarity of the wafer maps for wafers 103, 104, 105, 106, 108, and 109 is apparent. Wafers 101 and 107 are visually very different, and the correlation plot in Figure 3 shows that these wafers have low values ​​for spatial r-squared.

[0021] This concept is actually a mapping from inputs to outputs, but is based on the analysis of complex relationships from inputs to desired outputs, which in the main case is yield. Figure 6 is a flow chart showing a simple method for making die-level predictions of yield. In step 202, input data is obtained from each of the test sites formed across the wafer. In step 204, a die-level map of the wafer is obtained, providing graphical details of the features and locations. In step 206, for each die on the wafer, a machine learning model configured for the individual die predicts the yield of that die based on the test input data from all the test sites. The implicit attribution of features is primarily driven by yield performance, and the discovery of correlations between input data from across the test sites on a single wafer and individual dies, learned and continuously updated by the machine learning model, establishes a correspondence to PCM values ​​for individual die features. In optional step 208, the model can help identify the relative importance of certain PCM variables to yield. Finally, in step 210, the model is deployed for use in evaluating spatial patterns for yield. Using product yield and wafer sort parameter measurements as the intended responses for the model allows for implicit imputation of PCM parameters for individual dies, specifically to model outlier spatial patterns.

[0022] In addition to imputing PCM values ​​at multiple sites, this same technique can be used to incorporate metrology data such as tools, chambers, retention times, failure indicators, and other site level data such as wafer level data.

[0023] Thus, a machine learning model can be configured to attribute expected process control parameters for each die based on wafer sort parameter measurements at multiple test sites across the wafer, and the yield outcome for that wafer, allowing for better analysis of outlier spatial patterns that lead to improved yield outcomes.

Claims

[Claim 1] A method comprising: acquiring a plurality of test data from each of a respective plurality of test sites, the plurality of test sites being distributed across a semiconductor wafer; obtaining a die level map of the wafer; predicting, for each of a plurality of dies on the wafer indicated on the die-level map based on the plurality of test data and the die-level map, a yield for each of the plurality of dies using a respective machine learning model configured to model each of the plurality of dies; A method comprising:

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