MEMORY ARRAYS AND METHODS USED IN FORMING MEMORY ARRAYS - Patent application

Abstract

To provide memory arrays and methods used in forming a memory array.SOLUTION: A method comprises: forming a substrate (comprising a conductive tier, a first insulator tier thereabove, a sacrificial material tier thereabove, a second insulator tier thereabove, and a stack comprising vertically alternating insulative tiers and wordline tiers above the second insulator tier); forming channel material through the insulative tiers and the wordline tiers; forming horizontally elongated trenches through the stack to the sacrificial material tier; etching sacrificial material of the sacrificial material tier through the trenches selectively relative to material of the first and second insulator tiers, and exposing a laterally outer sidewall of the channel material in the sacrificial material tier; and forming a conductive structure directly against the laterally outer sidewall of the channel material, the conductive structure extending through the first insulator tier and directly electrically coupling the channel material to the conductive tier.SELECTED DRAWING: Figure 21

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The embodiments disclosed herein relate to memory arrays and methods used in forming memory arrays. [Background technology]

[0002] A memory is a type of integrated circuit used in computer systems to store data. A memory may be fabricated in one or more arrays of individual memory cells. The memory cells may be written to or read from using digit lines (sometimes called bit lines, data lines, or sense lines) and access lines (sometimes called word lines). The sense lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell is uniquely addressable by a combination of a sense line and an access line.

[0003] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells are capable of storing data for long periods of time in the absence of power. Non-volatile memory is conventionally defined as memory that has a retention time of at least about 10 years. Volatile memory loses memory and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless of the above, memory cells are configured to maintain or store memory in at least two different selectable states. In a binary system, the states are considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

[0004] A field effect transistor is a type of electronic component that can be used in memory cells. This type of transistor contains a pair of conductive source / drain regions with a semiconducting channel region between them. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Application of an appropriate voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, very little current can flow through the channel region. Field effect transistors may also contain additional structures, such as a reversibly programmable charge storage region, as part of the gate structure between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory that is used extensively in modern computers and devices. For example, a modern personal computer may have its BIOS stored in a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to use flash memory in solid-state drives to replace traditional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it allows manufacturers to accommodate new communication protocols as they become standardized, and it can provide the ability to remotely upgrade devices for increased functionality.

[0006] NAND may be the basic architecture of integrated flash memory. A NAND cell unit includes at least one selection device coupled in series to a series combination of memory cells (the series combination is commonly referred to as a NAND string). The NAND architecture may be configured in a three-dimensional array including vertically stacked memory cells each including a reversibly programmable vertical transistor. Control circuitry or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells each including a transistor. Summary of the Invention [Means for solving the problem]

[0007] Embodiments of the invention include methods used in forming arrays of transistors and / or memory cells, such as arrays of NAND or other memory cells with peripheral control circuitry (e.g., CMOS under-array) below the array. Embodiments of the invention include so-called "gate-last" or "replacement gate" processes, so-called "gate-first" processes, and other processes, whether existing or later developed independent of when the transistor gates are formed. Embodiments of the invention also include arrays of transistors and / or memory cells (e.g., NAND or other memory cells) independent of the fabrication method. A first exemplary method embodiment that can be considered a "gate-last" or "replacement gate" process will be described with reference to Figures 1 through 21. [Brief description of the drawings]

[0008] [Figure 1] 1 illustrates a cross-sectional view of a portion of a substrate during processing in accordance with one embodiment of the present invention. [Diagram 2] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Diagram 3] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 4] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Diagram 5] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 6] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 7] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 8]2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 9] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 10] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 11] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 12] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 13] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 14] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 15] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 16] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 17] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 18] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 19] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 20] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. [Figure 21] 2A-2D are sequential cross-sectional and / or enlarged views of the structure of FIG. 1 according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] FIG. 1 shows a structure 10 in a method of forming an array 12 of height-extending strings of transistors and / or memory cells (not yet shown). The structure 10 includes a base substrate 11 having any one or more of conductive / conductor / conductive, semiconductive / semiconductive, or insulating / insulator / insulating (i.e., electrically, as used herein) materials. Various materials are formed on the base substrate 11 in a height-extending manner. The materials may be on the side, inside, or outside the height-extending materials shown in FIG. 1. For example, other partially or fully fabricated components of an integrated circuit may be provided anywhere above, around, or within the base substrate 11. Control and / or other peripheral circuitry for operating components in the array of height-extending strings of memory cells (e.g., array 12) may also be fabricated and may or may not be entirely or partially within an array or sub-array. Multiple sub-arrays may also be fabricated and may operate independently, in conjunction, or in other manners relative to one another. In this specification, a "sub-array" may also be considered an array.

[0010] The substrate / structure 10 includes a conductive layer 16. An exemplary conductive layer 16 is made of a conductive material 19 (e.g., WSi x 1. Conductive layer 16 is shown as including a conductive material 17 (e.g., a conductively doped semiconductive material, such as conductively doped polysilicon) over a conductive material 18 (e.g., a conductively doped semiconductive material, such as conductively doped polysilicon). Conductive layer 16 may include part of control circuitry (e.g., peripheral under-array circuitry) used to control read and write access of transistors and / or memory cells to be formed in array 12.

[0011] The structure 10 includes a first insulator layer 13 over a conductive layer 16, a sacrificial material layer 14 over the first insulator layer 13, and a second insulator layer 15 over the sacrificial material layer 14. In some embodiments, the first insulator layer 13 includes an insulating metal oxide 31, and the second insulator layer 15, if present, includes an insulating metal oxide 23 that is the same or different composition as that of the insulating metal oxide 31. In the context of this specification, the "metal" of the "insulating metal oxide" is any elemental metal, including any of the elemental semi-metals (i.e., B, Si, Ge, As, Sb, Te, Po, and At). Some examples include SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , silicates, aluminates, Hf x Zr y O z , and Si x Al y O z In one embodiment, the insulating metal oxide comprises a plurality of elemental metals, and in one such embodiment, one of the elemental metals is Si. In one embodiment, at least a majority of the insulating metal oxide is stoichiometric, and in another embodiment, at least a majority of the insulating metal oxide is non-stoichiometric. Regardless, the insulating metal oxide may contain a conductive metal oxide species (e.g., RuO 2 , IrO 2 etc.), but when considered as a whole, are generally insulating (i.e., insulating metal oxides have a dielectric constant of 1×10 at 20° C. -10 The sacrificial material layer 14 comprises a sacrificial material 21 that can be etched selectively to the material 31 of the first insulator layer 13 and selectively to the material 23 of the second insulator layer 15. An ideal example is silicon nitride, but any other suitable material may be used, including metallic materials. A conductively doped semiconductive material layer 27 is above the sacrificial material layer 14 and comprises a conductively doped semiconductive material 28 (e.g., conductively doped polysilicon).

[0012] The substrate structure 10 includes a stack of layers 18 above the second insulator layer 15 (and the conductively doped semiconductive material layer 27, if present). The stack of layers 18 includes vertically alternating insulating layers 20 and wordline layers 22, with the conductively doped semiconductive material layer 27, if present, being vertically between the second insulator layer 15 and the bottom of the insulating layer 20. Although only a few layers 20 and 22 are shown, the stack of layers 18 often includes tens, a hundred, or even more layers 20 and 22. Other circuitry, which may or may not be part of peripheral and / or control circuitry, may be between the conductive layer 16 and the stack of layers 18. For example, multiple vertically alternating layers of conductive and insulating material of such circuitry may be below the bottom of the wordline layer 22 and / or above the top of the wordline layer 22. Nevertheless, the wordline layer 22 may not include a conductive material, and the insulating layer 20 may not include an insulating material or may be insulating at this point in the processing. An exemplary wordline layer includes a first material 26 (e.g., silicon nitride) that may be a sacrificial material in whole or in part. An exemplary insulating layer 20 includes a second material 24 (e.g., silicon dioxide) that may be a sacrificial material in whole or in part, of a different composition than the first material 26. Collectively, the stack 18 and layers 16, 13, 14, 15, and 27 may be considered a stack 100. Although only one stack 18 and one stack 100 are shown, multiple stacks 18 and / or one stack 100 may be above or below the stack 18 and / or stack 100 above or below the substrate 11 (not shown).

[0013] 2 and 3, channel openings 25 are formed (e.g., by dry anisotropic etching) in alternating layers 20 and 22. For purposes of illustration only, channel openings 25 are shown arranged in staggered row groups or columns of four openings 25 per row. Any alternative existing or future developed arrangements and structures may be used. The exemplary channel openings 25 are shown extending down to conductive layer 16, and in one embodiment, through material 17 and stopping on material 19.

[0014] The transistor channel material may be formed in each channel opening extending heightwise through the insulating layer and the word line layer, and each memory cell of the array may be formed to include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge passing material. The storage material of each memory cell (e.g., a floating gate material such as doped or undoped silicon or a charge trapping material such as silicon nitride, metal dots, etc.) is present along the heightwise direction in each of the charge blocking regions. An insulating charge passing material (e.g., a band gap engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulating oxides (e.g., silicon dioxide)) is present laterally between the channel material and the storage material.

[0015] 4 illustrates an embodiment in which a charge blocking material 30, a storage material 32, and a charge passing material 34 are formed in respective channel openings 25 along the height along the insulating layer 20 and the word line layer 22. The transistor materials 30, 32, and 34 (e.g., memory cell materials) may be formed, for example, by depositing respective thin layers on top of the stack 18 and in the respective channel openings 25, followed by planarizing such thin layers back to at least the top surface of the stack 18. A punch etch may be performed (not shown) to remove the materials 30, 32, and 34 from the base of the channel openings 25 to expose the conductive layer 16 (not shown). A channel material 36 is formed in the channel openings 25 along the height along the insulating layer 20 and the word line layer 22. Exemplary channel materials 36 include appropriately doped crystalline semiconductor materials such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness for each of materials 30, 32, 34 and 36 is 25 Angstroms to 100 Angstroms. Channel opening 25 is shown as including a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively, by way of example only, the radially central portion within channel opening 25 may include an empty space (not shown) and / or be devoid of solid material (not shown). Regardless, in one illustrated embodiment, a channel material 36 is formed within conductive layer 16 having a bottom 33 that is not directly adjacent any conductive material within conductive layer 16. In one embodiment, channel material 36 is formed through conductively doped semiconductive material layer 27.

[0016] 5 and 6, horizontally elongated trenches 40 are formed (e.g., by dry anisotropic etching) through stack 18 to sacrificial material layer 14. In one embodiment, horizontally elongated trenches 40 have respective bottoms 39 that are above bottom 41 of first insulator layer 13. In one such embodiment, bottoms 39 of horizontally elongated trenches 40 are above top 42 of first insulator layer 13, and in one such latter embodiment, bottoms 39 of horizontally elongated trenches 40 are below top 43 of sacrificial material layer 14.

[0017] 7, in one embodiment, a sacrificial sidewall liner 44 (e.g., doped or undoped polysilicon) is formed in the horizontally elongated trench 40. Such a liner may be of the same composition as the conductively doped semiconductive material 28 of the conductively doped semiconductive material layer 27. Such a liner 44 may be provided, for example, when material 26 is a sacrificial material and includes the same composition as the sacrificial material 21 (e.g., silicon nitride). Such a liner 44 may be subjected to a punch etch to remove the liner 44 from extending completely across the bottom 39 of the trench 40 to expose the sacrificial material 21 of the sacrificial material layer 14, for example, as shown.

[0018] 8, the sacrificial material 21 (not shown) is selectively etched (e.g., by wet etching, e.g., H if the sacrificial material comprises silicon nitride) through horizontally elongated trenches 40, selectively to the material 31 of the first insulator layer 13 and selectively to the material 23 of the second insulator layer 15. 3 PO 4 3. The sacrificial material 21 is etched away (using a sacrificial etching agent) such that the sacrificial material 21 forms an empty space 35. If a sacrificial sidewall liner 44 is present, the thickness of the sacrificial sidewall liner 44 may thereby be reduced, for example as shown.

[0019] The outer lateral sidewalls of the channels in the sacrificial material layer are eventually exposed, as shown, by way of example only, with reference to enlarged figures 9-12, where figure 9 is an enlarged view of a portion of figure 8 and figures 10-12 show successive subsequent processing thereon.

[0020] 10, material 30 in sacrificial material layer 14 is etched (e.g., using diluted HF 100:1 [by volume] if material 30 comprises silicon dioxide) to expose material 32. This may etch material 30 upwards and downwards (not shown) relative to sacrificial material layer 14.

[0021] 11 illustrates etching of material 32 within sacrificial material layer 14 to expose material 34, with exemplary upward and downward etching thereof also occurring. For example, if material 32 comprises silicon nitride, such etching may be selective to material 34 if at least its laterally outermost portions comprise silicon dioxide. 3 PO 4 Or it may be done by using 1000:1 (by volume) ultra-diluted HF.

[0022] FIG. 12 illustrates the use of 100:1 diluted HF, for example when material 34 includes silicon dioxide, and / or HF, for example when material 34 also includes silicon nitride. 3 PO 4 1 illustrates an exemplary subsequent etch of exposed material 34 selective to channel material 36 using a sacrificial layer 14. As a result, the laterally outer sidewalls 45 of channel material 36 in sacrificial layer 14 are exposed. Materials 30 and / or 34 may be etched upwards and downwards as shown.

[0023] 13 and 14, a conductive material 46 is formed in the trench 40 and in the sacrificial material layer 14, resulting in a conductive structure 51 that is in direct contact with the laterally outer sidewall 45 of the channel material 36 in the sacrificial material layer 14. The conductive structure 51 extends through the first insulator layer 13 and electrically couples the channel material 36 directly to the conductive layer 16. In one embodiment, the conductive material 46 is of the same composition as one or both of the materials 28 and 17 (e.g., a conductively doped semiconductive material such as conductively doped polysilicon). Such may also be of the same composition as the sacrificial sidewall liner 44, if present, in one embodiment. Notwithstanding this, in one embodiment shown, the conductive structure 51 includes a ring 47 (FIG. 13). Also, notwithstanding this, in one illustrated embodiment, the conductive structure 51 can be laterally within the conductively doped semiconductive material layer 27 between (a) the channel material 36 within the conductively doped semiconductive material layer 27 and (b) the conductively doped semiconductive material 28 of the conductively doped semiconductive material layer 27. In one embodiment, the conductivity-increasing dopant within the conductively doped semiconductive material 28 is diffused (e.g., by a dedicated annealing step or simply by an inherent thermal process during processing) laterally through the conductive structure 51 into the channel material 36 and upwardly into the channel material 36 above (and possibly below) the conductively doped semiconductive material layer 27. In one such embodiment, the conductive structure 51 includes a conductively doped semiconductive material (e.g., 46) that includes the conductivity-increasing dopant before and after such diffusion act.

[0024] 15, if conductive material 46 (not shown) and sacrificial sidewall liner 44 (not shown) are present, then, for example as shown, conductive material 46 and sacrificial sidewall liner 44 are removed through trench 40 to at least below conductively doped semiconductive material layer 27 (if conductively doped semiconductive material layer 27 is present).

[0025] 16, a first material 26 (not shown) of the wordline layer 22 is etched with a gas phase H 2 O 4 (e.g., when material 26 is silicon nitride and material 24 is silicon dioxide). 3 PO 4 or 1000:1 [by volume] ultra-dilute HF as the primary etchant) relative to the second material 24 .

[0026] 17, conductive material 48 is formed in wordline layer 22 through trenches 40, which will include the conductive material of the individual wordlines being formed. However, in one exemplary embodiment, conductive material 48 includes a conformal titanium nitride liner (not shown) that is first deposited, followed by the deposition of another compositional metallic material (e.g., elemental tungsten).

[0027] 18-20, conductive material 48 is removed from each trench 40. This results in word lines 29 and height-extending strings 49 of individual transistors and / or memory cells 56. The approximate locations of the transistors and / or memory cells 56 are indicated by brackets in FIG. 20 and partially by dashed outline in FIGS. 18 and 19, with the transistors and / or memory cells 56 essentially ring-shaped or annular in the illustrated example. Conductive material 48 can be considered to have terminations 50 (FIG. 20) that correspond to control gate regions 52 of the individual transistors and / or memory cells 56. The control gate regions 52 in the illustrated embodiment include individual portions of the individual word lines 29. Materials 30, 32 and 34 can be considered to be memory structures 65 that lie laterally between the control gate regions 52 and the channel material 36.

[0028] Between the storage material 32 and the respective control gate regions 52 is a charge blocking region (e.g., charge blocking material 30). The charge blocking may have the following functions in the memory cell: in a program mode, the charge blocking may prevent charge carriers from passing from the storage material (e.g., floating gate material, charge trapping material, etc.) towards the control gate, and in an erase mode, the charge blocking may prevent charge carriers from flowing from the control gate into the charge storage material. Thus, the charge blocking may function to block charge transfer between the control gate region and the storage material of the respective memory cell. An example of a charge blocking region as shown includes an insulator material 30. As another example, the charge blocking region may include a laterally (e.g., radially) outer portion of the storage material (e.g., material 32), such storage material being insulating (e.g., without any material of different composition between the insulating storage material 32 and the conductive material 48). Regardless, in yet another example, the interface between the storage material and the conductive material of the control gate may be sufficient to function as a charge blocking region without any separate composition insulator material 30. Also, the interface of conductive material 48 with material 30 (if present) can function together as a charge shielding region in combination with insulator material 30, or alternatively or additionally may be a laterally outer region of insulating storage material (e.g., silicon nitride material 32). Exemplary materials 30 are one or more of hafnium silicon oxide and silicon dioxide.

[0029] Referring to FIG. 21, a material 57 (dielectric and / or silicon-containing, such as undoped polysilicon) is formed within each of the trenches 40 .

[0030] In one embodiment, as described above, wordline layer 22 includes sacrificial material 26, and the method includes replacing sacrificial material 26 of wordline layer 22 with conductive wordline material 48 after forming conductive structures 51. In one such embodiment, if sacrificial sidewall liner 44 was formed in trench 40, sacrificial sidewall liner 44 is removed after etching of sacrificial material 21 in sacrificial material layer 14, and in one such embodiment, is removed after forming conductive structures 51.

[0031] Any other attributes or aspects shown and / or described herein for other embodiments may also be used with the above-described embodiments.

[0032] The embodiments of the present invention encompass memory arrays independent of the manufacturing method, although such memory arrays may have any of the attributes described herein in the method embodiments. Similarly, the method embodiments described above may incorporate and form any of the attributes described with respect to the device embodiments.

[0033] In one embodiment, a memory array (e.g., 12) includes a vertical stack (e.g., 100) including a conductive layer (e.g., 16), an insulator layer (e.g., 13) above the conductive layer, and a conductor layer (e.g., 14 in FIG. 21). The vertical stack includes vertically alternating insulating layers (e.g., 20) and word line layers (e.g., 22) above the conductor layer. The word line layers include gate regions (e.g., 52) of individual memory cells (e.g., 56). The gate lines individually include portions of the word lines (e.g., 29) in each of the word line layers. A channel material (e.g., 36) extends heightwise through the insulating layer and the word line layer. The individual memory cells include a memory structure (e.g., 65) between the gate region and the channel material. The memory structure includes charge blocking regions (e.g., 30) laterally inward of each of the gate regions, storage regions (e.g., 32) laterally inward of each of the charge blocking regions, and an insulating charge passing material (e.g., 34) laterally inward of each of the storage regions. Conductive structure 51 extends through the insulator layer and electrically couples the channel material directly to the conductive layer. In one embodiment, the memory array includes horizontally elongated insulator structures (e.g., 57) that extend heightwise through the insulator layer and the word line layer, such structures laterally separating the individual word lines in each of the word line layers. The horizontally elongated insulator structures each have a bottom (e.g., 39 in FIG. 21) that is above the bottom (e.g., 41) of the insulator layer. In one such embodiment, the bottom of the horizontally elongated structure is above the top (e.g., 42) of the insulator layer, and in one such latter embodiment, below the top (e.g., 43 in FIG. 21) of the conductor layer. In one embodiment, another insulator layer (e.g., 15) is above the conductor layer and below the conductively doped semiconductive material layer (e.g., 27). In one embodiment, the memory array includes a NAND. Any other attributes or aspects shown and / or described herein for other embodiments may also be used.

[0034] In one embodiment, a memory array (e.g., 12) includes a vertical stack (e.g., 100) including a conductive layer (e.g., 16), an insulator layer (e.g., 13) above the conductive layer, and a conductor layer (e.g., 14 in FIG. 21). The vertical stack includes vertically alternating insulating layers (e.g., 20) and word line layers (e.g., 22) above the conductor layer. The word line layers include gate regions (e.g., 52) of individual memory cells (e.g., 56). The gate lines individually include portions of the word lines (e.g., 29) in each of the word line layers. A channel material (e.g., 36) extends heightwise through the insulating layer and the word line layer. The individual memory cells include a memory structure (e.g., 65) between the gate region and the channel material. The memory structure includes charge blocking regions (e.g., 30) laterally inward of each of the gate regions, storage regions (e.g., 32) laterally inward of each of the charge blocking regions, and an insulating charge passing material (e.g., 34) laterally inward of each of the storage regions. The conductive structures (e.g., 51) electrically couple the channel material directly to the conductive layer. Horizontally elongated insulator structures (e.g., 57) extend heightwise through the insulating layer and the wordline layer, laterally separating each of the wordlines, each having a bottom (e.g., 39) above a bottom (e.g., 41) of the insulator layer. Any other attributes or aspects shown and / or described herein for other embodiments may also be used.

[0035] One embodiment of the present invention includes a memory array (e.g., 12) including a vertical stack (e.g., 100) including a conductive layer (e.g., 16), a first insulator layer (e.g., 13) above the conductive layer, a conductor layer (e.g., 14 in FIG. 21) above the insulator layer, a second insulator layer (e.g., 15) above the conductive layer, and a conductively doped semiconductive material layer (e.g., 27) above the second insulator layer. Vertically alternating insulator layers (e.g., 20) and word line layers (e.g., 22) are above the conductively doped semiconductive material layer. The word lines include gate regions (e.g., 52) of individual memory cells (e.g., 56). Each of the gate regions includes a portion of a word line (e.g., 29) in each of the word line layers. A channel material (e.g., 36) extends heightwise through the insulator layers and the word line layers. The individual memory cells include a memory structure (e.g., 65) between the individual gate regions and the channel material. The memory structure includes charge blocking regions (e.g., 30) laterally inward of each gate region, storage regions (e.g., 32) laterally inward of each of the charge blocking regions, and insulating charge passing material (e.g., 34) laterally inward of each of the storage regions. A conductive structure (e.g., 51) extends through the conductively doped semiconductive material layer, the second insulator layer, the conductor layer, and the first insulator layer. The conductive structure includes a sidewall (e.g., 45) that electrically couples the channel material directly to the conductive layer and is in direct contact with the sidewall of the conductive layer. Any other attributes or aspects shown and / or described herein for other embodiments may also be used.

[0036] The above processing or structure may be considered for an array of components formed as or in a single stack or a single deck of such components above or as part of an underlying base substrate (although a single stack / deck may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components in the array may also be formed anywhere as part of the completed structure, and in some embodiments may be below the array (e.g., CMOS under-array). Notwithstanding this, one or more additional such stacks / decks may be provided or fabricated above and / or below the stacks / deck shown in the figures or described above. Furthermore, the arrays of components may be the same or different relative to each other in the different stacks / decks. Intervening structures may be provided between immediately vertically adjacent stacks / decks (e.g., additional circuitry and / or dielectric layers). Also, the different stacks / decks may be electrically coupled to each other. Multiple stacks / decks may be fabricated separately and sequentially (e.g., one above the other), or two or more stacks / decks may be fabricated essentially simultaneously.

[0037] The above-described assemblies and structures can be used in integrated circuits / circuits and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application specific modules, and can include multi-layered multi-chip modules. The electronic systems can be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0038] In this specification, unless otherwise specified, "height", "higher", "top", "bottom", "top", "top", "bottom", "up", "down", "down", "straight below", "up" and "down" generally refer to the vertical direction. "Horizontal" refers to a direction generally along the main substrate plane (i.e., within 10 degrees) that may be the direction in which the substrate is processed during manufacturing, and vertical refers to a direction generally perpendicular to this direction. "Strictly horizontal" refers to a direction along the main substrate plane (i.e., no angle from the main substrate plane) that may be the direction in which the substrate is processed during manufacturing. Additionally, as used herein, "vertical" and "horizontal" are generally perpendicular to each other and are independent of the orientation of the substrate in three-dimensional space. Additionally, "extending height" and "extending height" refer to a direction angled at least 45° from strictly horizontal. Also, with respect to field effect transistors, "height-extending," "height-extending," "horizontally-extending," and "horizontally-extending," etc., refer to the orientation of the transistor's channel length, which in operation passes current between the source / drain regions. With respect to bipolar junction transistors, "height-extending," "height-extending," "horizontally-extending," and "horizontally-extending," etc., refer to the orientation of the base length, which in operation passes current between the emitter and collector. In some embodiments, any height-extending components, features, and / or regions extend vertically or within 10° of vertical.

[0039] Additionally, "directly above," "directly below," and "directly below" require at least some lateral (i.e., horizontal) overlap of the two described areas / materials / components relative to one another. Additionally, the use of "above" without the "direct" preceding it only requires that the portion of a described area / material / component that is above another area / material / component be vertically outside of the other (i.e., regardless of whether there is lateral overlap of the two described areas / materials / components). Thus, the use of "below" and "below" without the "direct" preceding it only requires that the portion of a described area / material / component that is below / below another area / material / component be vertically inside of the other (i.e., regardless of whether there is lateral overlap of the two described areas / materials / components).

[0040] Any of the materials, regions, and structures described herein may be homogeneous or non-homogenous, and may be continuous or discontinuous across any overlying material. Where one or more exemplary compositions are given for any material, the material may include, consist essentially of, or consist of such one or more compositions. Additionally, unless otherwise indicated, each material may be formed using any suitable technique or techniques, existing or developed in the future, of which atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation are examples.

[0041] Furthermore, "thickness" alone (without a preceding directional adjective) is defined as the average linear distance through a given material or region perpendicular to the nearest surface of directly adjacent materials or regions of different composition. Furthermore, the various materials or regions described herein can be of substantially constant or variable thickness. In the case of variable thickness, thickness refers to the average thickness unless otherwise specified, and such materials or regions will have some minimum thickness and some maximum thickness since the thickness is not constant. As used herein, "different composition" requires only that two described materials or regions that may be in direct contact with each other are chemically and / or physically different, for example, when such materials or regions are not homogeneous. When two described materials or regions are not in direct contact with each other, "different composition" requires only that the nearest portions of the two described materials or regions are chemically and / or physically different, when such materials or regions are not homogeneous. As used herein, a material, region, or structure is "directly in contact with" another material, region, or structure if there is a contact where at least a portion of the described materials, regions, or structures are in physical contact with each other. In contrast, "above," "on," "adjacent," "along," and "in contact," without the preceding "directly," encompass structures where the described materials, regions, or structures are not in physical contact with each other as a result of an intervening material, region, or structure, in addition to being "directly in contact."

[0042] As used herein, regions-materials-components are "electrically coupled" to one another if, during normal operation, electrical current can flow continuously from one to the other, and does so primarily by the transfer of subatomic positive and / or negative charges when sufficient charge is generated. There may be another electronic component between the region-material-components and they may be electrically coupled. In contrast, when a region-material-component is said to be "directly electrically coupled," there is no intervening electronic component (e.g., no diode, transistor, resistor, transformer, switch, fuse, etc.) between the directly electrically coupled region-material-components.

[0043] Any of the conductive / conductor / conductive material compositions herein may be metallic materials and / or conductively doped semiconductive / semiconductive materials. A "metallic material" is any one or combination of an elemental metal, a mixture or alloy of two or more elemental metals, and one or more conductive metal compounds.

[0044] As used herein, "selective" with respect to etching, etching away, removing, depositing, forming, and / or forming, refers to the action of one described material over another described material such that the amount of the action is at least a 2:1 ratio, and selectively depositing, selectively growing, or selectively forming refers to the deposition, growth, or formation of one material over another described material or materials in a ratio of at least a 2:1 ratio, for at least the first 75 Angstroms of deposition, growth, or formation.

[0045] Unless otherwise stated, the use of "or" herein includes either or both.

[0046] [Conclusion] In some embodiments, a method for use in forming a memory array includes forming a substrate including a conductive layer, a first insulator layer above the conductive layer, a sacrificial material layer above the first insulator layer, and a second insulator layer above the sacrificial material layer. A stack including vertically alternating insulating and word line layers is formed above the second insulator layer. A channel material is formed through the insulating layer and the word line layer. A horizontally elongated trench is formed through the stack to the sacrificial material layer. The sacrificial material is etched through the horizontally elongated trench selectively to the material of the first insulator layer and selectively to the material of the second insulator layer. A lateral outer sidewall of the channel material is exposed in the sacrificial material layer. A conductive structure is formed directly on the lateral outer sidewall of the channel material in the sacrificial material layer. The conductive structure extends through the first insulator layer and electrically couples the channel material directly to the conductive layer.

[0047] In some embodiments, a method for use in forming a memory array includes forming a substrate including a conductive layer, a first insulator layer comprising an insulating metal oxide above the conductive layer, a silicon nitride layer above the first insulator layer, and a second insulator layer comprising an insulating metal oxide above the silicon nitride layer. A stack including vertically alternating insulating and word line layers is formed above the second insulator metal oxide layer. A channel material is formed in the conductive layer through the insulating and word line layers. A horizontally elongated trench is formed through the stack to the silicon nitride layer. The silicon nitride layer is wet etched through the horizontally elongated trench selectively to the insulating metal oxide of the first insulator layer and the insulating metal oxide of the second insulator layer. A lateral outer sidewall of the channel material is exposed in a sacrificial material layer. A conductive structure is formed directly on the lateral outer sidewall of the channel material in the sacrificial material layer. The conductive structure extends through the first insulator layer and electrically couples the channel material directly to the conductive layer.

[0048] In some embodiments, the memory array includes a vertical stack including a conductive layer, an insulator layer above the conductive layer, a conductor layer above the insulator layer, and vertically alternating insulating and word line layers above the conductor layer. The word line layers include gate regions of individual memory cells. Each of the gate regions includes a portion of a word line in each of the word line layers. A channel material extends heightwise through the insulating and word line layers. The individual memory cells include a memory structure between the individual gate regions and the channel material. The memory structure includes a charge blocking region laterally inward of each of the individual gate regions, a storage region laterally inward of each of the charge blocking regions, and an insulating charge passing material laterally inward of the individual storage regions. The conductive structure extends through the insulator layer and electrically couples the channel material directly to the conductive layer.

[0049] In some embodiments, the memory array includes a vertical stack including a conductive layer, an insulator layer above the conductive layer, a conductor layer above the insulator layer, and vertically alternating insulating and word line layers above the conductor layer. The word line layers include gate regions of individual memory cells. Each of the gate regions includes a portion of a word line in each of the word line layers. A channel material extends heightwise through the insulating layer and the word line layer. The individual memory cells include a memory structure between the individual gate regions and the channel material. The memory structure includes a charge blocking region laterally inward of each of the gate regions, a storage region laterally inward of each of the charge blocking regions, and an insulating charge passing material laterally inward of each of the storage regions. The conductive structure electrically couples the channel material directly to the conductive layer. A horizontally elongated insulator structure extends heightwise through the insulating layer and the word line layer. The horizontally elongated insulator structures laterally separate each of the word lines and each have a bottom that is above a bottom of the insulator layer.

[0050] In some embodiments, the memory array includes a vertical stack including a conductive layer, a first insulator layer above the conductive layer, a conductor layer above the insulator layer, a second insulator layer above the conductive layer, a conductively doped semiconductive material layer above the second insulator layer, and vertically alternating insulating and word line layers above the conductively doped semiconductive material layer. The word line layer includes gate regions of individual memory cells. Each of the gate regions includes a portion of a word line in each of the word line layers. A channel material extends in a height direction through the insulating layer and the word line layer. The individual memory cells include a memory structure between the individual gate regions and the channel material. The memory structure includes a charge blocking region laterally inward of each of the individual gate regions, a storage region laterally inward of each of the charge blocking regions, and an insulating charge passing material laterally inward of the individual storage regions. The conductive structure extends through the conductively doped semiconductive material layer, the second insulator layer, the conductor layer, and the first insulator layer. The conductive structure electrically couples the channel material directly to the conductive layer and includes a sidewall directly adjacent to the sidewall of the conductive layer.

Claims

1. 1. A method for use in forming a memory array, comprising: forming a substrate including a conductive layer, a first insulator layer above the conductive layer, a sacrificial material layer above the first insulator layer, a second insulator layer above the sacrificial material layer, a conductively doped semiconductive material layer above the second insulator layer, and a stack including vertically alternating insulating layers and word line layers above the conductively doped semiconductive material layer; forming a channel opening through the vertically alternating insulating and word line layers, the first insulator layer, the sacrificial material layer, the second insulator layer, and the conductively doped semiconductive material layer to the conductive layer; sequentially forming a storage material, a charge passing material, and a channel material within the channel opening; forming a horizontally elongated trench through the stack to the sacrificial material layer; etching sacrificial material of the sacrificial material layer through the horizontally elongated trenches selective to a material of the first insulator layer and selective to a material of the second insulator layer, and etching a portion of the storage material and the charge passing material in the sacrificial material layer through the horizontally elongated trenches selective to a material of the first insulator layer and selective to a material of the second insulator layer to expose outer lateral sidewalls of the channel material in the first insulator layer, in the sacrificial material layer, in the second insulator layer, in the conductively doped semiconductive material layer and above the conductively doped semiconductive material layer; forming a conductive structure in the first insulator layer, in the sacrificial material layer, in the second insulator layer, in the conductively doped semiconductive material layer, and directly contacting the laterally outer sidewalls of the channel material above the conductively doped semiconductive material layer, the conductive structure extending through the first insulator layer and electrically coupling the channel material directly to the conductive layer; The method includes:

2. The method of claim 1 , wherein the material of the first dielectric layer and the material of the second dielectric layer are of the same composition as one another.

3. the word line layer includes a sacrificial material; The method of claim 2 , wherein the method further comprises, after forming the conductive structures, replacing the sacrificial material of the wordline layer with a conductive wordline material.

4. forming a sacrificial sidewall liner in said horizontally elongated trench prior to said etching; removing the sacrificial sidewall liner after the etching; 4. The method of claim 3, comprising:

5. The method of claim 4 comprising removing the sacrificial sidewall liner after forming the conductive structure.

6. A vertical stack, A first conductive layer; and a first insulator layer over the conductive layer; and a layer of conductive material over the first layer of insulator; a second conductive layer over the layer of conductive material; and vertically alternating insulating and word line layers over the second conductive layer; A vertical stack including: a channel material extending heightwise through the vertically alternating insulating and word line layers; a horizontally elongated insulator structure passing through said vertical stack to the conductive material of said conductive material layer within a horizontally elongated trench, said horizontally elongated insulator structure horizontally separating each one of said word line layers; a conductive structure extending vertically through the conductive material of the conductive material layer and through the solid material of the first insulator layer into the first conductive layer, directly contacting a laterally outer sidewall of the channel material, directly contacting a sidewall of the conductive material of the first conductive layer within the first conductive layer, and directly electrically coupling the channel material to the first conductive layer; 1. A memory array including:

7. The memory array of claim 6 wherein said first insulator layer comprises an insulating metal oxide.

8. 7. The memory array of claim 6, wherein said horizontally elongated trenches have respective bottoms that are above a bottom of said first insulating layer.

9. 9. The memory array of claim 8, wherein a bottom of said horizontally elongated trench is above a top of said first insulating layer.

10. 9. The memory array of claim 8 wherein a bottom of said horizontally elongated trench is below a top of said layer of conductive material.

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