Ceramic electronic components and their manufacturing method

Abstract

To provide a ceramic electronic component and a method of manufacturing the same capable of suppressing insulation deterioration while suppressing generation of defects of an inner structure.SOLUTION: A ceramic electronic component has a lamination structure in which a first dielectric layer containing ceramic as a main component, a first internal electrode layer, a second dielectric layer containing ceramic as a main component, and a second internal electrode layer are laminated in this order, and which lamination structure has a substantially rectangular parallelepiped shape, and is formed so that the first internal electrode layer is exposed at a first end surface having a substantially rectangular parallelepiped shape, and the second internal electrode layer is exposed at a second end surface having a substantially rectangular parallelepiped shape. The first dielectric layer comprises a thin layer part formed at an end part on the first end surface side of the first internal electrode layer so as to be thinner than a central part in an opposing direction of the first and second end surfaces. The second dielectric layer comprises a thick layer part formed at the end part on the first end surface side of the first internal electrode layer so as to be thicker than the central part in an opposing direction of the first end surface and the second end surface.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] In recent years, with the miniaturization and high performance of electronic devices, there has been an increasing demand for miniaturization and high capacitance of multilayer ceramic capacitors used in electronic devices. In order to increase the capacitance while keeping the size of the multilayer ceramic capacitor small, it is effective to make the dielectric layers and internal electrode layers of the multilayer ceramic capacitor thinner and increase the number of layers.

[0003] As the dielectric layers become thinner, the electric field strength in each dielectric layer increases, which may cause insulation deterioration in the dielectric layers at low voltages. As a result, a decrease in production yield is likely to occur. In particular, the electric field is likely to concentrate at the ends of the internal electrodes, causing deterioration. To solve this problem, a method has been proposed for obtaining a capacitor with high withstand voltage and good production yield by locally thickening the dielectric layer located at the ends of the internal electrodes (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-159140 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, as the number of layers increases, local thickness accumulates, which distorts the internal layer structure and makes it easier for delamination and cracks to occur due to insufficient adhesion. In addition, as thickness differences in the dielectric layers accumulate with layering, height differences occur in the thickness dimension of the final chip shape, which may make it difficult to increase the number of layers.

[0006] The present invention has been made in consideration of the above-mentioned problems, and has an object to provide a ceramic electronic component that can suppress the occurrence of defects in the internal structure while suppressing insulation deterioration, and a manufacturing method thereof. [Means for solving the problem]

[0007] The ceramic electronic component of the present invention has a laminated structure in which a first dielectric layer mainly composed of ceramic, a first internal electrode layer, a second dielectric layer mainly composed of ceramic, and a second internal electrode layer are laminated in this order, have a substantially rectangular parallelepiped shape, the first internal electrode layer is exposed at a first end face of the substantially rectangular parallelepiped shape, and the second internal electrode layer is exposed at a second end face of the substantially rectangular parallelepiped shape, the first dielectric layer has a thin layer portion formed at an end of the first internal electrode layer on the first end face side so as to be thinner than a central portion in the direction in which the first end face and the second end face face each other, and the second dielectric layer has a thick layer portion formed at an end of the first internal electrode layer on the first end face side so as to be thicker than a central portion in the direction in which the first end face and the second end face face each other.

[0008] In the ceramic electronic component, an overlap length between the thin layer portion and the thick layer portion in a direction in which the first end face and the second end face face each other may be 2 μm or more.

[0009] In the ceramic electronic component, an overlap length between the thin layer portion and the thick layer portion in a direction in which the first end face and the second end face face each other may be 80 μm or less.

[0010] In the above ceramic electronic component, in the first dielectric layer in which the thin layer portion is formed, the thin layer portion may be thinner by 0.05 μm or more and 0.3 μm or less than a central portion in a direction in which the first end face and the second end face oppose each other.

[0011] In the above ceramic electronic component, in the second dielectric layer in which the thick layer portion is formed, the thick layer portion may be 0.05 μm or more and 0.3 μm or less thicker than a central portion in a direction in which the first end face and the second end face face each other.

[0012] A method for producing a ceramic electronic component according to the present invention includes a first step of arranging a first pattern of a metal conductive paste on a green sheet containing main component ceramic particles; a second step of arranging a second pattern containing main component ceramic particles in an area of ​​the green sheet where the metal conductive paste is not arranged; a third step of stacking a plurality of lamination units obtained in the second step such that the arrangement positions of the first patterns are alternately shifted to obtain a ceramic laminate and exposing the first pattern alternately on a first end face and a second end face of the ceramic laminate; and a fourth step of firing the ceramic laminate obtained in the third step, wherein in the ceramic laminate before firing, at least one of the green sheets has a thin layer portion that is formed at an end portion on the first end face side of the first pattern and is thinner than a central portion in the direction in which the first end face and the second end face face each other, and the other green sheet adjacent to the first green sheet in the stacking direction has a thick layer portion that is formed at an end portion on the first end face side of the first pattern and is thicker than a central portion in the direction in which the first end face and the second end face face each other.

[0013] In the above-described method for manufacturing a ceramic electronic component, after the second step and before the third step, a third pattern of metal conductive paste may be arranged so as to cover the second pattern and to cover a portion of the first pattern, and after the third step and before the fourth step, the ceramic laminate obtained in the third step may be pressed in a stacking direction to form the thin layer portion and the thick layer portion. Effect of the Invention

[0014] According to the present invention, it is possible to provide a ceramic electronic component that can suppress the occurrence of defects in the internal structure while suppressing deterioration of insulation, and a method for manufacturing the same. [Brief description of the drawings]

[0015] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Diagram 2] 2 is a cross-sectional view taken along line AA in FIG. 1. [Diagram 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] 1(a) is an enlarged view of a cross section of a side margin, and (b) is an enlarged view of a cross section of an end margin. [Diagram 5] FIG. 2 is an enlarged view with hatching omitted. [Figure 6] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 7] 1(a) and (b) are diagrams illustrating the lamination process. [Figure 8] 1(a) to 1(d) are diagrams illustrating a lamination process. [Figure 9] FIG. 1 is a diagram illustrating a lamination process. [Figure 10] FIG. 1 is a diagram illustrating a lamination process. [Figure 11] FIG. 2 is a schematic SEM photograph of a cross section of the multilayer ceramic capacitor of Example 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment will be described with reference to the drawings.

[0017] (Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the upper and lower faces in the lamination direction are referred to as side faces. The external electrodes 20a, 20b extend on the upper, lower and two side faces in the lamination direction of the laminated chip 10. However, the external electrodes 20a, 20b are spaced apart from each other. In FIG. 1, the X-axis direction (first direction) is the length direction of the laminated chip 10, the direction in which the two end faces of the laminated chip 10 face each other, and the direction in which the external electrodes 20a and 20b face each other. The Y-axis direction (second direction) is the width direction of an internal electrode layer, which will be described later. The Z-axis direction is the stacking direction, and the X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.

[0018] The laminated chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers containing a base metal material are alternately laminated. The edges of the internal electrode layers are alternately exposed to a first end face on which the external electrode 20a of the laminated chip 10 is provided and a second end face on which the external electrode 20b is provided. As a result, each internal electrode layer is alternately conductive to the external electrode 20a and the external electrode 20b. As a result, the laminated ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are laminated via the internal electrode layers. The internal electrode layer connected to the external electrode 20a is referred to as the internal electrode layer 12a (first internal electrode layer). The internal electrode layer connected to the external electrode 20b is referred to as the internal electrode layer 12b (second internal electrode layer). In the laminated structure of the dielectric layers 11 and the internal electrode layers, the internal electrode layers are arranged on the outermost layers in the lamination direction, and the upper and lower surfaces of the laminate are covered with a cover layer 13. The cover layer 13 is mainly made of a ceramic material. For example, the material of the cover layer 13 is made of the same main ceramic material as that of the dielectric layer 11.

[0019] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0020] The internal electrode layers 12a and 12b are mainly composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). Noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals, may also be used for the internal electrode layers 12a and 12b. The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. The perovskite structure is an ABO3 structure that deviates from the stoichiometric composition. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaTiO3 (strontium titanate) which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≦x≦1, 0≦y≦1, 0≦z≦1), etc. can be used.

[0021] 2, a region where the internal electrode layer 12a connected to the external electrode 20a and the internal electrode layer 12b connected to the external electrode 20b face each other is a region that generates capacitance in the multilayer ceramic capacitor 100. Therefore, this region that generates capacitance is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers connected to different external electrodes face each other.

[0022] The region where internal electrode layers connected to the same external electrode face each other without an internal electrode layer connected to a different external electrode being interposed therebetween is called an end margin. The end margin 15 is a region where the internal electrode layers 12a connected to the external electrode 20a face each other without an internal electrode layer 12b connected to the external electrode 20b being interposed therebetween. The other end margin 15 is a region where the internal electrode layers 12b connected to the external electrode 20b face each other without an internal electrode layer 12a connected to the external electrode 20a being interposed therebetween. The end margin is a region where no capacitance is generated.

[0023] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12a, 12b are referred to as side margins 16. That is, the side margins 16 are regions provided to cover the ends of the multiple internal electrode layers 12a, 12b laminated in the above-mentioned laminated structure that extend to the two side surfaces. The side margins 16 are also regions that do not generate electrical capacitance.

[0024] 4(a) is an enlarged view of a cross section of the side margin 16. The side margin 16 has a structure in which the dielectric layers 11 and the reverse pattern layers 17 are alternately laminated in the lamination direction of the dielectric layers 11 and the internal electrode layers 12a, 12b in the capacitive region 14. The dielectric layers 11 in the capacitive region 14 and the dielectric layers 11 in the side margin 16 are continuous layers. With this configuration, the step between the capacitive region 14 and the side margin 16 is suppressed.

[0025] FIG. 4(b) is an enlarged view of the cross section of the end margin 15. In comparison with the side margin 16, in the end margin 15, the internal electrode layer 12b of every other one of the multiple stacked internal electrode layers 12a, 12b extends to the end face of the end margin 15. Or, in the multiple stacked internal electrode layers 12a, 12b, the internal electrode layer 12a extends to the end face of the end margin 15 of every other one of the multiple stacked internal electrode layers 12a, 12b. Also, in the layer in which the internal electrode layers 12a, 12b extend to the end face of the end margin 15, the reverse pattern layer 17 is not stacked. Each dielectric layer 11 of the capacitance region 14 and each dielectric layer 11 of the end margin 15 are layers that are continuous with each other. With this configuration, the step between the capacitance region 14 and the end margin 15 is suppressed.

[0026] In recent years, with the miniaturization and high performance of electronic devices, there is an increasing demand for miniaturization and high capacity of the multilayer ceramic capacitor 100 used in the electronic devices. In order to increase the capacitance while suppressing the size of the multilayer ceramic capacitor 100, it is effective to thin the dielectric layers 11 and the internal electrode layers 12a, 12b of the multilayer ceramic capacitor 100 and increase the number of layers. For example, the average thickness per layer of the internal electrode layers 12a, 12b is set to 0.5 μm or less. For example, the average thickness per layer of the dielectric layer 11 is set to 0.5 μm or less. The total number of layers of the internal electrode layers 12a, 12b is set to, for example, 100 to 500.

[0027] As the dielectric layers 11 become thinner, the electric field strength applied to each dielectric layer 11 increases, and this may cause insulation deterioration in the dielectric layers 11 at low voltages. As a result, the production yield of the multilayer ceramic capacitor 100 is likely to decrease. In particular, the electric field is likely to concentrate at the ends of the internal electrode layers 12a and 12b, causing deterioration. For example, the electric field is likely to concentrate on the dielectric layer 11 at the end of the internal electrode layer 12a on the external electrode 20b side. In addition, the electric field is likely to concentrate on the dielectric layer 11 at the end of the internal electrode layer 12b on the external electrode 20a side. Therefore, it is considered to locally thicken the dielectric layer 11 at the end of the internal electrode layer 12a on the external electrode 20b side and locally thicken the dielectric layer 11 at the end of the internal electrode layer 12b on the external electrode 20a side to improve the voltage resistance.

[0028] However, as the number of dielectric layers 11 increases, local thickness accumulates. As a result, the internal layer structure of the laminated chip 10 becomes distorted, and delamination, cracks, and the like are likely to occur due to insufficient adhesion. In addition, as thickness differences in the dielectric layers 11 accumulate due to lamination, height differences occur in the thickness dimension of the final chip shape, and there is a risk that the number of layers cannot be increased.

[0029] Therefore, the multilayer ceramic capacitor 100 according to this embodiment has a structure that can suppress the occurrence of defects in the internal structure while suppressing insulation deterioration.

[0030] FIG. 5 is an enlarged view of FIG. 2 with hatching omitted. As illustrated in FIG. 5, the dielectric layer 11 includes a thin layer portion 11a formed locally thin at the end of the internal electrode layer 12a on the external electrode 20b side (a predetermined range from the end on the external electrode 20b side to the external electrode 20a side). The next dielectric layer 11 in the Z-axis direction after the dielectric layer 11 includes a thick layer portion 11b formed locally thick at the end of the internal electrode layer 12a on the external electrode 20b side. The next dielectric layer 11 in the lamination direction after the dielectric layer 11 includes a thin layer portion 11a formed locally thin at the end of the internal electrode layer 12a on the external electrode 20b side. In this way, the thin layer portions 11a and the thick layer portions 11b are alternately laminated with the internal electrode layer sandwiched therebetween at the end of the internal electrode layer 12a on the external electrode 20b side. The region where the thin layer portion 11a and the thick layer portion 11b are laminated on the external electrode 20b side is referred to as a thickness change region 30b.

[0031] The dielectric layer 11 also includes a locally thinned thin layer portion 11a at the end of the internal electrode layer 12b on the external electrode 20a side (a predetermined range from the end on the external electrode 20a side to the external electrode 20b side). The next dielectric layer 11 after the dielectric layer 11 includes a locally thickened thick layer portion 11b at the end of the internal electrode layer 12b on the external electrode 20a side. The next dielectric layer 11 after the dielectric layer 11 includes a locally thinned thin layer portion 11a at the end of the internal electrode layer 12b on the external electrode 20a side. In this way, at the end of the internal electrode layer 12b on the external electrode 20a side, the thin layer portions 11a and the thick layer portions 11b are alternately laminated with the internal electrode layer sandwiched between them. The region where the thin layer portions 11a and the thick layer portions 11b are laminated on the external electrode 20a side is referred to as a thickness change region 30a.

[0032] According to this embodiment, the dielectric layer 11 is locally thickened and a thick layer portion 11b is arranged at the end of the internal electrode layer 12a on the external electrode 20b side where electric field concentration is likely to occur, thereby improving the voltage resistance. In the two adjacent dielectric layers 11, the thin layer portion 11a is arranged next to the thick layer portion 11b, thereby suppressing thickness accumulation. In addition, the dielectric layer 11 is locally thickened and a thick layer portion 11b is arranged at the end of the internal electrode layer 12b on the external electrode 20a side where electric field concentration is likely to occur, thereby improving the voltage resistance. In the two adjacent dielectric layers 11, the thin layer portion 11a is arranged next to the thick layer portion 11b, thereby suppressing thickness accumulation. From the above, it is possible to suppress the occurrence of defects in the internal structure while suppressing insulation deterioration.

[0033] If the overlap between the thin layer portion 11a and the thick layer portion 11b in the X-axis direction is short, the laminated structure may bend during the manufacturing process of the multilayer ceramic capacitor 100, resulting in a decrease in the withstand voltage. Therefore, it is preferable to set a lower limit for the overlap length between the thin layer portion 11a and the thick layer portion 11b in the X-axis direction. In this embodiment, the overlap length between the thin layer portion 11a and the thick layer portion 11b in the X-axis direction is preferably 2 μm or more, and more preferably 20 μm or more.

[0034] On the other hand, if the overlap between the thin layer portion 11a and the thick layer portion 11b in the X-axis direction is long, the thin layer portion 11a may become long and the voltage resistance may decrease. Therefore, it is preferable to set an upper limit on the overlap length between the thin layer portion 11a and the thick layer portion 11b in the X-axis direction. In this embodiment, the overlap length between the thin layer portion 11a and the thick layer portion 11b in the X-axis direction is preferably 80 μm or less, and more preferably 50 μm or less.

[0035] In the X-axis direction, each of the thin layer portions 11a and each of the thick layer portions 11b has a length of about 1 / 400 to 1 / 10 of the entire dielectric layer 11 in the X-axis direction. Alternatively, in the X-axis direction, each of the thin layer portions 11a and each of the thick layer portions 11b has a length of about 1 μm to 100 μm.

[0036] The thin layer portion 11a is preferably 0.05 μm or more thinner, and more preferably 0.1 μm or more thinner, than the central portion of the dielectric layer 11 in the X-axis direction. Also, the thin layer portion 11a is preferably 0.3 μm or less thinner, and more preferably 0.2 μm or less thinner, than the central portion of the dielectric layer 11 in the direction in which the external electrodes 20a and 20b face each other.

[0037] The thick portion 11b is preferably 0.05 μm or more thicker than the central portion of the dielectric layer 11 in the X-axis direction, and more preferably 0.1 μm or more thicker. Also, the thick portion 11b is preferably 0.3 μm or less thicker than the central portion of the dielectric layer 11 in the direction in which the external electrodes 20a and 20b face each other, and more preferably 0.2 μm or less thicker.

[0038] In the thickness change regions 30a and 30b, the thin layer portions 11a and the thick layer portions 11b may not be formed in all of the dielectric layers 11. In the thickness change regions 30a and 30b, some of the dielectric layers 11 may have the same thickness as the central portion in the direction in which the external electrodes 20a and 20b face each other.

[0039] In the thickness changing regions 30a and 30b, the layers may be stacked in the order of thin layer portion 11a, thick layer portion 11b, thick layer portion 11b, and thin layer portion 11a, or in the order of thick layer portion 11b, thin layer portion 11a, thin layer portion 11a, and thick layer portion 11b. In the X-axis direction, all of the thin layer portions 11a and thick layer portions 11b do not have to have the same length.

[0040] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG 6 is a diagram illustrating a flow of the method for manufacturing the multilayer ceramic capacitor 100.

[0041] (Raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The dielectric material includes the main component ceramic of the dielectric layer 11. The A-site elements and B-site elements included in the dielectric layer 11 are usually included in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. Various methods have been known so far as a method for synthesizing the main component ceramic of the dielectric layer 11, such as a solid-phase method, a sol-gel method, a hydrothermal method, and the like. In this embodiment, any of these methods can be adopted.

[0042] To the obtained ceramic powder, a predetermined additive compound is added according to the purpose. The additive compound includes oxides of Zr (zirconium), Ca (calcium), Sr (strontium), Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), and rare earth elements, as well as oxides or glasses of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium), and Si.

[0043] Next, a margin material for forming the end margin 15 and the side margin 16 is prepared. The margin material includes the main component ceramic of the end margin 15 and the side margin 16. For example, BaTiO3 powder is prepared as the main component ceramic. The BaTiO3 powder can be prepared by the same procedure as the dielectric material. A predetermined additive compound is added to the obtained BaTiO3 powder according to the purpose. The additive compound may be an oxide of Zr, Ca, Sr, Mg, Mn, V, Cr, or a rare earth element, or an oxide or glass of Co, Ni, Li, B, Na, K, or Si.

[0044] Next, a cover material for forming the cover layer 13 is prepared. The cover material contains the main component ceramic of the cover layer 13. For example, BaTiO3 powder is prepared as the main component ceramic. The BaTiO3 powder can be prepared by the same procedure as the dielectric material. A predetermined additive compound is added to the obtained BaTiO3 powder according to the purpose. Examples of the additive compound include oxides of Zr, Ca, Sr, Mg, Mn, V, Cr, and rare earth elements, as well as oxides or glasses of Co, Ni, Li, B, Na, K, and Si. The above-mentioned margin material may be used as the cover material.

[0045] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the dielectric material obtained in the raw powder preparation process and wet mixed. The obtained slurry is used to coat a strip-shaped dielectric green sheet 51 having a thickness of, for example, 0.8 μm or less on a substrate by, for example, a die coater method or a doctor blade method, and then dried.

[0046] 7(a), a metal conductive paste for forming an internal electrode containing an organic binder is printed on the surface of the dielectric green sheet 51 by screen printing, gravure printing, or the like to arrange a first pattern 52 for an internal electrode layer. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 11.

[0047] Next, a binder such as an ethyl cellulose-based binder and an organic solvent such as a terpineol-based solvent are added to the margin material obtained in the raw powder preparation process, and the mixture is kneaded in a roll mill to obtain a margin paste for the reverse pattern layer 17. As illustrated in Fig. 7(a), the margin paste is printed in the peripheral area on the dielectric green sheet 51 where the first pattern 52 is not printed, thereby disposing the second pattern 53 and filling the step with the first pattern 52. In this case, the thickness of the second pattern 53 is set to be equal to or less than the thickness of the first pattern 52.

[0048] Fig. 8(a) is a side view illustrating a state in which a first pattern 52 is arranged on the surface of a dielectric green sheet 51. Fig. 8(b) is a side view illustrating a state in which a second pattern 53 is arranged in a peripheral area on the dielectric green sheet 51 where the first pattern 52 is not printed.

[0049] 8(c), a third pattern 54 is arranged by printing a margin paste so as to cover the second pattern 53 and also to cover a part of the first pattern 52. For example, the thickness of the third pattern 54 is set to be 0.05 μm or more and ½ or less of the thickness of the second pattern 53.

[0050] 7(b), the dielectric green sheets 51, the first pattern 52 and the second pattern 53 are laminated so that the internal electrode layers and the dielectric layers 11 are alternated and the edges of the internal electrode layers are alternately exposed at both end faces in the length direction of the dielectric layers 11 and alternately drawn out to a pair of external electrodes 20a, 20b having different polarities. For example, the number of laminated dielectric green sheets 51 is set to 100 to 500.

[0051] Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the cover material obtained in the raw powder preparation process and wet mixed. The obtained slurry is used to coat a strip-shaped cover sheet 55 having a thickness of, for example, 10 μm or less on a substrate by, for example, a die coater method or a doctor blade method, and then dried. As illustrated in FIG. 9, a predetermined number of cover sheets 55 (for example, 2 to 10 layers) are laminated on the top and bottom of the laminated dielectric green sheets 51, thermocompression bonded, and cut to a predetermined chip size (for example, 1.0 mm x 0.5 mm). This results in a ceramic laminate. Note that a predetermined number of cover sheets 55 may be laminated and compressed, and then attached to the top and bottom of the laminated dielectric green sheets 51.

[0052] Fig. 8(d) is a diagram illustrating a state in which a plurality of dielectric green sheets 51 are stacked and pressure-bonded. As illustrated in Fig. 8(d), a step is generated in the second pattern 53 at a portion where the third pattern 54 covers the second pattern 53 due to pressure bonding. As a result, a portion where the dielectric green sheet 51 is thin and a portion where the dielectric green sheet 51 is thicker due to the addition of the thickness of the third pattern 54 are stacked alternately.

[0053] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in a N2 atmosphere, after which Ni paste, which would become the base for the external electrodes 20a and 20b, was applied thereto by a dipping method, and the ceramic laminate was then subjected to a dipping treatment in a nitrogen atmosphere under an oxygen partial pressure of 10 -5 ~10 -8 The laminated ceramic capacitor 100 is thus obtained, and is then fired in a reducing atmosphere of 1 atm at 1100 to 1300° C. for 10 minutes to 2 hours.

[0054] (Reoxidation treatment process) After that, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0055] (Plating process) Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, Sn, etc. by plating.

[0056] According to the manufacturing method of this embodiment, in the portion where the first pattern 52 becomes a step, the portion where the dielectric green sheet 51 becomes thinner becomes the thin layer portion 11a, and the portion where the third pattern 54 is added to the dielectric green sheet 51 becomes the thick layer portion 11b. In addition, the thin layer portion 11a and the thick layer portion 11b are laminated. Furthermore, when viewed from the lamination direction, the thin layer portion 11a and the thick layer portion 11b overlap each other in the direction in which the external electrode 20a and the external electrode 20b face each other. Therefore, the thick layer portion 11b, in which the dielectric layer 11 is locally formed thick, is arranged at the end of the internal electrode layer 12a on the external electrode 20b side, where electric field concentration is likely to occur, thereby improving the voltage resistance. In the two adjacent dielectric layers 11, the thin layer portion 11a is arranged next to the thick layer portion 11b, thereby suppressing the accumulation of thickness. Furthermore, the dielectric layer 11 is locally thickened to form thick layer portion 11b at the end of the internal electrode layer 12b on the external electrode 20a side where electric field concentration is likely to occur, improving voltage resistance. In two adjacent dielectric layers 11, the thin layer portion 11a is disposed next to the thick layer portion 11b, suppressing thickness accumulation. As a result, it is possible to suppress insulation deterioration while suppressing defects in the internal structure.

[0057] The region corresponding to the side margin 16 may be attached or applied to the side surface of the laminated structure. Specifically, as illustrated in Fig. 10, a laminated portion is obtained by alternately laminating dielectric green sheets 51 and first patterns 52 having the same width as the dielectric green sheets 51. Next, a sheet formed with a reverse pattern paste may be attached to the side surface of the laminated portion, or a fourth pattern 56 obtained by applying the reverse pattern paste may be formed to form the region corresponding to the side margin 16.

[0058] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may be used. EXAMPLES

[0059] Next, a multilayer ceramic capacitor according to the embodiment was fabricated, and its characteristics were examined.

[0060] (Examples 1 to 4) Additives were added to barium titanate powder, and the mixture was thoroughly wet-mixed and pulverized in a ball mill to obtain a dielectric material.Additives were added to barium titanate powder, and the mixture was thoroughly wet-mixed and pulverized in a ball mill to obtain a margin material.Additives were added to barium titanate powder, and the mixture was thoroughly wet-mixed and pulverized in a ball mill to obtain a cover material.

[0061] A butyral-based organic binder and toluene and ethyl alcohol as solvents were added to the dielectric material, and a dielectric green sheet 51 was produced by a doctor blade method. A first pattern 52 of metal conductive paste was printed on the obtained dielectric green sheet 51. A second pattern 53 was arranged on the dielectric green sheet 51 by printing a margin material in the peripheral area where the first pattern 52 was not printed. Next, a third pattern 54 was arranged by printing a margin paste so as to cover the second pattern 53 and also cover a part of the first pattern 52.

[0062] Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the cover material obtained in the raw powder preparation process and wet mixed. Using the obtained slurry, a cover sheet 55 is applied onto a substrate and dried. A predetermined number of cover sheets 55 are laminated on the top and bottom of the laminated dielectric green sheets 51, thermocompression bonded, and cut into a predetermined shape.

[0063] (Comparative Example) In the comparative example, no third pattern 54 was provided. The other conditions were the same as those in the first to fourth embodiments.

[0064] For Examples 1 to 4 and the Comparative Example, SEM photographs of the cross sections of the obtained multilayer ceramic capacitors were taken, and the size of each part was measured. In all of Examples 1 to 4 and the Comparative Example, the thickness of the central part of the dielectric layer 11 in the direction in which the external electrode 20a and the external electrode 20b oppose each other was 0.8 μm.

[0065] Fig. 11 is a schematic SEM photograph of a cross section of the multilayer ceramic capacitor of Example 1. As shown in Fig. 11, in Example 1, thin layer portions 11a with locally small thicknesses were formed in parts of the dielectric layer 11, and thick layer portions 11b with locally large thicknesses were formed. Furthermore, the thin layer portions 11a and the thick layer portions 11b were alternately laminated.

[0066] The thickness of the thin layer portion 11a was 0.6 μm in each of Examples 1 to 4. The thickness of the thick layer portion 11b was 1.0 μm in each of Examples 1 to 4. In the comparative example, neither the thin layer portion 11a nor the thick layer portion 11b was formed.

[0067] In Example 1, the length of the thickness change regions 30a, 30b in the direction in which the external electrode 20a and the external electrode 20b face each other was 2 μm. In Example 2, the length of the thickness change regions 30a, 30b was 20 μm. In Example 3, the length of the thickness change regions 30a, 30b was 50 μm. In Example 4, the length of the thickness change regions 30a, 30b was 80 μm. In the comparative example, the thickness change regions 30a, 30b were not formed.

[0068] (Voltage Test) A withstand voltage test was performed on the multilayer ceramic capacitors 100 obtained in Examples 1 to 4 and the comparative example. In the withstand voltage test, the applied voltage was increased until the multilayer ceramic capacitor 100 was short-circuited, and the dielectric breakdown voltage at this time was measured and defined as the withstand voltage. The results are shown in Table 1. [Table 1]

[0069] In the comparative example, the withstand voltage was 40V. Thus, since the thickness change regions 30a and 30b were not formed, a high withstand voltage was not obtained. In contrast, in Example 1, the withstand voltage was 100V. In Example 2, the withstand voltage was 120V. In Example 3, the withstand voltage was 110V. In Example 4, the withstand voltage was 60V. This is considered to be because the withstand voltage was increased by forming the thickness change regions 30a and 30b. Furthermore, no structural defects such as delamination or cracks were confirmed in Examples 1 to 4. From the above, it was found that by forming the thickness change regions 30a and 30b, it is possible to suppress the occurrence of defects in the internal structure while suppressing insulation deterioration.

[0070] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0071] 10 Stacked Chip 11 Dielectric layer 11a Thin layer part 11b Thick layer 12a,12b Internal electrode layer 13 Cover Layer 14 Capacity area 15 End Margin 16 Side Margin 17 Reverse Pattern Layer 20a,20b external electrode 30a, 30b Thickness change area 51 Dielectric green sheet 52 First Pattern 53 Second Pattern 54 Third Pattern 55 Cover Sheet 100 Multilayer ceramic capacitors

Claims

1. a laminated structure in which a first dielectric layer mainly made of ceramic, a first internal electrode layer, a second dielectric layer mainly made of ceramic, and a second internal electrode layer are laminated in this order, and have a substantially rectangular parallelepiped shape, the first internal electrode layer being exposed at a first end face of the substantially rectangular parallelepiped shape, and the second internal electrode layer being exposed at a second end face of the substantially rectangular parallelepiped shape; the first dielectric layer has a thin layer portion formed at the end of the first end face side of the first internal electrode layer thinner than a central portion in the direction in which the first end face and the second end face face oppose each other, by having a step at an end of the second internal electrode layer on the first end face side shifted in the stacking direction; and the second dielectric layer has a thick layer portion formed at the end of the first end face side of the first internal electrode layer thicker than a central portion in the direction in which the first end face and the second end face face oppose each other, by having a step at an end of the second internal electrode layer on the first end face side shifted in the stacking direction. a length of overlap between the thin layer portion and the thick layer portion in a direction in which the first end face and the second end face face each other is not less than 2 μm and not more than 80 μm.

2. 2. The ceramic electronic component according to claim 1, wherein in the first dielectric layer in which the thin layer portion is formed, the thin layer portion is thinner by 0.05 μm or more and 0.3 μm or less than a central portion in a direction in which the first end face and the second end face face each other.

3. 3. The ceramic electronic component according to claim 1, wherein in the second dielectric layer in which the thick layer portion is formed, the thick layer portion is 0.05 μm or more and 0.3 μm or less thicker than a central portion in a direction in which the first end face and the second end face face each other.

4. A first step of disposing a first pattern of a metal conductive paste on a green sheet including ceramic particles as a main component; a second step of disposing a second pattern including main component ceramic particles on an area on the green sheet where the metal conductive paste is not disposed; a third step of stacking a plurality of the laminate units obtained in the second step such that the arrangement positions of the first patterns are alternately shifted to obtain a ceramic laminate, and exposing the first patterns alternately on a first end surface and a second end surface of the ceramic laminate; A fourth step of firing the ceramic laminate obtained in the third step, a step in which an end portion of the first end face side of another first pattern adjacent to the first pattern in the stacking direction via the green sheet has a step that is shifted in the stacking direction, thereby providing a thin layer portion at the end portion of the first end face side of the first pattern that is thinner than a central portion in the direction in which the first end face and the second end face face face oppose each other; and a thick layer portion at the end portion of the first end face side of the first pattern that is thicker than a central portion in the direction in which the first end face and the second end face face oppose each other, wherein the other green sheet adjacent to the green sheet in the stacking direction has a step in which the end portion of the first end face side of the other first pattern has a step that is shifted in the stacking direction, thereby providing a thick layer portion at the end portion of the first end face side of the first pattern that is thicker than a central portion in the direction in which the first end face and the second end face face oppose each other.

5. After the second step and before the third step, a third pattern containing main component ceramic particles is disposed so as to cover the second pattern and to cover a part of the first pattern; The thickness of the third pattern is 0.05 μm or more and is ½ or less of the thickness of the second pattern, 5. The method for producing a ceramic electronic component according to claim 4, wherein the ceramic laminate obtained in the third step is pressure-bonded in a stacking direction after the third step and before the fourth step, thereby forming the thin layer portion and the thick layer portion.

Images