Semiconductor Device

Abstract

To provide a semiconductor device that suppresses variations in an electric characteristic of a transistor including an oxide semiconductor film.SOLUTION: A transistor 100 includes a first gate electrode 104, a first insulator film 106 on the first gate electrode, an oxide semiconductor film 108 on the first insulator film, a source electrode 112a electrically connected to the oxide semiconductor film, a drain electrode 112b electrically connected to the oxide semiconductor film, second insulator films 114, 116 on the oxide semiconductor film, a second gate electrode (oxide semiconductor film) 120b on the second insulator films, and a third insulator film 118 on the second gate electrode. The oxide semiconductor film contains In, M (M is Al, Ga, Y, or Sn), and Zn. The oxide semiconductor film 120b has a region containing atoms of In, the number of which is smaller than that of the oxide semiconductor film 108.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device including an oxide semiconductor film. Regarding the law.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. process, machine, manufacture, or composition of matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field-effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that makes up the field-effect transistor (FET) or thin-film transistor (TFT) is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Semiconductor materials such as silicon are widely known, but oxide semiconductors are also attracting attention. It is being watched.

[0005] The present invention provides a highly reliable semiconductor by imparting stable electrical characteristics to a transistor using an oxide semiconductor. To obtain the device, oxide semiconductor films with different compositions were stacked to place more In on the channel side. An oxide semiconductor film containing a large amount of stabilizers such as Ga was used on the back channel side. A semiconductor device using a compound semiconductor film has been disclosed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2013-175715 A Summary of the Invention [Problem to be solved by the invention]

[0007] When an oxide semiconductor film containing a large amount of In is used, the energy band gap (Eg) is small. In this case, the oxide semiconductor with a large Eg may be used. Oxide semiconductors with smaller Eg than conductive films (for example, Eg between 3.0 eV and 3.5 eV) The conductive film is more susceptible to light. For example, when a negative voltage is applied during light irradiation, the In the photo-induced stress test (photo-induced GBT stress test), the oxide semiconductor film with a small Eg was In a transistor having such a structure, the reliability may decrease.

[0008] The light negative GBT stress test is a type of accelerated test, and is performed under light exposure for a long period of time. The change in transistor characteristics caused by the use of the , the change in the threshold voltage of the transistor before and after the negative GBT light stress test (ΔVth ) is an important indicator for investigating reliability. Before and after the light negative GBT stress test, The smaller the change in threshold voltage (ΔVth), the higher the reliability.

[0009] In view of the above problems, in one embodiment of the present invention, a transistor including an oxide semiconductor film is One of the objectives of the present invention is to suppress the fluctuation of electrical characteristics and to improve reliability. In particular, in a transistor having an oxide semiconductor film containing a large amount of In, the electrical characteristics of the transistor tend to change. Another object of the present invention is to suppress the above-mentioned problems and to improve reliability. In the present invention, one of the objects is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device. Another object of the present invention is to provide a novel display device. This will be one of the challenges.

[0010] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above may be solved by the specification. The above problems are obvious from the description of the specification, etc., and problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a transistor, the transistor comprising: a gate electrode, a first insulating film on the first gate electrode, and an oxide semiconductor on the first insulating film. a source electrode electrically connected to the oxide semiconductor film; a drain electrode connected to the oxide semiconductor film; a second insulating film on the oxide semiconductor film; and a second insulating film on the second insulating film. a gate electrode and a third insulating film on the second gate electrode, and the oxide semiconductor film is a first a first oxide semiconductor film on the gate electrode side of the first oxide semiconductor film and a second oxide semiconductor film on the first oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film are made of In and M (M The second oxide semiconductor film has a first oxide semiconductor layer, and a second oxide semiconductor layer has a second oxide semiconductor layer. The second gate electrode has a region having a smaller number of In atoms than the oxide semiconductor film. The semiconductor device has at least one metal element contained in a conductive film.

[0012] Another embodiment of the present invention is a semiconductor device including a transistor. The photodiode includes a first gate electrode, a first insulating film on the first gate electrode, and an oxide film on the first insulating film. a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; a second insulating film on the oxide semiconductor film; a second gate electrode on the first insulating film and a third insulating film on the second gate electrode; The electrode is a first gate electrode through an opening provided in the first insulating film and the second insulating film. The oxide semiconductor film is electrically connected to the first gate electrode side of the first oxide semiconductor film. a second oxide semiconductor film over the first oxide semiconductor film, and the second oxide semiconductor film is made of In, M (M is Al, Ga, Y, or Sn), and Zn. and the second oxide semiconductor film has a smaller number of In atoms than the first oxide semiconductor film. the second gate electrode has a metal element contained in the oxide semiconductor film, The semiconductor device has

[0013] In the above embodiment, the first oxide semiconductor film is an oxide semiconductor film having a structure represented by In>M (M is Al, Ga, Y, or Sn), and the second oxide semiconductor film has a region satisfying a composition of In≦M (M is Al, Ga It is preferable that the composition of the Cr-based alloy be a region having a composition of Y or Sn.

[0014] In the above embodiment, the second gate electrode includes a third oxide semiconductor film and a third oxide and a fourth oxide semiconductor film on the third oxide semiconductor film, M has a region satisfying a composition of Al, Ga, Y, or Sn, and the fourth oxide semiconductor film It is preferable that the composition of the first and second indium-tin alloys is In≧M (M is Al, Ga, Y, or Sn). .

[0015] In the above aspect, the oxide semiconductor film has a crystal part, and the crystal part has a c-axis orientation. It is preferable to have

[0016] In the above aspect, the third insulating film contains either or both of hydrogen and nitrogen. It is preferable to have

[0017] Another aspect of the present invention is a semiconductor device comprising: Another embodiment of the present invention is a display device including the display device and a touch sensor. Another aspect of the present invention is a display module having any of the above aspects. The semiconductor device, the display device, or the display module according to any one of the preceding claims, and an operation key or or a battery.

[0018] Another aspect of the present invention is a method for manufacturing a semiconductor device comprising the steps of forming a first gate electrode and forming a first gate electrode. forming a first insulating film on the first insulating film; and forming a first oxide semiconductor film on the first insulating film. forming a second oxide semiconductor film over the first oxide semiconductor film; forming a source electrode and a drain electrode on the oxide semiconductor film; forming a second insulating film on the body film, the source electrode, and the drain electrode; forming a third oxide semiconductor film functioning as a second gate electrode over the oxide semiconductor film; forming a third insulating film containing hydrogen over the oxide semiconductor film of the first oxide In the step of forming a semiconductor film, the first oxide semiconductor film is formed in an atmosphere containing a first oxygen gas. The first oxide semiconductor film is formed by adding a first oxygen gas to the first insulating film. In the forming step, the second oxide semiconductor film is formed in an atmosphere containing a second oxygen gas. In the step of forming the third oxide semiconductor film, the third oxide semiconductor film is The second insulating film is formed in an atmosphere containing oxygen gas, and a third oxygen gas is added to the second insulating film. After the step of forming the insulating film or the step of forming the third insulating film, The present invention relates to a method for manufacturing a semiconductor device, in which hydrogen is added to an oxide semiconductor film.

[0019] In the above aspect, the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film The semiconductor films are preferably formed by sputtering.

[0020] Another aspect of the present invention is a method for manufacturing a semiconductor device comprising the steps of forming a first gate electrode and forming a first gate electrode. forming a first insulating film on the first insulating film; and forming a first oxide semiconductor film on the first insulating film. forming a second oxide semiconductor film over the first oxide semiconductor film; forming a source electrode and a drain electrode on the oxide semiconductor film; forming a second insulating film on the body film, the source electrode, and the drain electrode; forming a third oxide semiconductor film functioning as a second gate electrode over the oxide semiconductor film; A fourth oxide semiconductor film serving as a second gate electrode is formed over the first oxide semiconductor film. and forming a third insulating film containing hydrogen over the fourth oxide semiconductor film. In the step of forming the first oxide semiconductor film, the first oxide semiconductor film is The insulating film is formed in an atmosphere containing a gas, and a first oxygen gas is added to the first insulating film, and a second oxygen gas is added to the first insulating film. In the step of forming the second oxide semiconductor film, the second oxide semiconductor film contains a second oxygen gas. The third oxide semiconductor film is formed in a SiO 2 atmosphere. The film is formed in an atmosphere containing a third oxygen gas, and the third oxygen gas is added to the second insulating film. In the step of forming the fourth oxide semiconductor film, forming a third insulating film in an atmosphere containing oxygen gas; After the step of forming the third insulating film, hydrogen is added to the fourth oxide semiconductor film. A method for making a body device.

[0021] In the above aspect, the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film The first oxide semiconductor film and the fourth oxide semiconductor film are preferably formed by sputtering. It is.

[0022] In the above embodiment, the flow rate of the third oxygen gas is greater than the flow rate of the fourth oxygen gas. This is preferable. Effect of the Invention

[0023] According to one embodiment of the present invention, in a transistor including an oxide semiconductor film, In particular, oxide semiconductors containing a large amount of In can be used. Suppressing fluctuations in electrical characteristics and improving reliability in transistors with conductive films Alternatively, a semiconductor device with reduced power consumption according to one embodiment of the present invention can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a novel semiconductor device is provided. According to one embodiment of the present invention, a novel display device can be provided. .

[0024] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the descriptions in the claims, etc. [Brief description of the drawings]

[0025] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 2] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 3] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 5] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 6]FIG. 2 is a diagram for explaining a band structure. [Figure 7] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 12] FIG. 1 is a model diagram showing oxygen moving into an oxide semiconductor film. [Figure 13] FIG. 1 is a diagram illustrating the results of TDS measurement. [Figure 14] FIG. 1 is a diagram illustrating the results of TDS measurement. [Figure 15] FIG. 1 is a diagram illustrating the results of TDS measurement. [Figure 16] 13A and 13B are graphs showing the measurement temperature dependence of an oxide conductive film. [Figure 17] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 18] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 19] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 20] Electron diffraction pattern of CAAC-OS. [Figure 21] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 22] 1A to 1C are diagrams illustrating a method for forming a CAAC-OS film. [Figure 23] A diagram explaining the InMZnO4 crystal. [Figure 24] 1A to 1C are diagrams illustrating a method for forming a CAAC-OS film. [Diagram 25] FIG. 2 is a diagram for explaining the positions at which particles adhere to a pellet. [Figure 26] FIG. 2 is a diagram for explaining the positions at which particles adhere to a pellet. [Figure 27]1A and 1B are a top view illustrating one embodiment of a display device and a circuit diagram illustrating one embodiment of a pixel. [Figure 28] FIG. 1 is a top view illustrating one embodiment of a pixel. [Figure 29] FIG. 1 is a cross-sectional view showing one embodiment of a pixel. [Diagram 30] FIG. 1 is a cross-sectional view showing one embodiment of a pixel. [Diagram 31] FIG. 1 is a top view illustrating one embodiment of a pixel. [Diagram 32] FIG. 1 is a cross-sectional view showing one embodiment of a pixel. [Diagram 33] FIG. 1 is a cross-sectional view showing one embodiment of a pixel. [Diagram 34] FIG. 1 is a top view illustrating one embodiment of a pixel. [Diagram 35] FIG. 1 is a cross-sectional view showing one embodiment of a pixel. [Diagram 36] FIG. 1 is a cross-sectional view showing one embodiment of a pixel. [Figure 37] FIG. 1 is a top view illustrating one embodiment of a pixel. [Figure 38] FIG. 1 is a cross-sectional view showing one embodiment of a pixel. [Figure 39] FIG. 1 is a cross-sectional view showing one embodiment of a pixel. [Diagram 40] FIG. 1 is a cross-sectional view showing one embodiment of a pixel. [Diagram 41] FIG. 1 is a top view illustrating one embodiment of a pixel. [Diagram 42] FIG. 1 is a cross-sectional view showing one embodiment of a pixel. [Diagram 43] FIG. 1 is a top view illustrating one embodiment of a pixel. [Diagram 44] FIG. 1 is a cross-sectional view showing one embodiment of a pixel. [Diagram 45] FIG. 1 is a circuit diagram showing one form of a pixel. [Diagram 46] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 47] 1A and 1B are a top view and a cross-sectional view illustrating a display device. [Figure 48] FIG. 1 is a perspective view showing an example of a touch panel. [Figure 49] FIG. 1 is a cross-sectional view showing an example of a display device. [Figure 50] FIG. 1 is a cross-sectional view showing an example of a touch sensor. [Figure 51] FIG. 1 is a cross-sectional view showing an example of a touch panel. [Figure 52] 3A and 3B are a block diagram and a timing chart of a touch sensor. [Figure 53] Circuit diagram of a touch sensor. [Figure 54] 1A to 1C are diagrams illustrating displays on a display device according to one embodiment of the present invention. [Figure 55] 1A to 1C are diagrams illustrating displays on a display device according to one embodiment of the present invention. [Figure 56] 1A to 1C are diagrams illustrating an example of a display method on a display device according to an embodiment. [Figure 57] 1A to 1C are diagrams illustrating an example of a display method on a display device according to an embodiment. [Figure 58] FIG. 2 is a diagram illustrating a display module. [Figure 59] 1A to 1C are diagrams illustrating electronic devices. [Figure 60] FIG. [Figure 61] FIG. 2 illustrates a configuration of a film formation apparatus. [Figure 62] FIG. 13 is a graph showing Id-Vg characteristics of a transistor. [Figure 63] FIG. 13 is a graph showing Id-Vg characteristics of a transistor. [Figure 64] 13A to 13C are diagrams illustrating the results of a GBT test on a transistor and the results of repeated GBT tests on a transistor. [Figure 65] 1A to 1C are cross-sectional STEM images of a transistor. [Figure 66] 1A to 1C are diagrams illustrating a structure used in calculations and calculation results of current density distribution. [Figure 67] FIG. 13 illustrates a structure used in calculation and the Id-Vg characteristics of a transistor. [Figure 68] FIG. 13 is a graph showing calculation results of Id-Vg characteristics of a transistor. [Figure 69] 13A and 13B are diagrams illustrating probability distribution of threshold voltages of transistors. [Figure 70] 13A and 13B are diagrams illustrating probability distribution of threshold voltages of transistors. [Figure 71] 13A and 13B are graphs illustrating calculation results of variations in Id-Vg characteristics in the subthreshold region of a transistor. [Figure 72] FIG. 1 is a diagram illustrating a structure used in calculations. [Figure 73] FIG. 1 is a diagram for explaining the potential distribution in the film thickness direction when NBTS is applied. [Figure 74] 1A and 1B are a top view and a cross-sectional view of a transistor; [Figure 75] 1A and 1B are a top view and a cross-sectional view of a transistor; [Figure 76] FIG. 13 is a graph showing Id-Vg characteristics of a transistor. [Figure 77] FIG. 13 is a graph showing Id-Vg characteristics of a transistor. [Figure 78] FIG. 13 is a graph showing Id-Vg characteristics of a transistor. [Figure 79] FIG. 13 is a graph showing Id-Vg characteristics of a transistor. [Figure 80] FIG. 13 is a diagram showing Id-Vd characteristics of a transistor. [Figure 81] FIG. 13 is a diagram showing Id-Vd characteristics of a transistor. [Figure 82] FIG. 13 is a diagram showing Id-Vd characteristics of a transistor. [Figure 83] FIG. 13 is a graph showing Id-Vg characteristics of a transistor. [Figure 84] 13A and 13B are graphs illustrating maximum field-effect mobility and threshold voltage of a transistor. [Figure 85] 1A and 1B are diagrams illustrating potential distribution applied to a transistor. [Figure 86] 1A and 1B are conceptual diagrams illustrating potentials applied to a transistor. [Figure 87] 1A and 1B are conceptual diagrams illustrating potentials applied to a transistor. [Figure 88] 1A and 1B are conceptual diagrams illustrating potentials applied to a transistor. [Figure 89] 13A and 13B are diagrams illustrating probability distribution of threshold voltages of transistors. [Figure 90] 13A and 13B are diagrams illustrating probability distribution of threshold voltages of transistors. [Figure 91] FIG. 13 is a graph showing calculation results of Id-Vg characteristics of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, the embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above description, and the embodiments and details thereof are not limited to those described above without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the embodiments described below. It is not to be construed as being limited to the content.

[0027] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily shown in order to facilitate understanding. The actual position, size, range, etc. may not be shown. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc.

[0028] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. Therefore, for example, "first" should be changed to "second " or "third" can be used as appropriate. The ordinal numbers used to identify an aspect of the present invention may not match those used in the present invention. There is a match.

[0029] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used. The relationship is used for convenience in describing the drawings. The dimensions change depending on the direction in which each component is depicted. It is not limited to words and phrases, and can be rephrased appropriately depending on the situation.

[0030] In addition, in this specification and the like, when explaining the configuration of the invention using drawings, The reference numerals are used commonly among different drawings.

[0031] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The semiconductor device may include a semiconductor device.

[0032] In addition, even when the term "semiconductor" is used in this specification, for example, If the electrical conductivity is low enough, the material may have the properties of an insulator. The boundary between "insulators" and "insulators" is unclear, and it may not be possible to strictly distinguish them. In some cases, the term "semiconductor" in the above can be replaced with "insulator." In some cases, the term "insulator" in the specification can be replaced with "semiconductor." In some cases, the term "insulator" in this specification can be rephrased as "semi-insulator." .

[0033] In addition, even when the term "semiconductor" is used in this specification, for example, If the electrical conductivity is high enough, it may have the properties of a "conductor". The boundary between the term "conductor" and the term "electrical conductor" is unclear, and it may not be possible to strictly distinguish between them. In some cases, the term "semiconductor" in the above can be replaced with "conductor." The term "conductor" in the specification etc. may be replaced with "semiconductor" in some cases.

[0034] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A current flows through the drain, the channel region, and the source. In this specification and the like, the channel region refers to a region through which a current mainly flows. The flow area.

[0035] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0036] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). The source region or the channel region This refers to the distance between the drain (drain region or drain electrode) and the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one of the values, maximum The value may be the minimum or average value.

[0037] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The area where the gate electrode overlaps with the electrode (the area where the current flows) forms a channel. This refers to the length of the part of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. That is, The channel width of a transistor may not be determined to a single value. In the fine print, the channel width is any one of the values ​​in the region where the channel is formed, the maximum The value may be the minimum or average value.

[0038] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0039] Also, a voltage is a voltage between a certain potential and a reference potential (such as ground potential (GND) or source potential). Therefore, voltage can be replaced with electric potential. be.

[0040] In this specification and the like, a silicon oxynitride film is a film having a composition containing more oxygen than nitrogen. It refers to a film with a high content of oxygen, preferably 55 atomic % to 65 atomic % and 1 % to 20 atomic %, silicon is 25 atomic % to 35 atomic %, hydrogen is 0.1 atomic % The silicon oxide nitride film is a film containing silicon dioxide in a range of 10 atomic % or more. The nitrogen content is preferably 55 atomic % or more. 5 atomic % or less, oxygen is 1 atomic % to 20 atomic % or less, silicon is 25 atomic % to 35 atomic % %, and hydrogen at a concentration in the range of 0.1 atomic % to 10 atomic %.

[0041] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to:

[0042] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it includes the case where the angle is between 85° and 95°. refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0043] (Embodiment 1) In this embodiment, a semiconductor device and a manufacturing method of the semiconductor device according to one embodiment of the present invention will be described. The following description will be given with reference to FIGS.

[0044] <1-1. Configuration example 1 of semiconductor device> FIG. 1A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. 1B corresponds to a cross-sectional view taken along dashed line X1-X2 in FIG. 1A. FIG. 1C is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 1A. In FIG. 1A, in order to avoid complication, the transistor 100 Some of the components (such as the insulating film that functions as the gate insulating film) are omitted in the figure. The dashed line X1-X2 direction is the channel length direction, and the dashed line Y1-Y2 direction is the channel width direction. In the top view of the transistor, As in FIG. 1(A), some of the components may be omitted.

[0045] The transistor 100 includes a conductive film 104 that functions as a first gate electrode on a substrate 102. an insulating film 106 on the substrate 102 and the conductive film 104; and an insulating film 107 on the insulating film 106. The oxide semiconductor film 108 over the insulating film 107 and the insulating film 108 electrically connected to the oxide semiconductor film 108 The conductive film 112a serving as a source electrode and the oxide semiconductor film 108 are electrically connected to The conductive film 112b serving as a drain electrode is connected to the oxide semiconductor film 108 and the conductive film 11 2a and 112b, and an insulating film 114, 116 provided on the insulating film 116 and a conductive The oxide semiconductor film 120a electrically connected to the insulating film 112b and the oxide semiconductor film 120b on the insulating film 116 The conductive film 120b, the insulating film 116, and the insulating film 11 on the oxide semiconductor films 120a and 120b 8 and,

[0046] In the transistor 100, the insulating films 106 and 107 are The insulating films 114 and 116 function as a first gate insulating film. The insulating film 118 serves as a second gate insulating film for protecting the transistor 100. In this specification and the like, the insulating films 106 and 107 are the insulating film 114 and 116 as a second insulating film, the insulating film 118 as a third insulating film, In the transistor 100, the oxide semiconductor film 12 The oxide semiconductor film 120a functions as a pixel electrode for use in a display device, and the oxide semiconductor film 120b functions as a It functions as the second gate electrode of the transistor 100 .

[0047] In addition, the oxide semiconductor film 108 is formed on the oxide semiconductor film 104 side which functions as the first gate electrode. and an oxide semiconductor film 108c on the oxide semiconductor film 108b. The oxide semiconductor film 108b and the oxide semiconductor film 108c each contain In and , M (M is Al, Ga, Y, or Sn), and Zn.

[0048] For example, in the oxide semiconductor film 108b, a region in which the atomic ratio of In is larger than the atomic ratio of M is In addition, the oxide semiconductor film 108c preferably has a region It is preferable to have a region in which the number of In atoms is smaller than that of b.

[0049] the oxide semiconductor film 108b has a region in which the atomic ratio of In is higher than the atomic ratio of M; The field effect mobility (sometimes simply referred to as mobility, or μFE) of the transistor 100 is Specifically, the field effect mobility of the transistor 100 can be increased by 10c m 2 / Vs, and more preferably the field effect mobility of the transistor 100 is greater than 30 cm 2 / Vs can be exceeded.

[0050] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. A driver (especially a demux connected to the output terminal of a shift register of a gate driver) By using it in a semiconductor device or display device with a narrow frame (also called a narrow frame), Locations can be provided.

[0051] On the other hand, the oxide semiconductor film 108b has a region in which the atomic ratio of In is larger than the atomic ratio of M. In this case, the electrical characteristics of the transistor 100 are likely to vary when exposed to light. In the semiconductor device of one embodiment of the present invention, an oxide semiconductor film 108b is The oxide semiconductor film 108c is formed on the oxide semiconductor film 108b. Since the oxide semiconductor film 108b has a region with a lower atomic ratio of In than the oxide semiconductor film 108b, Eg is Therefore, the stack of the oxide semiconductor film 108b and the oxide semiconductor film 108c The oxide semiconductor film 108 having the structure has an improved resistance to a negative bias stress test using light. This becomes possible.

[0052] In addition, the oxide semiconductor film 108, particularly the channel region of the oxide semiconductor film 108b, Impurities such as hydrogen and moisture are problematic because they affect transistor characteristics. Therefore, in the channel region of the oxide semiconductor film 108b, hydrogen, moisture, and the like are The fewer the impurities, the more preferable. The oxygen vacancies that occur in the oxide semiconductor layer affect the transistor characteristics, which is a problem. When oxygen vacancies are formed in the channel region of the membrane 108b, hydrogen bonds to the oxygen vacancies, A carrier supply source is generated in the channel region of the oxide semiconductor film 108b. When the oxide semiconductor film 108b is formed, the electric characteristics of the transistor 100 including the oxide semiconductor film 108b are changed, Generally speaking, a shift in the threshold voltage occurs. In the hole region, the fewer the oxygen deficiencies, the more preferable.

[0053] In view of this, in one embodiment of the present invention, an insulating film in contact with the oxide semiconductor film 108, specifically, The insulating film 107 and the oxide semiconductor film 108 are formed below the oxide semiconductor film 108. The insulating films 114 and 116 formed above the insulating film 10 contain excess oxygen. 7, and oxygen or excess oxygen is transferred from the insulating films 114 and 116 to the oxide semiconductor film 108. By increasing the temperature, oxygen vacancies in the oxide semiconductor film can be reduced. To suppress the fluctuation of the electrical characteristics of the transistor 100, particularly the fluctuation of the transistor 100 due to light irradiation. This becomes possible.

[0054] In one embodiment of the present invention, the insulating film 107 and the insulating films 114 and 116 are treated with excess acid. In order to incorporate the element, there is no increase in the manufacturing process or the increase in the manufacturing process is very small. Therefore, the yield of the transistor 100 can be increased.

[0055] Specifically, in the step of forming the oxide semiconductor film 108b, a sputtering method is used. In addition, the oxide semiconductor film 108b is formed in an atmosphere containing oxygen gas. Oxygen or excess oxygen is added to the insulating film 107, which is to be the surface on which the film 108b is to be formed.

[0056] In addition, in the step of forming the oxide semiconductor films 120a and 120b, a sputtering method The oxide semiconductor films 120a and 120b are formed in an atmosphere containing oxygen gas using The insulating film 116, which is a surface on which the oxide semiconductor films 120a and 120b are to be formed, is When oxygen or excess oxygen is added to the insulating film 116, The insulating film 114 and the oxide semiconductor film 108 located below the insulating film 6 also contain oxygen or excess oxygen. May be added.

[0057] <1-2. Thermal Desorption Spectroscopy (TDS) Regarding the amount of oxygen released from insulating films during ectroscopy Here, by forming the oxide semiconductor film in an atmosphere containing oxygen gas, the oxide semiconductor The following is based on the results of measurements of the amount of release from the insulating film, which is the surface on which the body film is formed. do.

[0058] In order to measure the amount of oxygen released from the insulating film, the following samples A1 to A20 were prepared. The amount of oxygen released in TDS was evaluated.

[0059] [1-2-1. Confirm the amount of oxygen added to the insulating film by changing the target composition Evaluation for First, samples A1 to A5 will be described. This is a sample to confirm the amount of oxygen added to the insulating film by changing the composition.

[0060] (Sample A1) As the sample A1, a silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate by PECV. The silicon oxynitride film was formed using the D device and then heat-treated. The substrate temperature was set at 350° C., and the silane gas flow rate was 160 sccm and the silane gas flow rate was 4000 sccm. Nitrous oxide gas and nitrogen were introduced into the chamber, the pressure was set to 200 Pa, and the PECVD apparatus The formation was achieved by supplying 1500 W of RF power between the parallel plate electrodes placed inside the device. The treatment conditions were as follows: using an RTA apparatus, treatment was carried out at 650°C for 6 minutes in a nitrogen atmosphere. The heat treatment causes oxygen contained in the silicon oxynitride film during film formation to be released.

[0061] As samples A2 to A5, a silicon oxynitride film having a thickness of 400 nm was formed on a glass substrate. The silicon oxynitride film was formed using a PECVD apparatus and then heat-treated. A 50-nm-thick oxide semiconductor film was formed on the oxide semiconductor layer by using a sputtering apparatus. The conditions for forming the conductive film were a substrate temperature of 170°C and oxygen gas with a flow rate of 100 sccm. Introduce into the chamber, that is, make the atmosphere 100% oxygen gas, and set the pressure to 0.6 Pa. The target was placed in the sputtering device and supplied with 2500 W of AC power. Note that the target compositions of the oxide semiconductor films are different between Samples A2 to A5. The target compositions of the oxide semiconductor films A to A5 will be described later. After the film was formed, the oxide semiconductor film was removed to expose the surface of the silicon oxynitride film. The conditions for forming the oxide semiconductor film, the conditions for forming the silicon oxynitride film, and the conditions for the heat treatment are as follows: The thickness was the same as that of the sample A1 described above.

[0062] (Sample A2) The target composition of the oxide semiconductor film of sample A2 was In:Ga:Zn= The ratio was 1:1:1.2.

[0063] (Sample A3) The target composition of the oxide semiconductor film of sample A3 was In:Ga:Zn= The ratio was 4:2:4.1.

[0064] (Sample A4) The target composition of the oxide semiconductor film of sample A4 was In:Ga:Zn= The ratio was 3:1:2.

[0065] (Sample A5) The target composition of the oxide semiconductor film of sample A5 was In:Ga:Zn= The ratio was 1:3:6.

[0066] Next, mass released from the silicon oxynitride films of the samples A1 to A5 fabricated as described above The charge ratio (M / z) was 32, i.e., the amount of gas released was measured, which corresponds to oxygen (O2). The amount of gas released was measured using a TDS device. The amount of gas released, which corresponds to oxygen, was measured when the surface temperature of the film was in the range of 50°C to 600°C. .

[0067] The TDS measurement results of samples A1 to A5 are shown in FIG. 13. In FIG. 13, the vertical axis is M / The amount of release at z=32 is shown on the horizontal axis, and the sample name, etc. are shown on the horizontal axis.

[0068] From the results shown in FIG. 13, the emission amount of M / z=32 in sample A1 was 1.82×10 14 [pcs / cm 2 In addition, the amount of emission of M / z=32 in sample A2 was 1.22×10 15 [pcs / cm 2 In addition, the amount of M / z=32 released from sample A3 was 1.14×10 15 [pcs / cm 2 In addition, the amount of emission of M / z=32 from sample A4 was 1.18×10 15 [pcs / cm 2 In addition, the amount of emission of M / z=32 in sample A5 was 1.20×10 15 [pcs / cm2 ] was the case.

[0069] In this way, the insulating film (here, the silicon oxynitride film) on the surface on which the oxide semiconductor film is to be formed is By forming an oxide semiconductor film by a sputtering method, excess oxygen is added to the insulating film. It was suggested that it could be added.

[0070] Note that the amount of added metal in the insulating film may vary depending on the composition of the target used to form the oxide semiconductor film. No significant difference was observed in the amount of oxygen released from the insulating film.

[0071] [1-2-2. Evaluation of the amount of oxygen added to the insulating film by changing the deposition gas flow rate] Next, samples A6 to A8 will be described. Samples A6 to A8 were prepared by using a deposition gas flow. This is a sample for confirming the amount of oxygen added to the insulating film by changing the amount.

[0072] As samples A6 to A8, a silicon oxynitride film having a thickness of 400 nm was formed on a glass substrate. The silicon oxynitride film was formed using a PECVD apparatus and then heat-treated. A 50-nm-thick oxide semiconductor film was formed on the substrate by using a sputtering apparatus. The silicon oxynitride semiconductor film was then removed to expose the surface of the silicon oxynitride film. The conditions for forming the silicon film and the heat treatment were the same as those for the above-described samples A1 to A5. Moreover, the conditions for forming the oxide semiconductor films are different between Samples A6 to A8.

[0073] (Sample A6) The oxide semiconductor film of Sample A6 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 90 s. ccm of argon gas and 10 sccm of oxygen gas were introduced into the chamber. The atmosphere was set to 10% oxygen gas, the pressure was set to 0.6 Pa, and the device was placed in a sputtering device. The target (In:Ga:Zn=4:2:4.1) was supplied with 2500W of AC power. And it was formed.

[0074] (Sample A7) The oxide semiconductor film of Sample A7 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 50 s. ccm of argon gas and 50 sccm of oxygen gas were introduced into the chamber, i.e. The atmosphere was set to 50% oxygen gas, the pressure was set to 0.6 Pa, and the device was placed in a sputtering device. The target (In:Ga:Zn=4:2:4.1) was supplied with 2500W of AC power. And it was formed.

[0075] (Sample A8) The oxide semiconductor film of Sample A8 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 100 Oxygen gas was introduced into the chamber at a rate of 100 sccm, i.e., the atmosphere was 100% oxygen gas, and the pressure was The pressure was set to 0.6 Pa, and the target (In:Ga:Zn The thickness of the sample was 4:2:4.1) and 2500 W of AC power was supplied to the sample. This is the same sample as sample A3.

[0076] Next, mass released from the silicon oxynitride films of the samples A6 to A8 fabricated as described above The charge ratio (M / z) was 32, i.e., the amount of gas released was measured, which corresponds to oxygen (O2). The amount of gas released was measured using a TDS analyzer.

[0077] The TDS measurement results of samples A6 to A8 are shown in FIG. The vertical axis indicates the amount of emission of M / z=32, and the horizontal axis indicates the sample name, etc.

[0078] From the results shown in FIG. 14(A), the amount of emission of M / z=32 from sample A6 was 1.19×10 14 [pcs / cm 2 In addition, the amount of emission of M / z=32 in sample A7 was 5.02×10 14 [pcs / cm 2 In addition, the amount of emission of M / z=32 in sample A8 was 1.14×10 15 [pcs / cm 2 ] was the case.

[0079] In this way, the insulating film (here, the silicon oxynitride film) on the surface on which the oxide semiconductor film is to be formed is When an oxide semiconductor film is formed by a sputtering method, excess oxygen is added to the insulating film. In this case, the flow rate of oxygen gas is preferably increased as a condition for forming the oxide semiconductor film. , is found to be preferable.

[0080] [1-2-3. Evaluation of the amount of oxygen added to the insulating film by changing the deposition power] Next, samples A9 to A12 will be described. This is a sample for confirming the amount of oxygen added to the insulating film by changing the force.

[0081] As samples A9 to A12, a silicon oxynitride film having a thickness of 400 nm was formed on a glass substrate. The silicon oxynitride was formed using a PECVD apparatus and then heat-treated. A 50-nm-thick oxide semiconductor film was formed on the film by using a sputtering apparatus. The oxide semiconductor film was removed to expose the surface of the silicon oxynitride film. The conditions for forming the composite film and the heat treatment were the same as those for samples A1 to A8. The conditions for forming the oxide semiconductor films are different between Samples A9 to A12.

[0082] (Sample A9) The oxide semiconductor film of Sample A9 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 100 Oxygen gas was introduced into the chamber at a rate of 100 sccm, i.e., the atmosphere was 100% oxygen gas, and the pressure was The pressure was set to 0.6 Pa, and the target (In:Ga:Zn The antenna was formed by supplying 500 W of AC power to the 10-phase MOSFET (phase:100 / single-phase, phase:200 / single-phase, phase:400 / single-phase, phase:400 / single-phase, phase:1000 / single-phase, phase:2 ...

[0083] (Sample A10) The oxide semiconductor film of Sample A10 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 10 0 sccm of oxygen gas was introduced into the chamber, i.e., the atmosphere was 100% oxygen gas. The pressure was set to 0.6 Pa, and the target (In:Ga:Z The structure was formed by supplying 1500 W of AC power to a 4-phase gyro (n=4:2:4.1).

[0084] (Sample A11) The oxide semiconductor film of Sample A11 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 10 0 sccm of oxygen gas was introduced into the chamber, i.e., the atmosphere was 100% oxygen gas. The pressure was set to 0.6 Pa, and the target (In:Ga:Z n = 4:2:4.1) and an AC power of 2500 W was supplied to the sample A11. , which is the same sample as samples A3 and A8.

[0085] (Sample A12) The oxide semiconductor film of Sample A12 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 10 0 sccm of oxygen gas was introduced into the chamber, i.e., the atmosphere was 100% oxygen gas. The pressure was set to 0.6 Pa, and the target (In:Ga:Z The device was formed by supplying 4500 W of AC power to a 4:2:4.1 MOSFET (n=4:2:4.1).

[0086] Next, the quality of the silicon oxynitride films of the samples A9 to A12 was evaluated. The mass-to-charge ratio (M / z) is 32, i.e., the amount of gas released, which corresponds to oxygen (O2), was measured. The amount of released gas was measured using a TDS analyzer.

[0087] The TDS measurement results of samples A9 to A12 are shown in FIG. 14(B). The vertical axis indicates the amount of emission of M / z=32, and the horizontal axis indicates the sample name, etc.

[0088] From the results shown in FIG. 14(B), the amount of emission of M / z=32 from sample A9 was 9.28×10 14 [pcs / cm 2 In addition, the amount of emission of M / z=32 in sample A10 was 1.07×10 1 5 [pcs / cm 2 In addition, the amount of M / z=32 released from sample A11 was 1.14×10 15 [pcs / cm 2 In addition, the amount of emission of M / z=32 in sample A12 was 1.24×1 0 15 [pcs / cm 2 ] was the case.

[0089] In this way, the insulating film (here, the silicon oxynitride film) on the surface on which the oxide semiconductor film is to be formed is When an oxide semiconductor film is formed by a sputtering method, excess oxygen is added to the insulating film. In this case, it is preferable to increase the deposition power as a condition for forming the oxide semiconductor film. I can see that it is better.

[0090] [1-2-4. Evaluation of the amount of oxygen added to the insulating film by changing the deposition pressure] Next, Samples A13 to A15 will be described. 5 is a sample used to confirm the amount of oxygen added to the insulating film by changing the deposition pressure. be.

[0091] Samples A13 to A15 were prepared by forming silicon oxynitride films of 400 nm thickness on glass substrates. The silicon oxide film was formed using a PECVD apparatus and then heat-treated. A 50-nm-thick oxide semiconductor film was formed on the silicon film by using a sputtering apparatus. Thereafter, the oxide semiconductor film was removed to expose the surface of the silicon oxynitride film. The conditions for forming the silicon oxide film and the heat treatment were the same as those for the samples A1 to A12. The formation conditions of the oxide semiconductor films were different in Samples A13 to A15.

[0092] (Sample A13) The oxide semiconductor film of Sample A13 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 10 0 sccm of oxygen gas was introduced into the chamber, i.e., the atmosphere was 100% oxygen gas. The pressure was set to 0.3 Pa, and the target (In:Ga:Z The device was formed by supplying 2500 W of AC power to a 4-phase MOSFET (n = 4:2:4.1).

[0093] (Sample A14) The oxide semiconductor film of Sample A14 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 10 0 sccm of oxygen gas was introduced into the chamber, i.e., the atmosphere was 100% oxygen gas. The pressure was set to 0.6 Pa, and the target (In:Ga:Z n = 4:2:4.1) and an AC power of 2500 W was supplied to the sample A14. , which is the same sample as samples A3, A8, and A11.

[0094] (Sample A15) The oxide semiconductor film of Sample A15 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 10 0 sccm of oxygen gas was introduced into the chamber, i.e., the atmosphere was 100% oxygen gas. The pressure was set to 0.8 Pa, and the target (In:Ga:Z The device was formed by supplying 2500 W of AC power to a 4-phase MOSFET (n = 4:2:4.1).

[0095] Next, the following is released from the silicon oxynitride films of Samples A13 to A15: The mass-to-charge ratio (M / z) is 32, which corresponds to oxygen (O2). The amount of released gas was measured using a TDS analyzer.

[0096] The TDS measurement results of samples A13 to A15 are shown in FIG. The vertical axis indicates the amount of emission of M / z=32, and the horizontal axis indicates the sample name, etc.

[0097] From the results shown in FIG. 15(A), the amount of emission of M / z=32 from sample A13 was 1.17×10 1 5 [pcs / cm 2 In addition, the amount of emission of M / z=32 in sample A14 was 1.14×10 15 [pcs / cm 2 The amount of emission of M / z=32 in sample A15 was 1.15×10 15 [pcs / cm 2 ] was the case.

[0098] In this way, the amount of oxygen added to the insulating film varies depending on the pressure when the oxide semiconductor film is formed. No difference in the amount of oxygen (oxygen released from the insulating film) was observed.

[0099] [1-2-5. Evaluation of the amount of oxygen added to the insulating film by changing the film thickness] Next, Samples A16 to A20 will be described. 0 is a sample used to confirm the amount of oxygen added to the insulating film by changing the film thickness. .

[0100] Samples A16 to A20 were prepared by forming silicon oxynitride films having a thickness of 400 nm on a glass substrate. The silicon oxide film was formed using a PECVD apparatus and then heat-treated. An oxide semiconductor film was formed on the silicon film by using a sputtering apparatus. The conductive film was removed to expose the surface of the silicon oxynitride film. The formation conditions and heat treatment conditions were the same as those of the samples A1 to A15 described above. The thicknesses of the oxide semiconductor films in Samples A16 to A20 are different.

[0101] (Sample A16) The thickness of the oxide semiconductor film of Sample A16 was set to 0 nm. The sample A16 is the same sample as the sample A1.

[0102] (Sample A17) The thickness of the oxide semiconductor film of Sample A17 was 10 nm. The conditions for forming the thin film were a substrate temperature of 170°C and oxygen gas with a flow rate of 100 sccm. The atmosphere was 100% oxygen gas, the pressure was 0.6 Pa, and the The target (In:Ga:Zn=4:2:4.1 [atomic weight]) placed in the sputtering device The device was formed by supplying 2500 W of AC power to the 100-nm diameter gyro (semiconductor field-effect transistor).

[0103] (Sample A18) The thickness of the oxide semiconductor film of Sample A18 was set to 50 nm. The conditions for forming the solid film were the same as those for sample A17. This is the same sample as 8, A11, and A14. (Sample A19) The thickness of the oxide semiconductor film of Sample A19 was 100 nm. The conditions for forming the conductive film were the same as those for sample A17. (Sample A20) The thickness of the oxide semiconductor film of Sample A20 was 300 nm. The conditions for forming the conductive film were the same as those for sample A17.

[0104] Next, the following is released from the silicon oxynitride films of Samples A16 to A20: The mass-to-charge ratio (M / z) is 32, which corresponds to oxygen (O2). The amount of released gas was measured using a TDS analyzer.

[0105] The TDS measurement results of samples A16 to A20 are shown in FIG. In the graph, the vertical axis indicates the amount of emission of M / z=32, and the horizontal axis indicates the name of the sample.

[0106] From the results shown in FIG. 15(B), the amount of emission of M / z=32 in sample A16 was 1.82×10 1 4 [pcs / cm 2 In addition, the amount of emission of M / z=32 in sample A17 was 1.08×10 15 [pcs / cm 2 The amount of emission of M / z=32 in sample A18 was 1.14×10 15 [pcs / cm 2 The amount of M / z=32 released from sample A19 was 1.11×10 15 [pcs / cm 2The emission amount of M / z=32 in sample A20 was 1.17×10 15 [pcs / c m 2 ] was the case.

[0107] In this way, the insulating film (here, the silicon oxynitride film) on the surface on which the oxide semiconductor film is to be formed is By forming an oxide semiconductor film with a thickness of 10 nm or more by a sputtering method, It was suggested that excess oxygen could be added to the film.

[0108] <1-3. Oxide conductors> Next, the oxide conductor will be described. In the process, the oxide semiconductor films 120a and 120b are formed by absorbing oxygen from the insulating films 114 and 116. The oxide semiconductor films 120a and 120b function as protective films for suppressing emission. Before the step of forming the insulating film 118, the insulating film 118 has a function as a semiconductor. After the formation step, the oxide semiconductor films 120a and 120b function as conductors. Therefore, the oxide semiconductor films 120a and 120b are formed of an oxide conductor (OC It may also be called an Ide Conductor.

[0109] In order for the oxide semiconductor films 120a and 120b to function as conductors, the oxide semiconductor Oxygen vacancies are formed in the films 120a and 120b, and hydrogen is added to the oxygen vacancies from the insulating film 118. As a result, a donor level is formed near the conduction band. The oxide semiconductor films 120a and 120b have high conductivity and become conductors. In general, oxide semiconductors have the following properties: The large gap between the oxides allows them to transmit visible light. The oxide conductor is an oxide semiconductor having a donor level in the vicinity of the band. The effect of absorption due to levels is small, and the transparent property to visible light is comparable to that of oxide semiconductors. .

[0110] Here, the resistance of a film formed of an oxide conductor (hereinafter referred to as an oxide conductor film) The temperature dependency of the resistance will be explained with reference to FIG.

[0111] Here, samples B1 to B4 having an oxide conductive film were fabricated. A 100-nm-thick oxide semiconductor film was formed on a glass substrate by sputtering. Next, a hydrogen-containing film having a thickness of 100 nm was formed on the oxide semiconductor film by using a PECVD method. A silicon nitride film was formed. Note that in Samples B1 to B3, a target for an oxide semiconductor film was The composition and the formation conditions of the oxide semiconductor film are different. A conductive oxide film having a thickness of 100 nm was formed on a glass substrate by a deposition method.

[0112] The results of measuring the sheet resistance of each sample are shown in Figure 16. The sheet resistance was measured using a four-terminal The van der Pauw method was used. In FIG. 16, the vertical axis represents sheet resistance, The horizontal axis indicates the measurement temperature. The preparation method of each sample is described below.

[0113] (Sample B1) The oxide semiconductor film of Sample B1 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 100 Oxygen gas was introduced into the chamber at a rate of 100 sccm, i.e., the atmosphere was 100% oxygen gas, and the pressure was The pressure was set to 0.6 Pa, and the target (In:Ga:Zn The atomic ratio was 4:2:4.1 and an AC power of 2500 W was applied to the sample. In Fig. 16, the oxide semiconductor film of the sample B1 is IGZO(423). The values ​​are not the target composition but the composition of the formed film. IGZO(312), The same is true for IGZO(136).

[0114] (Sample B2) The oxide semiconductor film of Sample B2 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 100 Oxygen gas was introduced into the chamber at a rate of 100 sccm, i.e., the atmosphere was 100% oxygen gas, and the pressure was The pressure was set to 0.6 Pa, and the target (In:Ga:Zn = 3:1:2 [atomic ratio]) and an AC power of 2500 W was supplied to the sample. In this example, the oxide semiconductor film of Sample B2 is IGZO(312).

[0115] (Sample B3) The oxide semiconductor film of Sample B3 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 100 Oxygen gas was introduced into the chamber at a rate of 100 sccm, i.e., the atmosphere was 100% oxygen gas, and the pressure was The pressure was set to 0.8 Pa, and the target (In:Ga:Zn =1:3:6) and an AC power of 2500 W was supplied to the The oxide semiconductor film of Sample B3 is IGZO(136).

[0116] (Sample B4) The conditions for forming the oxide conductive film of sample B4 were: substrate temperature at room temperature, flow rate of 72 sccm Argon gas at a flow rate of 5 sccm and oxygen gas at a flow rate of 5 sccm were introduced into the chamber, and the pressure was set to 0.1 The pressure was 5 Pa, and the target (indium, tin, and silicon) was set in the sputtering device. Con and oxide target containing In2O3:SnO2:SiO2=85:10:5[ % by weight) was supplied with a DC power of 3200 W. The oxide conductor film of B4 is NITO.

[0117] From the results shown in FIG. 16, in the samples B1 and B2, the oxide conductor of the sample B4 The sheet resistance is higher than that of the film, but is 1.0×10 2 Ω / □ or more 1.0×10 3 Ω / □ or less It can be seen that the change in sheet resistance due to the measurement temperature is also extremely small. That is, the oxide conductors used in Samples B1 and B2 are degenerate semiconductors and have a conduction band below It is estimated that the edge and the Fermi level are coincident or nearly coincident. The sheet resistance is high and the measurement limit (1.0×10 6 Ω / □ or more), making measurement difficult. Ta.

[0118] As described above, in the semiconductor device of one embodiment of the present invention, the step of forming an oxide semiconductor film In the process, oxygen is added to a surface of the oxide semiconductor film on which the oxide semiconductor film is to be formed. a first oxide semiconductor film functioning as a gate electrode; and a second oxide semiconductor film functioning as a second gate electrode. The second oxide semiconductor film is formed by using an oxide semiconductor film having the same metal element as the first oxide semiconductor film. By forming an insulating film containing an element, the second oxide semiconductor film becomes an oxide conductive film. By adopting such a configuration, it is possible to suppress the fluctuation of electrical characteristics and realize a highly reliable semiconductor device. It can be realized.

[0119] <1-4. Components of Semiconductor Device> The components included in the semiconductor device of this embodiment will be described in detail below.

[0120] [substrate] There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, quartz substrates, and sa A fire substrate or the like may be used as the substrate 102. Also, a material such as silicon or silicon carbide may be used. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductors such as silicon germanium, etc. It is also possible to use a substrate, an SOI substrate, or the like, on which a semiconductor element is provided. The substrate 102 may be a glass substrate. If you have 6th generation (1500mm x 1850mm), 7th generation (1870mm x 220 0mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 280 By using large-area substrates such as 10th generation (2950mm x 3400mm), Larger display devices can be manufactured.

[0121] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer is preferably removed from the substrate 102 after a semiconductor device is partially or entirely completed thereon. The transistor 100 can be separated and used for transfer to another substrate. It can also be transferred to substrates with poor thermal properties or flexible substrates.

[0122] [Conductive Film Functioning as First Gate Electrode, Source Electrode, and Drain Electrode] A conductive film 104 functioning as a gate electrode and a conductive film 112 functioning as a source electrode. The conductive film 112b functioning as a drain electrode is made of chromium (Cr), copper (C u), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (M o), Tantalum (Ta), Titanium (Ti), Tungsten (W), Manganese (Mn), Ni A metal element selected from nickel (Ni), iron (Fe), and cobalt (Co), or the above The alloys are made of metal elements or alloys combining the above metal elements. It can be formed.

[0123] The conductive films 104, 112a, and 112b may have a single-layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, titanium on an aluminum film, A two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a titanium nitride film A two-layer structure in which a tungsten film is laminated on top of a tantalum nitride film or a tungsten nitride film A two-layer structure in which a tungsten film is laminated, a titanium film, and an aluminum film is laminated on the titanium film. There are three-layer structures, such as a titanium film on top of an aluminum film. Select from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film or a nitride film made by combining one or more of these may be used.

[0124] The conductive films 104, 112a, and 112b are made of indium tin oxide or tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light transmitting properties, such as indium tin oxide doped with silicon oxide, is used. It is also possible.

[0125] The conductive films 104, 112a, and 112b are made of a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied. This allows processing using a wet etching process, which reduces manufacturing costs. It becomes possible.

[0126] [Insulating film functioning as the first gate insulating film] The insulating films 106 and 107 functioning as the gate insulating film of the transistor 100 are Plasma Enhanced Chemical Vapor Deposition (PECVD) Silicon oxide is deposited by vapor deposition, sputtering, etc. silicon oxide film, silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film , hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, oxide Tantalum film, magnesium oxide film, lanthanum oxide film, cerium oxide film and neodymium oxide film Each of the insulating films 106 and 107 can be an insulating layer including one or more films. A single-layer insulating film selected from the above materials, or an insulating film having three or more layers, without using a laminated structure. may also be used.

[0127] The insulating film 106 also functions as a blocking film that suppresses oxygen permeation. For example, the insulating films 107, 114, and 116 and / or the oxide semiconductor film 108 may contain an excess of acid. When oxygen is supplied, the insulating film 106 can suppress oxygen permeation.

[0128] Note that the oxide semiconductor film 108 functioning as a channel region of the transistor 100 The insulating film 107 is preferably an oxide insulating film, and has an oxide content in excess of the stoichiometric composition. It is more preferable that the insulating film 1 has a region containing oxygen (an oxygen excess region). The insulating film 107 is capable of releasing oxygen. In order to provide the insulating film 107, for example, the insulating film 107 may be formed in an oxygen atmosphere. Oxygen may be added to the insulating film 107 after it is formed. More on this later.

[0129] When hafnium oxide is used as the insulating film 107, the following effects are obtained. Hafnium has a higher dielectric constant than silicon oxide and silicon oxynitride. Compared to the case where silicon oxide is used, the thickness of the insulating film 107 can be made larger, so that the tunnel This reduces the leakage current caused by the current. Furthermore, hafnium oxide, which has a crystalline structure, can be used to realize an amorphous structure. It has a higher relative dielectric constant than hafnium oxide, which has a low off-current. To form a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic. The types are not limited to these.

[0130] In this embodiment, a silicon nitride film is formed as the insulating film 106, and the insulating film 107 is The silicon oxide film is formed as a result of the above. The silicon nitride film has a lower dielectric constant than the silicon oxide film. The film thickness required to obtain the same capacitance as a silicon oxide film is large, so it is suitable for transistors. The gate insulating film of the transistor 150 is made physically thick by including a silicon nitride film. Therefore, the decrease in the dielectric strength of the transistor 100 can be suppressed, and the dielectric strength can be improved. The edge breakdown voltage can be improved and electrostatic breakdown of the transistor 100 can be suppressed.

[0131] [Oxide semiconductor film] For the oxide semiconductor film 108, the above-mentioned materials can be used.

[0132] When the oxide semiconductor film 108b is an In-M-Zn oxide, the In-M-Zn oxide is formed. The atomic ratio of the metal elements in the sputtering target used for this purpose satisfies In>M. It is preferable that the atomic ratio of the metal elements in such a sputtering target is I n:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4 .1 etc.

[0133] In addition, when the oxide semiconductor film 108c is an In-M-Zn oxide, The atomic ratio of metal elements in the sputtering target used to deposit the film is In≦M. It is preferable that the atomic ratio of the metal elements in such a sputtering target is In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn= 1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, etc. do.

[0134] The oxide semiconductor film 108b and the oxide semiconductor film 108c are each an In-MZ In the case of n-oxide, polycrystalline In-M-Zn oxide is used as the sputtering target. It is preferable to use a target containing polycrystalline In-M-Zn oxide. By using the above, the oxide semiconductor films 108b and 108c having crystallinity can be formed. Note that the oxide semiconductor film 108b and the oxide semiconductor film 108c are formed. The atomic ratios of the metal elements contained in the sputtering target are For example, the sputtering of the oxide semiconductor film 108b When the atomic ratio of In:Ga:Zn=4:2:4.1 is used as the target, the film is formed. The atomic ratio of the oxide semiconductor film 108b to be formed is approximately In:Ga:Zn=4:2:3. There are cases.

[0135] The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. By using a nitride semiconductor, the off-state current of the transistor 100 can be reduced. In particular, the oxide semiconductor film 108b has an energy gap of 2 eV or more, preferably The oxide semiconductor film 108c has an energy It is preferable to use an oxide semiconductor film whose gap is greater than or equal to 2.5 eV and less than or equal to 3.5 eV. In addition, the energy gap of the oxide semiconductor film 108c is larger than that of the oxide semiconductor film 108b. The larger the better.

[0136] The oxide semiconductor film 108b and the oxide semiconductor film 108c each have a thickness of 3n m or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 200 nm or less. More than 50nm.

[0137] As the oxide semiconductor film 108c, an oxide semiconductor film with low carrier density is used. For example, the second oxide semiconductor film 108c has a carrier density of 1×10 17 pieces / cm 3 Below Lower, preferably 1×10 15 pieces / cm 3Less than 1×10, more preferably 13 pieces / cm 3 Less than or equal to 1×10 11 pieces / cm 3 The following applies.

[0138] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of the transistor, the oxide semiconductor film 108b and the oxide semiconductor The carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, and interatomic It is preferable to set the distance, density, etc. appropriately.

[0139] Note that the oxide semiconductor films 108b and 108c each contain impurities. By using an oxide semiconductor film with a low concentration of dopants and a low density of defect states, it is possible to obtain even better electrical properties. In this embodiment, the impurity concentration is low, and A low density of defect levels (low oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film is characterized in that a carrier generation source is Therefore, the carrier density can be reduced. The transistor in which the gate region is formed has electrical characteristics in which the threshold voltage is negative (normal Also, it is rare for the product to become intrinsic or substantially intrinsic. In some oxide semiconductor films, the density of defect states is low, and therefore the density of trap states may also be low. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a significantly low off-state current. It is very small and has a channel width of 1×10 6 μm and the channel length L is 10 μm. When the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, The off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 After A The following characteristics can be obtained.

[0140] Therefore, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is provided with a channel. The transistors in which the regions are formed have small variations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor film are dissipated. It takes a long time for the charge to reach a certain level, and it may behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor film with a high density of trap states has a high current density. Impurities include hydrogen, nitrogen, alkali metals, or Alkaline earth metals, etc.

[0141] Hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. In this case, oxygen vacancies are formed in the lattice from which oxygen has been desorbed (or in the portion from which oxygen has been desorbed). When hydrogen enters the electron carrier, it can generate electrons. It can combine with oxygen, which combines with metal atoms, to generate electrons, which are carriers. A transistor using an oxide semiconductor film containing hydrogen has normally-on characteristics. For this reason, it is preferable that the amount of hydrogen in the oxide semiconductor film 108 be reduced as much as possible. Specifically, in the oxide semiconductor film 108, a hydrogen concentration obtained by SIMS analysis is Degrees, 2 x 10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than or equal to 5×1, more preferably 0 17 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 below Let us assume that.

[0142] In addition, the oxide semiconductor film 108b has a region with a lower hydrogen concentration than the oxide semiconductor film 108c. It is preferable that the oxide semiconductor film 108b has a region larger than the oxide semiconductor film 108c. By having a region with a low hydrogen concentration, a highly reliable semiconductor device can be obtained.

[0143] In addition, in the oxide semiconductor film 108b, silicon and carbon, which are Group 14 elements, If the oxide semiconductor film 108b contains oxygen, oxygen vacancies are increased in the oxide semiconductor film 108b, causing the oxide semiconductor film 108b to become n-type. Therefore, the concentrations of silicon and carbon in the oxide semiconductor film 108b and the oxide semiconductor film 10 The concentration of silicon and carbon near the interface with 8b (concentration obtained by SIMS analysis) is 2× 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following do.

[0144] In addition, in the oxide semiconductor film 108b, the alkali metal or or alkaline earth metal concentration, 1×10 18 atoms / cm 3 Below, preferably 2x 10 16 atoms / cm 3 The following applies: Alkali metals and alkaline earth metals are oxides. When it bonds with a semiconductor, carriers may be generated, increasing the off-state current of the transistor. For this reason, the alkali metal or alkaline earth metal of the oxide semiconductor film 108b may be It is preferable to reduce the concentration of metalloids.

[0145] When the oxide semiconductor film 108b contains nitrogen, electrons that serve as carriers are generated. The carrier density increases and the oxide semiconductor film containing nitrogen is easily converted to n-type. A transistor using the oxide semiconductor film tends to be normally on. In the present invention, it is preferable that the nitrogen content is reduced as much as possible. For example, it is preferable that the nitrogen content is reduced as much as possible by SIMS analysis. The resulting nitrogen concentration is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0146] The oxide semiconductor film 108b and the oxide semiconductor film 108c each have a non-single crystal structure. The non-single crystal structure may be, for example, CAAC-OS (C Axis Alias) which will be described later. gned Crystalline Oxide Semiconductor), polyconductor The non-single crystalline structure includes a crystalline structure, a microcrystalline structure, or an amorphous structure. The defect state density of CAAC-OS is the lowest.

[0147] [Insulating film that functions as the second gate insulating film] The insulating films 114 and 116 function as a second gate insulating film of the transistor 100 . The insulating films 114 and 116 have a function of supplying oxygen to the oxide semiconductor film 108. That is, the insulating films 114 and 116 contain oxygen. The insulating film 114 is an insulating film that can be used to form an insulating film 116 to be formed later. The oxide semiconductor film 108 also functions as a film for reducing damage to the oxide semiconductor film 108 during the formation of the oxide semiconductor film 108.

[0148] The insulating film 114 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm. Silicon oxide, silicon oxynitride, etc., having a thickness of 1 nm or less can be used.

[0149] In addition, it is preferable that the insulating film 114 has a small amount of defects. Typically, the insulating film 114 has a small amount of defects as determined by ESR measurement. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 3×10 17 spins / cm 3 This is because the insulating film 114 is preferably If the density of defects is high, oxygen will be bonded to the defects, and the oxygen in the insulating film 114 will The amount of transmission of the light is reduced.

[0150] In the insulating film 114, all of the oxygen that has entered the insulating film 114 from the outside is Some oxygen does not move to the outside of the insulating film 114 and remains in the insulating film 114. At the same time, oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, In some cases, oxygen may move through the film 114. When the oxide insulating film capable of forming the insulating film 116 is formed over the insulating film 114, The desorbed oxygen can be transferred to the oxide semiconductor film 108 through the insulating film 114. .

[0151] The insulating film 114 is formed using an oxide insulating film having a low density of states caused by nitrogen oxides. Note that the density of states due to the nitrogen oxides can be determined by the valence Energy of the upper edge of the electronic band (Ev_os) and the lower edge of the conduction band of the oxide semiconductor film The oxide insulating film may be formed between the gate electrodes of the SiO_O_2 layer and the gate electrodes of the SiO_O_2 layer. Silicon oxynitride film with low emission or aluminum oxynitride film with low emission of nitrogen oxide For example, a tungsten film or the like can be used.

[0152] In addition, the silicon oxynitride film, which emits a small amount of nitrogen oxide, is This membrane releases more ammonia than nitrogen oxides, and typically releases ammonia. The amount of emission is 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The following is the case. The amount of monia released is determined when the surface temperature of the membrane is 50°C or higher and 650°C or lower, preferably 50°C or higher and 55°C or lower. This is the amount released by heating at 0℃ or below.

[0153] Nitrogen oxides (NO x , x is more than 0 and not more than 2, preferably 1 or more and not more than 2), typically NO or NO forms a level in the insulating film 114 or the like. The level is Therefore, the nitrogen oxide is located in the energy gap of the insulating film 114 and When the oxide semiconductor film 108 diffuses to the interface, the level traps electrons on the insulating film 114 side. As a result, the trapped electrons may wrap around the insulating film 114 and the oxide semiconductor. Since the ions remain near the interface with the semiconductor film 108, the threshold voltage of the transistor is shifted in the positive direction. It will cause.

[0154] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxide contained in the insulating film 116 reacts with ammonia contained in the insulating film 116 during the heat treatment. Therefore, the amount of nitrogen oxide contained in the insulating film 114 is reduced. Electrons are less likely to be trapped at the interface between the oxide semiconductor film 106 and the oxide semiconductor film 108.

[0155] By using the oxide insulating film as the insulating film 114, the threshold voltage of the transistor It is possible to reduce the shift in the electrical characteristics of the transistor. can.

[0156] Heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher and lower than 350° C. By the heat treatment, the insulating film 114 shows the following characteristics in the spectrum obtained by ESR measurement at 100K or less: The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2.001 to 2.002. A second signal with a g value of .003 or less and a third signal with a g value between 1.964 and 1.966, inclusive. A null is observed. Note that the split width of the first signal and the second signal, The split width of the second and third signals is about 5 in the X-band ESR measurement. mT. The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966 The sum of the spin densities of the third signal is 1 × 10 18 spins / cm 3 Less than Typically, it is 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Not yet It is full.

[0157] In the ESR spectrum below 100K, the g value is 2.037 or more and 2.039 or less. The first signal below, the second signal with a g-value between 2.001 and 2.003, and the g-value The third signal, which is between 1.964 and 1.966, is nitrogen oxide (NO x , x is 0 The signal corresponds to a signal caused by nitrogen oxides (greater than 1 and less than 2, preferably 1 or more and less than 2). Representative examples include nitrogen monoxide and nitrogen dioxide. A first signal with a g value of 39 or less, a second signal with a g value of 2.001 to 2.003, and The sum of the spin densities of the third signal with a g value of 1.964 to 1.966 is small. It can be said that the smaller the amount of nitrogen oxide contained in the oxide insulating film, the smaller the amount of nitrogen oxide contained in the oxide insulating film.

[0158] The nitrogen concentration of the oxide insulating film measured by SIMS is 6×10 20 atoms / cm 3 The following is the result.

[0159] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the oxide insulating film by the VD method, a dense and hard film can be obtained. It can be formed.

[0160] The insulating film 116 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. The oxide insulating film containing more oxygen than the stoichiometric composition is formed using When heated, some of the oxygen is released. The oxygen content is greater than the stoichiometric composition. The oxide insulating film had a loss of oxygen of 1.0×10 in terms of oxygen atoms as determined by TDS analysis. 1 9 atoms / cm 3More than 3.0×10 20 atoms / cm 3 That's all. The oxide insulating film is used. The surface temperature of the film in the above TDS is 100°C or higher and 70°C or lower. A temperature range of 0° C. or lower, or 100° C. to 500° C. is preferred.

[0161] The insulating film 116 has a thickness of 30 nm to 500 nm, preferably 50 nm or more. Silicon oxide, silicon oxynitride, etc., having a thickness of 400 nm or less can be used.

[0162] In addition, it is preferable that the insulating film 116 has a small amount of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5×10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 Note that the insulating film 116 is preferably an oxide semiconductor compared to the insulating film 114. Since it is separated from the insulating film 108, it may have a higher defect density than the insulating film 114.

[0163] In addition, the insulating films 114 and 116 can be made of the same material, so that the insulating films In some cases, the interface between the film 114 and the insulating film 116 cannot be clearly seen. In this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a dashed line. In the embodiment, the two-layer structure of the insulating film 114 and the insulating film 116 has been described. For example, the insulating film 114 may have a single-layer structure without being limited thereto.

[0164] [An oxide semiconductor film functioning as a pixel electrode and an oxide semiconductor film functioning as a second gate electrode] Semiconductor film] The oxide semiconductor film 120a functions as a pixel electrode, and the oxide semiconductor film 120b functions as a second gate electrode. The oxide semiconductor film 120b may be formed using the same material as the oxide semiconductor film 108 described above. The same manufacturing method can be used to form the same.

[0165] Alternatively, the oxide semiconductor film 120a serving as a pixel electrode and the oxide semiconductor film 120b serving as a second gate electrode may be formed of a The oxide semiconductor film 120b that functions as the oxide semiconductor film 108 described above can be used as the oxide semiconductor film 120b. For example, the oxide semiconductor films 120a and 120b each include In oxide, In-Sn oxide, In-Zn oxide, In-Ga oxide, Zn oxide , Al-Zn oxide, or In-Ga-Zn oxide, etc. can be used. It is preferable to use In--Sn oxide or In--Ga--Zn oxide.

[0166] Specifically, the oxide semiconductor films 120a and 120b are made of indium gallium zinc oxide. oxide (IGZO), indium tin oxide (ITO), indium zinc oxide, indium A light-transmitting conductive material such as tin silicon oxide (ITSO) can be used.

[0167] That is, the oxide semiconductor film 120a functioning as a pixel electrode and the second gate electrode The oxide semiconductor film 120b that functions as the oxide semiconductor film 108 (the oxide semiconductor film 108 b and the oxide semiconductor film 108c). For example, The oxide semiconductor film 120b serving as a second gate electrode and the oxide semiconductor film 108 (oxide The nitride semiconductor film 108b and the oxide semiconductor film 108c have the same metal element. This makes it possible to reduce manufacturing costs.

[0168] For example, the oxide semiconductor film 120a serving as a pixel electrode and the oxide semiconductor film 120b serving as a second gate electrode In the case of In-M-Zn oxide, the oxide semiconductor film 120b that functions as a The atomic ratio of metal elements in the sputtering target used to form a Zn oxide film is as follows: It is preferable that In≧M is satisfied. The molecular ratio was In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M: Zn=4:2:4.1 etc.

[0169] In addition, the oxide semiconductor film 120a functions as a pixel electrode, and the oxide semiconductor film 120b functions as a second gate electrode. The structure of the oxide semiconductor film 120b that functions is a single layer structure or a stacked structure of two or more layers. In the case where the oxide semiconductor films 120a and 120b have a stacked-layer structure, The composition of the sputtering target is not limited to the above. The case where 120b has a laminated structure will be described later.

[0170] [Insulating film that functions as a protective insulating film for transistors] The insulating film 118 functions as a protective insulating film for the transistor 100 .

[0171] The insulating film 118 contains either hydrogen or nitrogen, or both. The insulating film 118 contains nitrogen and silicon. The insulating film 118 contains oxygen, hydrogen, water, and alkali. The insulating film 118 has a function of blocking metals, alkaline earth metals, etc. As a result, oxygen diffuses from the oxide semiconductor film 108 to the outside, and oxygen contained in the insulating films 114 and 116 is prevented from diffusing. The diffusion of oxygen from the outside and the entry of hydrogen, water, and the like into the oxide semiconductor film 108 from the outside are prevented. It can be prevented.

[0172] The insulating film 118 is formed on the oxide semiconductor film 120a functioning as a pixel electrode and the second The oxide semiconductor film 120b serving as a gate electrode may contain either hydrogen or nitrogen. In particular, the insulating film 118 contains hydrogen and converts the hydrogen into oxygen. It is preferable that the insulating film 118 has a function of supplying the insulating film 118 to the semiconductor films 120a and 120b. When hydrogen is supplied to the oxide semiconductor films 120a and 120b, the oxide semiconductor films 120a , 120b function as a conductor.

[0173] The insulating film 118 may be, for example, a nitride insulating film. Examples include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. etc.

[0174] Note that the various films described above, such as the conductive film, the insulating film, and the oxide semiconductor film, are formed by sputtering. It can be formed by the CVD method or PECVD method, but other methods such as thermal CVD (Ch Alternatively, the insulating layer may be formed by thermal CVD. As an example of the method, MOCVD (Metal Organic Chemical Vapor Deposition) Deposition method and ALD (Atomic Layer Deposition) method n) method may also be used.

[0175] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no additional steps are required.

[0176] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the reactants near or on the substrate under reduced pressure and depositing the reactants on the substrate. You may go.

[0177] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating the gas introduction sequence. For example, by switching between two or more switching valves (also called high-speed valves), The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so as not to mix the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the feed gas. In addition, when an inert gas is introduced at the same time, the inert gas is The second source gas may be introduced simultaneously with the introduction of the inert gas. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction sequence until a thin film of the desired thickness is formed. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film depends on the order of gas introduction. The thickness can be precisely adjusted by changing the number of times the process is repeated. This is suitable for producing thin FETs.

[0178] Thermal CVD methods such as MOCVD and ALD can be used to form the conductive film, insulating film, and oxide film of the above-mentioned embodiment. It is possible to form various films such as semiconductor films and metal oxide films. For example, In-Ga-Zn When forming an O film, trimethylindium, trimethylgallium, and dimethylzinc are used. Lead is used. The chemical formula for trimethylindium is In(CH3)3. The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for dimethylzinc is is Zn(CH3)2. In addition, the combination is not limited to these, and trimethylgalactan Triethylgallium (chemical formula Ga(C2H5)3) can be used instead of diethylgallium. Diethylzinc (chemical formula Zn(C2H5)2) can be used instead of methylzinc.

[0179] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is made by vaporizing hafnium amide (such as TDMAH) and acid. Two types of gases are used: tetrakisdimethylamide (TDA) and ozone (O3). The chemical formula for fluorine is Hf[N(CH3)2]4. Other liquid materials include tetrahydrofuran. Examples include rakis(ethylmethylamido)hafnium.

[0180] For example, when forming an aluminum oxide film using an ALD deposition system, A liquid containing a catalyst and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) is added. Two types of gases are used: vaporized source gas and H2O as an oxidizing agent. The chemical formula for aluminum is Al(CH3)3. Other liquid materials include Tris( Dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2 ,2,6,6-tetramethyl-3,5-heptanedionate).

[0181] For example, when forming a silicon oxide film using a deposition system that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, the chlorine contained in the adsorbed matter is removed, and the oxidizing gas (O 2. Nitrous oxide (NO) radicals are supplied to react with the adsorbed material.

[0182] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film was formed by repeatedly introducing B2H6 gas and WF A tungsten film is formed using B2H6 gas and H2 gas. iH4 gas may also be used.

[0183] For example, an oxide semiconductor film, such as In-Ga-ZnO, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- An O layer is formed, and then a GaO layer is formed using Ga(CH3)3 gas and O3 gas. After that, a ZnO layer is formed using Zn(CH3)2 gas and O3 gas. The order of these layers is not limited to this example. In addition, by mixing these gases, In-Ga-O layers and In A mixed compound layer such as a -Zn-O layer or a Ga-Zn-O layer may be formed. Instead of H, H2O gas obtained by bubbling with an inert gas such as Ar may be used. It is preferable to use O3 gas that does not contain In. (C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, Ga(C2 H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

[0184] <1-5. Configuration example 2 of semiconductor device> Next, examples of a configuration different from that of the transistor 100 shown in FIGS. This will be explained using 2(A),(B), and(C).

[0185] FIG. 2A is a top view of a transistor 150 which is a semiconductor device of one embodiment of the present invention. 2B corresponds to a cross-sectional view taken along dashed line X1-X2 in FIG. 2A. FIG. 2(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 2(A). Correct.

[0186] The transistor 150 has an opening 152 in the channel width direction of the transistor 100 shown above. The difference is that the transistors 152b and 152c are provided. 00 and has the same effect. We will explain about this.

[0187] As shown in FIG. 2C, the oxide semiconductor film 120b functioning as the second gate electrode is , the insulating films 106, 107, and the openings 152b, 15 2c, it is connected to the conductive film 104 which functions as the first gate electrode. The oxide semiconductor film 104 and the oxide semiconductor film 120b are supplied with the same potential.

[0188] In this embodiment, the openings 152b and 152c are provided to separate the conductive film 104 and the oxide film 105. However, the present invention is not limited to this. For example, only one of the openings 152b and 152c is formed, and the conductive film The oxide semiconductor film 104 may be connected to the oxide semiconductor film 120b. Unlike the transistor 100, the conductive film 104 and the oxide semiconductor film 120b are not connected. In this case, different potentials are applied to the conductive film 104 and the oxide semiconductor film 120b. This can be done.

[0189] As shown in FIG. 2B, the oxide semiconductor film 108 functions as a first gate electrode. The conductive film 104 functions as a second gate electrode, and the oxide semiconductor film 120b functions as a second gate electrode. The second gate electrode is sandwiched between two films that function as gate electrodes. The length in the channel length direction and the channel width of the oxide semiconductor film 120b functioning as the gate electrode of the The length in the channel width direction is the length in the channel length direction of the oxide semiconductor film 108 and the The length of each of the insulating films 114 and 116 is longer than that of the entire oxide semiconductor film 108. The oxide semiconductor film 120b is formed on the oxide semiconductor layer 120c and serves as a second gate electrode. The semiconductor film 120b and the conductive film 104 functioning as the first gate electrode are connected to an insulating film 106. , 107, and the insulating films 114, 116 are provided with openings 152b, 152c. Therefore, the side surfaces of the oxide semiconductor film 108 in the channel width direction are covered with the insulating films 114 and 116. The second gate electrode 120b faces the oxide semiconductor film 120b functioning as the second gate electrode with a gate electrode therebetween.

[0190] In other words, in the channel width direction of the transistor 150, The conductive film 104 and the oxide semiconductor film 120b functioning as the second gate electrode are Insulating films 106 and 107 functioning as a first gate insulating film and a second gate insulating film The insulating films 114 and 116 are connected to each other through openings, and the first gate The insulating films 106 and 107 function as first gate insulating films, and the insulating film 108 function as a second gate insulating film. The oxide semiconductor film 108 is surrounded by insulating films 114 and 116 therebetween.

[0191] With such a structure, the oxide semiconductor film 108 included in the transistor 150 The conductive film 104 functions as a first gate electrode and the conductive film 105 functions as a second gate electrode. The transistor 150 can be electrically surrounded by the electric field of the oxide semiconductor film 120b. As described above, a channel region is formed by the electric field of the first gate electrode and the second gate electrode. The device structure of the transistor that electrically surrounds the oxide semiconductor film is called the Surround This can be called an ed channel (S-channel) structure.

[0192] Since the transistor 150 has an S-channel structure, the first gate electrode The conductive film 104 functions as a gate insulating film, and the electric field for inducing the channel is effectively applied to the oxide semiconductor. This allows the current drive capability of the transistor 150 to be improved. It is possible to obtain high on-current characteristics. It is also possible to increase the on-current. Therefore, it is possible to miniaturize the transistor 150. The conductive film 104 functions as a first gate electrode and the oxide film 105 functions as a second gate electrode. Since the transistor 150 has a structure surrounded by the nitride semiconductor film 120b, Strength can be increased.

[0193] <1-5-1.Effects of S-channel structure> In the following, we will discuss a transistor having an oxide semiconductor (hereafter referred to as OS-FET) and a low-temperature Transistors with silicon (hereafter referred to as LTPS (Low Temperature Polysilicon) Effects obtained by using an S-channel structure for a y-Silicon (FET) This article explains:

[0194] <1-5-2. Improving current driving power (field effect mobility)> First, by adopting an S-channel structure, The current density distribution in the junction was calculated. The structure used for the calculation is shown in Figure 66(A). The calculation results of the intensity distribution are shown in FIG.

[0195] As shown in FIG. 66(A), the structure used in the calculation is an oxide semiconductor (OS) film. The oxide semiconductor film has a thickness of 35 nm, and gate electrodes are located above and below the oxide semiconductor film. The length from the gate electrode to the oxide semiconductor film was set to 250 nm. The length to the semiconductor film was set to 450 nm. The channel length of the oxide semiconductor film was set to 10 μm. The length of the source electrode and the drain electrode in contact with the oxide semiconductor film is 1 μm. The oxide semiconductor film was InGaZnO. The voltage (Vg) applied to the electrodes was set to 0.5V.

[0196] FIG. 66B shows the direction of the arrow A1-A2 shown in FIG. 66A, that is, the direction of the oxide semiconductor. The current density distribution in the thickness direction of the conductor film is shown in FIG. 66(B). It can be seen that the current density distribution is roughly uniform in the thickness direction of the membrane. It is suggested that this is because the FET is an accumulation type FET with an intrinsic channel and the active layer is thin. can be.

[0197] Next, the improvement of the field-effect mobility of OS-FET will be explained using Figures 67(A) and 67(B). Reveal.

[0198] The field-effect mobility of the OS-FET was calculated using a device simulator. The structure used in the calculation is shown in Figure 67(A). The main parameters used in the calculation are The channel length was 6 μm, the channel width was 50 μm, and the oxide semiconductor used in the channel region was The conductor is InGaZnO, and its thickness is 35 nm. The thickness of the insulating film was set to 280 nm, and the thickness of the upper gate insulating film was set to 480 nm. The mobility of nGaZnO is 10cm 2 / Vs.

[0199] The calculation was performed under two conditions. Condition 1 was that the upper gate electrode The upper gate electrode is connected to the lower gate electrode, and 0 V is applied to the upper gate electrode. A voltage of 10 V is applied to the gate electrode and 10 V (Vd=10 V) is applied to the drain electrode. The above condition 1 is sometimes called Bottom Gate Driving.

[0200] Condition 2 is that the upper gate electrode and the lower gate electrode are connected, and the upper gate electrode The lower gate electrode is applied with 10 V, the drain electrode with 10 V (Vd=10 V), The above condition 2 is called Dual Gate Driving. There is a match.

[0201] The calculation results of the field effect mobility of the OS-FET under the above conditions 1 and 2 are shown in Figure 67(B). In FIG. 67(B), the solid line represents the drain current (Id), and the dashed line represents the field effect mobility ( μFE) are shown respectively.

[0202] As shown in FIG. 67(B), the upper gate electrode and the lower gate electrode are not connected. Compared with Bottom Gate Driving, the upper gate electrode and the lower gate In the dual gate driving configuration, The resultant mobility is improved by more than two times. In the configuration where the and are not connected (Bottom Gate Driving), The calculated result was lower than the mobility of InGaZnO, which was the parameter used.

[0203] In this way, the OS-FET has gate electrodes above and below the oxide semiconductor. The gate electrode of the upper gate is connected to the gate electrode of the lower gate to form a dual gate driving This increases the field effect mobility more than Bottom Gate Driving. It was shown that.

[0204] <1-5-3. Suppression of characteristic variations> Next, the Single Gate structure and the S-channel structure are The variation in Id-Vg characteristics due to the variation in donor density was calculated.

[0205] The calculation conditions were Vd=10 V, and an OS-FET was used as the calculation model.

[0206] The calculation results are shown in Figure 68(A)(B). Note that Figure 68(A) is for Single Gate Figure 68(A) shows the calculation results for the S-channel structure, and Figure 68(B) shows the calculation results for the S-channel structure.

[0207] As shown in Figure 68(A) and (B), by using an S-channel structure, the donor density The amount of negative shift and the variation in threshold voltage (Vth) caused by Single Ga It can be seen that the capacitance is reduced to about half that of the te structure. S-channel structure This increases the gate capacitance, which leads to an increase in the threshold voltage (Vth) of the transistor. This suggests that the fluctuation in the

[0208] In addition, if the negative shift of Vth of the channel portion is -ΔVth, -ΔVth is expressed as follows: Charge amount Q due to donor impurities D and the gate capacitance C OX Specifically, For -ΔVth=-(Q D / C OX ) can be expressed as

[0209] By using the S-channel structure, the gate capacitance increases. The amount of the gate insulating film on the lower side and the gate insulating film on the upper side is the sum of the two, that is, "C OX =C OX1 +C OX2 " Note that C ox1 is the gate capacitance of the upper gate insulating film, and C ox2 but The gate capacitance of the lower gate insulating film is shown. Therefore, even if the impurity density in the channel varies, the threshold voltage (Vth) does not vary. can be reduced.

[0210] Next, the LTPS-FET will be described. First, an LTPS-FET is fabricated and the L We compared the Vth variation of TPS-FETs. The evaluation results of the variations are shown in Figures 69(A) and (B) and Figures 70(A) and (B).

[0211] FIG. 69(A) shows the Sing of an n-ch FET with an L length of 3 μm and a W length of 6 μm. The probability distribution of the threshold voltage (Vth) of the le Gate structure is shown in Fig. 69(B) for an L length of 3 The threshold voltage (V 70(A) shows the probability distribution of the L length of 3 μm and the W length of 6 μm. Probability of threshold voltage (Vth) of single gate structure of p-ch FET in μm The distribution of the S-ch of a p-ch FET with an L length of 3 μm and a W length of 6 μm is shown in FIG. The probability distribution of the threshold voltage (Vth) of the tunnel structure is shown in Fig.

[0212] As shown in Figures 69(A)(B) and 70(A)(B), in the LTPS-FET However, by using the S-channel structure, the threshold voltage (Vth) of the transistor can be It can be confirmed that the variation can be suppressed.

[0213] Next, we will examine the Id-Vg characteristics in the subthreshold region of LTPS-FET. The variance was calculated.

[0214] The calculation conditions for the Id-Vg characteristics in the subthreshold region are The channel length of the LTPS was 6 μm and the channel width was 10 μm. Mobility of the electrons is 300 cm 2 / Vs, Hall mobility at 30cm 2 / Vs, film thickness 50 nm In addition, the electron mobility of the grain boundaries of LTPS was increased to 30 cm 2 / Vs, Hall mobility 3cm 2 / Vs, the LTPS film thickness was 50 nm, and the grain boundary width of the LTPS was 100 nm. The doping concentration in the / D region is 5×10 18 cm -3 , doping in the channel region The concentration of the dye is 1×10 15 cm -3 In addition, the relative dielectric constant of the upper and lower gate insulating films is The thickness of the upper and lower gate insulating films was set to 300 nm. The energy function was set to 4.1 eV, and the voltage (Vd) applied to the drain electrode was set to 3 V.

[0215] Figure 71(A) and (B) show the variation of Id-Vg characteristics in the subthreshold region. The calculation results are shown in Fig. 71(A) and Fig. 71(B) show the calculation results for the Single Gate structure. 71(B) shows the calculation results for the S-channel structure. The LTPS grain boundary is configured to have one in the channel, and the position of the grain boundary is The nine patterns were arranged from the vicinity of the edge of the source electrode to the vicinity of the edge of the drain electrode. Therefore, nine Id-Vg characteristics are shown in FIGS. 71(A) and 71(B).

[0216] As shown in Figure 71(A) and (B), the threshold voltage is However, the negative shift of the voltage (Vth) caused by the grain boundaries is suppressed. It can be seen that there is no significant change in the characteristic variations in the subthreshold region.

[0217] <1-5-4.NBTS resistance in S-channel structure> Next, we investigated the NBTS( Negative Bias Temperature Stress (NBS) resistance The calculations were done.

[0218] The structure used in the calculation is shown in Figure 72(A)(B). Note that Figure 72(A) shows the structure of LTPS-F FIG. 72(B) is the structure used in the calculation of OS-FET. do.

[0219] In FIG. 72(A), the thickness of the Poly-Si is set to 50 nm. The thickness of the gate electrode (Bottom Gate) located below the The thickness of the gate electrode (Top Gate) located on the upper side of the ly-Si was set to 100 nm. In addition, there is an insulator between the bottom gate and the polysilicon. The insulating film had a thickness of 300 nm. An insulating film is provided between the gate and the poly-Si. The thickness of the insulating film is 300 nm. It was decided.

[0220] In FIG. 72B, the thickness of the OS is set to 50 nm, and the gate electrode located under the OS is The thickness of the bottom gate electrode is 100 nm. The thickness of the bottom gate electrode (B An insulating film is provided between the ottom gate and the OS, and the thickness of the insulating film is 300 nm. m. An insulating film was provided between the top gate electrode and the OS. The thickness of the insulating film was set to 300 nm.

[0221] The upper gate electrode (Top Gate) and the lower gate electrode (Bottom Gate) The calculation conditions were set assuming NBTS, with -10 V applied to each of the gates.

[0222] The calculation results of the potential distribution in the film thickness direction when NBTS is applied are shown in Figure 73(A)(B). Note that Figure 73(A) shows the calculation results for the LTPS-FET, and Figure 73(B) shows the results for the OS -FET calculation results.

[0223] As shown in FIG. 73(A), in the LTPS-FET, the upper gate electrode (Top The potential between the gate electrode and the bottom gate is In other words, an electric field is generated in the Poly-Si, and the upper The gate electrode (Top Gate) and the lower gate electrode (Bottom Gate) Even if the voltage applied to both is turned off, stress due to the electric field is applied to the Poly-Si. This suggests that LTPS-EFT is due to inversion, which generates minority carriers.

[0224] On the other hand, as shown in FIG. 73(B), in the OS-FET, the upper gate electrode (T The potential between the upper gate and the lower gate The potential is not changing or is roughly constant. The top gate and the bottom gate are at the same potential. This suggests that no electric field is applied to the OS and the insulating film. It is suggested that the NBTS resistance can be significantly improved by using a channel structure.

[0225] <1-5-5. Length of W in the S-channel structure> Next, the length of the S-channel structure in the W direction will be explained. The transistors shown in FIG. 74 and FIG. 75 were fabricated, and the PBTS (Positive-Si A tive Bias Temperature Stress (TBS) test was conducted.

[0226] FIG. 74(A) is a top view of transistor 400, and FIG. 74(B) is a top view of transistor 400. FIG. 74(C) corresponds to a cross-sectional view taken along the dashed line X1-X2 in FIG. 74(A). This corresponds to a cross-sectional view of the cut surface taken along dashed dotted line Y1-Y2 shown in FIG.

[0227] 75A is a top view of a transistor 400A, and FIG. 75B is a top view of a transistor 400B shown in FIG. 5(A) corresponds to a cross-sectional view taken along the dashed line X1-X2 in FIG. 75(C). 5(A) along dashed line Y1-Y2.

[0228] The transistor 400 and the transistor 400A include a conductive film 404 over a substrate 402, Insulating films 406 and 407 over the conductive film 404, and an oxide semiconductor film 408 over the insulating film 407, The conductive film 412a electrically connected to the oxide semiconductor film 408 and the oxide semiconductor film 408 The conductive film 412b, the oxide semiconductor film 408, the conductive film 412a, and the conductive film 412b are electrically connected to each other. The insulating films 414 and 416 on the conductive film 412b, the conductive film 420 on the insulating film 416, and the insulating film 4 16 and an insulating film 418 on a conductive film 420.

[0229] Note that in the transistors 400 and 400A, the oxide semiconductor film 408 is an oxide semiconductor. The oxide semiconductor film 408a is a laminated structure of an oxide semiconductor film 408b on the oxide semiconductor film 408a. In the transistors 400 and 400A, the conductive film 404 is a first gate electrode. The conductive film 420 functions as a second gate electrode. In the transistors 400 and 400A, the insulating films 406 and 407 are first gate insulating films. The insulating films 414 and 416 function as a second gate insulating film. In the transistors 400 and 400A, the conductive film 412a serves as a source electrode. The conductive film 412b functions as a drain electrode.

[0230] The transistor 400 shown in FIG. 74(A), (B), and (C) and the transistor 400 shown in FIG. The length of the conductive film 420 in the channel width W direction is different from that of the transistor 400A shown in FIG. The configuration other than the conductive film 420 is the same.

[0231] Specifically, in the transistor 400 shown in FIG. In the direction of the gate electrode, the conductive film 420 functioning as the second gate electrode is a W film of the oxide semiconductor film 408. On the other hand, the transistor 400 shown in FIG. In A, the conductive film 420 functioning as the second gate electrode is oxidized in the W length direction. In other words, in the transistor 400A, In this case, the side surface of the oxide semiconductor film 408 in the W direction is formed as a conductive film serving as a second gate electrode. The conductive film 420 covers the semiconductor layer, that is, the S-channel structure.

[0232] Note that the conductive film, the insulating film, and the oxide semiconductor film included in the transistors 400 and 400A are The structure was as follows:

[0233] The conductive film 404 is a tungsten film having a thickness of 200 nm, and the conductive film 420 is a tungsten film having a thickness of 100 nm. The conductive films 412a and 412b were made of tungsten films having a thickness of 50 nm. The laminated structure was a 400 nm thick aluminum film and a 200 nm thick titanium film. The oxide semiconductor film 408a is a 35-nm-thick IGZO film (In:Ga:Zn=3: 1:2 [atomic ratio]), and the oxide semiconductor film 408b is a 15-nm-thick IGZO film (In The atomic ratio of the insulating film 406 was 400 nm. The insulating film 407 was a silicon oxynitride film having a thickness of 50 nm. The insulating film 414 is a silicon oxynitride film having a thickness of 50 nm, and the insulating film 416 is a silicon oxynitride film having a thickness of 400 nm. The insulating film 418 was a silicon oxynitride film having a thickness of 100 nm. It was decided.

[0234] PBT of a transistor equivalent to the transistor 400 shown in FIG. The Id-Vg characteristics before and after the S test are shown in Figure 76(A), and the transistors shown in Figures 75(A), (B), and (C) are shown in Figure 76(B). Figure 76(a) shows the Id-Vg characteristics of a transistor equivalent to a 400A transistor before and after the PBTS test. B) are shown respectively.

[0235] In FIG. 76(A) and (B), the first vertical axis represents Id, the second vertical axis represents μFE, and the horizontal axis represents In addition, in FIG. 76(A) and (B), the solid line indicates the voltage before the stress test and the voltage after the break. The lines show the results after the stress test.

[0236] As shown in FIG. 76(A), a conductive film 420 functioning as a second gate electrode is made of an oxide. In the structure where the side surface of the semiconductor film 408 is not covered, the Id-Vg characteristics after the PBTS test On the other hand, as shown in FIG. 76(B), the second gate electrode and The conductive film 420 functions as a conductive film that covers the side surface of the oxide semiconductor film 408. In the channel structure, there is no change in the Id-Vg characteristics after the PBTS test, or It can be seen that there is very little change in the Id-Vg characteristics.

[0237] The phenomenon of the deterioration of the Id-Vg characteristics shown in Figures 76(A) and 76(B) is due to the island-shaped oxide semiconductor. This is because the side end of the semiconductor film 408 becomes n-type, and a parasitic channel is generated in the transistor 400. It is suggested that.

[0238] <1-5-6. Vd dependence of Id-Vg characteristics> Next, a transistor corresponding to the transistor 400A shown in FIG. (S-channel structure transistor) and the second gate of the transistor 400A. A transistor (single gate transistor) in which the conductive film 420 functioning as a gate electrode is not formed (a transistor with a MOSFET structure) and fabricated a transistor with a Vd Dependence was assessed.

[0239] Note that the insulating film, the conductive film, and the oxide semiconductor film used in the transistor fabricated here were Please refer to <1-5-5. Length in the W direction in the S-channel structure>. The transistor size was the same as that of the previous structure. The channel width W was set to 50 μm.

[0240] The Id-Vg characteristics of the transistor fabricated above were evaluated. The measurements were performed under two conditions: Vd=0.1V and Vd=10V.

[0241] Figures 77(A) and (B) show the Id-Vg characteristics of the transistor. is the result for a transistor with a Single Gate structure, and Fig. 77(B) is the result for an S-cha This is the result of a transistor with a n-type structure.

[0242] As shown in Figure 77(A), in the single gate structure, different Vd voltages The threshold voltage rise characteristics differ depending on the In the e structure, a negative shift in threshold voltage is observed. When a voltage of 10 V was applied, the negative shift of the threshold voltage was remarkable. do.

[0243] The above phenomenon is called DIBL (Drain-Induced Barrier Lowering). The DIBL effect is a phenomenon in which the drain field increases the This is a phenomenon in which the band barrier between the junction and the channel is lowered.

[0244] On the other hand, as shown in FIG. 77(B), in the S-channel structure, different Vd The threshold voltage rise characteristic is roughly the same regardless of the voltage. It is suggested that this is due to blocking by the gate electrode underneath.

[0245] Next, we evaluated the Vd dependence of the Id-Vg characteristics for LTPS-FET. The LTPS-FET is an nch transistor with L / W=6 / 50μm size. A p-channel transistor with L / W=6 / 50 μm was fabricated. The structure is the Single Gate structure explained above, and the S-channel structure. did.

[0246] The Id-Vg characteristics of the LTPS-FET are shown in Figures 78(A)(B) and 79(A(B) ) is shown in Fig. 78(A). Note that Fig. 78(A) shows the Id-Vg characteristics of the single gate structure of nch. Figure 78(B) shows the Id-Vg characteristics of the S-channel structure of nch. Figure 79(A) shows the Id-Vg characteristics of a pch Single Gate structure. FIG. 79(B) shows the Id-Vg characteristic results for the pch S-channel structure.

[0247] As shown in Figures 78(A)(B) and 79(A)(B), in the LTPS-FET, As with OS-FET, the single gate structure is made into an S-channel structure. This makes it possible to suppress the variation in threshold voltage rise characteristics at different Vd. In other words, by using the S-channel structure in the LTPS-FET, The IBL effect can be suppressed.

[0248] In addition, as shown in Figures 78(A)(B) and 79(A)(B), In the same way as the OS-FET, the single gate structure is changed to an S-channel structure. By doing so, it can be confirmed that the field effect mobility is improved. By adopting the S-channel structure, the field effect mobility is approximately 1.6 times higher. It can be seen that.

[0249] <1-5-7. Saturation of Id-Vd characteristics> Next, we investigated the Id-Vd characteristics of the single gate structure and the S-channel structure. The saturation property in the above will be explained.

[0250] A transistor (S-) corresponding to the transistor 400A shown in FIG. A second gate voltage Vcc of the transistor 400A is provided. A transistor in which the conductive film 420 functioning as an electrode is not formed (single gate structure) The saturation of the Id-Vd characteristics of the transistor was investigated. The evaluation was carried out.

[0251] Note that the insulating film, the conductive film, and the oxide semiconductor film used in the transistor fabricated here were Please refer to <1-5-5. Length in the W direction in the S-channel structure>. The transistor size was the same as that of the previous structure. The channel width W was set to 50 μm.

[0252] The Id-Vd characteristics of the single gate structure and the S-channel structure are shown in Fig. 8. 0(A)(B). Note that Figure 80(A) shows the Id-Vd Figure 80(B) shows the Id-Vd characteristics of the S-channel structure. do.

[0253] As shown in Figure 80(A) and (B), by using an S-channel structure, Id-Vd It can be seen that the saturation of the characteristics is improved. This is because the DIBL effect mentioned above is suppressed. In the single gate structure OS-FET, the DIB Due to the L effect, when the drain voltage is high, the drain The in-current (Id) increases.

[0254] By improving the saturation of the Id-Vd characteristic, for example, a display having an organic EL element The device can be suitably used as a driving FET for the device.

[0255] Next, regarding the saturation of the Id-Vd characteristics in LTPS-FET, Fig. 81(A)(B )(C) and Figures 82(A)(B)(C).

[0256] Figures 81(A)(B)(C) and 82(A)(B)(C) show the I The d-Vd characteristics are shown in Fig. 81(A) for a single Ga FIG. 81(B) shows the Id-Vd characteristic results of a transistor with a te structure, where L / W=10 / The Id-Vd characteristics of a 3 μm single gate transistor are shown in Fig. 8. 1(C) is the Id The results are shown in Fig. 82(A) for the S-channel with L / W = 6 / 3 μm. The Id-Vd characteristic results of the transistor with the l structure are shown in FIG. 82(B), where L / W=10 / 3. The Id-Vd characteristics of a transistor with an S-channel structure of 1.5 μm are shown in Fig. 82(C ) is the Id-Vd characteristic of an S-channel transistor with L / W=50 / 3μm Here are the results.

[0257] As shown in Figures 81(A)(B)(C) and 82(A)(B)(C), LTPS- In FETs, the DIBL effect can be suppressed by using an S-channel structure. It can be confirmed that the saturation of the Id-Vd characteristics is improved. Unlike S-FET, the drain voltage (Vd) increases, The phenomenon that the current increases again is confirmed. In particular, in transistors with short L, the drain The phenomenon in which the current increases again is clearly observed.

[0258] The above phenomenon occurs when hot carriers (holes) are generated due to an increase in the drain electric field. This is thought to be due to avalanche breakdown (impact ionization) occurring at the edge of the This is because the silicon used in LTPS has a higher band gap than the oxide semiconductor film. This is believed to be because the effect of impact ionization is large due to the small gap.

[0259] <1-5-8. About S value> Next, we compare the single gate transistor and the S-channel transistor. The S value of the transistor was calculated. The S value is the difference between the source electrode and the drain electrode. is the gate voltage required to increase the current (subthreshold current) by an order of magnitude. The smaller the S value, the larger the slope of the subthreshold current with respect to the gate voltage, and the It has excellent etching characteristics.

[0260] Single Gate structure transistor and S-channel structure transistor The calculation results of the Id-Vg characteristics of the Si capacitor are shown in FIG. The solid line is the result of the single gate structure, and the solid line is the result of the S-channel structure transistor. This is the result of Id-Vg characteristics.

[0261] In addition, the S value is calculated assuming an OS-FET and a transistor size of L / W=2 / 50μm.

[0262] As shown in Figure 83, the S-channel structure can reduce the S value. This is because the S-channel structure allows the choke to be controlled by the electric fields of the upper and lower gates. This is thought to be due to improved controllability of the channel.

[0263] Here, the above-described OS-FET and LTPS-FET are of S-channel structure. The effects of doing so are summarized in Table 1.

[0264] [Table 1]

[0265] As shown in Table 1, by using the S-channel structure in LTPS-FETs, Although several effects are expected, the OS-FET has an S-channel structure. There are many benefits to be gained.

[0266] <1-6. Configuration example 3 of semiconductor device> Next, examples of a configuration different from that of the transistor 100 shown in FIGS. This will be explained using 3(A),(B), and(C).

[0267] FIG. 3A is a top view of a transistor 160 which is a semiconductor device of one embodiment of the present invention. 3B corresponds to a cross-sectional view taken along dashed line X1-X2 in FIG. 3A. FIG. 3(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 3(A). Correct.

[0268] The transistor 160 is a combination of the transistor 100 shown above and an oxide layer that functions as a pixel electrode. The gate electrode is made of an oxide semiconductor film 120a and an oxide semiconductor film 120b that functions as a second gate electrode. The other configurations are the same as those of the transistor 100, and the same effects are obtained. The following describes the configurations that are different from the transistor 100.

[0269] The oxide semiconductor film 120a of the transistor 160, which functions as a pixel electrode, is The semiconductor layer 120a has a laminated structure of a nitride semiconductor film 120a_1 and an oxide semiconductor film 120a_2. The oxide semiconductor film 120b serving as a second gate electrode of the transistor 160 120b_1 and an oxide semiconductor film 120b_2 are stacked on top of each other.

[0270] The oxide semiconductor film 120a and the oxide semiconductor film 120b are formed into a stacked structure, so that the insulating Oxygen can be suitably introduced into the insulating film 116. By forming the insulating film 118 and the oxide semiconductor film 120b into a stacked structure, hydrogen contained in the insulating film 118 can be prevented from being generated. Therefore, it is possible to prevent the intrusion of the insulating film 116.

[0271] The oxide semiconductor film 120a_1 and the oxide semiconductor film 120b_1 are formed using a It is preferable that the atomic ratio of the metal elements in the sputtering target satisfies In≦M. The atomic ratio of the metal elements in such a sputtering target is In:M:Zn= 1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M :Zn=1:3:4, In:M:Zn=1:3:6, etc.

[0272] The oxide semiconductor film 120a_2 and the oxide semiconductor film 120b_2 are formed using a It is preferable that the atomic ratio of the metal elements in the sputtering target satisfies In≧M. The atomic ratio of the metal elements in such a sputtering target is In:M:Zn= 1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M :Zn=3:1:2, In:M:Zn=4:2:4.1, etc.

[0273] In addition, when the oxide semiconductor films 120a and 120b have a two-layer structure, the oxide semiconductor film The flow rate of the oxygen gas used to form the first oxide semiconductor film is set higher than that of the oxygen gas used to form the first oxide semiconductor film. The flow rate of the oxygen gas used to form the first oxide semiconductor film is preferably large. By increasing the amount of oxygen, oxygen can be suitably added to the insulating film 116. By reducing the flow rate of oxygen gas when the oxide semiconductor film is formed, The resistance can be lowered.

[0274] By configuring the oxide semiconductor film 120a and the oxide semiconductor film 120b as described above, Furthermore, a semiconductor device with excellent reliability can be provided.

[0275] <1-7. Configuration example 4 of semiconductor device> Next, a configuration example different from that of the transistor 150 shown in FIGS. This will be explained using 4(A),(B), and(C).

[0276] FIG. 4A is a top view of a transistor 170 which is a semiconductor device of one embodiment of the present invention. 4B corresponds to a cross-sectional view taken along the dashed line X1-X2 in FIG. 4A. FIG. 4(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 4(A). Correct.

[0277] The transistor 170 is a transistor 150 shown above and an oxide film that functions as a pixel electrode. The gate electrode is made of an oxide semiconductor film 120a and an oxide semiconductor film 120b that functions as a second gate electrode. The other configurations are the same as those of the transistor 150, and the same effects are obtained. In addition, the oxide semiconductor film 120a and the oxide semiconductor film 120b have the following structures: may be similar to the transistor 160 described above.

[0278] <1-8. Configuration example 5 of semiconductor device> Next, modified examples of the transistor 150 shown in FIGS. 2A, 2B, and 2C and the transistor 150 shown in FIG. B) A modified example of the transistor 170 shown in (C) will be described with reference to FIGS. 5 to 7. .

[0279] 5A and 5B are cross-sectional views of modified examples of the transistor 150 shown in FIGS. 2B and 2C. 5C and 5D are modified examples of the transistor 170 shown in FIGS. FIG.

[0280] The transistor 150A shown in FIGS. 5A and 5B is a transistor 150B shown in FIGS. The oxide semiconductor film 108 included in the capacitor 150 has a three-layer structure. The oxide semiconductor film 108 included in the transistor 150A includes an oxide semiconductor film 108a and an oxide The semiconductor layer 108 includes a nitride semiconductor film 108b and an oxide semiconductor film 108c.

[0281] The transistor 170A shown in FIG. 5C and FIG. 5D is a transistor 170A shown in FIG. The oxide semiconductor film 108 included in the capacitor 170 has a three-layer structure. The oxide semiconductor film 108 included in the transistor 170A includes an oxide semiconductor film 108a and an oxide The semiconductor layer 108 includes a nitride semiconductor film 108b and an oxide semiconductor film 108c.

[0282] Here, the band structure of the insulating film in contact with the oxide semiconductor films 108a, 108b, and 108c is 6, the band structures of the insulating films in contact with the oxide semiconductor films 108b and 108c are I will explain this in more detail.

[0283] FIG. 6A illustrates the insulating film 107, the oxide semiconductor films 108a, 108b, and 108c, and the insulating film 108. FIG. 6B is an example of a band structure in the thickness direction of a laminated structure having an insulating film 114. a stacked structure including an insulating film 107, oxide semiconductor films 108b and 108c, and an insulating film 114. The band structure is shown in FIG. 1 in the thickness direction of the structure. The conduction band of the insulating film 107, the oxide semiconductor films 108a, 108b, and 108c, and the insulating film 114 The lowest energy level (Ec) is shown.

[0284] FIG. 6A shows a case where a silicon oxide film is used as the insulating films 107 and 114, and an oxide semiconductor film is used. The metal oxide film 108a has an atomic ratio of In:Ga:Zn=1:1:1.2. The oxide semiconductor film 108b was formed using an oxide semiconductor film formed using a metal target. A metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=4:2:4.1 was used. The oxide semiconductor film 108c is formed by using an oxide semiconductor film having an atomic ratio of metal elements of The oxide formed using a metal oxide target of In:Ga:Zn=1:1:1.2 FIG. 1 is a band diagram of a configuration using a semiconductor film.

[0285] FIG. 6B shows a case where a silicon oxide film is used as the insulating films 107 and 114, and an oxide semiconductor film is used. The metal oxide film 108b has an atomic ratio of In:Ga:Zn=4:2:4.1. The oxide semiconductor film 108c was formed using an oxide semiconductor film formed using a metal target. A metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=1:1:1.2 was used. FIG. 1 is a band diagram of a structure using an oxide semiconductor film formed by

[0286] As shown in FIGS. 6A and 6B, in the oxide semiconductor films 108a, 108b, and 108c, In other words, the energy level at the bottom of the conduction band changes smoothly. In order to have such a band structure, the oxide At the interface between the semiconductor film 108a and the oxide semiconductor film 108b or at the interface between the oxide semiconductor film 108b and the oxide semiconductor film 108c, At the interface with the oxide semiconductor film 108c, defect states such as trap centers and recombination centers are generated. Assume that there are no impurities that would form

[0287] In order to form a continuous junction in the oxide semiconductor films 108a, 108b, and 108c, Each film is deposited using a multi-chamber deposition system (sputtering system) equipped with a lock chamber. It is necessary to continuously stack the layers without exposing them to the air.

[0288] With the structure shown in FIGS. 6A and 6B, the oxide semiconductor film 108b serves as a well. In the transistor using the above-mentioned stacked structure, the channel region is formed of the oxide semiconductor film 10 It can be seen that it is formed in 8b.

[0289] Note that the boundary between the oxide semiconductor film 108b and the insulating film (the insulating film 107 or the insulating film 114) The oxide semiconductor films 108a and 108c can prevent trap states from being formed in the vicinity of the surface. Therefore, the oxide semiconductor film 108b is located farther away.

[0290] In addition, the trap states are below the conduction band of the oxide semiconductor film 108b functioning as a channel region. The energy level of the edge (Ec) can be farther from the vacuum level, and electrons can be trapped in the trap level. The accumulation of electrons in the trap level leads to a fixed negative charge. This causes the threshold voltage of the transistor to shift in the positive direction. The trap level is lower than the energy level (Ec) of the conduction band minimum of the oxide semiconductor film 108b. It is preferable to configure the trap level so that the trap level is close to the empty level. This makes it difficult for electrons to accumulate, which makes it possible to increase the on-state current of the transistor. , the field effect mobility can be increased.

[0291] In addition, the oxide semiconductor films 108a and 108c have a conduction band lower than that of the oxide semiconductor film 108b. The energy level of the edge of the oxide semiconductor film 108b is close to the vacuum level, and typically, and the energy levels of the conduction band minimums of the oxide semiconductor films 108a and 108c. The difference between the two is 0.15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV That is, the electron affinity of the oxide semiconductor films 108a and 108c and the The difference between the electron affinity of the organic film 108b and the electron affinity of the organic film 108c is 0.15 eV or more, or 0.5 eV or more, and eV or less, or 1 eV or less.

[0292] With such a structure, the oxide semiconductor film 108b serves as a main current path. That is, the oxide semiconductor film 108b functions as a channel region, and the oxide semiconductor film 1 The oxide semiconductor film 108a and 108c function as oxide insulating films. a and 108c are metal elements constituting the oxide semiconductor film 108b in which the channel region is formed. Since the oxide semiconductor film 108a and the oxide At the interface with the oxide semiconductor film 108b or at the interface between the oxide semiconductor film 108b and the oxide semiconductor film 108c At the interface, the interface scattering is unlikely to occur. Therefore, at the interface, the movement of carriers is Since the electrons are not inhibited, the field effect mobility of the transistor is increased.

[0293] In addition, the oxide semiconductor films 108a and 108c function as part of a channel region. To prevent this, a material with sufficiently low electrical conductivity is used. The films 108a and 108c are also called oxide insulating films based on their physical properties and / or functions. Alternatively, the oxide semiconductor films 108a and 108c may have a low electron affinity (vacuum level and conduction band The energy level difference between the conduction band minimum and the conduction band minimum of the oxide semiconductor film 108b is smaller than that of the oxide semiconductor film 108b. The energy level of the oxide semiconductor film 108b is different from the energy level of the conduction band minimum of the oxide semiconductor film 108b (band-off In addition, a material having a drain voltage-dependent capacitance is used. In order to suppress the occurrence of a difference in the voltage between the oxide semiconductor films 108a and 108c, The energy level of the conduction band minimum of the oxide semiconductor film 108b is higher than the energy level of the conduction band minimum of the oxide semiconductor film 108b. For example, a material having a conductivity closer to a vacuum level than that of the oxide semiconductor film 108b is preferably used. The energy levels of the conduction band minimums of the oxide semiconductor films 108a and 108c are The difference from the -level is preferably 0.2 eV or more, more preferably 0.5 eV or more.

[0294] In addition, the oxide semiconductor films 108a and 108c do not contain a spinel crystal structure. It is preferable that the oxide semiconductor films 108a and 108c have a spinel crystal structure. In the case where the spinel type crystal structure is included, the conductive film 112a, 11 In some cases, a constituent element of the oxide semiconductor film 2b may diffuse into the oxide semiconductor film 108b. When the conductive films 108a and 108c are made of CAAC-OS, the structure of the conductive films 112a and 112b is This is preferable because it enhances the blocking property of the component element, for example, copper element.

[0295] The thicknesses of the oxide semiconductor films 108a and 108c are determined by the composition of the conductive films 112a and 112b. The insulating film has a thickness that is greater than or equal to a thickness that can prevent the insulating film from diffusing into the oxide semiconductor film 108b. The thickness of the oxide semiconductor film 108b is set to be less than the thickness at which oxygen supply from the film 114 to the oxide semiconductor film 108b is suppressed. For example, When the oxide semiconductor films 108a and 108c have a thickness of 10 nm or more, the conductive films 112a and This can prevent the constituent elements of the oxide semiconductor film 112b from diffusing into the oxide semiconductor film 108b. In addition, when the thickness of the oxide semiconductor films 108a and 108c is set to 100 nm or less, the insulating film 114 Therefore, oxygen can be effectively supplied to the oxide semiconductor film 108b.

[0296] In this embodiment, the oxide semiconductor films 108a and 108c are formed using a metal element. The atomic ratio of In:Ga:Zn was 1:1:1.2. However, the present invention is not limited to this structure. The compound semiconductor films 108a and 108c have an atomic ratio of In:Ga:Zn=1:1:1. In:Ga:Zn=1:3:2 [atomic ratio], In:Ga:Zn=1:3:4 [atomic ratio] ], or a metal oxide target with In:Ga:Zn=1:3:6 [atomic ratio] A formed oxide semiconductor film may be used.

[0297] Note that the oxide semiconductor films 108a and 108c were formed using a compound in which In:Ga:Zn=1:1:1 [original When a metal oxide target having a molecular weight ratio of 1:1 or less is used, the oxide semiconductor films 108a and 108c have a molecular weight ratio of 1:1 or less. In:Ga:Zn=1:β1(0<β1≦2):β2(0<β2≦2) In addition, the oxide semiconductor films 108a and 108c were formed of In:Ga:Zn=1:3:4 [prime When a metal oxide target having a molecular weight ratio of 1:1 or less is used, the oxide semiconductor films 108a and 108c have a molecular weight ratio of 1:1 or less. In:Ga:Zn=1:β3(1≦β3≦5):β4(2≦β4≦6) In addition, the oxide semiconductor films 108a and 108c were formed of In:Ga:Zn=1:3:6 [primary When a metal oxide target having a molecular weight ratio of 1:1 or less is used, the oxide semiconductor films 108a and 108c have a molecular weight ratio of 1:1 or less. In:Ga:Zn=1:β5(1≦β5≦5):β6(4≦β6≦8) .

[0298] In addition, the oxide semiconductor film 108c included in the transistor 150 and the transistor 150A In the drawing, the oxide semiconductor film 108c is exposed from the conductive films 112a and 112b. In other words, a part of the oxide semiconductor film has a depression. However, one embodiment of the present invention is not limited to this. The oxide semiconductor film in the region exposed from 2a and 112b does not necessarily have to have a recess. An example of this is shown in Figure 7(A)(B)(C)(D). 7A and 7B are cross-sectional views showing an example of a semiconductor device. The oxide semiconductor film 108c of FIG. 50 has no recess. 1 shows a structure in which an oxide semiconductor film 108c of a transistor 150A does not have a recess.

[0299] In addition, the transistor according to the present embodiment can be freely combined with each of the above structures. It is possible.

[0300] <1-9. Manufacturing method of semiconductor device> Next, a method for manufacturing the transistor 100 which is a semiconductor device of one embodiment of the present invention will be described with reference to FIG. 8 to 11 will be used to explain this.

[0301] 8(A) to 8(F), 9(A) to 9(F), and 10(A) to 1 11A to 11F are cross-sectional views illustrating a method for manufacturing a semiconductor device. 8(A)(C)(E), 9(A)(C)(E), 10(A)(C 11(A), (C), and (E) are cross-sectional views in the channel length direction, and FIG. 8(B) )(D)(F), Fig. 9(B)(D)(F), Fig. 10(B)(D)(F), and Fig. 11(B ) (D) and (F) are cross-sectional views in the channel width direction.

[0302] First, a conductive film is formed on the substrate 102, and the conductive film is then subjected to a lithography process and an etching process. Then, a conductive film 104 that functions as a first gate electrode is formed by carrying out a process. On the conductive film 104, insulating films 106 and 107 that function as a first gate insulating film are formed (see FIG. 8(A)(B)).

[0303] In this embodiment, a glass substrate is used as the substrate 102, which functions as the first gate electrode. A tungsten film having a thickness of 100 nm is formed by sputtering as the conductive film 104. In addition, a silicon nitride film having a thickness of 400 nm is formed as the insulating film 106 by the PECVD method. Then, a silicon oxynitride film having a thickness of 50 nm is formed as the insulating film 107 by the PECVD method. Form.

[0304] The insulating film 106 may have a stacked structure of a silicon nitride film. The insulating film 106 is made of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. A three-layer laminate structure with a silicon film can be formed. An example of the three-layer laminate structure is as follows: It can be formed as follows:

[0305] The first silicon nitride film is formed by, for example, silane at a flow rate of 200 sccm, PE-CV was performed using nitrogen at a flow rate of 100 sccm and ammonia gas at a flow rate of 100 sccm as source gas. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high-frequency If a power of 2000 W is supplied using a frequency power supply and the thickness is formed to be 50 nm, good.

[0306] For the second silicon nitride film, silane at a flow rate of 200 sccm, The nitrogen gas and the ammonia gas with a flow rate of 2000sccm were used as raw material gases in the PECVD equipment. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high-frequency power supply was used. A power of 2000 W may be supplied using the above method to form a film having a thickness of 300 nm.

[0307] The third silicon nitride film was prepared by using silane at a flow rate of 200 sccm and 5000 sccm. The pressure in the reaction chamber was kept at 100 The thickness was measured by controlling the temperature to 50 Pa and supplying 2000 W of power using a 27.12 MHz high frequency power source. It is sufficient to form it so that the thickness is 50 nm.

[0308] The first silicon nitride film, the second silicon nitride film, and the third silicon nitride film The substrate temperature during formation can be 350° C. or less.

[0309] By forming the insulating film 106 in a three-layered structure of silicon nitride films, for example, the conductive film 10 When a conductive film containing copper (Cu) is used for 4, the following effects are achieved.

[0310] The first silicon nitride film can suppress the diffusion of copper (Cu) elements from the conductive film 104. The second silicon nitride film has the function of releasing hydrogen and functions as a gate insulating film. The third silicon nitride film can improve the breakdown voltage of the insulating film. Hydrogen release from the silicon nitride film is small, and hydrogen released from the second silicon nitride film is diffused. can be suppressed.

[0311] The insulating film 107 is an oxide semiconductor film 108 (more specifically, an oxide In order to improve the interface characteristics with the semiconductor film 108b), the insulating film is formed of an oxygen-containing insulating film. preferable.

[0312] Next, the oxide semiconductor film 108b_0 and the oxide semiconductor film 108c_0 are formed over the insulating film 107. (See Figures 8(C)(D)(E)(F)).

[0313] 8C and 8D, the oxide semiconductor film 108b_0 is formed over the insulating film 107. 8(C) and (D) are schematic cross-sectional views of the inside of the film forming apparatus. A ring device is used, and a target 191 is installed inside the sputtering device. A plasma 192 formed below a get 191 is shown diagrammatically.

[0314] First, when the oxide semiconductor film 108b_0 is formed, a first oxygen gas-containing atmosphere is used. The plasma is discharged. At this time, the insulating film on which the oxide semiconductor film 108b_0 is to be formed is In addition, oxygen is added to the oxide semiconductor film 107. In addition to the oxygen gas in 1, inert gases (e.g., helium gas, argon gas, xenon gas) etc.) may be mixed.

[0315] The first oxygen gas is at least oxygen gas contained in the oxide semiconductor film 108b_0. The first gas in the deposition gas for forming the oxide semiconductor film 108b_0 may be the first gas in the deposition gas for forming the oxide semiconductor film 108b_0. The ratio of oxygen gas is more than 0% and less than 100%, preferably 10% to 100%. It is more preferably 30% or more and 100% or less.

[0316] In addition, in FIG. 8(C) and (D), oxygen or excess oxygen added to the insulating film 107 is simulated. This is represented formally by a dashed arrow.

[0317] Note that the substrate temperature during the formation of the oxide semiconductor film 108b_0 and the oxide semiconductor film 108c_0 was However, the thickness of the oxide semiconductor film 108b_0 and the thickness of the oxide semiconductor film 108b_1 may be the same or different. By making the substrate temperature the same as that of the conductive film 108c_0, the manufacturing cost can be reduced. This is preferable because

[0318] For example, the substrate temperature when the oxide semiconductor film 108 is formed is set to a temperature not lower than room temperature and not higher than 340° C. Preferably, the temperature is from room temperature to 300° C., more preferably from 100° C. to 250° C. The temperature is preferably 100° C. or more and 200° C. or less. By doing so, the crystallinity of the oxide semiconductor film 108 can be improved. In addition, when using a large glass substrate (for example, 6th generation to 10th generation), the oxide semiconductor When the substrate temperature during deposition of the solid film 108 is set to 150° C. or higher and lower than 340° C., Therefore, when using a large glass substrate, In this case, the substrate temperature during the formation of the oxide semiconductor film 108 is set to 100° C. or higher and lower than 150° C. By doing so, deformation of the glass substrate can be suppressed.

[0319] In addition, the sputtering gas must be highly purified. The oxygen gas and argon gas used in the present invention have a dew point of -40°C or less, preferably -80°C or less, and Preferably, the gas is purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using the above, it is possible to prevent moisture and the like from being absorbed into the oxide semiconductor film as much as possible. .

[0320] In addition, when the oxide semiconductor film is formed by a sputtering method, The chamber is a clarified chamber to remove water and other impurities that may be harmful to the oxide semiconductor film as much as possible. A high vacuum (e.g., 5×10) is created using an adsorption-type vacuum pump such as an ion pump. -7 Pa From 1×10 -4 It is preferable to evacuate the gas to a level of about 10 Pa. Alternatively, a turbo molecular pump may be used. A cold trap is used to trap gas, especially carbon or hydrogen, from the exhaust system into the chamber. It is preferable to prevent the gas contained therein from flowing backward.

[0321] After the oxide semiconductor film 108b_0 is formed, the oxide semiconductor film 108c The oxide semiconductor film 108c_0 is formed on the oxide semiconductor film 108b_0. When forming the layer 0, plasma may be discharged in an atmosphere containing the second oxygen gas.

[0322] Note that the ratio of the first oxygen gas and the ratio of the oxide semiconductor The ratio of the second oxygen gas when forming the conductive film 108c_0 may be the same as or different from that of the first oxygen gas when forming the conductive film 108c_0. For example, the second acid gas may be contained in the entire deposition gas when the oxide semiconductor film 108c_0 is formed. The ratio of the raw gas is more than 0% and not more than 100%, preferably 10% or more and not more than 100%. , and more preferably 30% or more and 100% or less.

[0323] Note that when the oxide semiconductor film 108c_0 is formed, the second oxygen gas and the argon gas are mixed. When using the above, it is preferable to make the flow rate of the argon gas greater than the flow rate of the second oxygen gas. By increasing the flow rate of argon gas, the oxide semiconductor film 108c_0 becomes a dense film. In order to form the oxide semiconductor film 108c_0 into a dense film, The substrate temperature when the oxide semiconductor film 108c_0 is formed is set to be high. Typically, the oxidation temperature is 250° C. or less, and preferably 150° C. or more and 190° C. or less. When the compound semiconductor film 108c_0 is a dense film, the gold contained in the conductive films 112a and 112b This can prevent metal elements from entering the oxide semiconductor film 108b_0.

[0324] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: 2:4.1 [atomic ratio]) by sputtering, 0 was formed, and then, in vacuum, an In-Ga-Zn metal oxide target (In: The oxide semiconductor was deposited by sputtering using Ga:Zn=1:1:1.2 (atomic ratio). The conductive film 108c_0 is formed. In addition, the substrate temperature during the formation of the oxide semiconductor film 108b_0 is The substrate temperature during the formation of the oxide semiconductor film 108c_0 is set to 170° C. In addition, the oxide semiconductor film 108b_0 was formed using an oxygen gas having a flow rate of 60 sccm. The oxide semiconductor film 108 is formed by oxidizing the oxide semiconductor film 108 with a flow rate of 100 sccm. The deposition gas for forming c_0 was oxygen gas with a flow rate of 100 sccm and cm of argon gas is used.

[0325] Next, the oxide semiconductor film 108b_0 and the oxide semiconductor film 108c_0 are formed into a desired shape. By this process, island-shaped oxide semiconductor films 108b and 108c are formed. (See Figures 9(A) and (B)).

[0326] Next, a source electrode and a drain electrode are formed over the insulating film 107 and the oxide semiconductor film 108. Then, a conductive film 112 is formed by a sputtering method (see FIGS. 9C and 9D).

[0327] In this embodiment, the conductive film 112 is a tungsten film having a thickness of 50 nm and a SiO 2 film having a thickness of 40 A laminate film in which a SiO2 film and a 0 nm aluminum film are laminated in this order is formed by sputtering. In this embodiment, the conductive film 112 has a two-layered structure, but the present invention is not limited to this. For example, the conductive film 112 may be a tungsten film having a thickness of 50 nm and a 400 nm thick The aluminum film with a thickness of 100 nm and the titanium film with a thickness of 100 nm were laminated in this order. You may do so.

[0328] Next, the conductive film 112 is processed into a desired shape to form conductive films separated from each other. 112a and 112b are formed (see Figures 9(E) and (F)).

[0329] In this embodiment, the conductive film 112 is processed using a dry etching apparatus. However, the method for processing the conductive film 112 is not limited to this. For example, a wet etching method may be used. A wet etching apparatus may be used to form the conductive film 112. The conductive film 112 can be processed by using a dry etching apparatus rather than a conventional etching method. On the other hand, a dry etching apparatus is used to form a conductive film 1 It is more efficient to process the conductive film 112 using a wet etching apparatus than to process the conductive film 12 using a wet etching apparatus. The manufacturing costs can be reduced.

[0330] After the conductive films 112a and 112b are formed, the oxide semiconductor film 108 (more specifically, The surface (back channel side) of the oxide semiconductor film 108c may be cleaned. For example, cleaning using a chemical solution such as phosphoric acid can be used. By performing the cleaning, impurities (e.g., impurities formed on the surface of the conductive film 108c) are removed. The cleaning can be performed without removing the elements contained in the SiO2 particles (e.g., elements contained in 112a and 112b). In some cases, cleaning may not be required.

[0331] In addition, either one of the steps of forming the conductive films 112a and 112b and the above-mentioned cleaning step may be performed. In either case, the region of the oxide semiconductor film 108 that is exposed from the conductive films 112a and 112b is But it may become thinner.

[0332] Next, the insulating film 114 and the conductive films 112a and 112b are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b. An insulating film 116 is formed (see FIGS. 10(A) and (B)).

[0333] After the insulating film 114 is formed, the insulating film 116 is successively formed without exposing it to the air. After the insulating film 114 is formed, it is preferable to adjust the flow rate, pressure, and temperature of the source gas without exposing the insulating film 114 to the air. By adjusting one or more of the frequency power and the substrate temperature, the insulating film 116 is continuously formed. The concentration of impurities derived from atmospheric components can be reduced at the interface between the insulating film 114 and the insulating film 116. At the same time, oxygen contained in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. As a result, the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced. .

[0334] For example, a silicon oxynitride film is formed as the insulating film 114 by using a PECVD method. In this case, the source gas may be a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include silane, disilane, etc. Examples of oxidizing gases include nitrous oxide, nitrous oxide, and trisilane. In addition, the flow rate of the oxidizing gas is set to 20 times or more the flow rate of the deposition gas. The pressure in the treatment chamber is set to less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the treatment chamber is set to less than 100 Pa. By using the PECVD method at a pressure of 50 Pa or less, preferably 50 Pa or less, the insulating film 114 is The insulating film contains the above and has a small amount of defects.

[0335] In this embodiment, the insulating film 114 is formed by heating the substrate 102 at a temperature of 220° C. The source gases were silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm. The pressure in the treatment chamber was set to 20 Pa, and the high frequency power supplied to the parallel plate electrodes was set to 13.56 M. Hz, 100W (power density is 1.6×10 -2 W / cm 2 ) PECVD method A silicon oxynitride film is formed using this.

[0336] The insulating film 116 is formed by depositing a substrate in a vacuum-evacuated processing chamber of a PECVD apparatus. The temperature is kept at 180°C or higher and 350°C or lower, and the raw material gas is introduced into the treatment chamber to increase the pressure in the treatment chamber. is set to 100 Pa or more and 250 Pa or less, and more preferably set to 100 Pa or more and 200 Pa or less. 0.17 W / cm2 at the electrode installed in the treatment chamber 2 More than 0.5W / cm 2 Below are some more Preferably 0.25W / cm 2 More than 0.35W / cm 2 The following high frequency power supply conditions are met: In this way, a silicon oxide film or a silicon oxynitride film is formed.

[0337] The conditions for forming the insulating film 116 are as follows: high frequency power density in a reaction chamber with the above pressure; By supplying power, the efficiency of decomposition of the source gas in the plasma increases, and the number of oxygen radicals increases. As the oxidation of the source gas progresses, the oxygen content in the insulating film 116 becomes lower than the stoichiometric composition. On the other hand, in the film formed at the above substrate temperature, the bonding strength between silicon and oxygen is Since the oxygen in the film is weak, some of the oxygen in the film is released by the heat treatment in the subsequent process. An oxide that contains more oxygen than satisfies the theoretical composition and loses some of the oxygen when heated. An insulating film can be formed.

[0338] In the step of forming the insulating film 116, the insulating film 114 serves as a protection film for the oxide semiconductor film 108. Therefore, the power density can be reduced while reducing damage to the oxide semiconductor film 108. The insulating film 116 can be formed using high radio frequency power.

[0339] In the deposition conditions for the insulating film 116, a deposition gas containing silicon is mixed with an oxidizing gas. By increasing the flow rate of the gas, it is possible to reduce the amount of defects in the insulating film 116. In the first place, ESR measurements revealed that the g value was 2.001, which is due to the dangling bonds of silicon. The spin density of the signal is 6×10 17 spins / cm 3 Less than 3 x 10 17 spins / cm 3 Less than or equal to 1.5×10 17 spins / cm 3 The following is a missing As a result, the signal quality of the transistor 100 can be improved. It can increase reliability.

[0340] After the insulating films 114 and 116 are formed, heat treatment (hereinafter referred to as first heat treatment) is performed. The first heat treatment is preferably performed to remove nitrogen oxide contained in the insulating films 114 and 116. Alternatively, the first heat treatment can reduce the amount of oxides in the insulating films 114 and 116. Part of the oxygen contained in the oxide semiconductor film 108 is transferred to the oxide semiconductor film 108. This can reduce the amount of oxygen vacancies.

[0341] The temperature of the first heat treatment is typically less than 400° C., preferably less than 375° C., and The first heat treatment is preferably performed at a temperature of 150° C. or higher and 350° C. or lower. Dry air (water content is 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb The reaction may be carried out under an atmosphere of air (see below) or a rare gas (argon, helium, etc.). It is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc. Heat treatment is performed using an electric furnace, RTA (Rapid Thermal Anneal), etc. It is possible.

[0342] Next, a mask is formed on the insulating film 116 by a lithography process, and the insulating films 114 and 11 An opening 152a is formed in a desired region of the conductive film 112b. (See Figures 10(C) and (D)).

[0343] Next, the oxide semiconductor film 120 is formed on the insulating film 116 so as to cover the opening 152a. (See Figures 10(E) and (F) and Figures 11(A) and (B)).

[0344] 10E and 10F show the state when the oxide semiconductor film 120 is formed on the insulating film 116. 10(E) and 10(F) are schematic cross-sectional views of the inside of a film forming apparatus. A ring device is used, and a target 193 is installed inside the sputtering device. A plasma 194 formed below the get 193 is also shown diagrammatically.

[0345] First, when forming the oxide semiconductor film 120, a plasma is generated in an atmosphere containing a third oxygen gas. At that time, the oxide semiconductor film 120 is formed on the insulating film 116. When the oxide semiconductor film 120 is formed, oxygen is added to the oxide semiconductor film 120. , by mixing inert gas (e.g., helium gas, argon gas, xenon gas, etc.) For example, argon gas and a third oxygen gas may be used, and the flow rate of the argon gas may be set to be lower than that of the oxygen gas. It is preferable to increase the flow rate of the third oxygen gas. In this way, oxygen can be suitably added to the insulating film 116. For example, The formation condition of 120 is to set the ratio of the third oxygen gas in the entire deposition gas to 50% or more. It is preferable that the ratio is 100% or less, and more preferably, 80% or more and 100% or less.

[0346] In addition, in FIG. 10E and FIG. 10F, oxygen or excess oxygen is added to the insulating film 116. This is shown diagrammatically by dashed arrows.

[0347] The substrate temperature during the formation of the oxide semiconductor film 120 is set to room temperature or higher and lower than 340° C. , preferably from room temperature to 300° C., more preferably from 100° C. to 250° C., The temperature is preferably 100° C. or higher and 200° C. or lower. The oxide semiconductor film 120 is formed by heating. This can improve the crystallinity of the oxide semiconductor film 120. Therefore, when a large glass substrate (for example, 6th generation to 10th generation) is used, the oxide semiconductor When the substrate temperature during the deposition of the film 120 is set to 150° C. or higher and lower than 340° C., the substrate 102 Therefore, when using a large glass substrate, In this case, the substrate temperature during the formation of the oxide semiconductor film 120 is set to 100° C. or higher and lower than 150° C. This makes it possible to suppress deformation of the glass substrate.

[0348] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=1: 3:6 [atomic ratio]) by a sputtering method to form the oxide semiconductor film 120. The substrate temperature during the formation of the oxide semiconductor film 120 is set to 170° C. The film forming gas used for forming the conductor film 120 is oxygen gas at a flow rate of 100 sccm.

[0349] The oxide semiconductor film 120 may be, for example, the oxide semiconductor film described above (e.g., In: Ga:Zn=1:1:1[atomic ratio], In:Ga:Zn=1:3:2[atomic ratio], I n:Ga:Zn=1:3:4[atomic ratio], In:Ga:Zn=1:3:6[atomic ratio] , In:Ga:Zn=3:1:2 [atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio] It is sufficient to use a ratio, etc.

[0350] Next, the oxide semiconductor film 120 is processed into a desired shape to form an island-shaped oxide semiconductor film 1 Then, an oxide semiconductor film 20a and an island-shaped oxide semiconductor film 120b are formed (see FIGS. 11C and 11D).

[0351] Next, the insulating film 118 is formed over the insulating film 116 and the oxide semiconductor films 120a and 120b. (See Figures 11(E) and (F)).

[0352] The insulating film 118 contains either hydrogen or nitrogen, or both. For example, a silicon nitride film is preferably used as the insulating film 118. For example, it can be formed by using a sputtering method or a PECVD method. When the insulating film 118 is formed by the PECVD method, the substrate temperature is set to less than 400° C., preferably less than 375° C. The temperature is preferably less than 180° C. and more preferably 350° C. or higher. In this case, it is preferable to set the substrate temperature in the above-mentioned range since a dense film can be formed. By setting the substrate temperature in the above range when forming the insulating film 118, the insulating films 114 and 1 Therefore, oxygen or excess oxygen in the oxide semiconductor film 106 can be moved to the oxide semiconductor film 108.

[0353] After the insulating film 118 is formed, a heat treatment similar to the first heat treatment described above (hereinafter, the first heat treatment) is performed. In this manner, when the oxide semiconductor film 120 is formed, After adding oxygen to the insulating film 116, the insulating film 116 is heated at a temperature lower than 400° C., preferably lower than 375° C., The heat treatment is preferably performed at a temperature of 180° C. or higher and 350° C. or lower. The oxygen or excess oxygen is moved into the oxide semiconductor film 108 (particularly the oxide semiconductor film 108b). Thus, oxygen vacancies in the oxide semiconductor film 108 can be filled.

[0354] Here, oxygen moving into the oxide semiconductor film 108 will be described with reference to FIG. FIG. 12 shows the relationship between the substrate temperature (typically less than 375° C.) during the deposition of the insulating film 118 and the temperature of the insulating film 118. The oxide semiconductor film 118 is then heated to a temperature of 375° C. or lower. 12 is a model diagram showing oxygen moving into the oxide semiconductor 108. The oxygen (oxygen radicals, oxygen atoms, or oxygen molecules) shown in the film 108 is represented by dashed arrows. is.

[0355] The oxide semiconductor film 108 illustrated in FIG. 12 is a film in contact with the oxide semiconductor film 108 (here, Oxygen moves from the insulating films 107 and 114, thereby filling the oxygen vacancies. In particular, in the semiconductor device of one embodiment of the present invention, the oxide semiconductor film 108b is formed by sputtering. During the deposition, oxygen gas is used to add oxygen to the insulating film 107. In addition, oxygen gas is used during the sputtering deposition of the oxide semiconductor film 120. Since oxygen is added to the insulating film 116, the insulating film 116 has an excess oxygen region. In other words, the oxide semiconductor film 108 sandwiched between the insulating films having the excess oxygen region has a preferable oxygen vacancy. will be appropriately compensated.

[0356] In addition, the insulating film 106 is provided below the insulating film 107, and the insulating films 114 and 11 An insulating film 118 is provided above the insulating films 106 and 118. By forming the insulating films 107, 114, and 116 from a thin material such as silicon nitride, Since the oxygen contained therein can be trapped on the oxide semiconductor film 108 side, the oxide semiconductor film 108 can be suitably oxidized. This allows oxygen to be transferred to the organic semiconductor film 108.

[0357] The insulating film 118 contains either hydrogen or nitrogen, or both. By forming the insulating film 118, the oxide semiconductor films 120a and 120b in contact with the insulating film 118 are formed. In 0b, the carrier density is high due to the addition of either hydrogen or nitrogen or both. Therefore, the oxide conductive film can function as an oxide conductive film.

[0358] In addition, when a silicon nitride film is formed as the insulating film 118 by the PECVD method, silicon It is preferable to use a deposition gas containing nitrile, nitrogen, and ammonia as the source gas. By using a small amount of ammonia compared to hydrogen, ammonia dissociates in the plasma and becomes active. The active species are generated by bonding with silicon and hydrogen contained in the silicon-containing deposition gas. This breaks the triple bond between silicon and nitrogen. As a result, the bond between silicon and nitrogen is promoted, It is possible to form a dense silicon nitride film with few silicon and hydrogen bonds and few defects. On the other hand, if the amount of ammonia relative to nitrogen is large, the deposition gas containing silicon and the nitrogen The decomposition of the silicon does not proceed, silicon and hydrogen bonds remain, and defects increase and the material becomes rough. For these reasons, the source gas is not suitable for ammonia. It is preferable that the flow rate ratio of nitrogen to oxygen is 5 times or more and 50 times or less, and more preferably 10 times or more and 50 times or less.

[0359] In this embodiment, the insulating film 118 is formed by depositing silane, nitrogen, etc., using a PECVD apparatus. A silicon nitride film with a thickness of 50 nm is formed using nitrogen and ammonia as source gases. The flow rates were 50 sccm for silane, 5000 sccm for nitrogen, and 100 for ammonia. The pressure in the processing chamber was 100 Pa, the substrate temperature was 350°C, and the flow rate was 27.12 MWh. A high-frequency power supply of 1000 W is supplied to the parallel plate electrodes. The device has an electrode surface area of ​​6000 cm 2 The parallel plate type PECVD equipment is The force can be converted to power per unit area (power density) of 1.7 x 10 -1W / cm 2 is .

[0360] In this embodiment, the insulating film 118 and the oxide semiconductor films 120a and 120b are Hydrogen or nitrogen is added to the oxide semiconductor films 120a and 120b to increase the carrier density. However, the present invention is not limited to this. For example, By performing treatment to add an impurity element to the oxide semiconductor films 120a and 120b, The carrier density of 0b may be increased.

[0361] Representative examples of the impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, and aluminum. Examples of rare gas elements include helium, silicon, phosphorus, chlorine, and rare gas elements. The impurity elements are uranium, neon, argon, krypton, and xenon. When added to the oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is broken, and oxygen vacancies are formed. Alternatively, when an impurity element is added to the oxide semiconductor film, the metal in the oxide semiconductor film is The oxygen that was bonded to the metal element bonds with an impurity element, and oxygen is released from the metal element, resulting in an oxygen deficiency. As a result, the carrier density in the oxide semiconductor film increases, and the conductivity will become higher.

[0362] Through the above steps, the transistor 100 illustrated in FIGS.

[0363] In addition, in all the manufacturing steps of the transistor 100, the substrate temperature is preferably less than 400° C. or less than 375°C, and more preferably 180°C to 350°C. This is preferable because it is possible to minimize deformation (distortion or warping) of the substrate even when using the substrate. In the manufacturing process of the transistor 100, the substrate temperature is increased. Typically, the substrate temperature during the formation of the insulating films 106 and 107 is less than 400° C., preferably The substrate temperature during deposition of the oxide semiconductor film 108 (room temperature or higher, 3 Less than 40°C, preferably 100°C to 200°C, more preferably 100°C to 15 0° C.), the substrate temperature during deposition of the insulating films 116 and 118 (less than 400° C., preferably 37 5°C or less, more preferably 180°C or more and 350°C or less), the first heat treatment or the second heat treatment Heat treatment (less than 400°C, preferably less than 375°C, more preferably 180°C to 35°C) 0℃ or below).

[0364] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0365] (Embodiment 2) In this embodiment, the structure of an oxide semiconductor will be described with reference to FIGS. He explains.

[0366] <2-1. Structure of oxide semiconductor> Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous l Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, etc.

[0367] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- These include OS, polycrystalline oxide semiconductor, and nc-OS.

[0368] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond length is short. In other words, it is a structure that has discrete order but does not have long-range order.

[0369] On the other hand, in the case of an essentially stable oxide semiconductor, In addition, it cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor, which is not amorphous (for example, has a periodic structure in a microscopic region), is transformed into a completely amorphous oxide. However, a-like OS is a semiconductor that can be used in a small area. Although it has a periodic structure, it has voids and is an unstable structure. In terms of physical properties, it can be said that the semiconductor is close to an amorphous oxide semiconductor.

[0370] In the oxide semiconductor film of one embodiment of the present invention, among the above-mentioned oxide semiconductors, C AAC-OS is preferable. By using CAAC-OS as the oxide semiconductor film, The crystallinity of the film is improved, and impurities, oxygen vacancies, or defect state density in the oxide semiconductor film is reduced. It is possible.

[0371] <2-2.CAAC-OS> First, let me explain about CAAC-OS.

[0372] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0373] A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by TEM. When observing the TEM image, multiple pellets can be seen. In the high-resolution TEM image, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is not possible to clearly confirm the presence of CAAC-OS due to the grain boundaries. This means that the decrease in electron mobility caused by the SiO2 film is unlikely to occur.

[0374] The CAAC-OS observed by TEM is described below. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration corrector function was used. , specifically called a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images are obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0375] A Cs-corrected high-resolution TEM image of the enlarged area (1) in Figure 17(A) is shown in Figure 17(B). From FIG. 17(B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0376] As shown in FIG. 17(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of each pellet is about 1 nm to 3 nm, and the size of each pellet is about 1 nm to 3 nm. It can be seen that the size of the gap caused by the inclination is about 0.8 nm. The pellets can also be called nanocrystals (nc). AAC-OS, CANC(C-Axis Aligned nanocrystals) ) can also be referred to as an oxide semiconductor.

[0377] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 17(D)). The inclination between the pellets observed in FIG. 17(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0378] FIG. 18(A) shows the C 18(A) shows the s-corrected high-resolution TEM images of regions (1), (2) and (3) in FIG. ) are enlarged Cs-corrected high-resolution TEM images shown in Fig. 18(B), Fig. 18(C), and Fig. 18(D), respectively. As shown in Figure 18(D), Figure 18(B), Figure 18(C) and Figure 18(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0379] Next, we will explain the CAAC-OS analyzed by XRD. The structure of CAAC-OS with nO4 crystals was solved by the out-of-plane method. When the diffraction angle (2θ) is 31°, a peak appears as shown in FIG. This peak is attributed to the (009) plane of the InGaZnO4 crystal. The CAAC-OS crystal has a c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface on which the CAAC-OS is formed or the upper surface. It can be seen that it is facing in the direction.

[0380] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31 In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is a structure obtained by the out-of-plane method. The analysis shows a peak at 2θ around 31° and no peak at 2θ around 36°.

[0381] On the other hand, in-pla, X-rays are incident on CAAC-OS from a direction nearly perpendicular to the c-axis. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I It is attributed to the (110) plane of the crystal of nGaZnO4. In the case of CAAC-OS, 2θ is set to 5 The sample was fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears, as shown in FIG. 19(B). On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane, as shown in Figure 19(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and the b-axis is irregular.

[0382] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, a probe diameter of 300 nm was used parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the InGaZnO4 The spots due to the (009) plane of the crystal are included. Therefore, even by electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in FIG. 0(B), a ring-shaped diffraction pattern is observed. Therefore, electron diffraction It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. In addition, the first ring in FIG. 20(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface, etc.

[0383] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0384] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0385] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps and In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0386] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, the carrier density is set to 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 Such an oxide semiconductor can be a highly pure intrinsic or substantially highly pure oxide semiconductor. CAAC-OS has a low impurity concentration and a low density of defect states. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0387] <2-3.nc-OS> Next, we will explain nc-OS.

[0388] In the high-resolution TEM image, the nc-OS is divided into two regions: one where the crystals can be confirmed, and the other where the clear The crystalline parts in nc-OS are In most cases, the size is between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In some cases, the nanocrystals are not clearly visible in the pellets of CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is referred to as the pellet. There is a chance to call.

[0389] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, the nc-OS may be a pellet with a larger diameter than the pellet. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, the probe diameter is larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction was performed on nc-OS, high brightness regions were observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. There may be cases where this occurs.

[0390] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) The oxide semiconductor or NANC (Non-Aligned Nanocrystal The semiconductor may also be referred to as an oxide semiconductor having a structure including a metal oxide layer.

[0391] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0392] <2-4.a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0393] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen, and areas where crystals can be seen. and areas where it is not possible to

[0394] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0395] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as sample B) and CAAC-OS (hereinafter referred to as sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0396] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that all the materials have crystalline parts.

[0397] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are layered in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing between the crystals is 0.28 nm to 0.30 nm are considered to be crystal parts of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0398] Figure 21 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes is the size of the crystal part. It can be seen that the crystalline part of the ke OS grows in size according to the cumulative dose of electron irradiation. Specifically, as shown by (1) in FIG. 21, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus), which was 4.2×10 8 e - / n m 2On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in Fig. 21, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that.

[0399] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not seen as a nc-OS or CAAC-OS. It is clear that it has an unstable structure compared to the OS.

[0400] In addition, because of the porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0401] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0402] In some cases, single crystals of the same composition do not exist. In such cases, crystals of different compositions may be used in any ratio. By combining single crystals of the desired composition, the density equivalent to that of a single crystal of the desired composition can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate the size of the single crystal by combining different types of single crystals.

[0403] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0404] <2-5. CAAC-OS film formation method> An example of a method for forming a CAAC-OS film will be described below.

[0405] FIG. 22 is a schematic diagram of the inside of the deposition chamber. CAAC-OS is deposited by sputtering. It is possible.

[0406] As shown in FIG. 22, the substrate 5220 and the target 5230 are disposed so as to face each other. There is a plasma 5240 between the substrate 5220 and the target 5230. A heating mechanism 5260 is provided below the substrate 5220. Although not shown, a target 5230 is bonded to the backing plate. A number of magnets are arranged opposite the magnet 5230. The sputtering method that uses magnetron sputtering to increase the deposition rate is called magnetron sputtering. can be.

[0407] The distance d between the substrate 5220 and the target 5230 (target-substrate distance (TS distance) The distance is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. The deposition chamber is mostly filled with deposition gas (e.g., oxygen, argon, or oxygen 5 volumes). % or more), and the pressure is 0.01 Pa to 100 Pa, preferably The pressure is controlled to be 0.1 Pa or more and 10 Pa or less. By applying a voltage, a discharge starts and plasma 5240 is observed. A high-density plasma region is formed near the nozzle 5230 by the magnetic field. In the region, the deposition gas is ionized to generate ions 5201. The ions 5201 are For example, the oxygen cation (O + ) and argon cations (Ar + ) etc.

[0408] The target 5230 has a polycrystalline structure having a plurality of crystal grains, and As an example, FIG. 23 shows a target 5230 containing InMZn The crystal structure of O4 (wherein element M is, for example, Al, Ga, Y, or Sn) is shown in FIG. A) is the crystal structure of InMZnO4 when observed parallel to the b-axis. In ZnO4 crystals, the oxygen atoms have a negative charge, so that two adjacent M-Zn Therefore, the InMZnO4 crystal is composed of two adjacent M -The cleavage plane is between the Zn-O layers.

[0409] Ions 5201 generated in the high-density plasma region are attracted to the target 5230 by the electric field. The cleavage plane is then accelerated and collides with the target 5230. At this time, flat or planar particles are generated from the cleavage plane. A pellet 5200, which is a pellet-shaped sputtered particle, is peeled off (see FIG. 22). 200 is the portion sandwiched between the two cleavage planes shown in FIG. 23(A). When only 200 is extracted, its cross section is as shown in Figure 23(B) and its top surface is as shown in Figure 23(C). It can be seen that the pellet 5200 is formed by the impact of the ion 5201. This can cause distortion of the structure.

[0410] The pellet 5200 is a flat or pellet-shaped pellet having a triangular, e.g., equilateral, plane. The pellet 5200 is a sputtered particle having a hexagonal, for example, a regular hexagonal plane. The sputtered particles are in the form of a plate or pellet. However, the shape of the pellet 5200 is not limited to a triangle or a hexagon, for example, it may be a shape made up of multiple triangles. For example, a quadrilateral (such as a rhombus) is made up of two triangles (such as an equilateral triangle). ) in some cases.

[0411] The thickness of the pellet 5200 is determined depending on the type of deposition gas. For example, 5200 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5200 has a width of 1 nm or more and 100 nm or less. The thickness is preferably 2 nm or more and 50 nm or less, and more preferably 3 nm or more and 30 nm or less. For example, The target 5230 having an In-M-Zn oxide is bombarded with ions 5201. As a result, a pellet 5 having three layers, an M-Zn-O layer, an In-O layer, and an M-Zn-O layer, was obtained. As the pellet 5200 is peeled off, particles are released from the target 5230. Particle 5203 is also ejected. Particle 5203 has an aggregate of one atom or several atoms. Therefore, the particle 5203 is called atomic particles. It is also possible.

[0412] As the pellet 5200 passes through the plasma 5240, the surface becomes negatively or positively charged. For example, the pellet 5200 may be in the plasma 5240. 2- negative charge from As a result, the oxygen atoms on the surface of the pellet 5200 may become negatively charged. In addition, when the pellet 5200 passes through the plasma 5240, the pellet 5200 may be mixed with the plasma 52 It may grow by combining with indium, element M, zinc, or oxygen in 40. .

[0413] The pellets 5200 and particles 5203 that have passed through the plasma 5240 are Some of the particles 5203 reach the surface because of their small mass. It may be discharged to the outside.

[0414] Next, the deposition of pellets 5200 and particles 5203 on the surface of the substrate 5220 is This will be explained with reference to FIG.

[0415] First, the first pellet 5200 is deposited on the substrate 5220. Since the pellets 52 are in the shape of a pellet, the flat side of the pellets 52 is deposited toward the surface of the substrate 5220. The charge on the surface of 00 on the substrate 5220 side is discharged through the substrate 5220.

[0416] Next, the second pellet 5200 reaches the substrate 5220. The surface of the pellet 5200 that is being held in the first position and the surface of the second pellet 5200 are charged. As a result, the second pellet 5200 is pushed into the pile already. Avoid placing the pellets 5200 on the substrate 5220, and place the flat side a little away from the surface of the substrate 5220. By repeating this process, countless pellets 52 are deposited on the surface of the substrate 5220. 00 is piled up to the thickness of one layer. Also, between the pellets 5200, Non-deposited areas are generated (see FIG. 24(A)).

[0417] Next, the particles 5203 that have received energy from the plasma reach the surface of the substrate 5220. The particles 5203 can accumulate in active areas such as the surface of the pellet 5200. Therefore, the particles 5203 move to the areas where the pellets 5200 are not deposited, and the pellets The particle 5203 adheres to the side of the nozzle 5200. The bond becomes more active, and the pellet 5200 is chemically bonded to the lateral growth portion 52. 02 (see Figure 24(B)).

[0418] Furthermore, the lateral growth portion 5202 grows in the lateral direction (also called lateral growth), The pellets 5200 are connected to each other (see FIG. 24(C)). Lateral growth 5202 is formed until it fills the undeposited area. Deposition mechanism of atomic layer deposition (ALD) method Similar to a rhythm.

[0419] Therefore, even if the pellets 5200 are piled up in different directions, Since the grains 5203 grow laterally and fill the gaps between the grains 5200, clear grain boundaries are formed. In addition, the particles 5203 smoothly connect the pellets 5200. Therefore, a crystal structure different from single crystal and polycrystal is formed. A crystal structure having distortion between the crystal regions (pellets 5200) is formed. Since the regions filling the gaps are distorted crystalline regions, it is not appropriate to refer to these regions as amorphous structures. It is considered that this is not the case.

[0420] Next, a new pellet 5200 is deposited with its flat side facing the surface (see FIG. 24(D)). ) Then, the particles 5203 accumulate to fill the unaccumulated areas of the pellet 5200. By stacking the particles 520, a lateral growth portion 5202 is formed (see FIG. 24(E)). 3 adheres to the side of the pellet 5200, and the lateral growth portion 5202 grows laterally. The pellets 5200 in the mth layer are connected together (see FIG. 24(F)). The deposition continues until a thin film structure having a laminate is formed.

[0421] The deposition of the pellets 5200 also changes depending on the surface temperature of the substrate 5220. For example, if the surface temperature of the substrate 5220 is high, the pellet 5200 may be heated to the surface of the substrate 5220. As a result, the pellets 5200 are connected to each other through the particles 5203. The proportion of bonds without any bonds increases, resulting in a CAAC-OS with higher orientation. The surface temperature of the substrate 5220 during the formation of the OS film is equal to or higher than room temperature and lower than 340° C., and preferably, is equal to or higher than room temperature. More preferably, the temperature is from 100° C. to 250° C. ℃ or more and 200 ℃ or less. Therefore, the substrate 5220 is a large-area substrate of the 8th generation or more. Even when using a CAAC-OS, warping due to the deposition of the CAAC-OS hardly occurs. I understand.

[0422] On the other hand, when the surface temperature of the substrate 5220 is low, the pellet 5200 is mixed with the surface of the substrate 5220. As a result, pellets 5200 do not pile up on each other. In the case of nc-OS, the pellet 5200 is negatively charged. Due to this, the pellets 5200 may accumulate at regular intervals. Although the orientation is low, the film has a slight regularity, which makes it easier to form a film than an amorphous oxide semiconductor. The result is a dense structure.

[0423] In addition, in CAAC-OS, the gaps between the pellets are extremely small, Large pellets of one type may be formed. The inside of one large pellet has a single crystal structure. For example, the size of the pellet is 10 nm to 200 nm, 15 It may be between 20 nm and 50 nm, or between 20 nm and 50 nm.

[0424] According to the above-described film formation model, it is believed that the pellets are deposited on the surface of the substrate. CAAC-OS can be deposited even on a substrate that does not have a crystalline structure. Therefore, the above-mentioned film formation model, which has a growth mechanism different from epitaxial growth, is highly valid. In addition, because of the above-mentioned deposition model, the CAAC-OS and nc-OS It can be seen that it is possible to form a uniform film even on a large glass substrate. For example, Even if the structure of the substrate surface (the surface on which the film is formed) is amorphous (e.g., amorphous silicon oxide), It is possible to form a film of CAAC-OS.

[0425] In addition, even if the surface of the substrate on which the coating is to be applied is uneven, the pellets will adhere to the shape of the uneven surface. It is clear that the arrangement is

[0426] In addition, from the above-mentioned deposition model, the following conditions are required to deposit a CAAC-OS film with high crystallinity: First, in order to lengthen the mean free path, we need to use a higher vacuum. Next, in order to reduce damage near the substrate, the plasma energy is Next, heat energy is applied to the surface to be formed, and the plasma damage is reduced each time a film is formed. It will heal.

[0427] In addition, the above-mentioned deposition model is an In-M-Zn oxide target with multiple crystal grains. In the case where the material has a polycrystalline structure of a complex oxide such as a crystalline material, and one of the crystal grains contains a cleavage plane, For example, a mixture having indium oxide, an oxide of element M, and zinc oxide may be used. The present invention can also be applied to the case where an object target is used.

[0428] The target of the mixture does not have a cleavage plane, so when sputtered, atoms are ejected from the target. During film formation, a strong electric field region of plasma is formed near the target. Therefore, atomic particles detached from the target are connected by the action of the strong electric field region of the plasma. For example, first, atomic particles of indium join together and grow laterally, forming In Next, M-Zn-O layers are formed above and below it to complement it. Thus, even when a mixed target is used, pellets may be formed. Therefore, the above-mentioned deposition model can be applied even when a mixture target is used. It is possible.

[0429] However, if a strong electric field region of the plasma is not formed near the target, the target Only atomic particles detached from the substrate are deposited on the substrate surface. In some cases, atomic particles grow laterally. However, the orientation of the atomic particles is not uniform. However, the crystal orientation in the resulting thin film is not uniform. .

[0430] <2-6. Lateral growth> In the following, the particles 5203 are attached (also called bonded or adsorbed) in the lateral direction of the pellet 5200. .) and explain lateral growth.

[0431] Figure 25 (A) (B) (C) (D) (E) shows the structure of pellet 5200 and the metal ion attached. The pellet 5200 is a pellet having a crystal structure of InMZnO4. From the structure, a cluster model was assumed in which 84 atoms were extracted while maintaining the stoichiometric composition. In the following, the case where the element M is Ga will be described. 25(G) shows the structure of the pellet 5200 as viewed from a direction parallel to the c-axis. The structure of the 5200 is shown as viewed from a direction parallel to the a-axis.

[0432] The positions where the metal ions are attached are indicated as position A, position B, position a, position b and position c. Position A is a grid surrounded by one gallium particle and two zinc particles on the top surface of the pellet 5200. Position B is above the interatomic site, on the top surface of pellet 5200, with two gallium and zinc Position a is above the interstitial site surrounded by one. Position b is the In-O layer and the Ga-Zn layer on the side of the pellet 5200. Position c is the gallium site on the side of pellet 5200. It is.

[0433] Next, metal ions were placed at the assumed positions A, B, a, b, and c. The relative energies for the two cases were evaluated by first-principles calculations. Using the Vienna Ab initio Simulation Package In addition, the exchange-correlation potential is PBE (Perdew-Burke-Ernzerh of) type Generalized Gradient Approximation (GGA) pproximation is used, and PAW (Project The cutoff energy was set at 40 0 eV, and k-point sampling was performed only at the Γ point. At positions b and c, indium ions (In 3+ ), gallium ion (Ga 3+ ) and and zinc ion (Zn 2+ The relative energy is shown when the In the calculated models, the energy of the lowest model is set to 0 eV. This is the relative value when

[0434] [Table 2]

[0435] As a result, it was found that metal ions were more likely to adhere to the side of the pellet 5200 than to the top. In particular, in the indium site at position a, not only indium ions but also The results also showed that zinc ions were most likely to adhere to the surface.

[0436] Similarly, oxygen ions (O 2- The adhesion of the fluoride was evaluated. 6(A)(B)(C)(D)(E) show the structure of pellet 5200 and the oxygen ions attached to it. FIG. 26(F) shows the position of the pellet 5200 from a direction parallel to the c-axis. FIG. 26(G) shows the structure of the pellet 5200 as viewed from a direction parallel to the b-axis. show.

[0437] The positions where oxygen ions are attached are shown as position C, position D, position d, position e, and position f. Position C is the position where the gallium on the top surface of the pellet 5200 is bonded. The position d is the position where the zinc on the top of the pellet 5200 is bonded to the zinc on the side of the pellet 5200. Position e is the position where the gallium on the side of pellet 5200 bonds with the indium. Position f is the position where the zinc bonds with the side of the pellet 5200.

[0438] Next, oxygen ions were placed at the assumed positions C, D, d, e, and f. The relative energies for the two cases are evaluated by first-principles calculations. Table 3 shows the relative energies for positions C, D, and d, oxygen ions (O 2- ) is placed in the vinegar.

[0439] [Table 3]

[0440] As a result, it was found that oxygen ions also tend to adhere to the side of the pellet 5200 rather than to its top. I did.

[0441] Therefore, the particle 5203 approaching the pellet 5200 is stuck to the side of the pellet 5200. It can be seen that the particles 52 adhere preferentially to the side of the pellet 5200. The above-mentioned deposition model in which the lateral growth of pellet 5200 occurs is highly valid. It can be said that.

[0442] The configuration shown in this embodiment may be appropriately combined with configurations shown in other embodiments or examples. , can be used in combination.

[0443] (Embodiment 3) In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 45. In the present embodiment, the display element of the display device is A configuration (liquid crystal display device) having a liquid crystal element will be specifically described.

[0444] <3-1.Liquid crystal display device> A liquid crystal display device 880 shown in FIG. 27(A) includes a pixel portion 871, a gate driver 874, and , a source driver 876, and a gate driver 8 74, m scanning lines 877 whose potentials are controlled by the and n signal lines 879 whose potentials are controlled by a source driver 876. Furthermore, the pixel section 871 has a plurality of pixels 870 arranged in a matrix. , along the signal line 879, each of which has a common line 875 arranged in parallel or approximately parallel to each other. In addition, the gate driver 874 and the source driver 876 may be collectively referred to as a drive circuit section. There is a match.

[0445] Each scanning line 877 corresponds to one of the pixels 870 arranged in m rows and n columns in the pixel section 871. , electrically connected to n pixels 870 arranged in any row. The line 879 is a pixel array of m pixels arranged in one of the columns of the pixels 870 arranged in m rows and n columns. The pixel 870 is electrically connected to the m and n. The pixel line 875 is formed by dividing m pixels 870 arranged in m rows and n columns in any one of the rows. The pixel 870 is electrically connected to the pixel 870.

[0446] FIG. 27B shows a pixel 870 of the liquid crystal display device 880 shown in FIG. 1 shows an example of a possible circuit configuration.

[0447] A pixel 870 shown in FIG. 27B includes a liquid crystal element 851, a transistor 852, and a capacitor. It has a child 855.

[0448] The transistor described in the above embodiment 1 can be used as the transistor 852. Cut.

[0449] One of a pair of electrodes of the liquid crystal element 851 is connected to a transistor 852. The other of the pair of electrodes of the liquid crystal element 851 is connected to the common line 875, and a common potential (common potential) is applied. The alignment state of the liquid crystal is controlled by data written to the transistor 852 .

[0450] The liquid crystal element 851 controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation effect of liquid crystals is achieved by the electric field applied to the liquid crystal (horizontal electric field, vertical electric field). The liquid crystal element 851 is controlled by a directional electric field or an oblique electric field. The liquid crystals used are thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, and polymer dispersed liquid crystals. The liquid crystal material may be a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like. Therefore, cholesteric phase, smectic phase, cubic phase, chiral nematic phase, etc. Shows dimensions etc.

[0451] In addition, when the in-plane switching method is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is used in the liquid crystal layer. It has a short response time and is optically isotropic. It also contains a liquid crystal that exhibits a blue phase and a chiral agent. The liquid crystal composition does not require alignment treatment and has little viewing angle dependency. Since the rubbing process is unnecessary, the electrostatic breakdown caused by the rubbing process is eliminated. Therefore, defects and damage to the liquid crystal display device during the manufacturing process can be reduced. do.

[0452] A liquid crystal display device 880 having a liquid crystal element 851 is driven by a TN (Twiste) d Nematic mode, IPS (In-Plane-Switching) mode , FFS (Fringe Field Switching) mode, ASM (Axia lly Symmetric aligned Micro-cell mode, OCB (Optical Compensated Birefringence) mode, F LC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. It can be used.

[0453] In addition, the liquid crystal display device 880 is a normally black type liquid crystal display device, for example, a vertical alignment ( The liquid crystal display device may be a transmissive type liquid crystal display device that employs a vertical alignment (VA) mode. MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV Modes, etc. can be used.

[0454] <3-2. In-plane switching mode LCDs> First, the horizontal electric field modes, typically the FFS mode and the IPS mode, will be described.

[0455] In the configuration of the pixel 870 shown in FIG. One of the drain electrodes is electrically connected to a signal line 879, and the other is a pair of drain electrodes of the liquid crystal element 851. The gate electrode of the transistor 852 is electrically connected to one of the electrodes of the scan line The transistor 852 is electrically connected to the data input terminal 877. It has the function of controlling.

[0456] In the configuration of the pixel 870 shown in FIG. 27B, one of a pair of electrodes of the capacitor 855 is , is connected to the other of the source electrode and the drain electrode of the transistor 852. The other of the pair of electrodes 5 is electrically connected to a common line 875. The value of is set appropriately according to the specifications of the pixel 870. The liquid crystal display functions as a storage capacitor to hold the data. In the liquid crystal display device 880, one of a pair of electrodes of the capacitor element 855 is connected to the liquid crystal element 851. The other of the pair of electrodes of the capacitor 855 is a liquid crystal It is a part or the whole of the other of the pair of electrodes of the element 851 .

[0457] <3-3. Configuration example 1 of transverse electric field mode element substrate> Next, a specific configuration of the element substrate included in the liquid crystal display device 880 will be described. A liquid crystal display device 880 driven in the FFS mode has a plurality of pixels 870a, 87 The top views of 870b and 870c are shown in FIG.

[0458] In FIG. 28, the conductive film 813 functioning as the scanning line is oriented in a direction substantially perpendicular to the signal line ( The conductive film 821a, which functions as a signal line, is provided so as to extend in the center (left and right direction). The scanning lines are provided so as to extend in a direction substantially perpendicular to the scanning lines (the vertical direction in the drawing). The conductive film 813 is electrically connected to a gate driver 874 and serves as a signal line. The functioning conductive film 821a is electrically connected to the source driver 876 (FIG. 27( See A).

[0459] The transistor 852 is provided near the intersection of the scan line and the signal line. The gate electrode 852 includes a conductive film 813 that functions as a gate electrode, a gate insulating film (not shown in FIG. 28), ), an oxide semiconductor film 808 in which a channel region is formed on the gate insulating film, The conductive film 821a and the conductive film 821b function as a source electrode and a drain electrode. The conductive film 813 also functions as a scan line. The conductive film 821a functions as a gate electrode of the transistor 852. The region overlapping with the oxide semiconductor film 808 serves as a source electrode or In FIG. 28, the scanning line has a top view with an end The portion is located outside the edge of the oxide semiconductor film 808. As a result, the oxide contained in the transistor Since the compound semiconductor film 808 is not irradiated with light, the fluctuation of the electrical characteristics of the transistor can be suppressed. can.

[0460] The conductive film 821b is electrically connected to the oxide semiconductor film 819a having a function of a pixel electrode. In addition, an insulating film (not shown in FIG. 28) is formed over the oxide semiconductor film 819a. A common electrode 829 is provided therebetween.

[0461] The common electrode 829 has striped regions extending in a direction intersecting the signal lines. The striped regions are connected to regions extending in a direction parallel or approximately parallel to the signal lines. In a plurality of pixels of the liquid crystal display device 880, a common electrode 82 having a striped region 9, each region is at the same potential.

[0462] The capacitor 855 is formed in a region where the oxide semiconductor film 819a and the common electrode 829 overlap with each other. The oxide semiconductor film 819a and the common electrode 829 have a light-transmitting property. The element 855 has light-transmitting properties.

[0463] In addition, since the capacitor 855 has a light-transmitting property, the capacitor 855 is large and is disposed in the pixel 870. Therefore, the aperture ratio can be increased, typically to 50% or more. Preferably, the charge amount can be increased to 60% or more. For example, in a display device with high resolution, such as a liquid crystal display device, The area of ​​the element is reduced, and the area of ​​the capacitive element is also reduced. This allows for a display device with high resolution. In this embodiment, however, the amount of charge stored in the capacitance element is small. Since the capacitor 855 has a light-transmitting property, the capacitor is provided in each pixel. This allows the aperture ratio to be increased while obtaining a sufficient amount of charge in the pixel. High resolution of 1000ppi or more, 300ppi or more, or even 500ppi or more The present invention can be suitably used in display devices.

[0464] In addition, in a liquid crystal display device, the larger the capacitance value of the capacitance element, the more In the liquid crystal display device, the period during which the alignment of the liquid crystal molecules in the liquid crystal element can be kept constant can be extended. When displaying a still image, the period can be extended, reducing the frequency with which image data is rewritten. It is possible to reduce the number of circuits, and therefore the power consumption. The structure shown in FIG. 1 can increase the aperture ratio even in a high-resolution display device. It is possible to efficiently use light from light sources such as backlights, thereby reducing the power consumption of display devices. It is possible.

[0465] Next, cross-sectional views taken along dashed lines Q1-R1 and S1-T1 in FIG. 9. The transistor 852 shown in FIG. 29 is a channel-etched transistor. The dashed line Q1-R1 indicates the channel length direction of the transistor 852 and the capacitance element 8 55, the cross section taken along line S1-T1 shows the channel width of transistor 852. In FIG. 28, the oxide semiconductor functioning as the second gate electrode is The membrane 819b has been omitted for clarity of the drawing.

[0466] The transistor 852 shown in FIG. 29 has a first gate electrode provided on a substrate 811. A conductive film 813 functioning as a first gate electrode, a substrate 811, and a conductive film 812 functioning as a first gate electrode. 3, an insulating film 815 formed on the insulating film 815, and an insulating film The oxide film 815 and the insulating film 817 overlap with the conductive film 813 functioning as a gate electrode. A semiconductor film 808 and a source electrode and a drain electrode in contact with the oxide semiconductor film 808 are The conductive films 821a and 821b functioning as a source electrode and a drain electrode, the oxide semiconductor film 808, and the conductive films 821a and 821b functioning as a source electrode and a drain electrode. Insulating films 823 and 825 are provided over the conductive films 821a and 821b which function as gate electrodes. an oxide semiconductor film 819b which functions as a second gate electrode over an insulating film 825; 825 and an insulating film 827 over the oxide semiconductor film 819b.

[0467] In addition, an oxide semiconductor film 819a is formed over the insulating film 825. 9a denotes one of conductive films 821a and 821b which function as a source electrode and a drain electrode. Here, the conductive film 821b, the insulating film 823, and the insulating film 825 are formed through openings. An insulating film 827 is formed over the insulating film 825 and the oxide semiconductor film 819a. In addition, a common electrode 829 is formed on the insulating film 827.

[0468] In addition, in a region where the oxide semiconductor film 819a, the insulating film 827, and the common electrode 829 overlap with each other, functions as a capacitor 855 .

[0469] The cross-sectional structure of one aspect of the embodiment of the present invention is not limited to this. For example, an oxide The oxide semiconductor film 819a may have a slit. The shape may also be used.

[0470] As shown in FIG. 30, the common electrode 829 is formed on the insulating film 827. The insulating film 828 may be provided on the insulating film 828. The insulating film 828 functions as a planarization film.

[0471] <3-4. Configuration example 2 of transverse electric field mode element substrate> Next, a liquid crystal display device 880 includes a plurality of pixels 8 having a different configuration from the pixels shown in FIG. 31 shows top views of 70d, 870e, and 870f. The liquid crystal display device 880 shown in FIG. is driven in IPS mode.

[0472] In FIG. 31, the conductive film 813 functioning as a scanning line is provided extending in the left-right direction in the figure. The conductive film 821a functioning as a signal line has a bent V-shape. The scanning line is extended in a direction substantially perpendicular to the scanning line (the vertical direction in the figure) so as to have a shape similar to that of the scanning line. The conductive film 813 functioning as a scan line is electrically connected to a gate driver 874. The conductive film 821a functioning as a signal line is electrically connected to the source driver 876. (See FIG. 27(A)).

[0473] The transistor 852 is provided near the intersection of the scan line and the signal line. The gate electrode 852 includes a conductive film 813 that functions as a gate electrode, a gate insulating film (not shown in FIG. 31), ), an oxide semiconductor film 808 in which a channel region is formed on the gate insulating film, The conductive film 821a and the conductive film 821b function as a source electrode and a drain electrode. The conductive film 813 also functions as a scan line. The conductive film 821a functions as a gate electrode of the transistor 852. The region overlapping with the oxide semiconductor film 808 serves as a source electrode or In FIG. 31, the scanning line has a top view with an end The portion is located outside the edge of the oxide semiconductor film 808. As a result, the oxide contained in the transistor Since the compound semiconductor film 808 is not irradiated with light, the fluctuation of the electrical characteristics of the transistor can be suppressed. can.

[0474] The conductive film 821b is electrically connected to the oxide semiconductor film 819a having a function of a pixel electrode. The oxide semiconductor film 819a is formed in a comb-like shape. An insulating film (not shown in FIG. 31) is provided on 819a, and a common electrode 829 is provided on the insulating film. The common electrode 829 is provided on the upper surface of the oxide semiconductor film 819a so as to partially overlap with the oxide semiconductor film 819a. In the plan view, the interdigital transducer 817 is formed in a comb shape so as to be engaged with the oxide semiconductor film 819a. The scan electrodes 829 are connected to areas that extend in a direction parallel or nearly parallel to the scan lines. Therefore, in a plurality of pixels of the liquid crystal display device 880, the common electrodes 829 are at the same potential. Note that the oxide semiconductor film 819a and the common electrode 829 are connected to the signal line (the conductive film 821a). It has a V-shaped curve that follows the curve.

[0475] The capacitor 855 is formed in a region where the oxide semiconductor film 819a and the common electrode 829 overlap with each other. The oxide semiconductor film 819a and the common electrode 829 have a light-transmitting property. The element 855 has light-transmitting properties.

[0476] Next, cross-sectional views taken along dashed lines Q2-R2 and S2-T2 in FIG. 2. The transistor 852 shown in FIG. 32 is a channel-etched transistor. The dashed line Q2-R2 indicates the channel length direction of the transistor 852 and the capacitance element 8 55, the cross section taken along line S2-T2 shows the channel width of transistor 852. In FIG. 31, the oxide semiconductor functioning as the second gate electrode is The membrane 819b has been omitted for clarity of the drawing.

[0477] The transistor 852 shown in FIG. 32 functions as a gate electrode provided on a substrate 811. A conductive film 813 serving as a gate electrode and a conductive film 814 serving as a gate electrode are formed on the substrate 811 and the conductive film 813. an insulating film 815 formed on the insulating film 815; an insulating film 817 formed on the insulating film 815; The oxide semiconductor film 8 overlaps with the conductive film 813 functioning as a gate electrode with the insulating film 817 interposed therebetween. 808 and a conductive film serving as a source electrode and a drain electrode in contact with the oxide semiconductor film 808. The oxide semiconductor film 808 is a source electrode and a drain electrode. Insulating films 823 and 825 provided on the functional conductive films 821a and 821b, and insulating film 82 The oxide semiconductor film 819b serving as a second gate electrode over the insulating film 825 and the oxide semiconductor film 826 and an insulating film 827 on the nitride semiconductor film 819b.

[0478] In addition, an oxide semiconductor film 819a is formed over the insulating film 825. 9a denotes one of conductive films 821a and 821b which function as a source electrode and a drain electrode. Here, the conductive film 821b, the insulating film 823, and the insulating film 825 are formed through openings. An insulating film 827 is formed over the insulating film 825 and the oxide semiconductor film 819a. In addition, a common electrode 829 is formed on the insulating film 827.

[0479] In addition, in a region where the oxide semiconductor film 819a, the insulating film 827, and the common electrode 829 overlap with each other, functions as a capacitor 855 .

[0480] The liquid crystal display device shown in FIGS. 31 and 32 includes an oxide semiconductor film 819a and a common electrode 82. The vicinity of the ends of the respective electrodes 9 are overlapped to form a capacitance element of the pixel. With such a configuration, the capacitance element can be appropriately sized without being too large in a large liquid crystal display device. It can be formed to any size.

[0481] As shown in FIG. 33, the common electrode 829 is disposed on the insulating film 827. It may be provided on 828.

[0482] 34 and 35, the oxide semiconductor film 819a and the common electrode 829 The size of the capacitor element may be determined according to the resolution and driving method of the display device. In this way, the positional relationship between the oxide semiconductor film 819a and the common electrode 829 can be appropriately determined. It should be noted that the common electrode 829 of the display device shown in FIG. 35 functions as a flattening film. Alternatively, the insulating film 828 may be provided on the insulating film 828 (see FIG. 36).

[0483] 31 and 32, the signal line (conductor) of the oxide semiconductor film 819a The width (d1 in FIG. 32) of the region extending in a direction parallel or approximately parallel to the conductive film 821a) is The width of the region of the signal line of the pin electrode 829 that extends in a direction parallel or approximately parallel to the signal line (d2 in FIG. 32) is As shown in Figs. 37 and 38, the width The width d1 may be greater than the width d2. Also, the width d1 and the width d2 may be equal. In a pixel (for example, pixel 870d), the oxide semiconductor film 819a and / or the common electrode The widths of a plurality of regions of the electrode 829 extending in a direction parallel or substantially parallel to the signal line are different from each other. It may be possible.

[0484] As shown in FIG. 39, an insulating film 828 provided on the insulating film 827 is 8 may be removed leaving only the area overlapping with the common electrode 829 on the substrate 8. In this case, the insulating film 828 can be etched using the common electrode 829 as a mask. The unevenness of the common electrode 829 on the insulating film 828, which functions as a flattening film, can be suppressed. The side of the insulating film 828 is gently sloping from the end of the common electrode 829 to the insulating film 827. As shown in FIG. 40, the surface of the insulating film 828 that is parallel to the substrate 811 A configuration in which part of the area is not covered by the common electrode 829 is also possible.

[0485] 41 and 42, the common electrode is formed in the same layer as the oxide semiconductor film 819a. The common electrode 821 may be provided on the insulating film 825. The electrode 819c is formed using the same material as the oxide semiconductor film 819a. It can be formed by processing.

[0486] <3-5. Vertical alignment mode liquid crystal display device> Next, we developed a liquid crystal display (LCD) that operates in vertical alignment (VA) mode. The structure of a pixel having a liquid crystal element will be described with reference to Figs. 43 and 44. 44 is a top view of a pixel included in a liquid crystal display device, taken along the line A1-B1 in FIG. FIG. 45 is an equivalent circuit diagram of a pixel included in the liquid crystal display device. do.

[0487] VA type is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. In a liquid crystal display device, when no voltage is applied, the liquid crystal molecules are oriented vertically to the panel surface. This is a method that faces the camera.

[0488] In the following, we will divide a pixel into several regions (subpixels) and The molecules are designed to bend in different directions. In the following explanation, a liquid crystal display device in which a multi-domain design is taken into consideration will be described. He explains.

[0489] In FIG. 43, Z1 is a top view of the substrate 600 on which the pixel electrode 624 is formed, and Z3 is a common 6 is a top view of the substrate 601 on which the electrode 640 is formed, and Z2 is a top view of the substrate 601 on which the pixel electrode 624 is formed. 6 is a top view of a state in which a substrate 600 and a substrate 601 on which a common electrode 640 is formed are superimposed. be.

[0490] On the substrate 600, a transistor 628 and a pixel electrode 624 connected thereto, and a capacitance element A drain electrode 618 of the transistor 628 is formed by insulating film 623 and The insulating film 625 is electrically connected to the pixel electrode 624 through an opening 633 formed in the insulating film 625. An insulating film 627 is provided on the element electrode 624 .

[0491] The transistor described in the first embodiment can be used as the transistor 628. Cut.

[0492] The capacitance element 630 is formed by a wiring 613 on the capacitance wiring 604 which is a first capacitance wiring and an insulating film 6 The capacitance wiring 604 is made up of a transistor 623, an insulating film 625, and a pixel electrode 624. The gate wiring 615 of the gate electrode 628 can be formed of the same material at the same time. 13 can be formed simultaneously with the drain electrode 618 and the wiring 616 using the same material. do.

[0493] The pixel electrode 624 is formed using the oxide semiconductor film having low sheet resistance described in Embodiment 1. can be applied.

[0494] The pixel electrode 624 is provided with a slit 646. The slit 646 controls the alignment of the liquid crystal. This is for the purpose.

[0495] The transistor 629 and the pixel electrode 626 and the capacitor element 631 connected thereto are The transistor 628, the pixel electrode 624, and the capacitor element 630 can be formed in the same manner. The transistor 628 and the transistor 629 are both connected to the wiring 616. 6 serves as a source electrode in the transistor 628 and the transistor 629. The pixel of the liquid crystal display panel shown in this embodiment has a pixel electrode 624 and a pixel electrode 626. The pixel electrode 624 and the pixel electrode 626 are sub-pixels.

[0496] A colored film 636 and a common electrode 640 are formed on the substrate 601. A structure 644 is formed. A slit 647 is provided in the common electrode 640. An alignment film 648 is formed on the pixel electrode 624, and a common electrode 640 and a structure An alignment film 645 is formed on the structure 644. A liquid crystal layer is formed between the substrate 600 and the substrate 601. 650 has been formed.

[0497] The slits 647 formed in the common electrode 640 and the structures 644 control the alignment of the liquid crystal. It has the function of controlling

[0498] When a voltage is applied to the pixel electrode 624 having the slit 646, The slit 646 and the structure 6 on the substrate 601 side generate distortion of the electric field (diagonal electric field). By arranging the slits 44 and slits 647 so that they interdigitate with each other, the oblique electric field is effectively By controlling the orientation of the liquid crystals, the direction in which the liquid crystals are oriented can be made to differ depending on the location. In other words, the viewing angle of the liquid crystal display panel is widened by making it multi-domain. Either the structure 644 or the slit 647 is provided on the plate 601 side. This is also fine.

[0499] FIG. 44 shows a state in which the substrate 600 and the substrate 601 are overlapped and liquid crystal is injected. The pixel electrode 624, the liquid crystal layer 650, and the common electrode 640 are overlapped with each other, so that the liquid crystal pixel A child is formed.

[0500] An equivalent circuit of this pixel structure is shown in FIG. 45. Transistors 628 and 629 are , both of which are connected to the gate wiring 602 and the wiring 616. In this case, the capacitance wiring 604 and the capacitance By making the potential of the wiring 605 different, the operations of the liquid crystal elements 651 and 652 can be made different. That is, the potentials of the capacitance wiring 604 and the capacitance wiring 605 can be controlled individually. This enables precise control of the alignment of the liquid crystals to widen the viewing angle.

[0501] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0502] (Embodiment 4) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 47. In the present embodiment, a display element of the display device is A configuration having an electroluminescence (EL) element will now be specifically described.

[0503] <4-1. Explanation of display device> The display device shown in FIG. 46A has a region having pixels of a display element (hereinafter, referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504) and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. This is also fine.

[0504] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or the whole of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Band). It can be implemented by using the onding.

[0505] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter, referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter, a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a) to provide a signal (data signal) for driving the display element of the pixel. The pixel circuit 504 includes a driver circuit such as a circuit (hereinafter, referred to as a source driver 504b).

[0506] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is input via a terminal unit 507, and a signal is output. For example, a start pulse signal, a clock signal, etc. are input to the gate driver 504a. The gate driver 504a outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it. However, the gate driver 50 has a function of supplying 4a can also supply other signals. For example, as shown in FIG. The light driver 504a is a wiring for controlling the potential of the light-emitting element (hereinafter, ANODE_1 to ANODE_2). NODE_X).

[0507] The source driver 504b includes a shift register and the like. Through the terminal section 507, a signal for driving the shift register as well as a source of a data signal are input. The source driver 504b outputs a pixel circuit based on the image signal. The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data line 101 through the data line 102. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0508] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a number of analog switches, The image signal can be time-division-multiplexed and output as a data signal. Also, a shift register, etc. This may be used to configure the source driver 504b.

[0509] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is inputted through the data line DL, and a data signal is given through one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. For example, The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or smaller than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via a source driver 504c (n is a natural number equal to or smaller than Y).

[0510] The protection circuit 506 shown in FIG. 46(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal unit 507. Alternatively, the protection circuit 506 may be a wiring between the source driver 504b and the terminal unit 507. The terminal unit 507 can be connected to a power supply and a power supply line from an external circuit to the display device. This refers to the part provided with terminals for inputting control signals and image signals.

[0511] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit This is a circuit that brings one wire into electrical continuity with another wire.

[0512] As shown in FIG. 46A, a protection circuit 50 is provided in each of a pixel section 502 and a driver circuit section 504. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrent caused by electrostatic discharge (ESD) and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a protection circuit 506 is connected to the source driver 504b Alternatively, a protection circuit 506 may be connected to the terminal portion 507. It can also be done like this.

[0513] In FIG. 46(A), the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a source driver circuit is formed separately. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is It may also be configured to be equipped with

[0514] <4-2. Example of pixel circuit configuration> In addition, the pixel circuits 501 shown in FIG. 46(A) may have a configuration shown in FIG. 46(B), for example. It can be said that:

[0515] The pixel circuit 501 shown in FIG. 46B includes transistors 552 and 554 and a capacitor 56. 2 and a light-emitting element 572. The transistor described in any of the above embodiments can be used for either or both of them.

[0516] A data signal is applied to one of the source and drain electrodes of the transistor 552. The transistor 55 is electrically connected to a wiring (hereinafter, referred to as a signal line DL_n). The gate electrode of 2 is electrically connected to the wiring (hereinafter referred to as the scanning line GL_m) to which the gate signal is applied. are connected to the network.

[0517] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0518] One of a pair of electrodes of the capacitor 562 is the source electrode and the drain electrode of the transistor 552. The other of the pair of electrodes of the capacitor 562 is electrically connected to the transistor. The second gate electrode (also referred to as a backgate electrode) of the transistor 554 is electrically connected to the second gate electrode (also referred to as a backgate electrode) of the transistor 554 . The capacitor 562 functions as a storage capacitor for storing written data.

[0519] One of the source and drain electrodes of the transistor 554 is connected to the anode line (ANODE _m).

[0520] One of the anode and cathode of the light emitting element 572 is connected to the source electrode of the transistor 554 and The other end is electrically connected to the cathode line (CATHODE). In addition, a capacitance element is electrically connected to one of the anode and the cathode of the light emitting element 572. The other of the pair of electrodes 562 is electrically connected.

[0521] The light emitting element 572 may be, for example, an organic EL element. The element 572 is not limited to this, and an inorganic EL element made of an inorganic material may also be used.

[0522] In a display device having the pixel circuit 501 shown in FIG. 46(B), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0523] In the pixel circuit 501 to which the data has been written, the transistor 552 is turned off. Furthermore, the transistor 554 is in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted with a brightness that corresponds to the flow rate. By performing this process row by row, an image can be displayed.

[0524] In this embodiment, the display device has a light-emitting element 572 as a display element. Although the configuration is illustrated, the display device is not limited to this and may have various elements. .

[0525] The display device may include, in addition to the liquid crystal element described above, LEDs (white LEDs, red LEDs, Green LED, blue LED, etc.), transistors (transistors that emit light according to the current), Electron emission element, electronic ink, electrophoretic element, grating light valve (GLV), Plasma display (PDP), MEMS (Micro-Electro-Mechanical System) Display elements using digital micromirror devices (DMDs), digital micromirror devices (DMSs), ·Micro·Shutter), MIRASOL (registered trademark), IMOD (Interference Modulation MEMS display elements using the shutter method, and MEMS display elements using the optical interference method MS display element, electrowetting element, piezoelectric ceramic display, carbon In addition to these, the device also has at least one display element using nanotubes. A display whose contrast, brightness, reflectance, transmittance, etc. change due to electrochemical or magnetic effects. An example of a display device using electron-emitting devices is a field-effect display device. Mission Display (FED) or SED type flat panel display (SED: Sur face-conduction electron-emitter display An example of a display device using liquid crystal elements is a liquid crystal display (transmission type liquid crystal display). LCD, semi-transmissive LCD, reflective LCD, direct-view LCD Spray, projection type liquid crystal display, etc. Electronic ink or electrophoretic element An example of a display device is electronic paper. To realize a reflective LCD, some or all of the pixel electrodes are reflective. For example, a part or the whole of the pixel electrode may be Aluminum, silver, etc. may be used. In that case, the reflective electrode may be provided below the reflective electrode. It is also possible to provide a memory circuit such as an SRAM. This further reduces power consumption. can be reduced.

[0526] The display device uses a progressive method, an interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB ( R stands for red, G for green, and B for blue). For example, It may be composed of four pixels, a B pixel and a W (white) pixel. Or, it may be arranged in a Pentile array. As shown in the figure, two colors of RGB compose one color element, and two different colors are selected depending on the color element. Alternatively, one or more colors such as yellow, cyan, magenta, etc. may be added to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a color display device, and may be used for a monochrome display device. The present invention can also be applied to display devices.

[0527] Also, backlights for display devices (organic EL elements, inorganic EL elements, LEDs, fluorescent lights, etc.) A white light (W) may be provided to the display device. Also, a colored layer (also called a color filter) may be provided to the display device. The colored layer may be, for example, a red (R), green (G), or blue (B ), yellow (Y), etc. can be used in appropriate combination. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a color layer and a region not having a color layer, The white light in the region may be directly used for display. By placing the colored layer over the entire display, the decrease in brightness caused by the colored layer can be reduced during bright display, and power consumption can be reduced by 2. However, in some cases, the emission of light from organic EL elements and inorganic EL elements can be reduced by about 10 to 30%. When using optical elements to display full color, R, G, B, Y, and white (W) are The color layer may be formed by using a self-luminous element. In some cases, power consumption can be reduced even further than when using a conventional method.

[0528] <4-3. Example of pixel configuration of display device> Here, regarding an example of a display device having the pixel circuit shown in FIG. FIG. 47(A) is a top view of a pixel portion of a display device, and FIG. 47(A) is a cross-sectional view taken along the dashed line X1-X2 in FIG. In order to avoid the diagram becoming too complicated, some of the components are omitted.

[0529] The display device shown in FIG. 47 includes a conductive film 70 functioning as a first gate electrode over a substrate 702. 4, insulating films 706 and 707 on the conductive film 704, and an oxide semiconductor film 70 on the insulating film 707. 8, and a source electrode and a drain electrode over the insulating film 707 and the oxide semiconductor film 708. The conductive films 712a and 712b that function, the conductive film 712c on the insulating film 707, and the oxide semiconductor Insulating films 714 and 716 cover the conductive film 708 and the conductive films 712a, 712b, and 712c. An oxide semiconductor film 720 serving as a second gate electrode over the film 716 and an insulating film and an insulating film 718 over the oxide semiconductor film 720, which serves as a planarizing insulating film over the insulating film 718. and conductive films 724a and 724b which function as pixel electrodes on the insulating film 722. b, and a structure having a function of suppressing electrical connection between the conductive film 724a and the conductive film 724b. 726, an EL layer 728 on the conductive films 724a, 724b and the structure 726, and an EL layer 72 8 and a conductive film 730 on the substrate 710.

[0530] The conductive film 712c is formed through an opening 752c provided in the insulating films 706 and 707. The oxide semiconductor film 702 is electrically connected to the conductive film 704. The conductive film 720 is connected to the conductive film 712 through an opening 752 a provided in the insulating films 714 and 716 . The conductive film 724a is electrically connected to the insulating films 714, 716, 718, and 719. 22 is electrically connected to the conductive film 712b through an opening 752b provided in the conductive film 752b.

[0531] In addition, a conductive film 724a functioning as a pixel electrode, an EL layer 728, a conductive film 730, The light emitting element 572 is formed. The EL layer 728 is formed by sputtering, evaporation, or the like. printing methods (including vacuum deposition methods), printing methods (such as letterpress printing, intaglio printing, gravure printing, It can be formed by methods such as lithographic printing, stencil printing, ink jet printing, coating, etc. do.

[0532] As shown in FIG. 46(B) and FIG. 47(A) and (B), the pixel configuration of the display device is as follows: By using a structure including two transistors and one capacitor, the number of wirings can be reduced. For example, as shown in FIG. 46(B) and FIG. 47(A), the pixel may have a gate. The three lines can be a ground line, a data line, and an anode line. This makes it possible to increase the aperture ratio of the pixels of the display device. This makes it difficult for short circuits to occur between adjacent wiring, providing display devices with high yields. It becomes possible to do so.

[0533] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0534] (Embodiment 5) In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention and a display device including the semiconductor device An electronic device having an input device attached thereto will be described with reference to FIGS.

[0535] <5-1. Explanation of the touch panel> In the present embodiment, an electronic device that combines a display device and an input device is used as an example of the electronic device. A touch panel 2000 having the touch sensor 2000 will be described. The case where the .

[0536] 48(A) and (B) are perspective views of the touch panel 2000. In B), representative components of touch panel 2000 are shown for clarity.

[0537] The touch panel 2000 includes a display device 2501 and a touch sensor 2595 (see FIG. 4). 8(B)). The touch panel 2000 includes a substrate 2510, a substrate 2570, and a substrate The substrate 2510, the substrate 2570, and the substrate 2590 are all However, any one of the substrates 2510, 2570, and 2590 may be flexible. Alternatively, one or all of the components may be configured to be inflexible.

[0538] The display device 2501 includes a plurality of pixels on a substrate 2510 and a display device that can supply signals to the pixels. The plurality of wirings 2511 are arranged around the periphery of the substrate 2510. The wire is routed through a wire loop, part of which constitutes the terminal 2519. The terminal 2519 is an FPC 2509 (1) and electrically connect it.

[0539] The substrate 2590 is electrically connected to the touch sensor 2595. The plurality of wirings 2598 are routed around the periphery of the substrate 2590. A part of the terminal is electrically connected to the FPC2509(2). In FIG. 48(B), for clarity, the back side of the substrate 2590 (substrate 2510) is shown. The electrodes and wiring of the touch sensor 2595 provided on the surface opposite to the touch panel 2591 are shown by solid lines. .

[0540] As the touch sensor 2595, for example, a capacitive touch sensor can be used. The capacitive type includes a surface type capacitive type and a projected type capacitive type.

[0541] The projected capacitive type is classified into self-capacitance type, mutual capacitance type, etc., mainly based on the difference in the driving method. The mutual capacitance method is preferable because it enables simultaneous multi-point detection.

[0542] The touch sensor 2595 shown in FIG. 48(B) is a projected capacitive touch sensor. This is a configuration in which the .

[0543] The touch sensor 2595 can detect the proximity or contact of a detection target such as a finger. Various sensors can be applied.

[0544] The projected capacitive touch sensor 2595 has an electrode 2591 and an electrode 2592. The electrode 2591 is electrically connected to one of a plurality of wirings 2598, and the electrode 2592 is It is electrically connected to any other of the multiple wirings 2598.

[0545] As shown in FIG. 48(A)(B), the electrodes 2592 are arranged in a single direction. The shape is such that the quadrilaterals are connected at their corners.

[0546] The electrode 2591 is quadrilateral and is repeated in a direction intersecting the direction in which the electrode 2592 extends. are placed.

[0547] The wiring 2594 is electrically connected to the two electrodes 2591 that sandwich the electrode 2592. In this case, it is preferable that the area of ​​the intersection between the electrode 2592 and the wiring 2594 is as small as possible. This reduces the area of ​​the region where no electrodes are provided, reducing variations in transmittance. As a result, the variation in the brightness of the light passing through the touch sensor 2595 can be reduced. can be done.

[0548] The shapes of the electrodes 2591 and 2592 are not limited to this, and may take various shapes. For example, multiple electrodes 2591 are arranged with as few gaps as possible, and are A plurality of electrodes 2592 are provided at intervals so that there is an area where the electrodes 2592 do not overlap with the electrodes 2591. In this case, a wire may be provided between two adjacent electrodes 2592, which is electrically isolated from the two adjacent electrodes 2592. Providing an insulated dummy electrode is preferable because it can reduce the area of ​​the region with different transmittance. .

[0549] In addition, the conductive films such as the electrodes 2591, the electrodes 2592, and the wiring 2598, that is, the touch panel Materials that can be used for the wiring and electrodes that make up the filter include indium oxide, tin oxide, and oxide. Examples of the transparent conductive film include a transparent conductive film having zinc oxide or the like (e.g., ITO, etc.). As a material that can be used for the wiring and electrodes that constitute the device, for example, a material with a low resistance value is preferable. Examples include silver, copper, aluminum, carbon nanotubes, graphene, and halogens. Metal halide (silver halide, etc.) may also be used. Even if metal nanowires (diameters of several nanometers) are used, which are made up of multiple conductors, Alternatively, a metal mesh made of a conductor may be used. Nanowires, Cu nanowires, Al nanowires, Ag mesh, Cu mesh, Al plate For example, Ag nanowires may be used for the wiring and electrodes that make up the touch panel. When using a material with a visible light transmittance of 89% or more and a sheet resistance of 40 Ω / cm 2 End 100Ω / cm 2 The wiring constituting the above-mentioned touch panel can be as follows. Examples of materials that can be used for the electrodes include metal nanowires, metal meshes, and carbon nanotubes. Nanotubes and graphene have high transmittance in visible light, so they are used in display elements. It may also be used as an electrode (for example, a pixel electrode or a common electrode).

[0550] <5-2. Explanation of display device> Next, the display device 2501 will be described in detail with reference to FIGS. 49(A) and 49(B). 9(A) and (B) correspond to a cross-sectional view taken along dashed line X1-X2 shown in FIG. 48(B).

[0551] The display device 2501 has a plurality of pixels arranged in a matrix. The display device has a display element and a pixel circuit for driving the display element.

[0552] [Configuration using EL elements as display elements] First, a configuration using an EL element as a display element will be described below with reference to FIG. In the following description, the case where an EL element that emits white light is applied is taken as an example. However, the EL element is not limited to this. For example, EL elements having different luminescent colors may be applied so that the colors of the EL elements are different.

[0553] The substrate 2510 and the substrate 2570 are, for example, a substrate having a water vapor permeability of 10 -5 g / (m 2 ·day) or less, preferably 10 -6 g / (m 2 -Flexibility of less than 1000m2 Alternatively, the thermal expansion coefficient of the substrate 2510 and the thermal expansion coefficient of the substrate 2570 may be set to be equal to or larger than the thermal expansion coefficient of the substrate 2570. It is preferable to use a material with a linear expansion coefficient approximately equal to that of the material. For example, a material with a linear expansion coefficient of 1×10 - 3 / K or less, preferably 5×10 -5 / K or less, preferably 1×10 -5 / K or less Certain materials may be used advantageously.

[0554] The substrate 2510 is made of an insulating layer 2510a for preventing impurities from diffusing into the EL element, and a flexible The substrate 2510b and the adhesive layer 2 that bonds the insulating layer 2510a and the flexible substrate 2510b together 510c. The substrate 2570 is a laminate having a structure for preventing diffusion of impurities into the EL element. and a flexible substrate 2570b. 2570b and an adhesive layer 2570c that bonds the first and second layers 2570a and 2570b to each other.

[0555] The adhesive layer 2510c and the adhesive layer 2570c may be made of, for example, polyester or polyolefin. Polyimide, polycarbonate or acrylic Materials containing polystyrene resin, polyurethane, epoxy resin or resin with siloxane bonds can be used.

[0556] In addition, a sealing layer 2560 is provided between the substrate 2510 and the substrate 2570. It is preferable that the refractive index of the sealing material is larger than that of air. When light is extracted to the layer 2560 side, the sealing layer 2560 can also serve as an optical element.

[0557] A sealant may be formed on the outer periphery of the sealing layer 2560. As a result, the area surrounded by the substrate 2510, the substrate 2570, the sealing layer 2560, and the sealant The sealing layer 2560 may have a structure in which the EL element 2550 is disposed in the insulating layer 2560. It is also possible to fill the container with an inactive gas (such as nitrogen or argon). In addition, a desiccant may be placed in the inactive gas. In addition, the above-mentioned sealing material may be, for example, It is preferable to use epoxy resin or glass frit. It is preferable to use a material that is not permeable to moisture or oxygen.

[0558] The display device 2501 shown in FIG. 49A includes a pixel 2505. 505 is a light emitting module 2580, an EL element 2550, and a The transistor 2502t can supply the 2t functions as a part of the pixel circuit.

[0559] The light emitting module 2580 also includes an EL element 2550 and a coloring layer 2567 . The EL element 2550 has a lower electrode, an upper electrode, and an EL element between the lower electrode and the upper electrode. The layer.

[0560] In addition, when the sealing layer 2560 is provided on the side from which light is extracted, the sealing layer 2560 has a property of E It contacts the L element 2550 and the colored layer 2567 .

[0561] The colored layer 2567 is located so as to overlap the EL element 2550. A part of the light emitted by the light emitting module 50 passes through the colored layer 2567 and travels in the direction of the arrow shown in the figure. It is ejected outside of the ball 2580.

[0562] Furthermore, the display device 2501 is provided with a light-shielding layer 2568 in the light-emitting direction. A layer 2568 is provided surrounding the colored layer 2567 .

[0563] The colored layer 2567 may have a function of transmitting light of a specific wavelength band. For example, For example, a color filter that transmits light in the red wavelength band, a color filter that transmits light in the green wavelength band, A color filter that transmits light in the blue wavelength range, a color filter that transmits light in the yellow wavelength range, Each color filter can be made of various materials. Printing method, inkjet method, etching method using photolithography technology, etc. It can be formed with.

[0564] The display device 2501 is provided with an insulating layer 2521. The insulating layer 2521 covers the transistor 2502t and the like. In addition, the insulating layer 2521 has a function of suppressing diffusion of impurities. This prevents the reliability of the transistors 2502t and the like from being deteriorated due to the diffusion of impurities. can be suppressed.

[0565] The EL element 2550 is formed above the insulating layer 2521. The lower electrode of 50 is provided with a partition wall 2528 that overlaps with an edge of the lower electrode. A spacer for controlling the distance between the substrate 2510 and the substrate 2570 is formed on the partition wall 2528. You may do so.

[0566] The scanning line driver circuit 2504 includes a transistor 2503t and a capacitor 2503c. Note that the driver circuit and the pixel circuit can be formed on the same substrate in the same process. .

[0567] Moreover, wiring 2511 capable of supplying signals is provided on the substrate 2510 . A terminal 2519 is provided on the wiring 2511. C2509(1) is electrically connected to FPC2509(1). FPC2509(1) also transmits video signals, It has the function of supplying clock signals, start signals, reset signals, etc. 509(1) may have a printed wiring board (PWB) attached.

[0568] Note that either one or both of the transistor 2502t and the transistor 2503t The transistor described in the above embodiment may be used for the transistor. The transistor has a highly purified oxide semiconductor film with high crystallinity. Therefore, the current value (off-state current value) at the time of the image signal or other electric signals can be reduced. The retention time of the data can be extended, and the write interval can also be set longer when the power is on. This reduces the frequency of refresh operations, resulting in reduced power consumption. The refresh operation will be described in detail later.

[0569] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a display device. By using this in the device 2501, the switching transistor of the pixel circuit and the In other words, a separate driver circuit can be formed on the same substrate. Since it is not necessary to use a semiconductor device formed of a silicon wafer or the like, The number of parts in the device can be reduced. Also, the pixel circuit can be driven at high speed. By using a transistor, a high-quality image can be provided.

[0570] [Configuration using liquid crystal elements as display elements] Next, a configuration in which a liquid crystal element is used as a display element will be described below with reference to FIG. In the following description, a reflective liquid crystal display device that displays images by reflecting external light will be described. However, the liquid crystal display device is not limited to this. For example, a light source (backlight , side lights, etc.) to create a transmissive liquid crystal display device, or a combination of reflective and transmissive functions. The liquid crystal display device may also be provided with such a function.

[0571] The display device 2501 shown in FIG. 49(B) has the following features similar to the display device 2501 shown in FIG. 49(A). The other configuration is the same as the display device 2501 shown in FIG. It is.

[0572] A pixel 2505 of a display device 2501 shown in FIG. 49(B) includes a liquid crystal element 2551 and a liquid crystal and a transistor 2502t capable of supplying power to the transistor 2551.

[0573] The liquid crystal element 2551 includes a lower electrode (also called a pixel electrode), an upper electrode, and a lower electrode and an upper electrode, and a liquid crystal layer 2529 between the lower electrode and the upper electrode. The alignment state of the liquid crystal layer 2529 can be changed by applying a voltage between the electrodes. In addition, a spacer 2530a and a spacer 2530b are provided in the liquid crystal layer 2529. Although not shown in FIG. 49B, the liquid crystal layer 25 of the upper electrode and the lower electrode An alignment film may be provided on each side in contact with 29.

[0574] The liquid crystal layer 2529 may be a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, or a high molecular weight polymer. The liquid crystal material can be a dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. Depending on the conditions, cholesteric phase, smectic phase, cubic phase, chiral nematic phase, etc. In addition, when the liquid crystal display device adopts the in-plane electric field method, the alignment film In the case where a liquid crystal exhibiting a blue phase is used, the alignment layer may be formed by using the liquid crystal having a blue phase. Since there is no need to provide a film, rubbing treatment is not required. It is possible to prevent electrostatic damage caused during the rubbing process, and the liquid crystal display during the manufacturing process This can reduce malfunctions and damage to display devices.

[0575] The spacers 2530a and 2530b are obtained by selectively etching the insulating film. The spacers 2530a and 2530b are spaced apart from the substrate 2510 and the substrate 2570. The spacers 2530a and 2530b are provided to control the cell gap. The sizes of the particles may be different from each other, and it is preferable that the particles are provided in a columnar or spherical shape. In FIG. 49(B), spacers 2530a and 2530b are provided on the substrate 2570 side. However, the present invention is not limited to this configuration, and the electrodes may be provided on the substrate 2510 side.

[0576] The upper electrode of the liquid crystal element 2551 is provided on the substrate 2570 side. An insulating layer 2531 is provided between the electrode and the coloring layer 2567 and between the electrode and the light-shielding layer 2568. The edge layer 2531 has a function of flattening unevenness caused by the colored layer 2567 and the light-shielding layer 2568. The insulating layer 2531 may be, for example, an organic resin film. The lower electrode 2551 functions as a reflective electrode. 501 is a reflection type display that uses external light, reflects the light at the lower electrode, and displays the light through the color layer 2567. In the case of a transmission type liquid crystal display device, a transparent electrode is used as the lower electrode. All that is needed is to give it a function as a pole.

[0577] The display device 2501 shown in FIG. 49(B) includes an insulating layer 2522. The insulating layer 2522 covers the transistor 2502t and the like. and forming unevenness in the lower electrode of the liquid crystal element. This makes it possible to form irregularities on the surface of the lower electrode. When light is incident on the lower electrode, it becomes possible for the light to be diffusely reflected on the surface of the lower electrode. In the case of a transmission type liquid crystal display device, the above-mentioned unevenness can be provided. It is also possible to adopt a configuration in which this is not necessary.

[0578] <5-3. Explanation of touch sensor> Next, the touch sensor 2595 will be described in detail with reference to FIG. 48(B) along dashed line X3-X4.

[0579] The touch sensor 2595 includes electrodes 2591 and electrodes 2592 arranged in a staggered pattern on a substrate 2590. 2592, an insulating layer 2593 covering the electrodes 2591 and 2592, and adjacent electrodes 25 91 and a wiring 2594 that electrically connects them.

[0580] The electrode 2591 and the electrode 2592 are formed using a light-transmitting conductive material. Examples of conductive materials having the above structure include indium oxide, indium tin oxide, and indium zinc oxide. Conductive oxides such as zinc oxide, zinc oxide doped with gallium can be used. A film containing graphene may also be used. The film containing graphene may be, for example, a film-like The graphene oxide-containing film formed on the substrate can be reduced to form the graphene oxide-containing film. An example of such a method is the application of heat.

[0581] For example, a light-transmitting conductive material is formed on the substrate 2590 by a sputtering method. After that, various patterning techniques such as photolithography are used to remove unnecessary parts. , an electrode 2591 and an electrode 2592 can be formed.

[0582] The material used for the insulating layer 2593 is, for example, a resin such as acrylic or epoxy. In addition to resins with siloxane bonds, silicon oxide, silicon oxynitride, aluminum oxide, Alternatively, inorganic insulating materials such as rubber may be used.

[0583] In addition, an opening reaching the electrode 2591 is provided in the insulating layer 2593, and a wiring 2594 is adjacent to the insulating layer 2593. The transparent conductive material is used to increase the aperture ratio of the touch panel. Since the electrode 2591 can be formed by the above-mentioned method, it can be suitably used for the wiring 2594. A material having a higher electrical conductivity than the electrode 2592 is preferable for the wiring 2594 because it can reduce electrical resistance. It can be used appropriately.

[0584] The electrodes 2592 extend in one direction, and a plurality of electrodes 2592 are provided in a stripe pattern. In addition, the wiring 2594 is provided so as to intersect with the electrode 2592.

[0585] A pair of electrodes 2591 are provided with one electrode 2592 interposed therebetween. A pair of electrodes 2591 are electrically connected.

[0586] In addition, the multiple electrodes 2591 are arranged in a direction that is not necessarily perpendicular to one electrode 2592. The angle does not have to be 0 degrees, and may be greater than 0 degrees but less than 90 degrees.

[0587] The wiring 2598 is electrically connected to the electrode 2591 or the electrode 2592. A part of the wiring 2598 functions as a terminal. The wiring 2598 is made of, for example, aluminum. Aluminum, gold, platinum, silver, nickel, titanium, tungsten, chromium, molybdenum, iron, Use of metal materials such as ballast, copper, or palladium, or alloy materials containing such metal materials. can be done.

[0588] An insulating layer is provided to cover the insulating layer 2593 and the wiring 2594, and the touch sensor 2595 may be protected.

[0589] The connection layer 2599 electrically connects the wiring 2598 and the FPC 2509(2). .

[0590] The connection layer 2599 is made of an anisotropic conductive film (ACF). conductive film) and anisotropic conductive paste (ACP) Conductive Paste) can be used.

[0591] <5-4. Explanation of the touch panel> Next, the touch panel 2000 will be described in detail with reference to FIG. 48(A) corresponds to a cross-sectional view taken along dashed line X5-X6 shown in FIG. 48(A).

[0592] The touch panel 2000 shown in FIG. 51(A) is a display device 250 described in FIG. 1 and the touch sensor 2595 described in FIG. 50 are bonded together.

[0593] In addition, the touch panel 2000 shown in FIG. 51(A) has the following configuration in addition to that described in FIG. , an adhesive layer 2597 and an anti-reflective layer 2569 .

[0594] The adhesive layer 2597 is provided in contact with the wiring 2594. The substrate 2590 is attached to the substrate 2570 so that the sensor 2595 overlaps the display device 2501. In addition, it is preferable that the adhesive layer 2597 is transparent. The material 597 may be a thermosetting resin or an ultraviolet-curing resin. For example, Acrylic resin, urethane resin, epoxy resin, or siloxane resin can be used. This can be done.

[0595] The anti-reflection layer 2569 is provided at a position overlapping the pixel. For example, a circular polarizer can be used.

[0596] Next, for a touch panel having a different configuration from that shown in FIG. 51(A), I will use this to explain.

[0597] FIG. 51(B) is a cross-sectional view of the touch panel 2001. The panel 2001 is a touch panel 2000 shown in FIG. The location of the touch sensor 2595 is different. The different configurations are described in detail here. The description of touch panel 2000 is cited for the parts in which such a configuration can be used.

[0598] The colored layer 2567 is located below the EL element 2550. The L element 2550 emits light to the side where the transistor 2502t is provided. As a result, a part of the light emitted by the EL element 2550 is transmitted through the colored layer 2567 and is reflected by the light emitting diode 2566 as shown by the arrows in the figure. The light is emitted to the outside of the light emitting module 2580 in the direction of the mark.

[0599] The touch sensor 2595 is provided on the substrate 2510 side of the display device 2501. .

[0600] The adhesive layer 2597 is between the substrate 2510 and the substrate 2590 and is in contact with the display device 2501. Stick the Chisensor 2595 together.

[0601] As shown in FIG. 51(A) and (B), the light emitted from the light emitting element is guided by the substrate 2510 and the substrate 2520. It may be injected through either or both of the plates 2570 .

[0602] <5-5. Explanation of touch panel driving method> Next, an example of a method for driving a touch panel will be described with reference to FIG.

[0603] FIG. 52(A) is a block diagram showing the configuration of a mutual capacitance type touch sensor. In (A), a pulse voltage output circuit 2601 and a current detection circuit 2602 are shown. In FIG. 52(A), the electrodes 2621 to which the pulse voltage is applied are designated as X1-X6, and the change in current The electrodes 2622 for detecting the change are shown as Y1-Y6, each having six wires. FIG. 52(A) shows a capacitance formed by overlapping an electrode 2621 and an electrode 2622. 2603. The electrodes 2621 and 2622 are interchangeable in function. It may be possible.

[0604] The pulse voltage output circuit 2601 is a circuit for applying pulses to the wirings X1-X6 in sequence. When a pulse voltage is applied to the wiring of X1-X6, the voltage that forms the capacitance 2603 An electric field is generated between the electrodes 2621 and 2622. The electric field generated between the electrodes is blocked by By using the change in the mutual capacitance of the capacitance 2603, the proximity of the object to be detected or A contact can be detected.

[0605] The current detection circuit 2602 detects the change in mutual capacitance of the capacitor 2603 between the wirings Y1-Y6. This is a circuit to detect changes in current at the sensor. The wiring of Y1-Y6 detects the proximity of the object to be detected, Or, if there is no contact, the detected current value will not change, but the proximity of the object to be detected, or When the mutual capacitance decreases due to contact, a change in the current value is detected. The detection may be performed using an integrating circuit or the like.

[0606] Next, FIG. 52(B) shows the input of the mutual capacitance type touch sensor shown in FIG. 52(A). The timing chart of the output waveform is shown in FIG. 52(B). In FIG. 52(B), the case where the object is not detected ( Two cases are shown: when the sensor detects a target object (touch) and when the sensor detects a target object (non-touch). For the wiring Y1-Y6, the waveform is shown as a voltage value corresponding to the detected current value. There are.

[0607] A pulse voltage is applied to the wires X1-X6 in sequence, and the The waveform in the Y6 wiring changes. When there is no proximity or contact of the object to be detected, X1-X6 The waveforms of Y1-Y6 change uniformly according to the change in the voltage of the wiring. Or, at the point of contact, the current value decreases, and the corresponding voltage waveform also changes. do.

[0608] In this way, by detecting the change in mutual capacitance, the proximity or contact of the object to be detected can be detected. It is possible.

[0609] <5-6. Explanation of sensor circuit> In FIG. 52A, only a capacitor 2603 is provided at the intersection of the wiring as a touch sensor. Although the configuration of a passive touch sensor has been shown, an active touch sensor having a transistor and a capacitor may also be used. One of the sensor circuits included in the active type touch sensor may be a An example is shown in Figure 53.

[0610] The sensor circuit shown in FIG. 53 includes a capacitor 2603, a transistor 2611, and a transistor 2612 and a transistor 2613.

[0611] A signal G2 is applied to the gate of the transistor 2613, and a voltage is applied to either the source or drain of the transistor 2613. A voltage VRES is applied to one electrode of a capacitor 2603 and a transistor 2611. The transistor 2611 has a source and a drain that are electrically connected to each other. One of the source and drain of the transistor 2612 is electrically connected to the other of the voltage VS A signal G1 is applied to the gate of the transistor 2612, and a signal S is applied to the source or The other electrode of the drain is electrically connected to the wiring ML. The other electrode of the capacitor 2603 is connected to a voltage VS S is given.

[0612] Next, the operation of the sensor circuit shown in FIG. 53 will be described. First, the signal G2 is When a potential is applied to turn on the transistor 2613, the gate of the transistor 2611 is turned on. A potential corresponding to the voltage VRES is applied to the node n to which the input is connected. When a potential that turns off the transistor 2613 is applied, the potential of the node n is Retained.

[0613] Next, the mutual capacitance of the capacitor 2603 changes due to the proximity or contact of a detection object such as a finger. Accordingly, the potential of the node n changes from VRES.

[0614] The read operation applies a potential to the signal G1 that turns on the transistor 2612. A current flows through the transistor 2611 in accordance with the potential of the node n, that is, a current flows through the wiring ML. By detecting this current, the proximity or contact of the object to be detected can be detected. This can be done.

[0615] The transistors 2611, 2612, and 2613 are In particular, the transistor 2613 may be a transistor having the above-mentioned structure. By using the transistor described in the embodiment, the potential of the node n can be maintained for a long period of time. It becomes possible to hold the voltage, and the operation of supplying VRES to node n again (refresh operation) ) can be reduced.

[0616] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0617] (Embodiment 6) In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention and a display device including the semiconductor device A method for driving the display device will be described with reference to FIGS.

[0618] Note that the display device of one embodiment of the present invention includes an information processing unit, a calculation unit, a storage unit, a display unit, and an input unit. The second embodiment may have a second portion, etc.

[0619] In addition, in the display device according to one embodiment of the present invention, the same image (still image) is continuously displayed. In this case, by reducing the number of times the same image signal is written (also called refreshing), This allows for a reduction in power consumption. The frequency of refreshing can be set as the refresh rate. The refresh rate is also called the scanning frequency or vertical synchronization frequency. The present invention describes a display device that reduces image distortion and reduces eye fatigue.

[0620] There are two types of eye fatigue: nervous fatigue and muscular fatigue. Staring at the light-emitting or flashing screen of the device for a long period of time can cause the brightness to irritate the retina, nerves, and brain. Muscular fatigue is caused by the ciliary muscles, which are used to adjust the focus. It tires the flesh by overworking it.

[0621] FIG. 54(A) is a schematic diagram showing a display of a conventional display device. As shown in FIG. In contrast, conventional display devices rewrite images 60 times per second. Looking at a screen for a long time can stimulate the retina, nerves, and brain of the user, causing eye fatigue. There was a risk of being woken up.

[0622] In the display device of one embodiment of the present invention, a transistor using an oxide semiconductor is provided in a pixel portion of the display device. A transistor using CAAC-OS, for example, is applied. The off-state current of the transistor is extremely small. Therefore, even if the refresh rate of the display device is lowered, the display This makes it possible to maintain the brightness of the display device.

[0623] In other words, as shown in FIG. 54(B), for example, an image can be rewritten once every five seconds. This allows the user to watch the same image for as long as possible, and the screen that is visible to the user is This reduces the stimulation of the retina, nerves, and brain of the user, and improves the nerve function. System fatigue is reduced.

[0624] Also, as shown in FIG. 55(A), when the size of one pixel is large (for example, when the resolution is...

Claims

1. A semiconductor device having a transistor, A first conductive layer; and a first insulating film on the first conductive layer; a first metal oxide film provided on the first insulating film and overlapping the first conductive layer via the first insulating film; a second metal oxide film on the first metal oxide film; a second conductive layer having a region in contact with an upper surface of the second metal oxide film; a third conductive layer having a region in contact with an upper surface of the second metal oxide film; a second insulating film on the second metal oxide film, the second conductive layer, and the third conductive layer; a third insulating film on the second insulating film; a third metal oxide film on the third insulating film; a fourth metal oxide film on the third metal oxide film; and a fourth insulating film on the fourth metal oxide film; the third insulating film has a thickness greater than that of the second insulating film; the fourth metal oxide film overlaps with the first conductive layer via the third insulating film, the second insulating film, the second metal oxide film, and the first metal oxide film; each of the first metal oxide film and the second metal oxide film contains In, M (M is Al, Ga, Y, or Sn), and Zn, and has a function as an oxide semiconductor; the second metal oxide film has a region having a smaller number of In atoms than the first metal oxide film, the fourth insulating film contains hydrogen or nitrogen; each of the third metal oxide film and the fourth metal oxide film contains at least one of the metal elements contained in the first metal oxide film and has a function as an oxide conductor; a third metal oxide film and a fourth metal oxide film each having a region extending beyond an end of the first metal oxide film and an end of the second metal oxide film;

2. A semiconductor device having a transistor, A first conductive layer; and a first insulating film on the first conductive layer; a first metal oxide film provided on the first insulating film and overlapping the first conductive layer via the first insulating film; a second metal oxide film on the first metal oxide film; a second conductive layer having a region in contact with an upper surface of the second metal oxide film; a third conductive layer having a region in contact with an upper surface of the second metal oxide film; a second insulating film on the second metal oxide film, the second conductive layer, and the third conductive layer; a third insulating film on the second insulating film; a third metal oxide film on the third insulating film; a fourth metal oxide film on the third metal oxide film; and a fourth insulating film on the fourth metal oxide film; the third insulating film has a thickness greater than that of the second insulating film; the fourth metal oxide film overlaps with the first conductive layer via the third insulating film, the second insulating film, the second metal oxide film, and the first metal oxide film; each of the first metal oxide film and the second metal oxide film contains In, M (M is Al, Ga, Y, or Sn), and Zn, and has a function as an oxide semiconductor; a ratio of In to M of the second metal oxide film, In / M, is smaller than a ratio of In to M of the first metal oxide film, In / M, the fourth insulating film contains hydrogen or nitrogen; each of the third metal oxide film and the fourth metal oxide film contains at least one of the metal elements contained in the first metal oxide film and has a function as an oxide conductor; a third metal oxide film and a fourth metal oxide film each having a region extending beyond an end of the first metal oxide film and an end of the second metal oxide film;

3. In claim 1 or 2, The semiconductor device, wherein the first metal oxide film or the second metal oxide film has a crystal part having a c-axis orientation.

Images