Amplifiers, semiconductor dies and wireless devices

Abstract

To provide a signal amplifier that reduces impedance mismatch in an amplification chain and improves signal quality.SOLUTION: A signal amplifier 10 includes a scalable impedance block 104 which has an input impedance varying across different bias currents and has a plurality of switchable amplification branches each of which is capable of being activated such that one or more of the activated amplification branches provide targeted adjustment for the input impedance Zin and provides a plurality of gain levels. The plurality of gain levels results in different input impedance values presented to the respective signals by the impedance block. The impedance block includes a plurality of switchable amplification branches that provide the targeted adjustment for the respective input impedance values and includes a plurality of switchable inductive elements Zs1 to Zs4 that is activated so as to provide the targeted adjustment for the respective input impedance values.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] TECHNICAL FIELD This disclosure relates generally to amplifiers for wireless communication devices.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application is based on the application filed on August 31, 2016 entitled "Gain Mode Reflection Loss and Mismatch Reduction" This application claims priority to U.S. Provisional Application No. 62 / 382,252, entitled "Improved Amplifier." , which is expressly incorporated by reference herein in its entirety for all purposes. [Background technology]

[0003] In electronic applications, such as radio frequency (RF) applications, It may be desirable to amplify the signal to be transmitted, for example by amplifying it with a power amplifier. The received signal can be amplified by a low noise amplifier. In applications, it is important to reduce impedance mismatch in the amplification chain to improve signal integrity. Improving quality would be advantageous. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2013 / 0314164(A1) Summary of the Invention

[0005] According to a number of implementations, the present disclosure provides a method for detecting input impedances that vary across different bias currents. The present invention relates to a signal amplifier having a gain of 100 MHz. Each of the plurality of switchable amplifier branches includes a gain stage including an active One or more of the activated amplification branches can input target adjustments. impedes.

[0006] In some embodiments, each of the plurality of switchable amplification branches is In a further embodiment, the first transistor includes a switching transistor and an RF stage transistor. In the first gain mode, a first plurality of RF stage transistors are active, In a second gain mode, which is lower than the first gain mode, a second plurality of RF stage transistors are active, and In the second gain mode, the number of active RF stage transistors is less than in the first gain mode. stomach.

[0007] According to a number of implementations, the present disclosure provides a method for implementing multiple gain controls that result in different input impedance values. The present invention relates to a signal amplifier including a variable gain stage configured to provide a signal level at different input impedances. A gain value is presented to each signal by a variable gain stage. The amplifier includes a plurality of switchable amplifier branches that can be active. One or more of the branches provides a target adjustment to each input impedance value.

[0008] In some embodiments, each of the plurality of switchable amplification branches is In a further embodiment, the first transistor includes a switching transistor and an RF stage transistor. In the first gain mode, a first plurality of RF stage transistors are active, In a second gain mode, which is lower than the first gain mode, a second plurality of RF stage transistors are active, and In the second gain mode, the number of active RF stage transistors is less than in the first gain mode. stomach.

[0009] According to a number of implementations, the present disclosure provides a method for implementing multiple gain controls that result in different input impedance values. The present invention relates to a signal amplifier including a variable gain stage configured to provide a signal level at different input impedances. A gain value is presented to each signal by a variable gain stage. The variable gain stage consists of multiple switching The present invention relates to a scalable impedance block having a switchable inductive element. The adjustable inductive elements are activated to provide a target adjustment to each input impedance value. It is configured to:

[0010] In some embodiments, the scalable impedance block is In some embodiments, the inductance is increased when the capacitance decreases. In the present invention, the scalable impedance block is a RF stage transistor of a variable gain stage. is bound to the source.

[0011] According to a number of implementations, the present disclosure provides a radio frequency (RF) The amplifier also includes a gain stage that includes multiple switchable amplifier branches. Each of the plurality of switchable amplifier branches can be active. One or more of the active amplifier branches provides a targeted adjustment to the input impedance.

[0012] In some embodiments, the RF amplifier is a low noise amplifier (LNA). In an embodiment, the LNA is implemented in a cascode configuration having an input stage and a cascode stage. It is possible.

[0013] In some embodiments, the input impedance at each of a plurality of gain settings The target adjustment for is to give approximately constant impedance at the input node. In some embodiments, the plurality of transistors is selected from a single transistor. operates at its lowest gain setting and uses one additional transistor for each increased gain setting. The controller is configured to operate.

[0014] According to a number of implementations, the present disclosure relates to a method of amplifying a signal, the method comprising: Configuring at least some of the gain settings to a selected one of a plurality of gain settings. The method also includes a gain stage that provides a differential impedance presented to the signal. This involves adjusting the impedance presented to the signal for a selected gain setting. The tuned impedance is a targeted constant impedance value across multiple gain settings. The input is configured to provide a

[0015] In some embodiments, the gain stage is part of a low noise amplifier (LNA). In some embodiments, the tuned impedance is approximately uniform across multiple gain settings. In some embodiments, the impedance is adjusted to provide a constant impedance. The gain stage is provided with one or more inductances coupled to the source of the RF stage transistor. This includes adjusting the

[0016] In some embodiments, adjusting the impedance comprises adjusting a number of transistors. in an electrically parallel configuration, each transistor being connected to an associated transistor. In a further embodiment, multiple transistors have associated switches for selectively activating the transistors. To operate a transistor, a current is applied to the drain of the transistor. This includes performing a switching operation to control the operation of the

[0017] According to a number of implementations, the present disclosure relates to a semiconductor die having radio frequency (RF) circuitry. The RF circuit includes a substrate and an RF amplifier mounted on the substrate. A gain amplifier including multiple switchable amplifier branches, each of which can be active. One or more of the active amplifier branches provide a target adjustment to the input impedance. do.

[0018] In some embodiments, the substrate comprises a silicon-on-insulator (SOI) substrate. In some embodiments, the RF amplifier is a low noise amplifier (LNA).

[0019] According to a number of implementations, the present disclosure provides a radio frequency (RF) module that includes a package substrate. The package substrate is a substrate for mounting a plurality of components thereon. and an RF amplifier, each of which is configured to receive a The active amplifier branch includes a gain stage including a plurality of switchable amplifier branches. One or more of the following provides a target adjustment to the input impedance:

[0020] In some embodiments, the RF amplifier is a semiconductor mounted on a package substrate. In some embodiments, the RF amplifier is a low noise amplifier (LNA). In some embodiments, the RF module includes a diversity receive (DRx) It is a module.

[0021] According to a number of implementations, the present disclosure provides a method for receiving at least a radio frequency (RF) signal. The present invention relates to a wireless device including an antenna configured to communicate with the antenna. Each active switchable amplifier contains an RF amplifier that receives One or more of the active amplifier branches includes a gain stage that includes a target phase. The input impedance is adjusted to provide a desired impedance. The wireless device also A transmitter / receiver configured to process the amplified RF signal having a targeted phase. Includes vessels.

[0022] In some embodiments, the wireless device is configured to include different gains in the receive operation. The mobile phone is configured as follows.

[0023] For purposes of summarizing the disclosure, certain aspects, advantages and novel features have been described herein. Not necessarily all such advantages will be achieved in any particular embodiment. Thus, embodiments of the present disclosure may be implemented with or without the benefit or group of benefits taught herein. without necessarily achieving any of the other advantages taught or suggested herein. The present invention can be carried out in the following manner. [Brief description of the drawings]

[0024] [Figure 1] 1 illustrates a signal amplifier having a gain stage and an impedance adjustment circuit. [Diagram 2] Illustratively, a low noise amplifier (LNA) having one or more features described herein can include a first transistor and a second transistor implemented in a cascode configuration and an impedance adjustment circuit. [Diagram 3] 1 illustrates a typical LNA configured as a cascode amplifier but without the impedance adjustment circuit. [Figure 4]4 illustrates an example of how the RF stage of FIG. 3 can be represented as an RLC circuit. [Diagram 5] 3 and 4 illustrate that R(gm*Ls / Cgs) can vary as a function of Idd. [Figure 6] 4 illustrates the variation of supply current as a function of gain mode. [Figure 7] 1 illustrates the relationship between device size W and supply current Idd for different gain modes. [Figure 8] 1 illustrates an example of a scalable gain stage that can be implemented for a signal amplifier to provide a variable input impedance. [Figure 9] 1 illustrates an example of a scalable gain stage that can be implemented for a signal amplifier to provide a variable input impedance. [Figure 10] 1 illustrates plots of Cgs / gm as a function of different gain modes. [Figure 11] 1 illustrates a plot of target impedance value Ls as a function of supply voltage and gain mode. [Figure 12] 1 illustrates an example of a scalable impedance block acting as an impedance adjustment circuit. [Figure 13] It is noted that in some embodiments, some or all of the features described herein can be implemented on a semiconductor die. [Figure 14] It is noted that in some embodiments, some or all of the features described herein can be implemented in a packaged module. [Figure 15] It is noted that in some embodiments, some or all of the features described herein can be implemented in a packaged module. [Figure 16] 1 illustrates an example of a wireless device having one or more advantageous features described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] The headings provided herein, if any, are merely for convenience and should not be construed as limiting the scope of the claims. It does not necessarily affect the scope or meaning of such inventions.

[0026] overview

[0027] Described herein, among other things, is the impedance adjustment feature for various gain modes. US20130232633A1 - Radio Frequency (RF) Amplifier Architecture, Circuit, Device and Method - Google Patents FIG. 1 shows a signal amplifier 10 having a gain stage 102 and an impedance adjustment circuit 104. 0. The signal amplifier 100 receives an input signal (IN) and amplifies the signal. In some implementations, the gain stage 102 may include one or more gain stages. For purposes of illustration, various examples of such a signal amplifier 100 include low It will be understood, however, that the present disclosure is not limited to the embodiments described herein. One or more features of the present invention may also be implemented for other types of signal amplifiers, including power amplifiers (PAs). It can also be equipped with

[0028] In many LNA applications, it is necessary to increase the power transfer between signal processing stages or to maximize It is desirable to match the impedance so that For example, in receive demodulation across different LNA gain modes, especially in high order modulation systems, In some embodiments, the methods described herein can maintain desirable signal characteristics. The LNA circuit has one or more characteristics that are determined by the input of the LNA circuit across different gain modes. The impedance is adjusted to match the input impedance at the Any significant reflections or misalignments that may lead to performance degradation should be eliminated or minimized. It is also desirable to have the actual value of the input impedance close to the target value (e.g., 50 Ω). It is.

[0029] The impedance adjustment circuit 104 has multiple switches, each of which can be active. A scalable gain stage having switchable amplifier branches may be provided. By selectively activating the width branches, the input impedance is adjusted to the desired The impedance can be adjusted, tailored, or otherwise adjusted as desired. The regulation circuit 104 has a number of switchable inductive elements that can be activated. A scalable impedance block can be provided that selectively adjusts the inductive element. By activating the Or any desired adjustment can be provided.

[0030] Advantageously, the impedance adjustment circuit 104 delivers maximum power across the gain modes. By fixing the LNA input impedance to transmit the The impedance adjustment circuit 104 can be configured to adjust the impedance of the input signal from the previous signal processing stage. To improve the receive NF performance by reducing or minimizing the impedance mismatch of the The impedance adjustment circuit 104 adjusts the impedance between the LNA circuit and the To maintain the performance of the LNA pre-filter by reducing or eliminating the impedance mismatch. It can be configured.

[0031] FIG. 2 illustrates an LNA 100 having one or more features described herein in a cascode configuration. A first transistor and a second transistor (collectively referred to as gain stage 102) packaged together For example, the first transistor Q1 may be a common source device (also referred to as an RF stage). and the second transistor Q2 can be configured to operate as a common gate device. (also called a cascode stage). , an input signal (IN) is shown being applied to the gate of a first transistor Q1, which is The first transistor Q1 is shown outputting a signal through its drain. The source of the first transistor Q1 is shown coupled to ground. The amplified signal is provided to the source of a second transistor Q2 for further amplification. This further amplified signal is output through the drain of the second transistor Q2. The gate of the second transistor Q2 is shown coupled to ground. The first and second transistors Q1 and Q2 are appropriately biased. In the example of FIG. 2, the second transistor Q2 has a supply voltage V DD is shown to be given.

[0032] FIG. 2 further illustrates that in some embodiments, the LNA 100 includes an impedance adjustment circuit. 104. Various examples of such impedance adjustment circuits are described herein. is described in detail in.

[0033] In the example of FIG. 2, the impedance adjustment circuit 104 includes a first transistor Q1 (RF stage ) However, it will be understood that such phase compensation The compensation circuit includes a first transistor Q1 (RF stage) and a second transistor Q2 (cascode stage). The grant may be given for either or both of the following:

[0034] FIG. 3 shows a typical cascode amplifier configuration without an impedance adjustment circuit. A typical LNA 10 is shown. The RF stage 12 is associated with various portions of transistor Q1. For example, the input path to the gate of Q1 is depicted as having an impedance The input impedance Zin presented to the input terminal may be an effective inductance. Similarly, the source ground path of Q1 has an effective inductance that results in a source impedance Zs. For example, the gate-source impedance Zgs and the transconductance One or more other impedances, including the impedance related to the current, gm*Zgs*Zs, This example of impedance arises from Q1, i.e., presented to the input RF signal The total impedance Ztot is Ztot=Zin+Zs+Zgs+gm*Zgs *Can be expressed as Zs.

[0035] FIG. 4 shows an example of how the RF stage 12 of FIG. 3 can be represented as an RLC circuit 12. The circuit may include a resistor R connected at one end to the input and at the other end to one end of an inductance L. The other end of the inductance L can be coupled to ground via a capacitance C. The resistance R is related to the transconductance term gm*Zgs*Zs, and the inductance The capacitance L is related to the sum of Zin and Zs, and the capacitance C is related to Zgs. In such a representation, the resonant frequency can be expressed as:

number

[0036] In the examples of FIGS. 3 and 4, the LNA 10 adjusts the supply current Idd to: It can operate in different gain modes. With such a change in Idd, the The electrical parameters may also be changed. For example, FIG. 5 shows the R(gm*Ls / Cg s) can vary as a function of Idd. That is, for the gain mode example G3, In a first Idd setting, R may have a first value. The second Idd setting may result in R having a second value greater than the first R value. As this continues, the third and fourth settings for the gain modes G1 and G0 become successively larger. That is, in FIG. 5, the third and fourth values ​​of R may be obtained. The lines depict an example of the relationship between R and Idd.

[0037] In the examples of Figures 3 and 4, the variation of R mentioned above results in the following as a function of Idd: A corresponding impedance variation is provided. Therefore, practically all of the gain modes and supply currents are It may be advantageous to adjust the R-value to achieve a constant R-value over time. The R value to be achieved is shown by the dotted line of the Y value in Figure 5. The target value Y is For a typical input, this is 50 Ω.

[0038] FIG. 6 illustrates the variation of the supply current as a function of gain mode. The relationship between the device size W and the supply current Idd for the following gain modes is illustrated. Therefore, for a fixed source inductance Ls, the target R value is the ratio gm / Cg This can be achieved by keeping s relatively constant. at the same rate that the supply current varies across the gain modes. This can be achieved by:

[0039] The actual impedance changes as a function of gain mode (e.g., as gain increases) Therefore, the actual R value at the input and the target R value (e.g., to reduce or minimize signal degradation) This creates an undesirable gap between the , an impedance including a scalable gain stage configured to provide a constant real value R These scalable gain stages keep the ratio gm / Cgs essentially constant. The impedance adjustment circuitry can be configured to The device width (W) is effectively scaled in proportion to the supply voltage. This includes mechanisms and elements that allow the actual inertia to be fixed at a targeted value. The device size ratio is roughly proportional to the supply current ratio (for example, I dd0 / Idd1≒W0 / W1, Idd1 / Idd2≒W1 / W2, and Idd2 / Id d3 ≒ W2 / W3).

[0040] This is done to provide a fixed real impedance across the different gain modes. The present invention relates to an impedance adjustment circuit including a scalable gain stage. 8 and 9 show possible implementations of a signal amplifier 100 (e.g., an LNA). 1 illustrates an example of a scalable gain stage 104. The scalable gain stage 104 includes a plurality of The R includes switches S1a to S1d and corresponding RF stage transistors Q1a to Q1d. A signal can be routed through one or more of the F-stage transistors in a selective manner.

[0041] The scalable gain stage 104 is an example of four RF stage transistors implemented in a parallel fashion. This includes the RF stage transistors Q1a, Q1b, Q1c, and Q1d. Processing of the input signal through one or more of Q1b, Q1c, and Q1d is permitted. Node IN is connected to the gates of the four RF stage transistors Q1a, Q1b, Q1c, and Q1d. The drain of each RF stage transistor is shown coupled to a switch transistor S 1a, S1b, S1c, and S1d through the cascode stage transistor Q2 (FIG. 9 For example, the drain of Q1a is shown routed to the first switch. The drain of Q1b is connected to the second switch transistor S1a. The signal is routed through transistor S1b to Q2, and so on. In one embodiment, the RF stage may be processed through one or more parallel RF stage transistors. .

[0042] As described herein, gm decreases as the supply current decreases. By selectively adding or removing resistors, the effective digital value of the scalable gain stage 104 can be adjusted. The device size can be changed. The device size decreases with decreasing gain. By this, a substantially constant actual impedance can be achieved. However, the impact on the supply current Idd varies with one or more dimensions of the RF stage transistor (see Fig. 8). In the example of FIG. 9, the RF stage transistors Dimensions Wa / La, Wb / Lb, Wc / L corresponding to sta Q1a, Q1b, Q1c, Q1d c, Wd / Ld are switched on and off to give different effective values ​​for different device sizes. For example, in high gain mode (G0), each switch is turned on. By switching on the high gain mode, four RF stage transistors can be activated. In the second gain mode (G1) which is lower than the first gain mode (G0), each switch is turned on. Therefore, three of the four RF stage transistors (e.g., RF stage transistors Q1b, Q1c, and Q 1d) can be activated. A third gain mode, lower than the second gain mode (G1), can be activated. In the step (G2), the four RF stage transistors are turned on by turning on each switch. Two of these (eg, RF stage transistors Q1c, Q1d) can be active. This can be achieved by using any suitable number of gain modes and RF stages in the scalable gain stage 104. It can be understood that the dimensions Wa / La , Wb / Lb, Wc / Lc, Wd / Ld are all substantially the same, all different, or can be any combination of these. By configuring in the above manner, different gains Different net R values ​​can be obtained for different modes. The dimensions of transistors Q1a, Q1b, Q1c, and Q1d are selected to give a desired R value. You can choose.

[0043] Thus, Figures 8 and 9 show the input impedance changing over different bias currents. 1 illustrates a signal amplifier 100 having an active The gain stage 104 includes a plurality of switchable amplifier branches that can be One or more of the active amplifier branches are targeted to an input impedance and custom Similarly, Figures 8 and 9 provide multiple gain levels. 1 illustrates a signal amplifier 100 that includes a variable gain stage 104 configured to provide multiple gain levels. The filters result in different input impedance values ​​being presented to each signal by the variable gain stage 104. Variable gain stage 104 has multiple switching stages, each of which can be active. One or more of the active amplifier branches may be targeted and tailored. 2. Apply any adjustments obtained or desired to each input impedance value.

[0044] FIG. 10 shows the Cgs / gm (e.g., dependent on Idd) as a function of different gain modes. For the RF stage transistor (e.g., FET), the value of Cgs is Compared to the change in gm due to the change in pressure, there is only a small change in Idd. It is reasonable to approximate that Cgs remains essentially fixed while gm decreases with This is represented on the plot as a solid line that decreases with increasing supply voltage. R Since is equal to Ls*gm / Cgs, R remains essentially fixed at the target value Y. It may be advantageous to tailor the impedance value Ls to match the Here, the target impedance value Ls is programmed as a function of the supply voltage and gain mode. To achieve the target impedance value Y, the impedance value Ls is plotted. is made equal to Y*Cgs / gm. This is illustrated by the solid line in the plot. For example, a typical target value for Y is 50 Ω.

[0045] The actual impedance changes as a function of gain mode (e.g., as gain increases) Therefore, the actual R value at the input and the target R value (e.g., to reduce or minimize signal degradation) This creates an undesirable gap between the , including a scalable impedance block configured to provide a constant real-world value R. The scalable impedance block is an impedance adjustment circuit that actually The source impedance (L s) can be configured to scale. The block includes a guiding element configured to provide scaling guiding values ​​for different gain modes. The switch includes a conductive element. By scaling Ls, the actual R value can be set to the target value. The change in gm is compensated to achieve

[0046] To vary the value of Ls as a function of gain mode, a A scalable impedance block can be provided that is integrated with the impedance of the The scalable impedance block 104 acts as an impedance adjustment circuit. An example is illustrated in FIG. 1. The scalable impedance block 104 includes switches S1, S 2, an inductive element Zs1 added to the signal amplifier 10, switchable using S3; For example, in the first gain mode (G0), the switch S1 becomes active and the impedance of the scalable impedance block 104 is given by the inductive element Zs1. Similarly, in the second gain mode (G1), the switch S2 becomes active and the impedance of the scalable impedance block 104 The impedance is provided by the inductive elements Zs1 and Zs2. In addition, in the third gain mode (G2), switch S3 is activated, and the scalable impedance block 10 The fourth gain module is provided by inductive elements Zs1, Zs2 and Zs3. In the mode (G3), all switches S1 to S3 are deactivated and the scaling The impedance of the tunable impedance block 104 is determined by the inductive elements Zs1, Zs2, and Zs 3 and Zs4. Thus, the impedance changes with the gain mode change. For example, the impedance can be scaled with increasing gain or supply voltage. Since the impedance may increase, the change in impedance is compensated for and the input ( A substantially constant target impedance is obtained at IN.

[0047] In the examples described herein, the impedance adjustment circuit generally counteracts the effects described. It will be understood that such effects may be known or unknown. By utilizing one or more features of the present disclosure, an inductor in an LNA may be used. Operating parameters such as impedance may be subject to such uncompensated effects, either with or without knowledge. , can be configured to any profile (substantially flat profile).

[0048] Thus, FIG. 12 includes a variable gain stage configured to provide multiple gain levels. 1 illustrates a signal amplifier 10. Multiple gain levels are presented to each signal by a variable gain stage. The variable gain stage uses multiple switchable inductive elements to provide different input impedance values. The scalable impedance block 104 has multiple switching The adjustable inductive elements are activated to provide a targeted adjustment to each input impedance value. It is composed of.

[0049] Products, Modules, Devices and Architecture

[0050] FIG. 13 illustrates, in some embodiments, a L having one or more features described herein. It is shown that some or all of NA 100 can be implemented on a semiconductor die 200. At least a portion of the impedance adjustment circuit 104 may be mounted on the substrate 202. It is possible to implement.

[0051] 14 and 15 illustrate, in some embodiments, one or more of the features described herein. A part or all of the LNA 100 having the above configuration can be mounted in a packaged module 300. Such a module may consist of one or more dies and one or more passive components. The semiconductor device may include a package substrate 302 configured to receive a number of such components.

[0052] In some implementations, an architecture having one or more of the features described herein; The device and / or circuitry may be included in an RF device, such as a wireless device. The architecture, device and / or circuit may be integrated directly into the wireless device. In some embodiments, the implementation may be in the form of a In the present invention, such a wireless device is, for example, a mobile phone, a smartphone, a mobile phone with a telephone function, or No handheld wireless devices, wireless tablets, wireless routers, wireless access points Although described in the context of a wireless device, the present disclosure may include a wireless It will be appreciated that one or more features of the present invention may be implemented in other RF systems, such as base stations. .

[0053] FIG. 16 illustrates an example wireless device 1300 having one or more advantageous features described herein. In some embodiments, an LNA having one or more of the features described herein may be Such a wireless device may be implemented in one or more locations. In some embodiments, such an advantageous feature includes one or more low noise amplifiers (LNAs). The diversity receive (DRx) module 1308 may be implemented in a module having It is.

[0054] FIG. 16 illustrates an example wireless device 1300 having one or more advantageous features described herein. In the context of one or more modules having one or more features described herein, Such modules are generally designated by dashed lines (eg, may be implemented as front-end modules). 1306, and a diversity 13. The signal processing unit 1302 is depicted by a receiver (DRx) module 1308.

[0055] Referring to FIG. 16, a plurality of power amplifiers (PAs) 1382 are provided in each of the transceivers 130. The transceiver 1304 can receive RF signals from the 1304 . The present invention relates to a method and apparatus for processing a received signal, the method comprising: The transceiver 1304 transmits data and / or voice signals appropriate for the user to the transceiver 1304. a baseband subsystem 130 configured to provide conversion between an RF signal suitable for 5. The transceiver 1304 is also shown to interact with the wireless device 1300. and communicating with a power management component 1307 configured to manage power for operational purposes. Such power management may also be implemented in the baseband subsystem 1305 as well as in the module 1306. The operation of modules 1306 and 1308 may also be managed.

[0056] The baseband subsystem 1305 receives and transmits voice and audio signals to and from the user. and / or a user interface 1301 to facilitate various inputs and outputs of data. The baseband subsystem 1305 is also shown connected to the wireless device's A memory 1 configured to facilitate operation and / or provide information storage for a user. 303. The memory 1303 is configured to store data and / or instructions. will be done.

[0057] In the example wireless device 1300, the output of the PA 1382 is The amplified and filtered signals are then matched and routed to each duplexer 1386. The filtered signals are then routed through a switching network 1309 for transmission. The duplex antenna 1360 may be routed to the secondary antenna 1360. The cascade 1386 allows a common antenna (e.g., the primary antenna 1360) to be used for transmission. In FIG. 16, the received signal is Now turning to the variable gain amplifier assembly 1310a, which provides the features and benefits of the illustrated variable gain amplifier. The DRx module 1308 also includes a similar variable gain amplifier adapter. Includes Assemblage 1310b.

[0058] In the example wireless device 1300, a primary antenna 1360 receives a signal and transmits it to a front The signal can be sent to the variable gain amplifier 1310a of the end module 1306. The gain amplifier 1310a may include an impedance adjustment circuit 1320. 10a receives a plurality of signals at an input 1311 and a plurality of signals at an output 1319. The variable gain amplifier 1310a is configured to output the processed signal. The signal is amplified based at least in part on the gain mode. The impedance adjustment circuit 1320 adjusts the input impedance based on the input signal. This is configured to optimize the LDO to transfer maximum power across multiple gain modes. By fixing the NA input impedance, the power loss is reduced or eliminated. The impedance adjustment circuit 1320 adjusts the impedance from the previous signal processing stage. The present invention is configured to improve the receive noise figure performance by reducing or minimizing the mismatch in the receive noise figure. The impedance adjustment circuit 1320 adjusts the impedance mismatch with the LNA circuit. The present invention is configured to maintain the performance of the LNA pre-filter by reducing or eliminating the interference. It is possible.

[0059] The wireless device also includes a diversity antenna 1370 and a diversity antenna The diversity receiver module 1308 receives signals from the diversity receiver 1370. The city receiver module 1308 is a variable gain in the front-end module 1306. The diversity receiver module includes a variable gain amplifier 1310b similar to the amplifier 1310a. The module 1308 and the variable gain amplifier 1310b process the received signal and output the processed signal as a 13. The diplexer 1302 transmits the signal to the transceiver 1304. A plexer, or other multiplexer or filter assembly, may be used as described herein. Between the diversity antenna 1370 and the diversity receiver module 1370 can be included in

[0060] A number of other wireless device configurations may also utilize one or more of the features described herein. For example, the wireless device does not need to be a multi-band device. In the present invention, a wireless device may include additional antennas, such as a diversity antenna, as well as a Wi-Fi May include additional connectivity features such as WiFi, Bluetooth and GPS. do.

[0061] One or more features of the present disclosure may be implemented in conjunction with the various cellular frequency bands described herein. Examples of such bands are given in Table 1. It will be understood that At least some of the bands may be divided into sub-bands. It is understood that implementations may be made with frequency ranges that do not have the designation as in the example of 1. The terms RF and radio frequency signals include at least the frequencies listed in Table 1. It is understood that reference is made to a signal. [Table 1]

[0062] This disclosure describes various features, any one of which may be independently utilized to benefit from the benefits described herein. It will be understood that various features described herein are within the skill of those in the art. As will be apparent to those skilled in the art, the following may be combined, modified, or omitted. Combinations and subcombinations other than those described above will be apparent to those skilled in the art. It is understood that various methods are disclosed herein and are intended to form part of this disclosure. It is understood that the steps and / or phases of the flowchart are described in relation to the steps and / or phases of the flowchart. However, in many cases, certain steps and / or phases may be represented by multiple steps shown in a flowchart. The steps and / or phases may be performed as a single step and / or phase. Certain steps and / or phases may also be combined together separately. In some examples, the method may be decomposed into additional subcomponents that can be implemented in a similar manner. The order of steps and / or phases may be rearranged and certain steps and / or phases may Alternatively, the method described herein may be modified in any manner as shown and described herein. The above description is provided so that additional steps and / or phases to those described may also be performed. It is understood to be Punendo.

[0063] Aspects of the systems and methods described herein can be advantageously implemented in, for example, a computer computer software, hardware, firmware or computer software, It may be implemented using any combination of hardware and firmware. The computer software is a computer readable medium that, when executed, performs the functions described herein. computer executable code stored on a non-transitory computer readable medium In some embodiments, the computer executable code may include one or more general purpose programs. Those skilled in the art will recognize in light of this disclosure that the present invention may be practiced by a general purpose computer processor. Any feature or functionality that can be implemented using software executed on a computer Furthermore, different combinations of hardware, software or firmware may be used For example, such a module may be implemented as a combination of integrated circuits. Alternatively or additionally, such features may be implemented entirely in hardware. The features or functions may be implemented in a computer system, rather than a general purpose computer, adapted to perform the specific functions described herein. The present invention may be implemented, in whole or in part, using special purpose computers designed for

[0064] Multiple distributed computing devices may be implemented using any one of the computing devices described herein. In such a distributed embodiment, a single computing device may be substituted. The functionality of the computing devices is distributed (e.g., across a network). Some functions are performed on each of the distributed computing devices. .

[0065] Some embodiments may be illustrated with reference to examples of formulas, algorithms and / or flow charts. These methods can be described as executable programs on one or more computers. These methods can also be implemented using computer program instructions. Each may be used as a separate computer program product or as a component of an apparatus or system. In this respect, each formula in the flowchart can be implemented as a , algorithms, blocks or steps, and combinations thereof, One or more devices embodied in firmware and / or computer readable program code logic. The above may be implemented by software, including computer program instructions. As will be appreciated, any such computer program instructions may be implemented in a general purpose computer or One or more computers, including, without limitation, special purpose computers, or other programmable processing devices. The program may be loaded into a computer or other programmable processing device. The computer program instructions executed in the process may be a formula, an algorithm, and / or a flow chart. - Implement the functionality specified in the chart. Each expression in the flow chart, The algorithms and / or blocks are implemented as specified functions or steps or as dedicated hardware. Dedicated hardware performing a combination of software and computer readable program code logic means. It will also be understood that the present invention may be implemented by a software-based computer system.

[0066] In addition, computer programs, such as those embodied in computer readable program code logic, The computer program instructions may also be stored in computer readable memory (e.g., non-transitory computer readable The information may be stored on one or more computers or other programmable processing devices. The device is caused to function in a particular manner. The instructions implement the functions identified in the flowchart blocks. Program instructions also refer to a sequence of operational steps performed by one or more computers or other programs. A computer-implemented process for performing on a mobile computing device. One or more computers or other programmable computing devices to The program may also be loaded into a computer or other programmable processing device. The instructions to be executed may be specified in formulas, algorithms and / or blocks of the flowchart. The method provides steps for implementing the specified function.

[0067] Some or all of the methods and tasks described herein may be performed by a computer system. The computer system can be used to perform some In this case, a number of separate components communicate and interoperate over a network to perform the described functions. A computer or computing device (e.g., a physical server, workstation, Such computing devices may include a variety of computing devices, including a single processor, ... The program stored in memory or other non-transitory computer-readable storage medium or device A processor (or multiple processors) that executes program instructions or modules. Various functions disclosed herein may be embodied in such program instructions. However, some or all of the disclosed functionality may alternatively be implemented in application specific circuits of a computer system. The computer system may be implemented in a network (e.g., ASIC or FPGA). In the case of multiple computing devices, these devices are co-located. The results of the disclosed methods and tasks may, but need not, be placed in a solid State memory chips and / or physical storage devices such as magnetic disks can be stored in different states. can be stored persistently by converting it to

[0068] Throughout this specification and claims, unless the context clearly indicates otherwise, The words "include", "comprise" and the like are used in an inclusive sense as opposed to an exclusive or exhaustive sense. In other words, it should be interpreted as meaning "including but not limited to." The word "coupled" as used herein means connected directly or through one or more intermediate elements. In addition, the words "here," "on," " "below" and words of similar import when used in this Application The term "Application" refers to the entire application and not to any specific portion of the Application. Where the context permits, the singular or plural forms may be used in the above detailed description of certain embodiments. Each word may also include the plural or the singular. " and "or" cover all of the following interpretations of the word: Any item on the list, all items on the list, and any combination of items on the list The word "exemplary" is used herein solely to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not intended to be construed as being comparable to other implementations. It should not necessarily be construed as preferred or advantageous over any other.

[0069] The present disclosure is not intended to be limited to the implementations shown herein. Various modifications thereto will be readily apparent to those skilled in the art and may be made in accordance with the general principles defined herein. The principles may be applied to other implementations without departing from the spirit and scope of the present disclosure. The teachings of the invention provided herein may be applied to other methods and systems, including those described above. The various embodiments described above are not limited to methods and systems. Thus, the novel methods and methods described herein can be combined to provide The system may be embodied in a variety of other forms. Various omissions, substitutions and changes in the form of the system may be made without departing from the spirit of the present disclosure. The appended claims and their equivalents are intended to fall within the scope and spirit of this disclosure. It is intended that the present invention cover such forms or modifications.

Claims

1. 1. A radio frequency (RF) signal amplifier configured to provide a plurality of gain modes, comprising: a power supply configured to provide a different source current for each of the plurality of gain modes; a gain stage including an RF stage transistor and a cascode stage transistor; an impedance adjustment circuit coupled to the gain stage; Including, An input RF signal is input to the gate of the RF stage transistor, The amplified RF signal is output from the drain of the cascode stage transistor; the gain stage is configured to receive the source current from the power supply to operate the gain stage in a corresponding one of the plurality of gain modes; a total input impedance presented to the input RF signal is related to the transconductance of the RF stage transistors; The impedance adjustment circuit is configured to provide a tailored adjustment that compensates for changes in the transconductance by including a plurality of inductive elements connected in series and a plurality of switches, each of which selectively couples a corresponding one of the plurality of inductive elements to a reference potential node.

2. the gain stage includes a plurality of switchable amplifier branches; 2. The amplifier of claim 1, wherein each of the plurality of switchable amplifier branches includes a switching transistor and an RF stage transistor.

3. A plurality of the RF stage transistors are activated in a first gain mode of the plurality of gain modes; a plurality of the RF stage transistors are activated in a second gain mode of the plurality of gain modes that is lower than the first gain mode; The RF stage transistors are connected in parallel to each other, 3. The amplifier of claim 2, wherein fewer of the RF stage transistors are activated in the second gain mode than in the first gain mode.

4. The amplifier of claim 1 , wherein the amplifier is a low noise amplifier (LNA).

5. 2. The amplifier of claim 1, wherein the tailored tuning is configured such that the total input impedance presented to the input RF signal is 50 ohms for each of the plurality of gain modes.

6. the gain stage is scalable and includes a plurality of transistors in an electrically parallel configuration; Each transistor is connected to one individual switchable amplifier branch; The amplifier of claim 1 , wherein the individually switchable amplifier branches activate transistors connected to the individually switchable amplifier branches.

7. The amplifier of claim 6 , wherein the impedance match circuit is further configured such that a ratio of the source currents for each of the plurality of gain modes matches a ratio of device sizes in the impedance match circuit.

8. 2. The amplifier of claim 1, wherein the tailored tuning is further configured to make a resistive contribution to the total input impedance constant.

9. The amplifier of claim 1 , wherein the plurality of gain modes includes a low gain mode, a high gain mode, and one or more intermediate gain modes.

10. 1. A semiconductor die having radio frequency (RF) circuitry, A substrate; an RF amplifier mounted to the substrate and configured to provide a plurality of gain modes; Including, the RF amplifier includes a power supply configured to provide a different source current for each of the plurality of gain modes; the RF amplifier further includes a gain stage including an RF stage transistor and a cascode stage transistor; An input RF signal is input to the gate of the RF stage transistor, The amplified RF signal is output from the drain of the cascode stage transistor; the gain stage is configured to receive the source current from the power supply to operate the gain stage in a corresponding one of the plurality of gain modes; a total input impedance presented to the input RF signal is related to the transconductance of the RF stage transistors; the RF amplifier further includes an impedance adjustment circuit coupled to the gain stage; The impedance adjustment circuit is configured to provide a tailored adjustment that compensates for changes in the transconductance by including a plurality of inductive elements connected in series and a plurality of switches, each of which selectively couples a corresponding one of the plurality of inductive elements to a reference potential node.

11. The semiconductor die of claim 10 , wherein the RF amplifier is a low noise amplifier (LNA).

12. the gain stage includes a plurality of switchable amplifier branches; The semiconductor die of claim 10 , wherein each of the plurality of switchable amplifier branches includes a switching transistor and an RF stage transistor.

13. The method of claim 12, wherein a plurality of the RF stage transistors are activated in a first gain mode among the plurality of gain modes; a plurality of the RF stage transistors are activated in a second gain mode of the plurality of gain modes, the second gain mode being lower than the first gain mode; The RF stage transistors are connected in parallel to each other, The semiconductor die of claim 12 , wherein a fewer number of the RF stage transistors are activated in the second gain mode than in the first gain mode.

14. 11. The semiconductor die of claim 10, wherein the tailored tuning is configured such that the total input impedance presented to the input RF signal is 50Ω for each of the plurality of gain modes.

15. The semiconductor die of claim 10 , wherein the tailored tuning is further configured to make a resistive contribution to the total input impedance constant.

16. 1. A wireless device, comprising: an antenna configured to at least receive a radio frequency (RF) signal; an RF amplifier in communication with the antenna; Transmitter and receiver Including, the RF amplifier is configured to provide a plurality of gain modes to generate an amplified RF signal; the RF amplifier includes a power supply configured to provide a different source current for each of the plurality of gain modes; the RF amplifier further includes a gain stage including an RF stage transistor and a cascode stage transistor; An input RF signal is input to the gate of the RF stage transistor, The amplified RF signal is output from the drain of the cascode stage transistor; the gain stage is configured to receive the source current from the power supply to operate the gain stage in a corresponding one of the plurality of gain modes; a total input impedance presented to the input RF signal is related to the transconductance of the RF stage transistors; the RF amplifier further includes an impedance adjustment circuit coupled to the gain stage; the impedance adjustment circuit is configured to provide tailored adjustments that compensate for changes in the transconductance by including a plurality of inductive elements connected in series and a plurality of switches, each switch selectively coupling a corresponding one of the plurality of inductive elements to a reference potential node; The transceiver is configured to process the amplified RF signal.

17. 17. The wireless device of claim 16, wherein the wireless device is a cellular phone configured to utilize the multiple gain modes in a receive operation.

18. 17. The wireless device of claim 16, wherein the tailored tuning is configured such that the total input impedance presented to the input RF signal is 50Ω for each of the multiple gain modes.

19. 17. The wireless device of claim 16, wherein the tailored tuning is further configured to make a resistive contribution to the total input impedance constant.

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