Droop detection and control for digital frequency locked loops - Patents.com

Abstract

The apparatus includes a reference signal generator, a droop detection circuit, a digital frequency locked loop (DFLL), and a DFLL control circuit. The reference signal generator receives a digital value and generates a pulse density modulated signal based on the digital value. The droop detection circuit converts the pulse density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and generates a droop detection signal in response to detecting a droop of the monitored supply voltage below a value specified for the analog signal. The DFLL provides a clock signal for synchronizing circuits within the domain of the monitored supply voltage. The DFLL control circuit causes the DFLL to slow down the clock signal in response to receiving the droop detection signal.

Description

[Background technology]

[0001] Integrated circuits and discrete circuits include terminals for receiving power from a power source and providing a power supply voltage to associated circuits. Circuits, for example inverters, are often connected between a power source and a circuit common or ground. In the case of a metal-oxide semiconductor field-effect transistor (MOSFET), a certain voltage at the gate terminal activates the transistor to generate a circuit path that drives a circuit element connected between the output terminal and the power source or ground, driving the operation of a subsequent circuit connected to the output terminal. The amount of current and circuit load is usually related to both the operating speed and the supply voltage. Due to the active nature of many circuits, the load fluctuates from time to time and can sometimes cause the supply voltage level to drop or be reduced from a desired level.

[0002] Voltage droop is a term used to refer to a drop in voltage from a desired voltage level when a power supply drives a load. In a regulated system, a sudden, sharp increase in load can cause the output voltage to drop. For example, a transient load condition can occur that causes voltage droop. If the droop is too great, circuit failure occurs.

[0003] In prior art systems, a supply regulation circuit or "header" circuit is operatively disposed between the power source and the circuitry and is adjusted to regulate or compensate for such variations in the power source. For example, some solutions include a header circuit that constantly switches at a high frequency relative to other power management features such as power state changes to minimize load from transients and regulate the supply voltage. These header circuits are often optimized to respond very quickly to voltage droop due to transient load conditions and other load conditions.

[0004] These prior art systems typically have significant customized analog design blocks and add significant overhead because they switch relatively large field effect transistors on and off to respond to transient load conditions. This overhead occurs even when operating in a steady-state mode. Thus, such systems not only consume valuable integrated circuit real estate, but are also inefficient from a power perspective. [Brief description of the drawings]

[0005] [Figure 1] 1 is a block diagram of a system for regulating supply voltages to multiple processor cores according to the prior art. [Diagram 2] FIG. 2 illustrates, in partial block diagram and partial schematic form, further details of a regulator system that compensates for droop, according to the prior art; [Figure 3A] FIG. 1 is a block diagram of a power supply monitor that can respond more quickly to voltage droop, according to some embodiments. [Figure 3B] FIG. 13 is a block diagram of a power supply monitor according to an additional embodiment. [Figure 4] 13A-13C are block and circuit diagrams of a power supply monitor according to yet an additional embodiment. [Diagram 5] FIG. 13 is a block and circuit diagram of a droop detection circuit according to a further additional embodiment that can respond more quickly to voltage droop while employing a reduced area of ​​silicon for the circuit. [Figure 6] 5 is a graph showing respective signals associated with the power supply monitor circuit of FIG. 4; [Figure 7] FIG. 13 is a block diagram of a power supply monitor, according to some additional embodiments. [Figure 8] FIG. 1 is a flow diagram illustrating operation of an electrical design current relaxation process according to some embodiments that provide reduced power consumption. [Figure 9] 8 is a graph of several signals illustrating respective signals associated with the power supply monitor circuit of FIG. 7; [Figure 10] 1 is a block diagram of an accelerated processing unit (APU) in accordance with some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] In the following description, the use of the same reference numbers in different figures indicates similar or identical items. Unless otherwise noted, the word "coupled" and its related verb forms include both direct and indirect electrical connections by means well known in the art, and unless otherwise noted, any description of a direct connection also refers to alternative embodiments using a suitable form of indirect electrical connection.

[0007] The apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator receives a digital value and generates a pulse density modulated signal based on the digital value. The droop detection circuit converts the pulse density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and generates a droop detection signal in response to detecting a droop of the monitored supply voltage below a value specified for the analog signal. The DFLL provides a clock signal to synchronize circuits within the domain of the monitored supply voltage. The DFLL control circuit causes the DFLL to slow down the clock signal in response to receiving the droop detection signal.

[0008] A method monitors a power supply. The method includes receiving a binary number and creating a scaled pulse density modulated signal based on the binary number. The pulse density modulated signal is converted to an analog signal and compared to a monitored supply voltage. In response to detecting a droop in the monitored supply voltage below a value specified for the analog signal, a droop detect signal is generated.

[0009] In response to the droop detection signal, the method slows down a clock signal to a digital frequency locked loop (DFLL) that provides a clock signal for synchronizing circuits within the domain of the monitored supply voltage.

[0010] The data processing system includes an integrated circuit having at least two processor tiles. Each processor tile includes digital logic, a local DFLL that provides a clock signal for synchronizing the digital logic, and a local power supply monitor for monitoring a respective monitored local supply voltage. Each power supply monitor includes a reference signal generator, a droop detection circuit, and a DFLL control circuit. The reference signal generator receives a digital value and generates a pulse density modulated signal based on the digital value. The droop detection circuit converts the pulse density modulated signal to an analog signal, compares the analog signal to a respective monitored local supply voltage, and generates a droop detection signal in response to detecting a droop of the respective monitored local supply voltage below a value specified for the analog signal. The DFLL control circuit causes the local DFLL to slow down the clock signal in response to receiving the droop detection signal.

[0011] 1 is a block diagram of a system for regulating supply voltages to multiple processor cores according to the prior art. A supply voltage VDD 12 is connected to multiple supply adjustment blocks (SABs) 14A-14C. Each of the supply adjustment blocks 14A-14C is connected to generate a regulated supply voltage to a processor core 16A-16C. Each of the processor cores 16A-16C includes a power supply monitor (PSM) 30A-30C, a fast droop detector (FDD) 26A-26C, and a digital low voltage regulator (DLVR) 22A-22C. Each of the DLVRs 22A-22C is formed within the processor core 16A-16C. The processor cores and their associated circuitry may be referred to as a "processor tile."

[0012] In some versions, a supply regulation block (SAB) 60 may be used in addition to or instead of the supply regulation block 14. As can be seen, the supply regulation block 60 is a footer circuit rather than a header circuit, meaning that the supply regulation block is connected between the processor core and ground instead of between the processor core and the power supply. In versions of the system of FIG. 1 in which the supply regulation block 60 is included, certain discrete logic is modified to support the desired operation, and one skilled in the art can easily make such a conversion in the design. The first regulators (22A-22C) and FDDs (26A-26C) remain the same. Thus, for example, the charge injection signal generated by the FDDs 26A-26C serves to activate or select a resistive element in the supply regulation block 60. Although only one supply regulation block 60 is shown in dashed lines, it should be understood that multiple supply regulation blocks 60 may be included in the version of FIG. 1. Similar to the supply regulation block 14 including the header circuitry, the second regulators, i.e., FDDs 26A-26C, generate charge injection signals that activate selected resistive elements to regulate the voltage drop across the supply regulation blocks 14A-14C and thus the voltages generated to the processor cores 16A-16C.

[0013] 2 shows, in part block diagram and part schematic form, further details of a regulator system for compensating for droop, according to one embodiment of the present invention. A supply voltage VDD 12 is connected to a supply regulation block 14, which generates a regulated supply voltage to a processor core 16. The magnitude of the regulated supply voltage is based on the values ​​of a control word, a charge control word, and a charge injection signal (shown as an additional input to SAB 14) generated by FDD 26. In the illustrated version, PSM 30, DLVR 22, and FDD 26 are all formed within the processor core block 16 of the version of FIG. 2.

[0014] The regulated supply voltage is provided to the PSM 30, which generates a digital representation of the magnitude of the regulated supply voltage to the DLVR 22. The regulated supply voltage is also generated to the FDD 26. The DLVR 22 is further connected to receive a target regulated supply voltage, shown as "target", and a droop threshold level from an external source, which in one embodiment may be a power management block. The DLVR 22 generates the droop threshold level to the FDD 26. The DLVR 22 also generates a control word "ctrl[(n-1): 0]" and a charge control word "chg_ctrl[(n-1): 0]" to the supply regulation block 14.

[0015] The FDD 26 includes a digital-to-analog converter (DAC) 62 connected to receive the droop threshold level from the DLVR 22 and configured to generate an analog signal at a plus (+) input of a comparator 64 with a magnitude corresponding to the received droop threshold level. In the illustrated version, the DAC 62 is a sigma-delta converter. A minus (-) of the comparator 64 is connected to receive a regulated supply voltage generated by the supply regulation block 14. The comparator 64 generates a charge injection signal that activates the supply regulation block 14 whenever the regulated supply voltage falls below the analog droop threshold level or voltage. Note that if the charge selection block utilizes NAND logic, a logic one for the charge injection signal triggers charge injection or, more specifically, supply voltage regulation for the selected MOSFET. A logic zero is generated only if the droop threshold is lower than the regulated supply voltage. Note also that the version of FIG. 2 includes a first regulator (DLVR 22) formed within the processor core block 16. In an alternative version, the first regulator, DLVR 22 , may be formed external to the processor core 16 .

[0016] The FDD 26 performs its processing very quickly by performing an analog comparison of the regulated supply voltage with the droop threshold. Thus, the charge injection signal can be generated almost instantly, much faster than processor-based digital logic that requires several clock cycles to obtain all necessary data and process that data. Thus, the second control loop, including the FDD 26, is a fast acting control loop to immediately correct or adjust the regulated supply voltage whenever the regulated supply voltage falls below the droop threshold level. In contrast, the first regulation loop, including the first regulator (DLVR 22), is a slower acting loop that compares the regulated supply voltage with a target regulated supply voltage value. By utilizing a fast acting second control loop with the FDD 26, a simpler and slower first regulation loop can be utilized to reduce the area of ​​the IC and associated power consumption. Furthermore, because the decision making in the second control loop is done in analog (real time), the first control loop can be clocked at a slower rate, thereby saving power.

[0017] 3 is a block diagram of two embodiments of a power supply monitor, labeled 300 (FIG. 3A) and 302 (FIG. 3B), in accordance with some embodiments. Power supply monitor 300 includes a reference signal generator 320, a fast droop detector 340, a DFLL control circuit 350, a digital frequency locked loop (DFLL) 360, and a finite state machine (FSM) 370. In this embodiment, droop detection performed by fast droop detector 340 is used to control DFLL 360 to increase or decrease its output clock signal frequency.

[0018] The reference signal generator 320 is connected to the local power controller and has an input for receiving a digital number indicative of a reference voltage, and an output for providing a modulated digital signal indicative of the reference voltage. The reference voltage is related to a desired level of the local supply voltage "VDD_CORE" to be monitored. The fast droop detector 340 has an input connected to the output of the reference signal generator 320, an input for receiving the VDD_CORE supply voltage, a third input, and an output.

[0019] DFLL control circuit 350 has an input connected to the output of fast droop detector 340 and an output connected to DFLL 360. DFLL 360 has a number of control and enable inputs (not shown) and an output that provides a clock signal for synchronizing circuitry within the domain of the monitored supply voltage.

[0020] FSM 370 has an input connected to an output of fast droop detector 340, an output connected to a second input of fast droop detector 340, and may include several other control inputs (not shown).

[0021] In operation, the local power controller for the monitored supply voltage, in this case the VDD_CORE voltage domain, is operable to adjust the monitored supply voltage and provide a new value of a binary number corresponding to the adjusted monitored supply voltage to reference signal generator 320. Reference signal generator 320 provides a digitally modulated signal carrying the provided value. Fast droop detector 340 compares the VDD_CORE supply voltage to an analog signal based on the digitally modulated signal to detect droop in the VDD_CORE supply voltage. Based on detecting such droop, fast droop detector 340 sends a droop detection signal to DFLL control circuitry 350. Based on this signal, DFLL control circuitry 350 instructs DFLL 360 to slow down the clock for a specified period of time or to stop and then slow down the clock.

[0022] Power supply monitor 302 includes a reference signal generator 320, a fast droop detector 340, a DFLL control circuit 350, a digital frequency locked loop DFLL 360, a clock gate 380, and a finite state machine 370. In this embodiment, the DFLL control scheme of Figure 3B is used in conjunction with clock gate 380 to provide a faster response to detected droop.

[0023] 3B is connected to the local power controller and has an input for receiving a digital number indicative of a reference voltage, and an output for providing a modulated digital signal indicative of the reference voltage. The reference voltage is related to a desired level of the local supply voltage "VDD_CORE" to be monitored. The fast droop detector 340 has an input connected to the output of the reference signal generator 320, an input for receiving the VDDCORE supply voltage, a second input, and an output.

[0024] DFLL control circuit 350 has an input connected to the output of fast droop detector 340 and an output connected to DFLL 360. DFLL 360 has a number of control and enable inputs (not shown) and an output providing a clock signal for synchronizing circuitry within the domain of the monitored supply voltage. Clock gate 380 has a first input connected to the output of DFLL 360, a second input connected to the output of fast droop detector 340, and an output for selectively providing a clock signal from DFLL 360.

[0025] FSM 370 has an input connected to an output of fast droop detector 340, an output connected to a second input of fast droop detector 340, and may include several other control inputs (not shown).

[0026] In operation of PSM 302, a local power controller for the voltage domain of the monitored supply voltage is operable to adjust the monitored supply voltage and provide a new value of a binary number corresponding to the adjusted monitored supply voltage to the reference signal generator. Reference signal generator 320 provides a digitally modulated signal carrying the provided value. Fast droop detector 340 compares the VDD_CORE supply voltage to an analog signal based on the digitally modulated signal to detect droop in the VDD_CORE supply voltage. Based on detecting such droop, fast droop detector 340 sends a droop detection signal to clock gate 380 and DFLL control circuit 350. Based on this signal, clock gate 380 gates the clock immediately while DFLL control circuit 350 commands DFLL 360 to slow down the clock for a specified period of time. Because DFLL 360 is relatively slow to respond to commands to implement changes in the clock frequency, fast droop detector 340 controls clock gate 380 in response to the droop detect signal to gate the clock signal for a specified period of time to reduce power consumed by the circuitry and mitigate droop undervoltage on the VDD_CORE power supply. FSM 370 controls the specified period of time by resetting the clock gate control signal, such as by controlling a latch.

[0027] FIG. 4 is a block diagram and circuit diagram of a power supply monitor 400 according to yet an additional embodiment. The power supply monitor 400 includes an extreme voltage minimum (XVMIN) detection circuit 410, a digital frequency locked loop DFLL 460, a clock gate 480, and a graphics DFLFSM 490 (GDFLL FSM). The power supply monitor 400 is an exemplary embodiment of the power supply monitor of FIG. 3B that provides a faster response to detected droop. Although the illustrated embodiment performs power monitoring of a graphics processor, the power supply monitor 400 is suitable for use with a wide variety of integrated circuits (ICs) that require power monitoring, such as central processing units (CPUs) or other data processors and application-specific ICs (ASICs). These processors and associated power supply monitors can be implemented in devices such as laptops, desktops, smartphones, tablets, servers, gaming consoles, and many other devices that incorporate processors and require power monitoring.

[0028] The XVMIN detection circuit 410 includes a first input receiving a graphics supply voltage to be monitored labeled "VDDGFX", a second input receiving a system management network clock signal labeled "SMNCLK(VDDGFX)", a first output providing a signal labeled "Xvmin_trig", a second output labeled "Xvmin_clk_stop", a fast droop detector 420, a pole voltage minimum trigger circuit 470 labeled "Xvmin_trigger", an AND gate 472, an OR gate 474, and an AND gate 476.

[0029] Fast droop detector 420, in this embodiment, generally includes a reference signal generator that receives a digital value and generates a pulse density modulated signal based on the digital value, and a droop detection circuit that converts the pulse density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and generates a droop detection signal in response to detecting a droop of the monitored supply voltage below a specified value relative to the analog signal. For example, Figure 5 illustrates an embodiment of a fast droop detector suitable for use as fast droop detector 420. Fast droop detector 420 has an input that receives a voltage to be monitored VDDGFX, an input that receives a clock signal SMNCLK(VDDGFX), an input that receives a signal labeled "ResetDD_Xvmin", and an output that provides a signal labeled "DDlatched_sync".

[0030] Xvmin_trigger 470 is a control circuit in this embodiment of the FSM and includes an input that receives the DDlatched_sync signal from fast droop detector 420, an output that provides a ResetDD_Xvmin signal to fast droop detector 420, an input that receives the clock signal SMNCLK (VDDGFX), and an output that provides a signal labeled "clk_gator."

[0031] OR gate 474 has a first input receiving signal DDlatched sync from fast droop detector 420, a second input receiving signal clk_gator from Xvmin trigger 470, and an output. AND gate 472 has a first input connected to the output of OR gate 474, a second input receiving a clock stop enable signal labeled "Reg_Xvmin_clkstop_en" from a configuration register (not shown), and an output providing a signal labeled "Xvmin_clk_stop."

[0032] AND gate 476 has a first input that receives signal DDlatched_sync from fast droop detector 420, a second input that receives an enable signal labeled "Reg_Xvmin_en" from a configuration register (not shown), and an output that provides signal Xvmin_trig.

[0033] DFLL 460 has a first input receiving a clock signal labeled "RefCLK," a second input receiving a signal labeled "DFLLConfigC[4:0]," a third input receiving a signal labeled "FcsTrig," and an output providing a clock signal, in this embodiment labeled "GFXCLK," a graphics processing core clock for synchronizing circuits in the domain of the monitored supply voltage VDDGFX. Clock gate 480 has a first input receiving clock signal GFXCLK from DFLL 460, a second input receiving signal Xvmin_clk_stop from AND gate 472 of XVMIN detection circuit 410, and an output providing a gated version of clock signal GFXCLK.

[0034] GDFLL FSM 490 includes an input connected to receive signal Xvmin_trig from XVMIN detection circuit 410, a frequency control stretch trigger output providing signal FcsTrig, a second output providing signal DFLLConfigC[4:0] containing the frequency control word (FCW) of DFLL 460, a control arbitration circuit 495 labeled "Arbitration", a peak current control (PCC) client stretch control circuit 491, a power brake client stretch control circuit 492 labeled "Power Brake", an adaptive PCC client stretch control circuit 493 labeled "APCC", and an XVMIN client stretch control circuit 494 labeled "Xvmin-stretch".

[0035] The PCC client stretch control circuit 491 receives a signal (not shown) from the host IC's voltage regulator indicating whether the inductor current associated with the overall IC power supply is at risk of exceeding a maximum threshold. Based on this signal, the PCC client stretch control circuit 491 generates an output indicative of a requested amount of clock stretch (slowing down) that is provided to the control arbitration circuit 495 as a requested amount of frequency control stretch (FCS). The power brake client stretch control circuit 492 receives a signal (not shown) from the system state controller to throttle the power consumption of the circuit based on the workload and generates an output that is provided to the control arbitration circuit 495 indicative of the requested amount of FCS. The APCC 493 has an input that receives a signal (not shown) from the adaptive peak current control circuit that is generated based on the amount of time the peak current control signal is active. The APCC 493 generates an output that is provided to the control arbitration circuit 495 indicative of the requested amount of FCS. The Xvmin-stretch 494 has an input that receives the signal Xvmin_trig and an output connected to the control arbitration circuit 495. Xvmin_stretch 494 generates an output signal to control and arbitration circuitry 495 indicating the amount of FCS requested based on the amount of time that signal Xvmin_trig is active.

[0036] The control arbitration circuit 495 has four inputs connected to the outputs of the PCC 491, the power brake 492, the APCC 493, and the Xvmin-stretch 494, which also have respective inputs (not shown) for receiving signals related to their functions. The control arbitration circuit 495 generally functions to select which of the four connected stretch clients will control the amount of clock stretch required for the DFLL 460, as described further below.

[0037] In operation, the fast droop detector 420 of FIG. 4 monitors the supply voltage VDDGFX and asserts an internal signal "Droopdetected" if the voltage exceeds some predetermined threshold level. This internal signal is latched at the output of the fast droop detector 420 in normal operation and shown as signal DDlatched_sync. The Xvmin_Trig state machine receives the signal DDlatched_sync as an input and initiates gating of the clock signal GFXCLK via the signal Xvmin_clk_stop. When the frequency of this clock drops to no clock, the current drawn from the supply voltage VDDGFX is reduced and the VDDGFX rail voltage comes out of droop. The signal internal Droopdetected that triggers this sequence is a latched signal that remains high (regardless of the voltage of VDDGFX) unless reset by the ResetDD_Xvmin signal from Xvmin_trig 470. This Droopdetected signal is also output to the GDFLL FSM 490 as a trigger signal (Xvmin_Trig).

[0038] The GDFLL FSM 490 has different clients 491, 492, 493, 494 that request different amounts of stretch for different programmable durations. While these particular clients are shown, other clients employed in performance and power control may be employed, and of course fewer clients may be used in various embodiments. Xvmin_stretch 494 is one of the clients that requests stretch and is triggered by signal Xvmin_Trig. In response, Xvmin_stretch 494 initiates a sequence of states to control how the clock frequency increases back to its previous state. This sequence is performed through a force stretch mode of the DFLL 460, in which the frequency control word that controls the DCO clock frequency in the DFLL 460 is gradually increased to its initial operating state. Typically, when the power delivery network (PDN) providing the supply voltage VDDGFX responds to a large current change event (known as a di / dt event) such as the extreme stretch generated by the trigger described above, the supply voltage tends to oscillate between droop and overshoot at the PDN resonant frequency for several cycles before eventually decaying. By gradually increasing the clock frequency in this manner, the illustrated circuit ensures that the frequency of the supply voltage changes is much lower than the natural resonant frequency of the PDN, preventing further oscillations. Different clients can request different amounts of stretch at different times, and the control arbitration circuit 495 arbitrates between all these requests. Preferably, the client requesting the largest amount of stretch gets priority and controls the DFLL 460.

[0039] Referring more specifically to the triggering process, in this embodiment, the logic of GDFLL FSM 490 operates on the clock signal SMNCLK, which exceeds 400 Mhz as shown, rather than on the system reference clock, which is typically slower, around 100 Mhz, to reduce the latency to initiate a stretch event. Xvmin_trigger 470 is triggered as soon as signal DDlatched_sync switches high. In the event of an extreme voltage minimum event, the goal of power supply monitor 400 is to drop clock signal GFXCLK as fast as possible and stretch as deeply as possible. However, any updates to DFLL 460 of FCWs to change the clock frequency must go through GDFLL FSM 490, and arbitration therein requires several clock cycles. Therefore, instead, Xvmin_trigger 470 generates a signal Xvmin_clock_gator that goes to clock gate 480. However, even with this fast path, it takes 2-3 cycles of the SMNCLK (VDDGFX) clock for power supply monitor 400 to operate to synchronize after a droop event. To avoid this additional delay, signal DDlatched_sync is ORed with the clock_gator signal generated by Xvmin_Trig 470 to control clock gate 480. DDlatched_sync stays high once triggered and should therefore be glitch-free. Additionally, clock gate 480 internally synchronizes its inputs (over 2-3 GFXCLK cycles and GFXCLK runs at a relatively high frequency) so that glitches cannot pass through. In this way, GFXCLK is stopped within a delay of 2-3 GFXCLK cycles (+ logic and propagation delays) following a droop event.

[0040] In a preferred embodiment, the Xvmin trigger 470 first resets the fast droop detector 420 latch with the ResetDD_Xvmin signal (FIG. 6), forces the signal DDlatched_sync low after a programmable count, and then releases the clock gating after an additional programmable cycle count. This sequence ensures that the following constraints are respected: First, DDlatched_sync is properly synchronized and remains high and stable long enough to initiate the Xvmin-stretch 494 in the GDFLL FSM 490. Second, by resetting DDlatched_sync before releasing the clock gating, the circuit ensures that the mafdd is ready to react if there is a new droop event (when GFXCLK is suddenly restored).

[0041] The programmability of signal Xvmin_clock_stop ensures that the circuit can stop the clock for at least a few more cycles than it takes to propagate the FCS stretch amount through the GDFLL FSM 490 (including arbitration and synchronization) and ultimately to the DFLL 460 to update its FCW and change to the stretched clock frequency.

[0042] The DFLL460 supports an external trigger to stretch the output CLK, so different parts of the host system can use this stretching trigger to implement different features that take advantage of the DFLL stretch functionality. One of these different features is the peak current control (PCC) feature that limits the amount of current consumed by the VDDGFX domain for protection of the off-chip voltage regulator. A similar feature exists for the power brake (PB) feature for throttle performance. The amount of stretch for these two features is the same and is programmable between 3% and 97.5% of the clock speed. The GDFLL FSM490 supports hysteresis counters for both inputs that can be used to filter the stretch inputs and make the stretch last longer.

[0043] Adaptive PCC (or APCC) is a feature that dynamically changes the amount of stretch depending on how long the PCC signal is asserted. The longer the PCC assertion, the greater the amount of stretch. When the PCC input is deasserted, the amount of stretch is decreased rather than suddenly switching to zero. To implement this feature, the APCC 493 is a programmable state machine within the GDFLL block that controls the initial stretch, increment stretch, maximum stretch, decrement stretch, final stretch, and the time for each step.

[0044] In previous clock stretch arbitration schemes, triggers from different features are ORed together, i.e., triggers from any feature program the DFLL stretch amount in the same way. XVMIN 410 exists to protect any voltage excursions above a specified minimum voltage "Vmin", so Xvmin_stretch 494 requests a larger amount of stretch than other deep stretch events. However, when XVMIN 410 is out of deep stretch, the GDFLL FSM 490 must compare its own FCS request with other FCS requests from other clients, and whichever client requests maximum stretch is treated as the final FCWoffset. This ensures that all clients get the protection they need. This arbitration process is implemented within the GDFLL FSM.

[0045] When Xvmin_Trig is asserted, Xvmin_stretch 494 generates the maximum FCS stretch amount. This stretch amount is preferably programmable. When the Xvmin_Trig input is deasserted, the stretch amount is gradually decreased rather than suddenly switched to zero. It utilizes a programmable state machine in the GDFLL block to control the initial stretch, increment stretch, max stretch, decrement stretch, final stretch, and the time of each step. All mentioned settings are preferably programmable and controlled via a register interface.

[0046] Figure 5 is a block diagram and circuit diagram of a portion of a power supply monitor 500 according to yet an additional embodiment. The illustrated portion of power supply monitor 500 is suitable for use with the monitoring and control topologies shown in Figures 3, 4 and 5, as well as other circuits in which a power supply is monitored to detect fast droop of the power supply voltage. For example, the design of power supply monitor 500 is employed in some embodiments to control a charge injection system, such as the prior art systems shown in Figures 1 and 2. Power supply monitor 500 generally includes a reference signal generator 510 and a fast droop detection circuit 550.

[0047] In this embodiment, the reference signal generator 510 has an input labeled "fddConfigln" that receives a binary number and an output labeled "LSIN" that provides a pulse density modulated signal. Generally, the reference signal generator 510 operates to scale the pulse density modulated signal based on the binary number. The reference signal generator 510 includes a control circuit 512, an expander 514, and a second order delta-sigma modulator 516. The control circuit 512 has a first input that receives the 10-bit binary number carried at the fddConfigln input, a second input that receives a reset signal labeled "resetDD", and an output labeled "ref" that carries the 10-bit binary number. The control circuit 512 generally operates to stop passing the 10-bit binary number when resetDD indicates that the fast droop detection circuit 550 is disabled or reset, and to pass the 10-bit binary number to its output when the fast droop detector is operational. Expander 514 has an input connected to the output of control circuit 512, and an output. Expander 514 expands a 10-bit number to a 16-bit number.

[0048] In this embodiment, delta-sigma modulator 516 is a second order delta-sigma modulator having an input connected to the output of expander 514, and an output providing a pulse density modulated binary signal LSIN. Although delta-sigma modulation is used in this embodiment, other suitable modulation schemes can be employed to provide a pulse density modulated signal based on a binary number representing a desired voltage level of the monitored power supply.

[0049] The reference signal generator 510 generates a bitstream whose average value is (ideally) equal to the supply voltage VDD at which the reference signal generator 510 operates, scaled by a 10-bit binary number received as a reference at the fddConfigln input. The long-term average output voltage of the bitstream LSIN corresponds to Equation 1 below, where "ref value" is the value of the 10-bit number provided to the fddConfigln input. (1)<lsin>avg=ref_value*VDD

[0050] Although this particular modulator design is employed in this embodiment, other embodiments employ other suitable delta-sigma modulator designs or other types of modulators for generating the pulse density modulated signal. The pulse density modulated signal LSIN is provided to an input of the fast droop detection circuit 550.

[0051] Fast droop detection circuit 550 includes a power sniffer 552, a level shifter 554, a low pass filter 551, a comparator 561, a second level shifter 574, a latch 580, a 2-to-1 multiplexer 576, and an AND gate 578. Fast droop detection circuit 550 is suitable for use in the power supply monitoring circuits of Figures 3, 4, and 5, as well as other power supply monitoring circuits.

[0052] The level shifter 554 has a first input that receives the pulse density modulated signal LSIN, a second input that receives an enable signal from the power sniffer 552, and an output that provides a pulse density modulated signal referenced to a clean supply voltage labeled "VDDCR_SOC" at a node labeled 555 (the voltage on this node is referred to as "Voltage 555"). The level shifter 554 may also include an inverting input 553 to provide an inverter version of the signal LSIN for use in level shifting. The level shifter 554 is supplied with two voltages for the two domains that shift the voltage levels from VDD to VDDCR_SOC.

[0053] Power sniffer 552 has a first input for receiving a power indication signal labeled "PwrOkVDD", a second input for receiving a clean supply voltage VDDCR_SOC, and an output connected to level shifter 554. Power sniffer 552 enables level shifter 554 in response to its two inputs if VDD is within a specified range.

[0054] Low pass filter 551 has an input coupled to the output of level shifter 254, and an output. Many low pass filter designs and component values ​​are suitable for use in various embodiments.

[0055] The comparator 561 has a first input coupled to the output of the low pass filter 551, a second input receiving the monitored supply voltage VDDCORE, and an output. In general, the comparator 561 provides a droop detection signal at its output in response to the monitored supply voltage VDDCORE dropping below a predetermined level with respect to the first input. In this embodiment, the comparator 561 comprises a series of four inverters including a first complementary-metal-oxide-semiconductor (CMOS) inverter 562, a second CMOS inverter 564, a third CMOS inverter 566, and a fourth CMOS inverter 568. Each inverter 562, 564, 566, 568 includes a positive supply terminal connected to the second input of the comparator to provide VDDCORE as a supply voltage for the inverter. The CMOS inverter 562 has an input connected to the first input of the comparator, and the inverters 564, 566, 568 are connected in series after the inverter 562. The output of the inverter 568 provides a droop detect signal to a level shifter 574 .

[0056] In this embodiment, inverters 562, 564, 566, 568 are biased to be configured to operate in a "crowbar" mode or crowbar region of operation in which both p-type metal-oxide semiconductor (PMOS) and n-type metal-oxide semiconductor (NMOS) sides of the inverters are turned on when the monitored supply voltage is at approximately a predetermined level relative to the voltage on the respective inverter input. In this embodiment, the predetermined level is twice the level of the voltage at the inverter input. Thus, when one-half of VDDCORE drops to the voltage at the output of low pass filter 551, inverters 562, 564, 566, 568 enter crowbar mode and switch from a digital low to a digital high, signaling a droop. Such operation provides high gain and fast response to detect droop below a specified level relative to the threshold voltage provided at the input of inverter 562. Because the inverters are biased in a crowbar state, they are highly sensitive to any noise on the input VDD rail. In some embodiments, at least inverter 562 or inverters 562 and 564 are biased in such a crowbar state.

[0057] Level shifter 574 has an input connected to the output of comparator 561 and an output. Level shifter 574 is supplied with both the VDDCORE supply voltage (the monitored voltage) and the VDD supply voltage. Level shifter 574 may also include an inverting input 573 to provide an inverted version of the droop comparator output for use in level shifting. Level shifter 574 operates to shift the droop detect signal relative to the VDD voltage.

[0058] A multiplexer 576 has a first input connected to the output of the level shifter 574 for receiving the droop detect signal, a second input, a selector input labeled "latchMode", and an output coupled to a clock gate (i.e., 360 in FIG. 3, 560 in FIG. 5) for gating the clock signal in response to the droop detect signal.

[0059] Latch 580 is a set-reset (SR) flip-flop with an "S" input connected to the output of level shifter 574, an "R" input that receives a reset signal labeled "resetDD_X", a "Q" output connected to a second input of multiplexer 576, and a "Q-NOT" output that is unused in this embodiment. The latchMode input of multiplexer 576 is used to select between the two inputs.

[0060] AND gate 578 has a first input that receives an enable signal for the droop detection circuit labeled “FDDEN,” a second input that receives the droop detection signal from the output of multiplexer 576, and an output that provides the final output of fast droop detection circuit 550 labeled “droopDetected.”

[0061] In operation, the fast droop detection circuit 550 receives the LSIN pulse density modulated signal. Due to the variability of VDD, this signal needs to be converted to a fixed voltage, which is accomplished by a level shifter 554 supplied from VDDCR_SOC. This VDDCR_SOC voltage is a stable regulated voltage that provides a fixed amplitude for the level-shifted pulse density modulated output of level shifter 554. This new fixed amplitude signal is fed to a low pass filter 551, which averages the value of the pulse density modulated signal to generate a stable analog voltage for use with comparator 561. This stable analog value provides a threshold for detecting droop in the VDDCORE voltage supply. In this embodiment, the threshold ("fdd threshold", FIG. 7) is twice the voltage of the stable analog value. The low pass filter 551 is a double RC low pass filter operating with a cutoff frequency of less than 10 MHz.

[0062] The output of low pass filter 561 is fed to a series of inverters in comparator 561, which is fed from VDDCORE, that function as an analog comparator. Because they are biased in the "crowbar" region, the series of inverters responds quickly to droop below a specified threshold. Preferably, at least two inverters are used to provide stability to the droop detect signal, and more preferably, at least three or four (as shown). The droop detect signal at the output of comparator 561 is level shifted back to the VDD domain to be used to control various circuits to mitigate power supply droop, such as the clock gating and PLL circuits shown in Figures 3, 4 and 5. A latch 580 is included to hold the droop detect signal at a digital high for a specified period of time to provide proper timing for control of operations such as one-time charge injection operations or PLL adjustments. When latch 580 is enabled, the droop detect signal will remain on when triggered until actively turned off by the local FSM.

[0063] Figure 6 is a graph 600 showing respective signals associated with the power supply monitor circuit 400 of Figure 4. Signals 601, 602, 603, 604, 605 show the digital levels of the signals over time when two droops are detected in the monitored supply voltage VDDGFX, while signal 606 shows the normalized speed of the DFLL output clock GFXCLK. The illustrated signals are aligned with respect to time.

[0064] For signal 601, the monitored supply voltage VDDCORE is shown against the Xvmin threshold at which the fast droop detector 420 detects droop. VDDCORE droops below the threshold twice in the illustrated scenario. The fast droop detector 420 detects the droop and generates the "Droopdetected" signal shown in graph 602. The XVmin_FSM 440 provides a signal "ResetDD_Xvmin" in graph 603, which controls the latch that holds the Droopdetected signal to reset it after a droop is detected.

[0065] Signal 604 is a latched droop detect signal DDlatched_sync, which is activated HIGH when the droop detect signal activates the latch output and remains HIGH until reset. XVmin_FSM 440 has a programmable period that can be adjusted depending on the use of the DDlatched sync signal. Signal 605 shows the signal Xvmin_clk_stop, which in the embodiment of FIG. 4 is generated by XVMIN detect circuit 410 to control clock gate 480. Signal 606 shows the normalized clock speed of DFLL 460 relative to its maximum operating speed before the droop detect event. As can be seen from the graph, the DDlatched_sync signal first causes clock gate 408 to gate the clock down to a normalized level of no clock or zero. Then, when control arbitration circuit 495, in response to its input, starts to control the frequency of DFLL 460 after three cycles of RefCLK, it causes DFLL 460 to gradually increase the speed of GFXCLK. In the illustrated scenario, a second droop is detected before GFXCLK reaches its full normalized value, so GFXCLK is gated again and the ramp-up process is then completed.

[0066] 7 is a block diagram of a power supply monitor 700 according to several additional embodiments of additional features for mitigating potential electrical design current (EDC) events. Power supply monitor 700 includes reference signal generator 320, fast droop detector 340, digital frequency locked loop (DFLL) 360, DFLL control circuit 745, and finite state machine 370. Similar to that of FIG. 3A, fast droop detector 340 performs droop detection that is used to control DFLL 360 to increase or decrease its output clock signal frequency. FSM 370 also functions similarly to that of FIG. 3A.

[0067] In this embodiment, the DFLL control circuit 745 includes additional features to mitigate potential EDC events that may, for example, violate peak current constraints of a power supply associated with the socket through which power is supplied to the host IC. Traditionally, EDC events are managed by PCC signals, such as those provided to the PCC client stretch control circuit 491 (FIG. 4). Typically, such EDC events are not instantaneous, but occur over a period of time, such as 500 nanoseconds or 1 microsecond. However, because PCC signals are typically generated away from the host IC, they take a relatively long time to reach the internal circuitry to the IC to be used for throttling and power control functions. The power supply monitor 700 provides an alternative way to measure such events occurring on-chip, and thus can respond more quickly to potential EDC events and prevent them more effectively.

[0068] DFLL control circuit 745 has an input connected to the output of fast droop detector 340, an output connected to DFLL 360, various digital control logic (not shown) that may be implemented as described above, and a counter 747. The counter value increments while droop is detected and decrements toward a zero value while droop is not detected. In response to the counter value exceeding a specified threshold, DFLL control circuit 745 provides a signal indicating there is a potential EDC event that may violate the peak current constraint.

[0069] 8 is a flow diagram 800 illustrating operation of an electrical design current relaxation process, according to some embodiments. The illustrated process is suitable for use with the power supply monitor 700 of FIG. 7 or other power supply monitor circuits.

[0070] The process begins at block 802, where it is determined whether a droop below a defined loadline level is detected. Thereafter, the process runs continuously. If a droop is detected at block 802, the process proceeds to block 804, where a counter, such as counter 747, is incremented. If a droop is not detected, the process proceeds to block 808, where the counter is decremented. (If the counter is already at zero, no action is taken.)

[0071] If the counter exceeds a predetermined threshold for detecting a potential EDC event at block 810, the process proceeds to block 812 where an EDC event trigger signal is activated or held. Such a signal may be used at various locations on the host IC to trigger a response to a potential EDC event. For example, the process may provide a signal to a stretch client as described with respect to FIG. 4, thus activating stretching of the DFLL through an arbitration process involving other clients. If the counter does not exceed the EDC event threshold at block 810, the process starts a separate hysteresis counter to deactivate the EDC event trigger signal. The hysteresis counter is reset at block 810 if the EDC threshold is crossed again if the other exceeds the threshold. If the hysteresis counter reaches a specified value without being reset, the EDC event trigger signal from block 812 is deactivated. The process continues in response to droop being detected or not detected, as indicated by the arrow back to block 802.

[0072] Figure 9 is a graph 900 illustrating respective signals associated with the power supply monitor circuit 700 of Figure 7. Signals 901, 902, 903, 904, 905 illustrate the behavior over time when three droops are detected in the monitored supply voltage VDDCORE. The illustrated signals are aligned with respect to time.

[0073] In signal 901, the monitored supply voltage, labeled "RVDD" in this example, is shown against the Xvmin threshold at which fast droop detector 420 detects droop. In this embodiment, the Xvmin threshold is set relative to the bottom of the Load Line (LL) region to allow for potential EDC events to be detected. In the illustrated scenario, RVDD droops below the threshold twice. Fast droop detector 420 detects the droop and generates the "Droop detected" signal shown in graph 902.

[0074] In signal 903, the value of a counter, such as counter 747 (FIG. 7), increments whenever the Droop detected signal is active. An unlatched droop detected signal, such as that described with respect to FIG. 5, is employed for this function to provide an accurate value for the counter. The counter decrements in response to droop no longer being detected. After the second illustrated droop in signal 901, a third droop begins before the counter is fully decremented, causing the counter to increment again. This droop continues long enough to cause the counter to exceed a specified threshold, labeled "Xvmin_count_threshold."

[0075] Signal 904 represents the EDC event trigger signal "Xvmin_trig_filt" generated in block 812 of the process of FIG. 8 to indicate an EDC event. Signal Xvmin_trig represents a programmable delay "Hysteresis_2" provided by DFLL control circuit 745 (FIG. 7) to control the period of time that signal Xvmin_trig_filt is held HIGH after being triggered, as shown in block 814 of FIG. 8. Signal 905 represents the signal "Xvmin_trig", which functions similarly to signal DDlatched_sync shown in FIG. 6 to provide a latched version of the Droopdetected signal to stabilize the functioning of the droop detection circuit. Signal Xvmin_trig represents a programmable delay "Hysteresis_1" provided by FSM 370 (FIG. 7) to control the latching of fast droop detection circuit 340 in this embodiment. As can be seen by comparing signals 904 and 905, the process using the counter filters the Xvmin_trig events such that only events that last for a specified number of clock cycles are recognized as potential EDC events and activate the trigger Xvmin_trig_filt.

[0076] FIG. 10 is a block diagram of an accelerated processing unit (APU) 1000, according to some embodiments. The APU 1000 is implemented as a system-on-chip (SoC) that may be part of various host data processing platforms in various embodiments. Although an APU is shown in this embodiment, other data processing platforms such as a central processing unit (CPU) or a graphics processing unit (GPU) may be used. For example, in some embodiments, the fine-grained memory access techniques herein are embodied in a GPU chip employed in a graphics card or other graphics processing module. In other embodiments, a dedicated processor core such as an intelligence processing unit (IPU) may be employed. In this embodiment, APU 1000 generally includes a CPU core complex 1010, a graphics core 1020, a set of display engines 1030, a memory management hub 1040, a data fabric 1050, a set of peripheral controllers 1060, a set of peripheral bus controllers 1070, a system management unit (SMU) 1080, flash memory 205, and a set of FG_DRAM memory controllers 1090.

[0077] The CPU core complex 1010 includes a processor tile 1012 and a processor tile 1014, each of which includes a CPU core, a power supply monitor (PSM), a fast droop detector (FDD), and a digital low voltage regulator (DLVR). In this example, the CPU core complex 1010 includes two processor tiles, but in other embodiments, the processor tile complex 1010 can include any number of processor tiles. Each of the processor tiles 1012 and 1014 is bidirectionally connected to a system management network (SMN) 1045 and a data fabric 1050 that form a control fabric, and can provide memory access requests to the data fabric 1050. Each of the processor tiles 1012 and 1014 can be a single core, or can be a core complex having two or more single cores that further share certain resources such as caches. All of the FDD embodiments of Figures 3-5 and 7 are suitable for use with the processor tiles 1012 and 1014 in various embodiments. Each FDD controls the local PLL or DFLL for its local CPU core according to the techniques described above.

[0078] Each of the graphics cores 1020 is a high-performance graphics processing unit (GPU) capable of performing graphics operations such as vertex processing, fragment processing, shading, texture blending, etc., in a highly integrated and parallel manner. Power monitoring using FDDs such as those in FIGS. 3-5 and 7 may be implemented in each of the graphics cores 1020 in various embodiments. Each graphics core 1020 is bidirectionally connected to the SMN 1045 and the data fabric 1050 and may provide memory access requests to the data fabric 1050. In this regard, the APU 1000 may support either a unified memory architecture in which the CPU core complex 1010 and the graphics core 1020 share the same memory space, or a memory architecture in which the CPU core complex 1010 and the graphics core 1020 share a portion of the memory space, while the graphics core 1020 also uses a private graphics memory inaccessible by the CPU core complex 1010.

[0079] A display engine 1030 renders and rasterizes objects generated by the graphics core 1020 for display on a monitor. The graphics core 1020 and the display engine 1030 are bidirectionally connected to a common memory management hub 1040 for uniform translation to appropriate addresses in memory, which in turn is bidirectionally connected to a data fabric 1050 for generating such memory accesses and receiving read data returned from the memory system.

[0080] Data fabric 1050 includes a crossbar switch for routing memory access requests and responses between any memory accessing agent and memory controller 1090. The data fabric also includes a system memory map defined by the basic input / output system (BIOS) to determine where to send memory accesses based on system configuration, as well as buffers for each virtual connection.

[0081] Peripheral controllers 1060 include a USB controller 1062 and a serial advanced technology attachment (SATA) interface controller 1064, each of which is bidirectionally connected to a system hub 1066 and an SMN 1045. These two controllers are merely examples of peripheral controllers that may be used in APU 1000.

[0082] Peripheral bus controller 1070 includes a system controller hub 1072 and a peripheral controller hub 1074, each of which is bidirectionally connected to an input / output (I / O) hub 1076 and an SMN 1045. System controller hub 1072 connects to flash memory 205 via a suitable communications link. I / O hub 1076 is bidirectionally connected to system hub 1066 and data fabric 1050. Thus, for example, a CPU core can program registers in USB controller 1062, SATA interface controller 1064, system controller hub 1072, or peripheral controller 1074, with accesses routed by data fabric 1050 through I / O hub 1076.

[0083] The SMU 1080 is a local controller that controls the operation of resources on the APU 1000 and synchronizes communication between them. The SMU 1080 manages the power-up sequencing of the various processors on the APU 1000 and controls multiple off-chip devices via reset, enable and other signals. The SMU 1080 also manages the power of the various processors and other functional blocks.

[0084] Although an SoC embodiment is shown, this is not limiting and other computing platforms may benefit from the techniques described herein.

[0085] The circuits of Figures 3A, 3B, 4, 5, 7 and 10, or any portion thereof, may be described or represented by a computer-accessible data structure in the form of a database or other data structure that may be read by a program and used directly or indirectly to manufacture an integrated circuit. For example, the data structure may be a behavioral or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that can synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware that comprises the integrated circuit. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing steps to manufacture the integrated circuit. Alternatively, the database on the computer-accessible storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, if desired.

[0086] While specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. It is therefore intended that the appended claims cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.< / lsin>

Claims

1. An apparatus comprising: a reference signal generator for receiving a digital value and generating a pulse density modulated signal based on the digital value; a droop detection circuit that converts the pulse density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and generates a droop detection signal in response to detecting a droop of the monitored supply voltage below a value specified for the analog signal; a digital frequency locked loop (DFLL) for providing a clock signal for synchronizing circuits within the domain of the monitored supply voltage; a DFLL control circuit that, in response to receiving the droop detection signal, causes the DFLL to slow down the clock signal. Device.

2. a clock gate coupled to the DFLL for gating the clock signal; a latch having an input for receiving the droop detect signal and an output coupled to the clock gate for gating the clock signal in response to the droop detect signal.

2. The apparatus of claim 1.

3. a state machine having an input for receiving the droop detect signal and an output coupled to control the latch; the state machine controls the latch to hold the droop detect signal for a specified period of time after the droop detect circuitry no longer detects the droop and to reset the droop detect signal after the specified period of time.

3. The apparatus of claim 2.

4. The DFLL control circuit includes: a first input for receiving the droop detection signal; one or more additional inputs for receiving a clock stretch request signal from respective additional circuits within the integrated circuit; arbitration logic for selecting whether the droop detect signal or the one or more additional inputs determines how much to slow down the DFLL.

2. The apparatus of claim 1.

5. the DFLL control circuit is operable to set a DFLL increment amount in the DFLL to control how quickly the DFLL increases the speed of the clock signal after the clock signal has been slowed down.

2. The apparatus of claim 1.

6. the droop detection circuit includes a level shifter for converting the reference pulse density modulated signal to a clean supply voltage; 2. The apparatus of claim 1.

7. the droop detection circuit includes a comparator comprising a series of inverters including at least a first complementary metal-oxide semiconductor (CMOS) inverter and a second CMOS inverter, each having a positive supply terminal receiving the monitored supply voltage; the first CMOS inverter includes an input for receiving the analog signal, the first CMOS inverter configured to operate in a crowbar mode when the monitored supply voltage is near a specified level; 2. The apparatus of claim 1.

8. A counter receiving the droop detect signal from a comparator, the counter including a counter value that increments while the droop detect signal indicates that droop is detected and that decrements while the droop detect signal indicates that droop is not detected; and and a control circuit that compares the counter value with a threshold and, in response to the counter value exceeding the threshold, provides a signal indicating the presence of a potential electrical design current (EDC) event that may violate a peak current constraint.

2. The apparatus of claim 1.

9. the apparatus being a processor; 2. The apparatus of claim 1.

10. the apparatus comprises a device that is any one of a laptop computer, a desktop computer, a smartphone, a tablet computer, a server, a game console, and a multimedia device; 2. The apparatus of claim 1.

11. 1. A method for monitoring a power source, comprising: Receiving a digital value; generating a scaled pulse density modulated signal based on the digital values; converting said pulse density modulated signal to an analog signal and comparing said analog signal to a monitored supply voltage; generating a droop detect signal in response to detecting droop of the monitored supply voltage below a value specified for the analog signal; and slowing down a clock signal in response to the droop detection signal to a digital frequency locked loop (DFLL) that provides a clock signal for synchronizing circuits within the domain of the monitored supply voltage. method.

12. gating the clock signal for a specified period in response to the droop detection signal.

12. The method of claim 11.

13. controlling a latch in response to the droop detect signal to hold the droop detect signal for a designated period of time after a droop detection circuit no longer detects the droop and to reset the droop detect signal after the designated period of time.

12. The method of claim 11.

14. after slowing down the clock signal, increasing the speed of the clock signal over time in specified periodic increments.

12. The method of claim 11.

15. setting a DFLL increment amount to control how quickly the DFLL increases the speed of the clock signal after the clock signal has been slowed down.

15. The method of claim 14.

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