Semiconductor device and method for manufacturing the same

Abstract

To increase gate leakage current when a diamond layer is formed on the semiconductor element.SOLUTION: A semiconductor element has an electron driving layer, an electron supply layer formed on the electron driving layer, a source electrode and a drain electrode, a gate electrode formed on the electron supply layer and containing nickel, and a nickel silicide layer formed between the electron supply layer and the gate electrode.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, an amplifier, and a power supply device. [Background technology]

[0002] High electron mobility transistors (HEMTs) are known as one type of semiconductor element. Semiconductor elements such as HEMTs become hotter as their output power increases. Therefore, a technology has been proposed to form a heat dissipation layer made of diamond on the surface of the element where the gate electrode is provided. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-157829 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the inventors' research has revealed that when a diamond layer is formed on a semiconductor element, a problem arises in that the gate leakage current increases.

[0005] According to one aspect, an object of the present invention is to provide a semiconductor element capable of reducing an increase in gate leakage current. [Means for solving the problem]

[0006] According to one embodiment, there is provided a semiconductor device including an electron transit layer, an electron supply layer formed on the electron transit layer, a source electrode and a drain electrode, a gate electrode formed on the electron supply layer and containing nickel, and a nickel silicide layer formed between the electron supply layer and the gate electrode. Effect of the Invention

[0007] According to one aspect, an increase in gate leakage current can be reduced. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of a semiconductor element using a Schottky junction. [Figure 2A] FIG. 2A illustrates an example of a semiconductor device having insulating layers of different thicknesses. [Figure 2B] FIG. 2B illustrates an example of a semiconductor device having insulating layers of different thicknesses. [Figure 2C] FIG. 2C is a diagram showing the change in drain current before and after heating for semiconductor elements having insulating layers of different thicknesses. [Diagram 3] FIG. 3 is a diagram showing the change in structure when a structure having an insulating layer containing silicon nitride is heated. [Figure 4] FIG. 4 is a diagram showing the change in drain current after the semiconductor device is heated to different temperatures. [Diagram 5] FIG. 5 is a diagram illustrating an example of a semiconductor device according to the first embodiment. [Figure 6A] FIG. 6A is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6B] FIG. 6B is a diagram illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6C] FIG. 6C is a diagram illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6D] FIG. 6D is a diagram illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6E] FIG. 6E is a diagram illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6F] FIG. 6F is a diagram illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6G] FIG. 6G is a diagram illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6H] FIG. 6H is a diagram illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6I] FIG. 6I is a diagram illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a diagram illustrating an example of a semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a diagram illustrating an example of a semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a diagram illustrating an example of a semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a diagram illustrating an example of a semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a diagram illustrating an example of a semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a diagram showing an example of a cross section taken along line ab in FIG. [Figure 13] FIG. 13 is a diagram illustrating an example of a semiconductor device according to the second embodiment. [Figure 14A] FIG. 14A is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 14B] FIG. 14B is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 14C] FIG. 14C is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 14D] FIG. 14D is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 14E] FIG. 14E is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 14F] FIG. 14F is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 14G] FIG. 14G is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 14H] FIG. 14H is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 15]FIG. 15 is a diagram illustrating an example of a semiconductor device according to the second embodiment. [Figure 16] FIG. 16 is a diagram illustrating an example of a semiconductor device according to the second embodiment. [Figure 17] FIG. 17 is a diagram illustrating an example of a semiconductor device according to the second embodiment. [Figure 18] FIG. 18 is a diagram illustrating an example of a semiconductor device according to a third embodiment. [Figure 19A] FIG. 19A is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 19B] FIG. 19B is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 19C] FIG. 19C is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 19D] FIG. 19D is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 19E] FIG. 19E is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 19F] FIG. 19F is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 19G] FIG. 19G is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 19H] FIG. 19H is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 19I] FIG. 19I is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 19J] FIG. 19J is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 19K] FIG. 19K is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 19L] FIG. 19L is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 20] FIG. 20 is a diagram illustrating an example of a semiconductor device according to a third embodiment. [Figure 21]FIG. 21 is a diagram illustrating an example of an amplifier using the semiconductor devices according to the first to third embodiments. [Figure 22] FIG. 22 is a diagram showing an example of a power supply device using the semiconductor elements according to the first to third embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An embodiment of the present invention will be described with reference to the drawings. Note that the embodiment described in the specification is one of the modes for realizing the invention, and the content and execution order of each process in the embodiment can be appropriately changed within the scope of the invention.

[0010] Example 1 First, an example of a problem to be solved by this embodiment will be described with reference to FIG.

[0011] FIG. 1 is a diagram showing an example of a semiconductor device using a Schottky junction. The semiconductor device 100 is an example of a HEMT using a Schottky junction. The semiconductor device 100 includes a substrate 101, a buffer layer 102, an electron transit layer 103, a two-dimensional electron gas (2DEG) 104, an electron supply layer 105, a source electrode 106, a drain electrode 107, and a gate electrode 108. The substrate 101 is a layer containing, for example, silicon carbide or the like. The buffer layer 102 is a layer containing, for example, aluminum gallium nitride or the like. The electron transit layer 103 is a layer containing, for example, gallium nitride or the like. The electron supply layer 105 is a layer containing, for example, aluminum gallium nitride or the like. The source electrode 106 and the drain electrode 107 are electrodes containing, for example, an alloy of titanium (hereinafter, referred to as Ti) and aluminum (hereinafter, referred to as Al) or the like. The gate electrode 108 is an electrode containing nickel (hereinafter, referred to as Ni), for example. In addition, the gate electrode 108 can form a Schottky junction with the electron supply layer 105 containing aluminum gallium nitride, for example, by having a layer containing Ni in the vicinity of the electron supply layer 105 of the gate electrode 108. Furthermore, the gate electrode 108 forms a Schottky junction with the electron supply layer 105, thereby generating a Schottky barrier on the electron supply layer 105 side of the interface between the gate electrode 108 and the electron supply layer 105. Therefore, when a voltage is applied to the gate electrode 108 so that the potential of the gate electrode 108 is lower than the potential of the electron supply layer 105, the mobility of electrons from the electron supply layer 105 to the gate electrode 108 can be suppressed.

[0012] A piezoelectric polarization occurs in the aluminum gallium nitride due to a difference in lattice constant between the gallium nitride contained in the electron transit layer 103 and the aluminum gallium nitride contained in the electron supply layer 105. This piezoelectric polarization and the spontaneous polarization of the aluminum gallium nitride induce electrons in the electron transit layer 103 near the interface between the electron transit layer 103 and the electron supply layer 105, and a 2DEG 104 in which electrons are distributed is obtained. When a high voltage is applied to the drain electrode 107 with respect to the source electrode 106, the electrons move from the source electrode 106 to the drain electrode 107 via the 2DEG 104. That is, a current flows through the 2DEG 104 between the source electrode 106 and the drain electrode 107. The semiconductor element 100 generates heat, for example, near the 2DEG 104 through which the current flows.

[0013] When a low voltage is applied to the gate electrode 108 with respect to the 2DEG 104 below the gate electrode 108, a depletion layer is formed in the electron supply layer 105 below the gate electrode 108 due to the field effect of the voltage applied to the gate electrode 108. By applying a lower voltage to the gate electrode 108 with respect to the 2DEG 104, the depletion layer spreads over a wider range. By controlling the voltage of the gate electrode 108, the spread of the depletion layer can be controlled, and the depletion layer can be made to act on the 2DEG 104, thereby controlling the electron density of the 2DEG 104. Therefore, by controlling the voltage applied to the gate electrode 108, the drain current flowing through the 2DEG 104 can be controlled. Here, when the semiconductor element 100 is turned off by applying a voltage to the gate electrode 108, the gate electrode 108 and the electron supply layer 105 are connected to each other through a Schottky junction, thereby suppressing the flow of gate leakage current. Here, in this embodiment, a state in which substantially no current flows from the drain electrode 107 to the source electrode 106 is referred to as an off state. In this embodiment, the current flowing between the gate electrode 108 and the drain electrode 107 is referred to as a gate leakage current.

[0014] As one research aimed at increasing the output of the semiconductor element 100, in order to improve heat dissipation, a diamond layer is formed on the electrode side of the semiconductor element 100, that is, on the surface on which the gate electrode 108 is formed. The diamond layer can be formed, for example, by a method of growing diamond crystals. The growth temperature of diamond crystals is 300[℃] to 1200[℃]. Diamond crystals grown at high temperatures are larger than diamond crystals grown at low temperatures. Therefore, a diamond layer formed by gathering diamond crystals grown at high temperatures has a higher thermal conductivity than a diamond layer formed by gathering diamond crystals grown at low temperatures. Therefore, in order to improve the heat dissipation of the semiconductor element 100, it is required to form diamond on the gate electrode 108 side of the semiconductor element 100 at a temperature of, for example, 500[℃] or higher.

[0015] However, the inventors' research has revealed that when a diamond layer is formed on the gate electrode 108 side of the semiconductor element 100 at a temperature of 500[°C] or higher, the gate leakage current increases compared to before the diamond layer is formed. The inventors' research has revealed that one of the causes of this problem is that metal atoms (e.g., Ni, etc.) contained in the gate electrode 108 are diffused to the electron supply layer 105 by a temperature of 500[°C] or higher. It is believed that the diffusion of metal atoms from the gate electrode 108 to the electron supply layer 105 destroys the Schottky barrier that has been generated at the interface between the gate electrode 108 and the electron supply layer 105, thereby increasing the gate leakage current.

[0016] Therefore, in this embodiment, an object is to provide a semiconductor element in which a diamond layer is formed so that Ni contained in the gate electrode does not diffuse into the electron supply layer, for example.

[0017] 2A and 2B are diagrams showing an example of a semiconductor element having insulating layers of different thicknesses, and FIG. 2C is a diagram showing the change in drain current before and after heating for a semiconductor element having insulating layers of different thicknesses. FIG. 2A is an example of a cross-sectional view of a semiconductor element 100a having an insulating layer 109a between the electron supply layer 105 and the gate electrode 108. The insulating layer 109a is, for example, a layer having a thickness of 10 [nm] containing silicon nitride or the like. FIG. 2B is an example of a cross-sectional view of a semiconductor element 100b having an insulating layer 109b between the electron supply layer 105 and the gate electrode 108. The insulating layer 109b is, for example, a layer having a thickness of 40 [nm] containing silicon nitride or the like. However, in FIGS. 2A and 2B, when the configuration is the same as that of the semiconductor element 100 shown in FIG. 1, the same reference numerals are used and the description is omitted.

[0018] The change in drain current with respect to the gate voltage when the semiconductor element 100a and the semiconductor element 100b were heated at 700° C. was measured. FIG. 2C is a graph showing the change in characteristics before and after heating. Here, in FIG. 2C, the drain current mainly indicates the total current value of the current flowing from the drain electrode 107 to the source electrode 106 and the gate leakage current. Also, in FIG. 2C, the gate voltage indicates the voltage value applied to the gate electrode. Furthermore, in FIG. 2C, the drain voltage is 10 V (constant). Here, in the semiconductor element 100a before heating, the off state is reached at a gate voltage of about −6 V, and at this time, the value of the drain current can be regarded as substantially indicating the value of the gate leakage current. Here, in this embodiment, the voltage value of the gate voltage required to control the off state is referred to as the off threshold voltage. Furthermore, in this embodiment, the state in which a current flows from the drain electrode 107 to the source electrode 106 is referred to as the on state. Also, the voltage value of the gate voltage required to control the on state is referred to as the on threshold voltage. When the characteristics of the semiconductor element 100a before heating are examined, the element is turned off when the gate voltage is about -6 V. At this time, the drain current is about 10 -7On the other hand, when the characteristics of the semiconductor element 100a after heating are examined, the drain current is about 10 -4 Next, looking at the characteristics of the semiconductor element 100b before heating, the element is turned off when the gate voltage is about -22 [V], and the drain current is about 10 -7 On the other hand, when the characteristics of the semiconductor element 100b after heating are examined, the drain current is about 10 -7 It can be seen that the current density [A / mm] does not substantially increase compared to before heating. In addition, the OFF threshold voltage of the semiconductor element 100b after heating changes from approximately -22 [V] before heating to approximately -6 [V]. Furthermore, the ON threshold voltage of the semiconductor element 100b after heating changes from approximately -10 [V] before heating to approximately 0 [V]. Therefore, it can be seen that the semiconductor element 100b after heating has changed to a better state in terms of switching characteristics compared to before heating.

[0019] Next, we explain the change in structure when a structure having a 40 nm thick insulating layer containing silicon nitride is heated to 700°C.

[0020] FIG. 3 is a diagram showing the change in structure when a structure having a silicon nitride layer is heated. As shown in FIG. 3, a structure having a gallium nitride layer, an aluminum gallium nitride layer, a gallium nitride layer to which silicon (hereinafter referred to as Si) has been added, a silicon nitride layer, and a Ni layer was heated at 700[℃] for 100 hours. As shown in FIG. 3, after heating, Ni is diffused from the Ni layer into the silicon nitride layer, but Ni is not diffused into the gallium nitride layer, aluminum gallium nitride layer, and gallium nitride layer to which Si has been added below the silicon nitride layer. Since Ni atoms and Si atoms bond at 300[℃] or higher, it is considered that Ni atoms diffused into the silicon nitride layer heated to 700[℃] bond with Si atoms in the silicon nitride layer to form nickel silicide. In addition, since the diffusion of Ni is suppressed after 100 hours of heating, it is considered that the nickel silicide layer formed in the silicon nitride layer functions to suppress further diffusion of Ni.

[0021] FIG. 4 shows the change in drain current after the semiconductor element is heated to different temperatures. A semiconductor element having a 40 nm thick insulating layer containing silicon nitride was heated at 750°C for 1 to 100 hours and at 900°C for 1 hour. The gate voltage was -30 V, and the semiconductor element was in the off state. As shown in FIG. 4, for example, before heating, when the drain voltage was 60 V, the gate leakage current was about 10 -10 In contrast, when heated at 750°C for 1 hour, 10 hours, and 100 hours, the gate leakage current was approximately 10 -10 [A / mm], which shows that the gate leakage current has not increased substantially compared to before heating. On the other hand, when heated at 900°C for 1 hour, the gate leakage current is about 10 -6[A / mm], and the current value of the gate leakage current is increased compared to before heating. In contrast to these results, the current value of the gate leakage current does not substantially increase when heated at 750[℃], which is believed to be due to the formation of a nickel silicide layer before Ni is diffused into the lower semiconductor layer. On the other hand, the current value of the gate leakage current increases when heated at 900[℃], which is believed to be due to the fact that Ni is diffused into the lower semiconductor layer before the nickel silicide layer is formed. In the experiment shown in FIG. 4, the thickness of the insulating layer containing silicon nitride of the heated semiconductor element was set to 40[nm]. However, for example, by appropriately adjusting the thickness of the insulating layer, it is believed that the nickel silicide layer can be formed before Ni is diffused into the lower semiconductor layer even when heated at 900[℃].

[0022] From the experimental results and considerations explained using Figures 2 to 4, it is considered that the nickel silicide layer plays a role in preventing Ni diffusion. Therefore, in order to suppress the increase in gate leakage current due to Ni diffusion in a high-temperature environment, a nickel silicide layer is formed between the electron supply layer and the gate electrode.

[0023] 〔structure〕 The structure of the semiconductor device according to the first embodiment will be described with reference to FIG.

[0024] Fig. 5 shows an example of a semiconductor device according to Example 1. The semiconductor device 200 shown in Fig. 5 includes, for example, a substrate 201, a buffer layer 202, an electron transit layer 203, a 2DEG 204, an electron supply layer 205, a source electrode 206, a drain electrode 207, a gate electrode 208, an insulating layer 209, and a nickel silicide layer 210.

[0025] The substrate 201 is, for example, a layer containing silicon carbide or the like and having a thickness of 10 [um] to 400 [um]. The buffer layer 202 is, for example, a layer containing aluminum gallium nitride or the like and having a thickness of 400 [um] to 600 [um]. The electron transit layer 203 is, for example, a semiconductor layer containing intrinsic semiconductor gallium nitride not doped with n-type impurities such as Si and having a thickness of 1 [um]. The 2DEG 204 is generated near the electron supply layer 205 in the electron transit layer 203, and is a region having a higher electron density than regions other than the 2DEG 204 in the electron transit layer 203 and the electron supply layer 205. When the semiconductor device 200 is in an on-state, a drain current flows from the drain electrode 207 to the source electrode 206 via the 2DEG 204. The electron supply layer 205 is, for example, a layer containing aluminum gallium nitride or the like and having a thickness of 20 [nm]. The source electrode 206 and the drain electrode 207 are electrodes containing, for example, an alloy of Ti and Al. The thickness of the alloy constituting the source electrode 206 and the drain electrode 207 is 150 [nm] to 650 [nm]. The gate electrode 208 is, for example, a laminate of a layer containing Ni and having a thickness of 10 [nm] to 50 [nm] and a layer containing Au and having a thickness of 300 [nm] to 500 [nm]. The insulating layer 209 is, for example, a layer containing silicon nitride and having a thickness of 10 [nm]. The nickel silicide layer 210 is, for example, a layer containing nickel silicide and having a thickness of 30 [nm]. The nickel silicide layer 210 may be, for example, a layer containing nickel silicide and silicon nitride, which are compounds, and elemental Ni, Si, and nitrogen (hereinafter referred to as N). Furthermore, in this specification, the composition ratio of each of the nickel silicide and the silicon nitride is not limited.

[0026] The semiconductor device 200 has, for example, a nickel silicide layer 210 between the electron supply layer 205 and the gate electrode 208 containing Ni. Therefore, the semiconductor device 200 can suppress the diffusion of Ni from the gate electrode 208 into the electron supply layer 205 when exposed to high temperatures. Therefore, the semiconductor device 200 can reduce an increase in gate leakage current when exposed to a high temperature environment.

[0027] [Manufacturing method] Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 6A to 6I.

[0028] 6A, an example of a method for forming the buffer layer 202, the electron transit layer 203, the electron supply layer 205, the source electrode 206, and the drain electrode 207 on the substrate 201 will be described. The buffer layer 202, the electron transit layer 203, and the electron supply layer 205 can be formed by a crystal growth method such as a metal organic chemical vapor deposition (MOCVD) method. The buffer layer 202, the electron transit layer 203, and the electron supply layer 205 may also be formed by a molecular beam epitaxy (MBE) method, for example.

[0029] In this embodiment, as an example, a method for growing aluminum gallium nitride, gallium nitride, and aluminum nitride using the MOCVD method will be described. In the MOCVD method, for example, a mixed gas of trimethylaluminum gas as an Al source, trimethylgallium gas as a gallium source, and ammonia gas as an N source is used. In addition, gallium will be expressed as Ga below. In addition, trimethylaluminum gas will be expressed as TMA gas, trimethylgallium gas will be expressed as TMG gas, and ammonia gas will be expressed as NH3 gas, respectively. At this time, the presence or absence of supply of TMA gas and TMG gas and the flow rate are appropriately determined according to the composition of the nitride semiconductor to be grown. The flow rate of NH3 gas, which is a raw material common to each nitride semiconductor, is, for example, 100 [ccm] to 10 [LM]. In addition, for example, the growth pressure is 50 [Torr] to 300 [Torr], and the growth temperature is 1000 [℃] to 2000 [℃]. The growth conditions for indium aluminum nitride are a growth pressure of 50 [Torr] to 200 [Torr] and a growth temperature of 650 [°C] to 800 [°C].

[0030] The source electrode 206 and the drain electrode 207 can be formed as follows. The regions on the electron supply layer 205 where the source electrode 206 and the drain electrode 207 are to be formed are exposed, and a photoresist is formed to cover the other regions. Then, using the photoresist as a mask, dry etching is performed using a chlorine-based gas to remove a part of the electron transit layer 203 and the electron supply layer 205 from the surface of the electron supply layer 205 to a depth of 40 [nm]. Then, using this photoresist as a growth mask, Ti is laminated to a thickness of 50 [nm] to 150 [nm] by evaporation, and then Al is laminated to a thickness of 100 [nm] to 500 [nm] to form a metal film in which a layer of Ti and a layer of Al are laminated. Then, the photoresist is removed together with the metal film formed thereon. Next, heat treatment is performed for 1 minute at 400 [℃] to 1000 [℃] in a nitrogen atmosphere or a hydrogen atmosphere to alloy Ti and Al. In this way, the source electrode 206 and the drain electrode 207, which are electrodes in which Ti and Al are alloyed, are formed.

[0031] An example of a method for forming the insulating layer 209 will be described with reference to FIGS. 6B to 6E. The insulating layer 209 can be formed by, for example, a sputtering method, an atomic layer deposition (ALD) method, an MOCVD method, or the like. For example, when a sputtering method is used to form the insulating layer 209, silicon nitride is deposited to a thickness of 40 [nm] using a rare gas such as Ar with a silicon nitride target (FIG. 6B). Then, a photoresist 211a is formed on the insulating layer 209 in a region where the gate electrode 208 and the nickel silicide layer 210 are to be formed (FIG. 6C). Dry etching is performed using a chlorine-based gas with the photoresist 211a as a mask (FIG. 6D). Then, the photoresist 211a is removed using an organic solvent at 200 [° C.] (FIG. 6E).

[0032] An example of a method for forming the gate electrode 208 will be described with reference to Figs. 6F to 6H. The region on the insulating layer 209 where the gate electrode 208 is to be formed is exposed, and a photoresist 211b is formed so as to cover the surfaces of the electron supply layer 205, the source electrode 206, and the drain electrode 207 (Fig. 6F). Using the photoresist 211b as a growth mask, a metal layer containing Ni is formed on the entire surface by a deposition method (Fig. 6G). Thereafter, the photoresist 211b is removed using an organic solvent at 200[°C] (Fig. 6H). At this time, the metal layer containing Ni on the photoresist 211b is removed together with the photoresist 211b, thereby forming the gate electrode 208 selectively formed on the insulating layer 209.

[0033] Next, an example of a method for forming the nickel silicide layer 210 will be described with reference to FIG. 6I. The gate electrode 208 containing Ni and the insulating layer 209 containing silicon nitride are heated to 700° C. After performing this heating process for 1 to 100 hours, the layer is cooled to 50° C. by natural air cooling or the like. By heating to 700° C., Ni is diffused from the gate electrode 208 into the insulating layer 209, and the diffused Ni atoms are bonded to the Si atoms contained in the insulating layer 209 to form nickel silicide. Then, the nickel silicide layer 210 is formed in a region of the insulating layer 209 up to 30 nm from the interface of the gate electrode 208. In this way, the semiconductor element 200 as shown in FIG. 6I is formed. In addition, the forming conditions of the nickel silicide layer 210 are appropriately determined so that the nickel silicide layer 210 is formed in the entire region of the insulating layer 209, not in a part of the insulating layer 209.

[0034] [Alternative form] Another embodiment of the semiconductor device according to the first embodiment will be described with reference to FIGS.

[0035] Fig. 7 is a diagram showing an example of the semiconductor element according to the embodiment 1. As shown in Fig. 7, in the semiconductor element 200, for example, an insulating layer 209a may be formed in the peripheral portion of the gate electrode 208. In this case, for example, the thickness of the insulating layer 209a in the peripheral portion of the gate electrode 208 may be formed to be 2 [nm] to 500 [nm].

[0036] For example, in a state where the insulating layer 209a is formed in the peripheral portion of the gate electrode 208 as shown in FIG. 7, the nickel silicide layer 210 can be formed by the heat treatment as described in FIG. 6I. At this time, for example, when the insulating layer 209a is made of silicon nitride having an amorphous structure, the bonding force of the hydrogen atoms bonded to the dangling bonds of the silicon nitride is weakened, and hydrogen is easily desorbed from the dangling bonds. For example, when the heat treatment as described in FIG. 6I is performed in an air atmosphere (or a nitrogen atmosphere), hydrogen desorbed from the dangling bonds in the insulating layer 209a may bond with nitrogen in the atmosphere. In this case, when the semiconductor element 200 is operated after the heat treatment, that is, after the nickel silicide layer 210 as shown in FIG. 6I is formed, the dangling bonds from which hydrogen is desorbed in the insulating layer 209a act to attract electrons near the 2DEG 204. As a result, the electron concentration of the 2DEG 204 decreases, which may cause the performance of the semiconductor element to deteriorate. Such a problem can be reduced, for example, by performing the heat treatment described in FIG. 6I in a hydrogen atmosphere. By heating in a hydrogen atmosphere, while there are hydrogen atoms that are detached from the dangling bonds and flow out from the insulating layer 209a into the atmosphere, the hydrogen atoms in the atmosphere can be made to flow into the insulating layer 209a. Therefore, after the heat treatment, that is, after the nickel silicide layer 210 shown in FIG. 6I is formed, the hydrogen atoms in the insulating layer 209a are bonded to the dangling bonds, so that the dangling bonds of the insulating layer 209 can be prevented from attracting electrons near the 2DEG 204.

[0037] FIG. 8 is a diagram showing an example of a semiconductor element according to the first embodiment. A diamond layer 212 may be formed on the electrode side surface of the semiconductor element 200, as opposed to the back surface on the substrate side. The diamond layer 212 is, for example, a layer containing diamond. The diamond layer 212 can be formed by, for example, an infiltration method or a hot filament chemical vapor deposition (HF-CVD) method. First, the semiconductor element 200 is immersed in an aqueous solution in which diamond particles are dispersed, and the diamond particles are attached to the electrode side surface of the semiconductor element 200. Thereafter, the diamond layer 212 is formed by growing the diamond particles attached to the semiconductor element 200 using a mixed gas of methane and hydrogen as a raw material gas. At this time, the diamond growth conditions are, for example, a concentration of methane relative to hydrogen of 0.05[%] to 10[%]. The growth pressure is 0.5[kPa] to 100[kPa], and the growth temperature is 300[℃] to 1200[℃] (for example, 700[℃]). Oxygen, nitrogen, etc. may be supplied depending on the growth conditions. The diamond layer 212 may be formed by a forming method such as a bias-enhanced nucleation method or a plasma CVD method. For example, the diamond layer 212 may be formed after the insulating layer 209 and the gate electrode 208 are formed (i.e., after FIG. 6H), and the nickel silicide layer 210 may be formed by utilizing the heat treatment when forming the diamond layer 212. When a mixed gas containing hydrogen and a raw material gas is used in the heat treatment when forming the diamond layer 212, the problem of hydrogen being desorbed from the insulating layer 209 due to the heat treatment as described above can be solved.

[0038] Although the method of forming the nickel silicide layer 210 has been described with reference to Fig. 6I, the method of forming the nickel silicide layer 210 is not limited thereto. For example, as described with reference to Figs. 6A to 6H, the insulating layer 209 and the gate electrode 208 are formed on the electron supply layer 205. Thereafter, as described with reference to Fig. 8, the diamond layer 212 is formed at a growth temperature of 500°C or higher. At this time, Ni is diffused from the gate electrode 208 to the insulating layer 209 by the heat treatment when forming the diamond layer 212, and the nickel silicide layer 210 can be formed.

[0039] The gate electrode 208 of the semiconductor element 200 is exposed to a high-temperature environment by the heat treatment when the diamond layer 212 is formed. For example, when a diamond layer is similarly formed on the semiconductor element 100 shown in FIG. 1, Ni contained in the gate electrode 108 is diffused into the electron supply layer 105, and as a result, it is considered that the gate leakage current of the semiconductor element 100 increases. On the other hand, when the diamond layer 212 is formed on the semiconductor element 200 as shown in FIG. 8, since the semiconductor element 200 has the nickel silicide layer 210, Ni contained in the gate electrode 208 can be prevented from diffusing into the electron supply layer 205. Therefore, the diamond layer 212 can be formed on the electrode side surface of the semiconductor element 200 by, for example, a heat treatment of 500[°C] or more. The semiconductor element 200 can improve the heat dissipation efficiency of the semiconductor element 200 by having, for example, the diamond layer 212.

[0040] In addition, in the first embodiment, the heat treatment in the diamond layer forming process is described as an example of the situation in which the semiconductor element 200 is exposed to a high temperature environment, but the situation in which the semiconductor element 200 is exposed to a high temperature environment is not limited to this. For example, when the semiconductor element 200 or a device composed of other electronic components is operated in a nuclear reactor or in outer space, the vicinity of the gate electrode 208 of the semiconductor element 200 may reach a high temperature of 500° C. or more. Even in such a case, the semiconductor element 200 can suppress the increase in gate leakage current by having, for example, the nickel silicide layer 210.

[0041] FIG. 9 is a diagram showing an example of a semiconductor element according to the first embodiment. As shown in FIG. 9, a diamond layer 212b may be formed on the back surface of the substrate side of the semiconductor element 200 with respect to the electrode side surface. The diamond layer 212b is, for example, a layer containing diamond. When the diamond layer 212b is formed on the back surface of the substrate side of the semiconductor element 200, for example, if the back surface of the substrate 201 has a flat structure, the diamond layer 212b may be formed separately from the semiconductor element 200 and bonded to the back surface of the substrate 201. The diamond layer 212 and the diamond layer 212b may be formed on both the electrode side surface and the back surface of the substrate side of the semiconductor element 200, or on either one of them. For example, by forming both the diamond layer 212 and the diamond layer 212b, the semiconductor element 200 can improve heat dissipation compared to forming only one of them.

[0042] FIG. 10 is a diagram showing an example of a semiconductor device according to the first embodiment. In the semiconductor device 200, for example, a cap layer 213 may be formed between the electron supply layer 205 and the insulating layer 209. The cap layer 213 is, for example, a layer containing gallium nitride and having a thickness of 1 [nm] to 10 [nm]. The cap layer 213 can be formed by using, for example, an MOCVD method or an MBE method. The cap layer 213 may be an intrinsic semiconductor gallium nitride, or a gallium nitride to which Si is added. For example, by employing a semi-insulating gallium nitride or the like for the cap layer 213, it is possible to suppress a current from flowing from the 2DEG 204 to the gate electrode 208. That is, by having the cap layer 213, for example, the semiconductor device 200 can reduce a gate leakage current.

[0043] FIG. 11 is a diagram showing an example of a top view of a semiconductor element according to Example 1. The semiconductor element 200 shown in FIG. 11 has a diamond layer 212 on the surface on which a source electrode 206, a drain electrode 207, and a gate electrode 208 are formed. A contact hole 206a on which the diamond layer 212 is not formed is provided in a partial region of the surface of the source electrode 206. A contact hole 207a on which the diamond layer 212 is not formed is provided in a partial region of the surface of the drain electrode 207. A contact hole 208a on which the diamond layer 212 is not formed is provided in a partial region of the surface of the gate electrode 208. In addition, FIG. 11 shows the source electrode 206, the drain electrode 207, and the gate electrode 208 formed under the diamond layer 212 so as to be visible.

[0044] FIG. 12 is a diagram showing an example of the a-b cross section in FIG. 11. For example, when a drain current flows through the 2DEG 204, heat is generated in the region of the 2DEG 204 of the electron transit layer 203. The heat generated by the flow of this drain current can be dissipated through the diamond layer 212 formed on the electrode side. On the other hand, for example, in order to wire the semiconductor element 200 to other semiconductor elements or electronic components, contact holes 206a, 207a, and 208a are provided as shown in FIG. 11 and FIG. 12. In addition, although not shown, for example, the contact holes may be provided from the electrode toward the substrate 201 side, rather than on the surface.

[0045] The semiconductor device 200 has the nickel silicide layer 210 formed between the electron supply layer 205 and the gate electrode 208 containing Ni, and thus can reduce an increase in gate leakage current due to, for example, heat treatment.

[0046] Furthermore, by having the diamond layer 212 shown in FIG. 8, the semiconductor device 200 can improve, for example, the heat dissipation efficiency.

[0047] Furthermore, the semiconductor element 200 has the insulating layer 209 between the electron supply layer 205 and the gate electrode 208, and thus, for example, it is possible to reduce an increase in gate leakage current. Furthermore, according to the manufacturing method of the semiconductor element 200 described with reference to FIGS. 6A to 6I, it is possible to form the nickel silicide layer 210 while leaving the insulating layer 209 between the electron supply layer 205 and the gate electrode 208. In this way, the nickel silicide layer 210 suppresses the diffusion of Ni, and further, the insulating layer 209 can reduce the gate leakage current.

[0048] Furthermore, the configuration of the semiconductor device 200 is not limited to the above-mentioned configuration. The substrate 201 may contain Si, sapphire, gallium nitride, diamond, etc. The aluminum gallium nitride contained in the buffer layer 202 is Al x Ga 1-xIt may also be a multilayer structure in which the ratio of Al to Ga decreases from the substrate 201 side toward the electron transport layer 203 side with a composition ratio of N(0.2 < x < 0.8). Further, for example, when the substrate 201 contains Si, the buffer layer 202 may be a layer containing aluminum nitride. Further, for example, when the substrate 201 contains gallium nitride and the electron transport layer 203 contains gallium nitride, the buffer layer 202 may not be formed. The electron transport layer 203 may be, for example, a layer containing aluminum gallium nitride, aluminum gallium arsenide, gallium arsenide, or the like. The composition ratio of aluminum gallium nitride contained in the electron supply layer 205 may be, for example, Al x Ga 1-x N(x = 0.2). The electron supply layer 205 may be, for example, a layer containing indium aluminum gallium nitride, indium aluminum nitride, aluminum nitride, aluminum gallium arsenide, gallium arsenide, or the like. The source electrode 206 and the drain electrode 207 may be electrodes in which a gold layer (hereinafter referred to as Au) and a platinum layer (hereinafter referred to as Pt) are laminated on a Ti layer. Further, the source electrode 206 and the drain electrode 207 may be electrodes in which a plurality of different metal elements are laminated and then alloyed. The gate electrode 208 may be, for example, an electrode in which a Pt layer, a molybdenum layer (hereinafter referred to as Mo), a tungsten layer (hereinafter referred to as W), an Al layer, a lead layer (hereinafter referred to as Pb), a Ti layer, or the like is laminated on a Ni layer. The insulating layer 209 may be, for example, a layer containing silicon oxide. Further, the insulating layer 209 may further have an aluminum oxide layer, a hafnium oxide layer, or the like laminated thereon.

[0049] 6H, nickel silicide is gradually formed from the gate electrode 208 side toward the electron supply layer 205 side in the insulating layer 209. Therefore, the metal concentration is higher on the gate electrode 208 side in the insulating layer 209 than on the electron supply layer 205 side in the insulating layer 209. Also, for example, Ni is diffused into the insulating layer 209 to form a nickel silicide layer, and the metal concentration on the gate electrode 208 side of the insulating layer 209 is saturated, thereby making it possible to suppress further diffusion of Ni from the gate electrode 208.

[0050] Example 2 〔structure〕 Fig. 13 is a diagram showing an example of a semiconductor device according to Example 2. The semiconductor device 300 shown in Fig. 13 includes, for example, a substrate 301, a buffer layer 302, an electron transit layer 303, a 2DEG 304, an electron supply layer 305, a source electrode 306, a drain electrode 307, a gate electrode 308, and a nickel silicide layer 310. The semiconductor device 300 has a configuration partially similar to that of the semiconductor device 200 shown in Fig. 5, for example, and in that case, detailed description may be omitted. For example, the substrate 301, the buffer layer 302, the electron transit layer 303, and the 2DEG 304 have the same configurations as the substrate 201, the buffer layer 202, the electron transit layer 203, and the 2DEG 204 of the semiconductor device 200 shown in Fig. 5, respectively. The electron supply layer 305, the source electrode 306, the drain electrode 307, the gate electrode 308, and the nickel silicide layer 310 have the same configuration as the electron supply layer 205, the source electrode 206, the drain electrode 207, the gate electrode 208, and the nickel silicide layer 210 shown in Fig. 5. As described in the first embodiment, for example, Ni diffused into the layer containing silicon nitride is thought to combine with Si to form nickel silicide, thereby suppressing further diffusion of Ni. Therefore, in the second embodiment, a method for manufacturing a semiconductor device 300 having a nickel silicide layer 310 formed by a method different from that described in the first embodiment will be described.

[0051] 13 has a higher electric resistance than Ni used as the material of the gate electrode 308. Therefore, by forming the nickel silicide layer 310 between the electron supply layer 305 and the gate electrode 308, it is possible to reduce the gate leakage current. The nickel silicide layer 310 may be a layer containing, for example, nickel silicide and silicon nitride, which are compounds, and elemental Ni, Si, and N.

[0052] [Manufacturing method] A method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. 14A to 14H.

[0053] 14A, a substrate 301, a buffer layer 302, an electron transit layer 303, an electron supply layer 305, a source electrode 306, and a drain electrode 307 are formed. The substrate 301, the buffer layer 302, the electron transit layer 303, the electron supply layer 305, the source electrode 306, and the drain electrode 307 can be formed by, for example, the same method as in Example 1, and therefore detailed description thereof will be omitted.

[0054] An example of a method for forming the nickel silicide layer 310 will be described with reference to FIG. 14B to FIG. 14E. The nickel silicide layer 310 can be formed by, for example, a sputtering method, an ALD method, an MOCVD method, or the like. In this embodiment, as an example, a case where the nickel silicide layer 310 is formed by using a sputtering method will be described. Si and Ni (or nickel silicide) are targeted and a rare gas such as argon (hereinafter, referred to as Ar) is used to deposit Si and Ni (or nickel silicide) to a thickness of 30 [nm]. At this time, for example, when depositing Si and Ni, the nickel silicide layer 310 is formed by performing a heat treatment at 300 [℃] to 400 [℃] (FIG. 14B). After that, a pattern of a photoresist 311a is formed in a region on the nickel silicide layer 310 where the gate electrode 308 is to be formed (FIG. 14C). Dry etching is performed using a chlorine-based gas with the photoresist 311a as a mask (FIG. 14D). Then, the photoresist 311a is removed using an organic solvent at 200° C. (FIG. 14E).

[0055] Next, an example of a method for forming the gate electrode 308 will be described with reference to FIGS. 14F to 14H. First, a region on the nickel silicide layer 310 where the gate electrode 308 is to be formed is exposed, and a pattern of photoresist 311b is formed to cover the other regions (FIG. 14F). Using the photoresist 311b as a growth mask, a metal layer containing Ni is formed on the entire surface by deposition (FIG. 14G). Then, the photoresist 311b is removed using an organic solvent at 200° C. (FIG. 14H). At this time, the metal layer containing Ni on the photoresist 311b is removed together with the photoresist 311b, thereby forming the gate electrode 308 selectively formed on the nickel silicide layer 310. In this manner, the semiconductor element 300 shown in FIG. 14H can be formed.

[0056] [Alternative form] Another embodiment of the semiconductor device according to the second embodiment will be described with reference to FIGS.

[0057] Fig. 15 is a diagram showing an example of a semiconductor element according to Example 2. A diamond layer 312 may be formed on the electrode side surface of the semiconductor element 300 as opposed to the substrate side back surface. The diamond layer 312 is, for example, a layer containing diamond or the like. The diamond layer 312 can be formed by, for example, a method similar to that for the diamond layer 212 shown in Fig. 8, and therefore a detailed description thereof will be omitted.

[0058] FIG. 16 is a diagram showing an example of a semiconductor element according to the second embodiment. A diamond layer 312b may be formed on the electrode side surface of the semiconductor element 300 and on the substrate side back surface. The diamond layer 312b is, for example, a layer containing diamond. The diamond layer 312b can be formed, for example, by a method similar to that of the diamond layer 212b shown in FIG. 9, and therefore the description is omitted. The diamond layer 312 and the diamond layer 312b may be formed on both the electrode side surface and the substrate side back surface of the semiconductor element 300, or on either one of them. For example, by forming both the diamond layer 312 and the diamond layer 312b, the semiconductor element 300 can improve heat dissipation compared to forming only one of them.

[0059] Fig. 17 is a diagram showing an example of a semiconductor device according to Example 2. In the semiconductor device 300, for example, a cap layer 313 may be formed between the electron supply layer 305 and the nickel silicide layer 310. The cap layer 313 is, for example, a layer containing gallium nitride and having a thickness of 1 [nm] to 10 [nm]. The cap layer 313 can be formed by, for example, a method similar to that for the cap layer 213 shown in Fig. 10, and therefore a detailed description thereof will be omitted.

[0060] Although not shown, contact holes may be formed in order to wire the semiconductor element 300 on which the diamond layer 312 is formed to other semiconductor elements or electronic components. In this case, a part of the diamond layer 312 may not be formed in order to form the contact holes.

[0061] Example 3 Although the first and second embodiments have been described using a HEMT as an example, for example, a field effect transistor, which is an example of a semiconductor element, also has the same problems as those described using the first and second embodiments. In the third embodiment, a field effect transistor different from a HEMT will be described as an example.

[0062] 〔structure〕 A semiconductor device according to a third embodiment will be described with reference to FIG.

[0063] Fig. 18 is a diagram showing an example of a semiconductor device according to Example 3. A semiconductor device 400 shown in Fig. 18 includes, for example, a substrate 401, a drift layer 402, a channel layer 403, a contact layer 404, a source electrode 405, a drain electrode 406, an insulating layer 407, a nickel silicide layer 408, and a gate electrode 409.

[0064] The substrate 401 is doped with n-type impurities such as Si at a concentration of 5×10 16 [cm -3 The drift layer 402 is a layer having a thickness of 1.0 [um] that contains gallium nitride doped with n-type impurities such as Si at a concentration of 8×10 15 [cm -3 The channel layer 403 is a layer having a thickness of 0.2 [um] containing gallium nitride doped with n-type impurities such as Si at a concentration of 5×10 16 [cm -3 The contact layer 404 is a semiconductor layer having a thickness of 0.2 [um] and containing gallium nitride doped with an n-type impurity such as Si at a concentration of 2×10 18 [cm -3] is a layer having a thickness of 0.2 [um] containing gallium nitride doped with gallium nitride. The source electrode 405 and the drain electrode 406 are electrodes formed by stacking, for example, a layer having a thickness of 50 [nm] to 150 [nm] containing Ti and a layer having a thickness of 100 [nm] to 500 [nm] containing Al. The insulating layer 407 is, for example, a layer having a thickness of 10 [nm] containing silicon nitride. The nickel silicide layer 408 is, for example, a layer having a thickness of 30 [nm] containing nickel silicide. The nickel silicide layer 408 is, for example, a layer containing nickel silicide, silicon nitride, and elemental elements Ni, Si, and N. The gate electrode 409 is, for example, an electrode formed by stacking, for example, a layer having a thickness of 10 [nm] to 50 [nm] containing Ni and a layer having a thickness of 300 [nm] to 500 [nm] containing Au.

[0065] In the semiconductor element 400, a drain current flows from the drain electrode 406 to the source electrode 405 through the substrate 401, the drift layer 402, the channel layer 403, and the contact layer 404 by applying a high voltage to the drain electrode 406 relative to the source electrode 405. For example, when a low voltage is applied to the gate electrode 409 relative to the channel layer 403, a depletion layer is formed in the channel layer 403 from the interface between the gate electrode 409 and the channel layer 403 due to the field effect of the voltage applied to the gate electrode 409. By applying a lower voltage to the gate electrode 409 relative to the channel layer 403, the depletion layer spreads over a wider range. By controlling the voltage applied to the gate electrode 409, the spread of the depletion layer can be controlled, and the depletion layer can be made to act on the channel layer 403, thereby controlling the electron density of the channel layer 403. Therefore, in the semiconductor element 400, for example, by controlling the voltage applied to the gate electrode 409, the drain current flowing through the channel layer 403 can be controlled.

[0066] In order to improve the heat dissipation of the semiconductor element 400, it is required to form diamond on the drift layer 402 of the semiconductor element 400 at a temperature of, for example, 500° C. or higher. For example, when the channel layer 403 and the gate electrode 409 are Schottky junctioned, if a diamond layer is formed on the drift layer 402 of the semiconductor element 400 at a temperature of 500° C. or higher, a problem occurs in that the gate leakage current increases. Research by the inventors has revealed that one of the causes of this problem is that metal atoms (e.g., Ni, etc.) contained in the gate electrode 409 are diffused into the channel layer 403. It is considered that the diffusion of metal atoms from the gate electrode 409 into the channel layer 403 destroys the Schottky barrier that has been generated at the interface between the gate electrode 409 and the channel layer 403, which increases the gate leakage current. This problem can be solved by forming a nickel silicide layer, which is the nickel silicide layer 408, between the channel layer 403 and the gate electrode 409. In other words, by forming the nickel silicide layer 408 between the channel layer 403 and the gate electrode 409 of the semiconductor element 400, an increase in the gate leakage current can be suppressed even when the diamond layer is formed at a temperature of 500° C. or higher.

[0067] [Manufacturing method] A method for manufacturing a semiconductor device according to the third embodiment will be described with reference to FIGS. 19A to 19L.

[0068] An example of a method for forming the substrate 401, drift layer 402, channel layer 403, and contact layer 404 will be described with reference to FIG. 19A. The substrate 401, drift layer 402, channel layer 403, and contact layer 404 can be formed by a crystal growth method such as MOCVD or MBE. At this time, Si, which is an impurity, is added at a flow rate according to the composition of the nitride semiconductor to be grown, thereby forming a gallium nitride to which Si is added. For example, when the MOCVD method is used to grow a gallium nitride to which Si is added, a mixed gas of TMG gas and NH3 gas is used. At this time, the flow rate of the TMG gas is appropriately determined according to the composition of the nitride semiconductor to be grown. The flow rate of the NH3 gas is, for example, 100 [ccm] to 10 [LM]. In addition, for example, the growth pressure is 50 [Torr] to 300 [Torr], and the growth temperature is 1000 [℃] to 2000 [℃].

[0069] An example of a method for removing unnecessary regions of the channel layer 403 and the contact layer 404 will be described with reference to FIGS. 19B to 19G. First, a photoresist 410a and a photoresist 410b are formed on the contact layer 404 (FIG. 19B). Then, an opening of 0.3 [um] is formed in the photoresist 410b (FIG. 19C), and a photoresist 410c is formed (FIG. 19D). Next, the photoresist 410b is removed together with the photoresist 410c formed on the photoresist 410b (FIG. 19E). Then, using the photoresist 410c as a mask, dry etching is performed using a chlorine-based gas, and the channel layer 403, the contact layer 404, and the photoresist 410a are removed down to the surface of the drift layer 402 (FIG. 19F). Then, the photoresist 410a and the photoresist 410c are removed (FIG. 19G).

[0070] Next, an example of a method for forming the source electrode 405, the drain electrode 406, the insulating layer 407, and the gate electrode 409 will be described with reference to FIGS. 19H to 19K. First, a Ti layer and an Al layer are selectively laminated on the region on the contact layer 404 by vapor deposition to form the source electrode 405 (FIG. 19H). Next, a Ti layer and an Al layer are laminated on the back surface of the substrate 401 by vapor deposition to form the drain electrode 406 (FIG. 19I). Next, silicon nitride is deposited on the surfaces of the drift layer 402 and the channel layer 403 by ALD to form the insulating layer 407 (FIG. 19J). After that, Ni is deposited on the insulating layer 407 by vapor deposition to form the gate electrode 409 (FIG. 19K).

[0071] An example of a method for forming the nickel silicide layer 408 will be described with reference to FIG. 19L. The gate electrode 409 and the insulating layer 407 of the semiconductor element 400 are heated to 700° C. to form the nickel silicide layer 408. At this time, the heat treatment is performed for 1 hour to 100 hours, and then cooled to 50° C. by natural air cooling or the like. In this manner, the semiconductor element 400 as shown in FIG. 19L is formed. Also, for example, the forming conditions of the nickel silicide layer 408 are appropriately determined so that the nickel silicide layer 408 is formed not in a part of the insulating layer 407 but in the entire insulating layer 407.

[0072] [Alternative form] Another embodiment of the semiconductor device according to the third embodiment will be described with reference to FIG.

[0073] As shown in FIG. 20, the semiconductor element 400 may have a diamond layer 412 formed on the surface of the source electrode 405 and the gate electrode 409. The diamond layer 412 is, for example, a layer containing diamond. The diamond layer 412 may be formed, for example, by the infiltration method and the HF-CVD method, similarly to the diamond layer 212 shown in FIG. 8 of the first embodiment. For example, after the insulating layer 407 and the gate electrode 409 are formed (that is, after the step shown in FIG. 19K), the diamond layer 412 may be formed, and the nickel silicide layer 408 may be formed by utilizing the heat treatment during the formation of the diamond layer 412.

[0074] When the diamond layer 412 is formed on the semiconductor element 400, the nickel silicide layer 408 can prevent Ni of the gate electrode 409 from diffusing into the channel layer 403. Therefore, the diamond layer 412 can be formed on the semiconductor element 400. For example, the diamond layer 412 can improve the heat dissipation efficiency of the semiconductor element 400. In addition, for example, when the semiconductor element 400 or a device formed by combining other electronic components is operated in a nuclear reactor or outer space, it is considered that the semiconductor element 400, especially the vicinity of the gate electrode 409, becomes hot. Even in such a case, the semiconductor element 400 can suppress the increase in gate leakage current when exposed to a high-temperature environment.

[0075] Although the method of forming the nickel silicide layer 408 has been described with reference to FIG. 19L, the method of forming the nickel silicide layer 408 is not limited thereto. For example, as described with reference to FIG. 19A to FIG. 19K, the insulating layer 407 and the gate electrode 409 are formed on the side surface of the channel layer 403. Thereafter, as described with reference to FIG. 20, the diamond layer 412 is formed at a growth temperature of 500° C. or more. At this time, Ni is diffused from the gate electrode 409 to the insulating layer 407 by the heat treatment when the diamond layer 412 is formed, and the nickel silicide layer 408 can be formed.

[0076] Although not shown, for example, the nickel silicide layer 408 of the semiconductor element 400 may be formed directly on the side surface of the channel layer 403 by using a sputtering method or the like. In this case, for example, the insulating layer 407 may not be formed.

[0077] The configuration of the semiconductor element 400 is not limited to the above-mentioned configuration. The source electrode 405 and the drain electrode 406 may be electrodes in which, for example, an Au layer, a Pt layer, or the like is laminated on a Ti layer. The source electrode 405 and the drain electrode 406 may be electrodes in which, for example, layers of different metal elements are laminated and then alloyed. The insulating layer 407 may be a layer containing, for example, silicon oxide. The insulating layer 407 may further be laminated with, for example, an aluminum oxide layer, a hafnium oxide layer, or the like. The gate electrode 409 may be an electrode in which, for example, a Pt layer, a Mo layer, a W layer, an Al layer, a Pb layer, a Ti layer, or the like is laminated on a Ni layer.

[0078] Although not shown, contact holes may be formed in order to wire the semiconductor element 400 on which the diamond layer 412 is formed to other semiconductor elements or electronic components. In this case, a part of the diamond layer 412 may not be formed in order to form the contact holes.

[0079] In addition to the explanation given using Examples 1 to 3, the techniques described using Examples 1 to 3 may be applied to, for example, a field effect transistor that employs Ni as the material for the gate electrode and a semiconductor compound as the material for the channel layer.

[0080] Example 4 An example of a device or apparatus using the semiconductor elements according to the first to third embodiments will be described.

[0081] 〔amplifier〕 FIG. 21 is a diagram showing an example of an amplifier using the semiconductor devices according to the first to third embodiments. The amplifier 500 includes, for example, a digital predistortion circuit 501, mixers 502a and 502b, and a power amplifier 503. The digital predistortion circuit 501 compensates for nonlinear distortion of an input signal. The mixer 502a mixes the input signal, the nonlinear distortion of which has been compensated for, with an AC signal. The power amplifier 503 includes, for example, a semiconductor device having a structure similar to that of any of the semiconductor devices according to the first to third embodiments, and amplifies the AC signal and the mixed input signal. In this embodiment, for example, a switch is turned to mix the output side signal with the AC signal in the mixer 502b, and the mixed signal is sent to the digital predistortion circuit 501. The amplifier 500 may be used as, for example, a high-frequency amplifier or a high-output amplifier. The high-frequency amplifier may be used, for example, in a transmitting / receiving device for a mobile phone base station, a radar device, and a microwave generator.

[0082] [Power supply device] 22 is a diagram showing an example of a power supply device using the semiconductor elements according to Examples 1 to 3. The power supply device 600 has, for example, a transformer 603 provided between a high-voltage primary side circuit 601 and a low-voltage secondary side circuit 602. The primary side circuit 601 has a power factor correction (PFC) circuit 604 and a full-bridge inverter circuit 605.

[0083] The PFC circuit 604 includes, for example, a switch element 606, a diode 607, a choke coil 608, a capacitor 609a, a capacitor 609b, and a diode bridge 610. The drain electrode of the switch element 606 is connected to the anode terminal of the diode 607 and one terminal of the choke coil 608. The source electrode of the switch element 606 is connected to one terminal of the capacitor 609a and one terminal of the capacitor 609b. The other terminal of the capacitor 609a is connected to the other terminal of the choke coil 608. The other terminal of the capacitor 609b is connected to the cathode terminal of the diode 607. A gate driver (not shown) is connected to the gate electrode of the switch element 606. An alternating current (AC) power supply 611 is connected between both terminals of the capacitor 609a via the diode bridge 610. A DC power supply (not shown) is connected between both terminals of the capacitor 609b.

[0084] The full-bridge inverter circuit 605 has, for example, four switch elements 612a, 612b, 612c, and 612d.

[0085] The secondary side circuit 602 includes, for example, three switch elements 613a, 613b, and 613c.

[0086] The power supply device 600 can use, for example, a semiconductor device having a structure similar to any of the semiconductor devices according to Examples 1 to 3 for the switch element 606 of the PFC circuit 604. Also, the power supply device 600 can use, for example, a semiconductor device having a structure similar to any of the semiconductor devices according to Examples 1 to 3 for the switch elements 612a, 612b, 612c, and 612d of the full-bridge inverter circuit 605.

[0087] Although preferred embodiments have been described above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0088] 100, 200, 300, 400 Semiconductor elements 101, 201, 301, 401 boards 102, 202, 302 Buffer layer 103, 203, 303 Electron transport layer 403 Channel Layer 104, 204, 304 2DEG 105, 205, 305 electron supply layer 106, 206, 306, 405 Source electrode 107, 207, 307, 406 Drain electrode 108, 208, 308, 409 Gate electrode 109, 209, 407 Insulating layer 210, 310, 408 Nickel silicide layer 212, 312, 412 Diamond Layer 500 Amplifier 600 power supply

Claims

1. An electron transport layer; an electron supply layer formed on the electron transit layer; A source electrode and a drain electrode; a gate electrode containing nickel formed on the electron supply layer; a nickel silicide layer formed between the electron supply layer and the gate electrode; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, further comprising a diamond layer on said electron supply layer.

3. 3. The semiconductor device according to claim 1, further comprising an insulating layer formed between the electron supply layer and the nickel silicide layer.

4. the electron transport layer contains either aluminum gallium nitride or gallium nitride, The electron supply layer contains any one of aluminum gallium nitride, indium aluminum gallium nitride, indium aluminum nitride, and aluminum nitride.

4. The semiconductor device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

5. forming an electron transport layer; forming an electron supply layer on the electron transit layer; forming a source electrode and a drain electrode; forming a gate electrode containing nickel on the electron transport layer; forming a nickel silicide layer between the electron supply layer and the gate electrode; 2. A method for manufacturing a semiconductor device comprising the steps of:

6. The method further includes a step of forming an insulating layer containing silicon on the electron supply layer, the step of forming the gate electrode is a step of forming the gate electrode on the insulating layer, The step of forming the nickel silicide layer is a step of converting at least a part of the insulating layer into the nickel silicide layer by heating the insulating layer and the gate electrode in a hydrogen atmosphere after the step of forming the insulating layer and the gate electrode.

6. The method for manufacturing a semiconductor device according to claim 5.

7. The method further includes a step of forming an insulating layer containing silicon on the electron supply layer, the step of forming the gate electrode is a step of forming the gate electrode on the insulating layer, The step of forming the nickel silicide layer is a step of converting at least a part of the insulating layer into the nickel silicide layer by heating the insulating layer and the gate electrode to form a diamond layer after the step of forming the insulating layer and the gate electrode.

6. The method for manufacturing a semiconductor device according to claim 5.

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