Stacked semiconductor package and method for manufacturing same

Abstract

To provide a stacked semiconductor package that can be made thinner.SOLUTION: A stacked semiconductor package has a first substrate, a three-dimensional device stacked in a first direction with respect to the first substrate, and a first connecting member connecting the first substrate and the three-dimensional device, the three-dimensional device has a plurality of components including semiconductor integrated circuit components and passive components stacked in the first direction, a first major surface of the first substrate facing the three-dimensional device and a first major surface of the three-dimensional device facing the first substrate are connected via the first connecting member in a separated state, and a first major surface of the semiconductor integrated circuit component facing the passive component and a first major surface of the passive component facing the semiconductor integrated circuit component each include a flat surface, and the flat surface of the semiconductor integrated circuit component and the flat surface of the passive component are joined, in contact.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a stacked semiconductor package and a manufacturing method thereof. [Background technology]

[0002] In recent years, the miniaturization and high performance of stacked semiconductor packages have led to greater integration of electronic circuits. A conventional stacked semiconductor package is described in Japanese Patent No. 5448393 (Patent Document 1). This stacked semiconductor package has a first semiconductor package, a second semiconductor package stacked on the first semiconductor package, and a capacitor provided between the first semiconductor package and the second semiconductor package and connected to the first semiconductor package and the second semiconductor package. In this way, the footprint (area of ​​circuits and components) is reduced by stacking the first semiconductor package, the second semiconductor package, and the capacitor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5448393 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional stacked semiconductor package, the first semiconductor package, the second semiconductor package, and the capacitor are connected using solder balls or solder paste, which increases the overall thickness of the stacked semiconductor package, making it difficult to achieve a thin structure.

[0005] Therefore, an object of the present disclosure is to provide a stacked semiconductor package that can be made thinner, and a manufacturing method thereof. [Means for solving the problem]

[0006] In order to solve the above problems, a stacked semiconductor package according to one aspect of the present disclosure comprises: A first substrate; a three-dimensional device stacked in a first direction on the first substrate; a first connection member that connects the first substrate and the three-dimensional device; Equipped with the three-dimensional device has a plurality of components including semiconductor integrated circuit components and passive components stacked in the first direction; a first main surface of the first substrate facing the three-dimensional device and a first main surface of the three-dimensional device facing the first substrate are connected to each other via the first connection member in a spaced-apart state; A first main surface of the semiconductor integrated circuit component facing the passive component and a first main surface of the passive component facing the semiconductor integrated circuit component each include a flat surface, and the flat surface of the semiconductor integrated circuit component and the flat surface of the passive component are joined in a contacting state.

[0007] According to this aspect, the flat surface of the semiconductor integrated circuit component and the flat surface of the passive component are joined in a contacting state, so that the thickness of the three-dimensional device can be reduced, and the thickness of the stacked semiconductor package can be reduced.

[0008] Preferably, in one embodiment of the method for manufacturing a stacked semiconductor package, bonding a semiconductor integrated circuit component having a flat surface and a passive component having a flat surface with the flat surfaces in contact with each other to form a three-dimensional device; connecting a first main surface of the three-dimensional device and a first main surface of a first substrate via a connecting member while being spaced apart from each other; Equipped with.

[0009] According to the embodiment, the flat surface of the semiconductor integrated circuit component and the flat surface of the passive component are joined in a contacting state, so that the thickness of the three-dimensional device can be reduced, and the thickness of the stacked semiconductor package can be reduced. Effect of the Invention

[0010] According to the stacked semiconductor package and the manufacturing method thereof according to one aspect of the present disclosure, a thinner structure can be achieved. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic cross-sectional view showing a first embodiment of a stacked semiconductor package. [Figure 2A] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of the stacked semiconductor package. [Figure 2B] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of the stacked semiconductor package. [Figure 2C] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of the stacked semiconductor package. [Figure 2D] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of the stacked semiconductor package. [Figure 2E] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of the stacked semiconductor package. [Figure 2F] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of the stacked semiconductor package. [Figure 2G] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of the stacked semiconductor package. [Figure 3A] 11A to 11C are schematic cross-sectional views illustrating a modified example of the method for manufacturing a stacked semiconductor package. [Figure 3B] 11A to 11C are schematic cross-sectional views illustrating a modified example of the method for manufacturing a stacked semiconductor package. [Figure 3C] 11A to 11C are schematic cross-sectional views illustrating a modified example of the method for manufacturing a stacked semiconductor package. [Figure 4] 2 is a schematic bottom view of the inductor component 3 as viewed from the bottom side. [Diagram 5] FIG. 5 is a cross-sectional view of FIG. 4 . [Figure 6] 6 is a cross-sectional view taken along line VI-VI of FIG. 4. [Figure 7A] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an inductor component. [Figure 7B] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an inductor component. [Figure 7C] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an inductor component. [Figure 7D] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an inductor component. [Figure 7E] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an inductor component. [Figure 7F] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an inductor component. [Figure 7G] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an inductor component. [Figure 7H] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an inductor component. [Figure 7I] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an inductor component. [Figure 7J] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an inductor component. [Figure 7K] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an inductor component. [Figure 8] FIG. 11 is a simplified cross-sectional view showing a first modified example of a stacked semiconductor package. [Figure 9] FIG. 11 is a simplified cross-sectional view showing a second modified example of the stacked semiconductor package. [Figure 10A] FIG. 4 is a simplified cross-sectional view showing a second embodiment of a stacked semiconductor package. [Figure 10B] FIG. 11 is a simplified plan view showing a second embodiment of a stacked semiconductor package. [Figure 11] 11 is a simplified cross-sectional view showing a modified example of a stacked semiconductor package. [Figure 12] FIG. 11 is a simplified cross-sectional view showing a third embodiment of a stacked semiconductor package. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, a stacked semiconductor package and a manufacturing method thereof according to one aspect of the present disclosure will be described in detail with reference to the illustrated embodiments. Note that the drawings include schematic views and may not reflect actual dimensions or proportions.

[0013] First Embodiment 1.Schematic configuration (Configuration of stacked semiconductor package 1) Fig. 1 is a simplified cross-sectional view showing a first embodiment of a stacked semiconductor package. As shown in Fig. 1, the stacked semiconductor package 1 includes a first substrate 210 and a three-dimensional device 300 stacked in a first direction D1 on the first substrate 210. The first direction D1 is the upward direction in the figure.

[0014] The first substrate 210 is, for example, an inorganic substrate made of Si or SiO2 (so-called a silicon interposer substrate or a glass interposer substrate), or an organic substrate made of FR4 (Flame Retardant Type 4), epoxy, polyimide, or the like (so-called an organic package substrate). Wiring is provided inside or on the main surface of the first substrate 210, and is electrically connected to the three-dimensional device 300. The main surface of the first substrate 210 may be provided with conductive members such as external terminals, conductive bumps, conductive pillars, and solder. A similar conductive member may also be provided on the main surface of the three-dimensional device 300 that faces the first substrate 210.

[0015] The three-dimensional device 300 has a semiconductor integrated circuit component 310 and a passive component 320 stacked on top of each other in a first direction D1. The semiconductor integrated circuit component 310 is, for example, an electronic component such as an integrated circuit (IC), a central processing unit (CPU), a power management IC (PMIC), a memory, or a transistor. The passive component 320 is an electronic component such as a resistor, a capacitor, or an inductor, and does not include an active element such as a transistor. The passive element of the passive component 320 is a resistor element, a capacitor element, an inductor element, or the like. In other words, the passive component includes an element body, an internal wiring, or the like, and the passive element represents, for example, a coil or the like in the passive component, and does not include an element body or the like. The semiconductor integrated circuit component 310 and the passive component 320 may be stacked in any order in the first direction D1.

[0016] The first main surface 211 of the first substrate 210 facing the three-dimensional device 300 and the first main surface 301 of the three-dimensional device 300 facing the first substrate 210 are connected in a separated state via a first connection member 5. The first connection member 5 is, for example, solder, a conductive bump, a conductive pillar, or the like. There are multiple first connection members 5, and it is sufficient that at least some of the multiple first connection members 5 are conductive, and some of the multiple first connection members 5 may be insulating.

[0017] A first main surface 311 of the semiconductor integrated circuit component 310 facing the passive component 320 includes a flat surface 311a. A first main surface 321 of the passive component 320 facing the semiconductor integrated circuit includes a flat surface 321a. The flat surfaces 311a, 321a are each a flat surface. The flat surface 311a of the semiconductor integrated circuit component 310 and the flat surface 321a of the passive component 320 are joined in a contacting state.

[0018] According to the above configuration, the flat surface 311a of the semiconductor integrated circuit component 310 and the flat surface 321a of the passive component 320 are bonded in a contacting state, so that the thickness of the three-dimensional device 300 can be reduced, and the thickness of the stacked semiconductor package 1 can be reduced. Furthermore, since the passive component 320 is provided, noise removal and power supply control can be performed more easily.

[0019] In this specification, "flatness of flat surface 311a of semiconductor integrated circuit component 310" refers to a state in which the surface roughness of flat surface 311a is either 1 / 1000 or less of the thickness of semiconductor integrated circuit component 310 or 10 nm or less, and "flatness of flat surface 321a of passive component 320" refers to a state in which the surface roughness of flat surface 321a is either 1 / 1000 or less of the thickness of passive component 320 or 10 nm or less. The thickness of each component refers to the size of each component in the first direction D1.

[0020] The "surface roughness" is Sa (arithmetic mean height). Flatness refers to a state in which Sa is 0.2 nm, for example. An atomic force microscope (AFM: Atomic Force Microscope) is used to measure Sa. The surface roughness is the average value of Sa at five points on the surface of the component. When the flat surfaces 311a, 321a can be separated from each other, this method can be used, but when the flat surfaces 311a, 321a cannot be separated, the surface roughness may be calculated from the cross section of the three-dimensional device. Specifically, the cross section of the joint portion of the flat surfaces 311a, 321a is exposed by a known method such as ion milling, and an image of the joint portion is obtained by a transmission electron microscope (TEM: Transmission Electron Microscope) or the like. At this time, the magnification is preferably 300K or more. The interface between the flat surfaces 311a, 321a can be recognized from the difference in grain boundaries, etc. Using the obtained image, a straight line (a line drawn by the least squares method) is drawn at a position corresponding to the interface. The surface roughness can be calculated by measuring the arithmetic mean roughness (Ra) of this straight line.

[0021] In addition, "bonding of the flat surfaces 311a and 321a" refers to room temperature direct bonding by atomic diffusion or ionic bonding, hybrid bonding by applying heat, etc. In addition, "bonding" may refer to a chemical bonding state such as covalent bonding, ionic bonding, or metallic bonding, or may refer to a bonding state based on mechanical strength. For example, a method of measuring the bonding strength is to bond the flat surface of a passive component to the flat surface of a semiconductor integrated circuit component, fix the semiconductor integrated circuit component and the passive component, and apply a vertical force to the bonded flat surface, for example, with a bond tester, to measure the bonding strength. Alternatively, a pressing tool may be placed above the bonded flat surface, and the bonding strength may be measured by pressing sideways. The bonding strength is considered to be in close contact if it is 1N or more. If it is 1N or more, it will not peel off due to vibration or handling, for example, pressing sideways with tweezers. In addition, the bonding strength may be determined by a destruction mode instead of the fixing force. If destruction occurs other than the bonded flat surface, commonly known as bulk destruction, the bonding strength is said to be strong enough.

[0022] Moreover, "the first main surface 211 of the first substrate 210 and the first main surface 301 of the three-dimensional device 300 are separated" means that the first main surface 211 of the first substrate 210 and the first main surface 301 of the three-dimensional device 300 are separated in a parallel state. "Parallel" includes parallelism within the range of general manufacturing variations. Specifically, the angle between the first main surface 211 of the first substrate 210 and the first main surface 301 of the three-dimensional device 300 is 10° or less. Furthermore, when both the first main surface 211 of the first substrate 210 and the first main surface 301 of the three-dimensional device 300 are warped, the distance between the first main surface 211 and the first main surface 301 (corresponding to the second distance L2 in FIG. 1) is obtained using a surface obtained by the least squares method. The second distance L2 represents the average distance between the first main surface 211 of the first substrate 210 and the first main surface 301 of the three-dimensional device 300 in a specific cross section obtained by performing cross-section polishing or the like on the stacked semiconductor package 1. The distance between the first main surface 211 and the first main surface 301 is, for example, 20 μm. Note that an underfill, a mold resin material, or the like may be filled between the first main surface 211 and the first main surface 301.

[0023] (Method of Manufacturing Stacked Semiconductor Package 1) Next, a method for manufacturing the stacked semiconductor package 1 will be described.

[0024] 1, the first main surface 311 of the semiconductor integrated circuit component 310 is polished to provide a flat surface 311a. Also, the first main surface 321 of the passive component 320 is polished to provide a flat surface 321a. Thereafter, the flat surface 311a of the semiconductor integrated circuit component 310 and the flat surface 321a of the passive component 320 are bonded in a contacting state to form the three-dimensional device 300. Thereafter, the first main surface 301 of the three-dimensional device 300 and the first main surface 211 of the first substrate 210 are connected via the first connecting member 5 in a spaced-apart state.

[0025] According to this, the flat surface 311a of the semiconductor integrated circuit component 310 and the flat surface 321a of the passive component 320 are joined in a contacting state, so that the thickness of the three-dimensional device 300 can be reduced, and the stacked semiconductor package 1 can be made thinner.

[0026] Alternatively, a semiconductor substrate including a plurality of semiconductor integrated circuit components and a passive substrate including a plurality of passive components may be prepared, the semiconductor substrate and the passive substrate may be bonded together, and then each set of the semiconductor integrated circuit components and the passive substrate may be singulated to form a plurality of stacked semiconductor packages. Alternatively, one of the semiconductor substrate and the passive substrate may be singulated into individual components, the singulated components may be bonded to the other of the semiconductor substrate and the passive substrate, and then the other substrate may be singulated into individual components to form a plurality of stacked semiconductor packages.

[0027] 2. Preferred form (Configuration of stacked semiconductor package 1) 1, the first substrate 210 has a first main surface 211 and a second main surface 212 opposite the first main surface 211. The three-dimensional device 300 has a second main surface 302 opposite the first main surface 301. The semiconductor integrated circuit component 310 has a second main surface 312 opposite the first main surface 311. The passive component 320 has a second main surface 322 opposite the first main surface 321.

[0028] A first main surface 301 of the three-dimensional device 300 coincides with a second main surface 312 of the semiconductor integrated circuit component 310. A second main surface 302 of the three-dimensional device 300 coincides with a second main surface 322 of the passive component 320. The passive component 320 is stacked relative to the semiconductor integrated circuit component 310 in a first direction D1.

[0029] The semiconductor integrated circuit component 310 and the passive component 320 are electrically connected via the flat surfaces 311a, 321a. This allows the flat surfaces 311a, 321a to simultaneously satisfy mechanical and electrical connections. Note that the semiconductor integrated circuit component 310 and the passive component 320 do not need to be electrically connected, which improves the degree of freedom in circuit design.

[0030] Preferably, the area of ​​the flat surface 311a of the semiconductor integrated circuit component 310 is larger than half the area of ​​the first main surface 311 of the semiconductor integrated circuit component 310, and the area of ​​the flat surface 321a of the passive component 320 is larger than half the area of ​​the first main surface 321 of the passive component 320. In this way, by increasing the area of ​​the flat surface, unnecessary irregularities can be reduced, and the thickness of the three-dimensional device 300 can be made thinner.

[0031] At least a part of the first main surface 311 may be the flat surface 311a. However, if the area of ​​the flat surface 311a is small, the adhesive force between the components 310 and 320 decreases, so it is preferable that more than half of the area of ​​the first main surface 311 is the flat surface 311a. Similarly, it is preferable that at least a part of the first main surface 321 is the flat surface 321a, and it is preferable that more than half of the area of ​​the first main surface 321 is the flat surface 321a.

[0032] The positions of the opposing flat surfaces 311a, 321a may be misaligned to an extent permitted in a typical manufacturing process. For example, when wiring exposed on each flat surface is to be brought into contact with each other, the misalignment of the flat surfaces 311a, 321a until the contact area of ​​the wiring when there is no misalignment between the flat surfaces 311a, 321a is reduced to 50% of the reference contact area is within the range permitted in the manufacturing process.

[0033] Preferably, the flat surface 311a of the semiconductor integrated circuit component 310 and the flat surface 321a of the passive component 320 are each made of an inorganic material. Examples of the inorganic material include Cu, Al, Au, Ti, Ta, Si, Ge, GaN, GaP, GaAs, InP, SiN, TiN, and SiO2. This makes it easier to flatten the flat surfaces 311a and 321a compared to when the flat surfaces 311a and 321a are made of an organic material. In addition, the hardness of each of the flat surfaces 311a and 321a is high, and the strength of the three-dimensional device 300 can be increased.

[0034] The inorganic materials of the flat surfaces 311a and 321a may be the same or different. The inorganic materials of parts of the same flat surfaces 311a and 321a may be different from the inorganic materials of other parts of the same flat surfaces 311a and 321a. For example, in the flat surface 321a of the passive component 320, a part of the flat surface 321a may be composed of a surface of the lead wiring of the passive element, and the other part of the flat surface 321a may be composed of a surface of an insulating layer containing Si.

[0035] It is sufficient that at least the flat surface 311a of the semiconductor integrated circuit component 310 is made of an inorganic material, and the other parts of the semiconductor integrated circuit component 310 may be made of an organic material. Similarly, it is sufficient that at least the flat surface 321a of the passive component 320 is made of an inorganic material, and the other parts of the passive component 320 may be made of an organic material.

[0036] 1, the stacked semiconductor package 1 further includes a second substrate 220. The first substrate 210 is stacked on the second substrate 220 in a first direction D1. A second main surface 212 of the first substrate 210 facing the second substrate 220 and a first main surface 221 of the second substrate 220 facing the first substrate 210 are spaced apart from each other and connected via a second connecting member 6. The second connecting member 6 is made of the same material as the first connecting member 5.

[0037] A first distance L1 between the second main surface 212 of the first substrate 210 and the first main surface 221 of the second substrate 220 is greater than a second distance L2 between the first main surface 211 of the first substrate 210 and the first main surface 301 of the three-dimensional device 300. This allows the circuit system to be enlarged, improving the degree of freedom in circuit design.

[0038] "The second main surface 212 of the first substrate 210 and the first main surface 221 of the second substrate 220 are separated" means that the second main surface 212 of the first substrate 210 and the first main surface 221 of the second substrate 220 are separated in a parallel state. "Parallel" includes parallelism within the range of general manufacturing variations. Specifically, the angle between the second main surface 212 of the first substrate 210 and the first main surface 221 of the second substrate 220 is 10° or less. In addition, when both the second main surface 212 of the first substrate 210 and the first main surface 221 of the second substrate 220 are warped, the first distance L1 between the second main surface 212 and the first main surface 221 is calculated using a surface calculated by the least squares method. The first distance L1 represents an average distance between the second main surface 212 of the first substrate 210 and the first main surface 221 of the second substrate 220 in a specific cross section obtained by performing cross-section polishing or the like on the stacked semiconductor package 1. The first distance L1 is, for example, 300 μm. Note that an underfill, a mold resin material, or the like may be filled between the second main surface 212 and the first main surface 221.

[0039] The second substrate 220 has a lower (rougher) design accuracy than the first substrate 210. In other words, the second connection member 6 provided on the second substrate 220 is larger than the first connection member 5 provided on the first substrate 210. Therefore, the height of the second connection member 6 connected between the second substrate 220 and the first substrate 210 is higher than the height of the first connection member 5 connected between the first substrate 210 and the three-dimensional device 300. That is, the first distance L1 is larger than the second distance L2. In this way, the difference in design accuracy between the first substrate 210 and the second substrate 220 is related to the difference in size of the connection members 5, 6, that is, the difference in size between the first distance L1 and the second distance L2. When the design accuracy is fine, the distance becomes smaller, and when the design accuracy is coarse, the distance becomes larger.

[0040] (Method of Manufacturing Stacked Semiconductor Package 1) Next, a method for manufacturing the stacked semiconductor package 1 will be described with reference to Figures 2A to 2G. For convenience, the aspect ratio of the three-dimensional device is changed in Figures 2A to 2E compared to Figures 2F and 2G. For convenience, the number of wirings 3316 is changed in Figures 2A to 2E compared to Figure 2F.

[0041] As shown in FIG. 2A, a semiconductor substrate 3310 including a plurality of semiconductor integrated circuit components and a passive substrate 3320 including a plurality of passive components are prepared. The semiconductor substrate 3310 includes a device layer consisting of a semiconductor element region, that is, an active layer 3315, and a plurality of wirings 3316 for extracting signals from the active layer 3315 and supplying power. The wirings 3316 may be wirings extending in the substrate thickness direction by a known method such as TSV (through Si Via) as shown in FIG. 2A, or may be laminated on the semiconductor substrate surface as BEOL (back-end-of-line) wiring. The passive substrate 3320 includes a plurality of passive elements 3325. In FIG. 2A, the passive elements 3325 are inductor elements. The semiconductor substrate 3310 includes a first main surface 3311 and a second main surface 3312 located opposite to each other. The passive substrate 3320 includes a first main surface 3321 and a second main surface 3322 located opposite to each other. A flat surface 3311a is provided by polishing a first main surface 3311 of the semiconductor substrate 3310. A flat surface 3321a is provided by polishing a first main surface 3321 of the passive substrate 3320. In this example, CMP (Chemical Mechanical Polisher) polishing is used.

[0042] As shown in FIG. 2B, the flat surface 3311a of the semiconductor substrate 3310 and the flat surface 3321a of the passive substrate 3320 are bonded in contact with each other to form a laminate 3330. As shown in FIG. 2C, a tape 3340 is attached to the second main surface 3322 of the passive substrate 3320 and fixed to a base (not shown), and the second main surface 3312 (see FIG. 2B) side of the semiconductor substrate 3310 is polished to form a new second main surface 3312A. An external terminal (not shown) connected to the wiring 3316 is formed on the second main surface 3312A of the semiconductor substrate 3310. Thereafter, the tape 3340 on the second main surface 3322 of the passive substrate 3320 is peeled off.

[0043] 2D, tape 3340 is attached to the second main surface 3312A of the semiconductor substrate 3310 and fixed to a base (not shown), and the second main surface 3322 (see FIG. 2C) side of the passive substrate 3320 is ground to form a new second main surface 3322A. Then, tape 3340 is peeled off from the second main surface 3312A of the semiconductor substrate 3310.

[0044] As shown in FIG. 2E, the laminate 3330 is diced along cut lines C into individual pairs of semiconductor integrated circuit components 310 and passive components 320 to form a plurality of three-dimensional devices 300 each composed of a pair of semiconductor integrated circuit components 310 and passive components 320.

[0045] As shown in FIG. 2F, the first substrate 210 is prepared, and the first connecting member 5 is provided on the first main surface 211 of the first substrate 210. Then, as shown in FIG. 2G, the first main surface 301 of the three-dimensional device 300 and the first main surface 211 of the first substrate 210 are connected via the first connecting member 5 while being spaced apart from each other. The first main surface 301 of the three-dimensional device 300 corresponds to the second main surface 3312A of the semiconductor substrate 3310, and the second main surface 302 of the three-dimensional device 300 corresponds to the second main surface 3322A of the passive substrate 3320. The wiring 3316 of the semiconductor integrated circuit component 310 is connected to the first connecting member 5.

[0046] 1, a second substrate 220 is prepared, a connection member 6 is provided on a first main surface 221 of the second substrate 220, and the second main surface 212 of the first substrate 210 and the first main surface 221 of the second substrate 220 are connected to each other via the connection member 6 while being spaced apart from each other. In this way, a stacked semiconductor package 1 is manufactured.

[0047] (Modification of the Manufacturing Method of the Stacked Semiconductor Package 1) Next, a modified example of the manufacturing method of the stacked semiconductor package 1 will be described with reference to Figures 3A to 3C. For convenience, the aspect ratio of the three-dimensional device is changed in Figures 3A and 3B compared to Figure 3C.

[0048] As shown in FIG. 3A, a semiconductor substrate 3310 including a plurality of semiconductor integrated circuit components and a plurality of passive substrates 3320 including passive components are prepared. The semiconductor substrate 3310 includes an active layer and a plurality of wirings as described above. The passive substrate 3320 includes a passive element 3325. The semiconductor substrate 3310 includes a first main surface 3311 and a second main surface 3312 located on opposite sides to each other. The passive substrate 3320 includes a first main surface 3321 and a second main surface 3322 located on opposite sides to each other. The first main surface 3311 of the semiconductor substrate 3310 is polished to provide a flat surface 3311a. The first main surface 3321 of the passive substrate 3320 is polished to provide a flat surface 3321a. Thereafter, the flat surface 3311a of the semiconductor substrate 3310 and the flat surface 3321a of the passive substrate 3320 are bonded in a contacted state to form a laminate 3330.

[0049] Thereafter, the second main surface 3322 side of the passive substrate 3320 is ground to form a new second main surface 3322A of the passive substrate 3320 as shown in FIG. 3B. Thereafter, the laminate 3330 is divided into individual sets of semiconductor integrated circuit components 310 and passive components 320 along cut lines C to form a plurality of three-dimensional devices 300 each consisting of a set of semiconductor integrated circuit components 310 and passive components 320. As shown in FIG. 3C, the first main surface 301 of the three-dimensional device 300 corresponds to the second main surface 3312 of the semiconductor substrate 3310, and the second main surface 302 of the three-dimensional device 300 corresponds to the second main surface 3322A of the passive substrate 3320.

[0050] 1, the first main surface 301 of the three-dimensional device 300 and the first main surface 211 of the first substrate 210 are connected to each other via a first connecting member 5 while being spaced apart. Then, the second main surface 212 of the first substrate 210 and the first main surface 221 of the second substrate 220 are connected to each other via a connecting member 6 while being spaced apart. In this way, the stacked semiconductor package 1 is manufactured.

[0051] 3. Preferred form of passive components (Schematic configuration of inductor component 3) The passive component 320 is preferably an inductor component 3. FIG. 4 is a schematic bottom view of the inductor component 3 as viewed from the bottom side. FIG. 5 is a VV cross-sectional view of FIG. 4. FIG. 6 is a VI-VI cross-sectional view of FIG. 4. For convenience, the element body 10 is drawn transparent in FIG. 4 so that the structure can be easily understood, but it may be semi-transparent or opaque. Also, in FIG. 4, the insulator and inorganic layers are omitted.

[0052] The inductor component 3 is a surface-mount type inductor component used in, for example, a high-frequency signal transmission circuit. As shown in Figures 4, 5, and 6, the inductor component 3 includes an element body 10, a coil 110 provided on the element body 10 and wound in a spiral shape along an axis AX, an inorganic layer 21 provided on a first main surface (bottom surface 100b) of the element body 10, and an insulator 22 provided on a second main surface (top surface 100t) of the element body 10. The bottom surface 21a of the inorganic layer 21 corresponds to a flat surface 321a of a first main surface 321 of a passive component 320.

[0053] The element body 10 has a length, a width, and a height. The element body 10 has a first end face 100e1 and a second end face 100e2 at both ends in the length direction, a first side face 100s1 and a second side face 100s2 at both ends in the width direction, and a bottom face 100b and a top face 100t at both ends in the height direction. In other words, the outer surface 100 of the element body 10 includes the first end face 100e1 and the second end face 100e2, the first side face 100s1 and the second side face 100s2, the bottom face 100b, and the top face 100t.

[0054] As shown in the drawings, for the sake of convenience, the length direction (longitudinal direction) of element body 10, which is the direction from first end face 100e1 to second end face 100e2, is defined as the X direction. The width direction of element body 10, which is the direction from first side face 100s1 to second side face 100s2, is defined as the Y direction. The height direction of element body 10, which is the direction from bottom face 100b to top face 100t, is defined as the Z direction. The X direction, Y direction, and Z direction are mutually orthogonal, and when arranged in the order of X, Y, Z, they form a right-handed system.

[0055] In this specification, the "outer surface 100 of the element body" including the first end surface 100e1, the second end surface 100e2, the first side surface 100s1, the second side surface 100s2, the bottom surface 100b, and the top surface 100t of the element body 10 does not simply mean a surface facing the outer periphery of the element body 10, but a surface that is a boundary between the outside and the inside of the element body 10. In addition, "above the outer surface 100 of the element body 10" does not mean an absolute direction such as vertically upward defined by the direction of gravity, but refers to a direction toward the outside of the outside and the inside with the outer surface 100 as a boundary, based on the outer surface 100. Therefore, "above the outer surface 100" is a relative direction determined by the orientation of the outer surface 100. In addition, "above" with respect to a certain element includes not only an upper side away from the element, that is, an upper position via another object on the element or an upper position with a space therebetween, but also a position directly above the element (on).

[0056] The axis AX of the coil 110 is arranged parallel to the bottom surface 100b. The coil 110 includes a plurality of first coil wirings (bottom surface wirings 11b) provided on the bottom surface 100b side with respect to the axis AX and arranged along the axis AX on a plane parallel to the bottom surface 100b, a plurality of second coil wirings (top surface wirings 11t) provided on the top surface 100t side with respect to the axis AX and arranged along the axis AX on a plane parallel to the top surface 100t, a plurality of first through wirings 13 extending from the bottom surface wiring 11b toward the top surface wiring 11t and arranged along the axis AX, and a plurality of second through wirings 14 extending from the bottom surface wiring 11b toward the top surface wiring 11t, provided on the opposite side of the first through wirings 13 with respect to the axis AX and arranged along the axis AX. The bottom surface wirings 11b, the first through wirings 13, the top surface wirings 11t, and the second through wirings 14 are connected in this order to form at least a part of a spiral shape.

[0057] The axis AX is an intersection line between a first plane passing through the center between the bottom wiring 11b and the top wiring 11t and a second plane passing through the center between the first through wiring 13 and the second through wiring 14. In other words, the axis AX is a straight line passing through the center of the inner diameter part of the coil 110. The axis AX of the coil 110 does not have a dimension in a direction perpendicular to the axis AX.

[0058] (Inductor component 3) The volume of the inductor component 3 is 0.08 mm 3 or less, and the size of the long side of the inductor component 3 is 0.65 mm or less. The size of the long side of the inductor component 3 refers to the largest value among the length, width, and height of the inductor component 3, and in this embodiment, refers to the length in the X direction. With the above configuration, the volume of the inductor component 3 is small and the long side of the inductor component 3 is short, so that the weight of the inductor component 3 is light. Therefore, even if the external electrodes 121 and 122 are small, the necessary mounting strength can be obtained. Furthermore, the thickness of the inductor component 3 is preferably 200 μm or less. This allows the inductor component 3 to be made thin.

[0059] Specifically, the size of the inductor component 3 (length (X direction) × width (Y direction) × height (Z direction)) is 0.6 mm × 0.3 mm × 0.3 mm, 0.4 mm × 0.2 mm × 0.2 mm, 0.25 mm × 0.125 mm × 0.120 mm, etc. Furthermore, the width and height do not have to be equal, and may be, for example, 0.4 mm × 0.2 mm × 0.3 mm.

[0060] (body 10) The element body 10 is made of insulating resin. For example, a photosensitive permanent film (permanent photoresist) or an insulating resin containing inorganic filler is used as the insulating resin. The photosensitive permanent film is a photoresist that is not removed after processing.

[0061] The element body 10 may be made of, for example, a sintered glass body or a glass substrate. The glass substrate may be a single-layer glass substrate, and since most of the element body is made of glass, losses such as eddy current losses at high frequencies can be suppressed.

[0062] (Coil 110) The coil 110 includes a plurality of bottom wirings 11b, a plurality of top wirings 11t, a plurality of first through wirings 13, and a plurality of second through wirings 14. The bottom wirings 11b, the first through wirings 13, the top wirings 11t, and the second through wirings 14 are connected in sequence to form at least a portion of the coil 110 wound in the axial direction AX.

[0063] According to the above configuration, the coil 110 is a so-called helical-shaped coil 110, so that in a cross section perpendicular to the axis AX, the area in which the bottom wiring 11b, the top wiring 11t, the first through wiring 13 and the second through wiring 14 run parallel to the winding direction of the coil 110 can be reduced, and the stray capacitance in the coil 110 can be reduced.

[0064] Here, a helical shape refers to a shape in which the number of turns in the entire coil is greater than 1, and the number of turns in the coil in a cross section perpendicular to the axis is less than 1. "One turn or more" refers to a state in which, in a cross section perpendicular to the axis, the coil wiring has parts that are adjacent in the radial direction when viewed from the axial direction and run parallel to the winding direction, and "less than 1 turn" refers to a state in which, in a cross section perpendicular to the axis, the coil wiring does not have parts that are adjacent in the radial direction when viewed from the axial direction and run parallel to the winding direction.

[0065] The bottom wiring 11b extends in the Y direction at a slight incline toward the X direction. The bottom wiring 11b is embedded in the element body 10 so as to be exposed from the bottom surface 100b. The multiple bottom wirings 11b are arranged in parallel along the X direction. When viewed from a direction perpendicular to the bottom surface 100b, the bottom wirings 11b at both ends in the axis AX direction are formed in a triangular shape, and the other bottom wirings 11b are formed in a linear shape.

[0066] The top surface wiring 11t extends in the Y direction. The top surface wiring 11t is provided on the top surface 100t. The multiple top surface wirings 11t are arranged in parallel along the X direction. When viewed from a direction perpendicular to the bottom surface 100b, the top surface wirings 11t at both ends in the axis AX direction are formed in a rectangular shape, and the other top surface wirings 11t are formed in a linear shape.

[0067] The bottom wiring 11b and the top wiring 11t are made of a good conductor material such as copper, silver, gold, or an alloy thereof. The bottom wiring 11b and the top wiring 11t may be a metal film formed by plating, vapor deposition, sputtering, or the like, or may be a metal sintered body formed by applying and sintering a conductive paste. The bottom wiring 11b and the top wiring 11t may also have a multilayer structure in which multiple metal layers are stacked. The thickness of the bottom wiring 11b and the top wiring 11t is preferably 5 μm or more and 50 μm or less.

[0068] The first through wiring 13 is disposed on the first side surface 100s1 side with respect to the axis AX in the through hole V of the element body 10, and the second through wiring 14 is disposed on the second side surface 100s2 side with respect to the axis AX in the through hole V of the element body 10. The first through wiring 13 and the second through wiring 14 extend in a direction perpendicular to the bottom surface 100b and the top surface 100t, respectively. This allows the lengths of the first through wiring 13 and the second through wiring 14 to be shortened, thereby suppressing the direct current resistance (Rdc). All the first through wiring 13 and all the second through wiring 14 are disposed in parallel along the X direction, respectively. The first through wiring 13 and the second through wiring 14 are made of the same material as the bottom surface wiring 11b and the top surface wiring 11t.

[0069] (Inorganic layer 21) The inorganic layer 21 is provided on the bottom surface 100b of the element body 10, and covers the exposed portion of the bottom surface wiring 11b from the bottom surface 100b. This protects the bottom surface wiring 11b from external forces, prevents damage to the bottom surface wiring 11b, and improves the insulation of the bottom surface wiring 11b. The inorganic layer 21 is made of an inorganic material. Examples of the inorganic material include Cu, Al, Au, Ti, Ta, Si, Ge, GaN, GaP, GaAs, InP, SiN, TiN, and SiO2. The bottom surface 21a of the inorganic layer 21 corresponds to the flat surface 321a of the first main surface 321 of the passive component 320.

[0070] (Insulator 22) The insulator 22 is provided on the top surface 100t of the element body 10 and covers the top surface wiring 11t. This protects the top surface wiring 11t from external forces, prevents damage to the top surface wiring 11t, and improves the insulation of the top surface wiring 11t. The insulator 22 is preferably an organic insulator. For example, the insulator 22 may be a resin film such as an epoxy-based or polyimide-based resin that is easy to form.

[0071] (first via wiring 121v and second via wiring 122v) The inductor component 3 further includes a first via wiring 121v and a second via wiring 122v. The first via wiring 121v is connected to a first end of the coil 110, and the second via wiring 122v is connected to a second end of the coil 110.

[0072] The first via wiring 121v is provided on the first end face 100e1 side with respect to the center of the element body 10 in the X direction. The second via wiring 122v is provided on the second end face 100e2 side with respect to the center of the element body 10 in the X direction.

[0073] The first via wiring 121v is embedded in the inorganic layer 21 and exposed from the bottom surface 21a of the inorganic layer 21. The first via wiring 121v is connected to an end of the bottom surface wiring 11b located on the first end surface 100e1 side in the axis AX direction.

[0074] The second via wiring 122v is embedded in the inorganic layer 21 and exposed from the bottom surface 21a of the inorganic layer 21. The second via wiring 122v is connected to an end of the bottom surface wiring 11b located on the second end surface 100e2 side in the axis AX direction.

[0075] (Manufacturing Method of Inductor Component 3) Next, a manufacturing method of inductor component 3 will be described with reference to Figures 7A to 7K. Figures 7A, 7B, 7C, 7J, and 7K are views corresponding to the VI-VI cross section of Figure 4. Figures 7D to 7I are views corresponding to the VV cross section of Figure 4.

[0076] 7A, an inorganic substrate 1021 corresponding to the inorganic layer 21 is prepared. The inorganic substrate 1021 is, for example, a Si substrate. A first resist layer 1001 is applied to the upper surface of the inorganic substrate 1021, and openings 1001a of a predetermined pattern are formed in the first resist layer 1001 by a photolithography process.

[0077] As shown in Fig. 7B, the inorganic substrate 1021 is etched through the opening 1001a to form the groove 1021a. The etching may be either dry etching or wet etching. In this embodiment, since a Si substrate is used as the inorganic substrate 1021, plasma etching using a fluorine-based gas is used.

[0078] After that, the first resist layer 1001 is peeled off, and as shown in Figures 7C and 7D, a seed layer (not shown) is formed on the upper surface of the inorganic substrate 1021, a second resist layer 1002 is applied on the upper surface of the seed layer, and an opening 1002a of a predetermined pattern is formed in the second resist layer 1002 by a photolithography process. Then, a bottom conductor layer 1011b corresponding to the bottom wiring 11b is provided in the opening 1002a by electrolytic plating, and a first via conductor layer 1121v corresponding to the first via wiring 121v is provided in the groove 1021a. Also, although not shown, a second via conductor layer corresponding to the second via wiring 122v is provided in the same manner as the first via conductor layer 1121v.

[0079] In this embodiment, a semi-additive method is used as a method for forming the bottom conductor layer and the via conductor layer, but a subtractive method, a full additive method, a conductive paste printing method, or other known methods may be used. In this embodiment, Ti / Cu is used for the seed layer, but W, TiW, Ag, or other seed species and combinations thereof may be selected as necessary.

[0080] Thereafter, the second resist layer 1002 is peeled off, the seed layer is etched, and an insulating resin layer 1010 corresponding to the element body 10 is provided on the upper surface of the inorganic substrate 1021 as shown in FIG. 7E. A predetermined pattern of openings 1010a is formed in the insulating resin layer 1010 by a photolithography process, a part of the bottom conductor layer 1011b is exposed from the openings 1010a, and the insulating resin layer 1010 is cured. In this embodiment, a photosensitive permanent film is used for the insulating resin layer 1010, but for example, an opening may be formed by a laser method or a blast method using an insulating resin containing an inorganic filler, or an inorganic insulating layer may be deposited by CVD or the like and an opening may be formed by an etching method or the like.

[0081] As shown in FIG. 7F, a second through conductor layer 1014 corresponding to the second through wiring 14 is formed in the opening 1010a of the insulating resin layer 1010. Although not shown, a first through conductor layer corresponding to the first through wiring 13 is provided in the same manner as the second through conductor layer 1014. Specifically, in this embodiment, a Ti / Cu seed layer is formed on the upper surface of the insulating resin layer 1010 and the inner surface of the opening 1010a by anisotropic sputtering. Thereafter, filling plating is performed, and the upper surface of the insulating resin layer 1010 is flattened by CMP or mechanical polishing. As another method for forming the through conductor layer, a current-carrying portion is provided in advance in the bottom conductor layer, and the through conductor layer may be formed by electrolytic plating by supplying electricity from the current-carrying portion.

[0082] Thereafter, a seed layer (not shown) is formed on the upper surface of the insulating resin layer 1010, a resist layer (not shown) is applied on the upper surface of the seed layer, and a predetermined pattern of openings is formed in the resist layer by a photolithography process. Then, a top surface conductor layer 1011t corresponding to the top surface wiring 11t is provided in the openings by electrolytic plating, and as shown in FIG. 7G, the resist layer is peeled off and the seed layer is etched.

[0083] As shown in FIG. 7H, an insulating layer 1022 corresponding to the insulator 22 is provided on the upper surface of the insulating resin layer 1010 so as to cover the top surface conductor layer 1011t, and the insulating layer 1022 is cured. The insulating layer 1022 may be made of the same resin as the insulating resin layer 1010, or may be made of a different resin. Since the insulating layer 1022 is in contact with the outside, it is preferable to use a resin having excellent water resistance or high hardness compared to the insulating resin layer 1010, and further, it is preferable to use a resin containing an inorganic filler, etc., which improves the insulation. Furthermore, it is preferable to use a resin having high light blocking (shielding) properties compared to the insulating resin layer 1010 for the insulating layer 1022.

[0084] As shown in Figures 7I and 7J, the inorganic substrate 1021 is polished to expose the end faces of the first via conductor layer 1121v and the end faces of the second via conductor layer. CMP is preferable for polishing the inorganic substrate 1021. If necessary, the insulating layer 1022 may be polished to adjust the thickness.

[0085] 7K, the substrate is cut into individual pieces along cut lines C. In this way, inductor components 3 are manufactured as shown in FIG.

[0086] 4. Variations (First Modification) Fig. 8 is a simplified cross-sectional view showing a first modified example of a stacked semiconductor package. As shown in Fig. 8, in the stacked semiconductor package 1A of the first modified example, the configuration of a three-dimensional device 300A is different from that of the stacked semiconductor package 1 of Fig. 1. The other configurations are the same as those of the first embodiment, and the description thereof will be omitted.

[0087] 8, the three-dimensional device 300A has a plurality of integrated circuit components 401-403, a plurality of inductor components 501-503, and a plurality of capacitor components 601, 602. The integrated circuit components 401-403 correspond to an example of a "semiconductor integrated circuit component" in the claims, and for example, correspond to an example of the semiconductor integrated circuit component 310 in the first embodiment. The inductor components 501-503 and the capacitor components 601, 602 correspond to an example of a "passive component" in the claims, and for example, correspond to an example of the passive component 320 in the first embodiment.

[0088] The multiple semiconductor integrated circuit components (integrated circuit components 401-403) are arranged side by side in the first direction D1. This can improve the degree of freedom in circuit design. Specifically, the first integrated circuit component 401, the second integrated circuit component 402, and the third integrated circuit component 403 are stacked in order in the first direction D1. The multiple semiconductor integrated circuit components may be arranged side by side in the first direction D1 or in a direction perpendicular to the first direction D1.

[0089] A plurality of passive components (inductor components 501 to 503 and capacitor components 601, 602) are arranged side by side in the first direction D1. This can improve the degree of freedom in circuit design. Specifically, the first inductor component 501, the second inductor component 502, and the third inductor component 503 are stacked in order in the first direction D1. The first capacitor component 601 and the second capacitor component 602 are stacked in order in the first direction D1. The first inductor component 501, the first capacitor component 601, and the second capacitor component 602 are stacked in order in the first direction D1.

[0090] The first inductor component 501 is located between the first integrated circuit component 401 and the second integrated circuit component 402. The second inductor component 502 and the first capacitor component 601 are located between the second integrated circuit component 402 and the third integrated circuit component 403. The third inductor component 503 and the second capacitor component 602 are stacked on the third integrated circuit component 403.

[0091] The multiple passive components (inductor components 502, 503 and capacitor components 601, 602) are arranged side by side in a direction perpendicular to the first direction D1. This can improve the degree of freedom in circuit design. Specifically, the second inductor component 502 and the first capacitor component 601 are arranged side by side in a direction perpendicular to the first direction D1. The third inductor component 503 and the second capacitor component 602 are arranged side by side in a direction perpendicular to the first direction D1. Note that the multiple passive components may be arranged side by side in the first direction D1 or in a direction perpendicular to the first direction D1.

[0092] Here, the bonding between the first integrated circuit component 401 and the first inductor component 501, the bonding between the first inductor component 501 and the second integrated circuit component 402, the bonding between the second integrated circuit component 402 and the second inductor component 502, the bonding between the second integrated circuit component 402 and the first capacitor component 601, the bonding between the second inductor component 502 and the third integrated circuit component 403, the bonding between the first capacitor component 601 and the third integrated circuit component 403, the bonding between the third integrated circuit component 403 and the third inductor component 503, and the bonding between the third integrated circuit component 403 and the second capacitor component 602 are direct bonding using each other's flat surfaces as described in the first embodiment.

[0093] Preferably, all of the semiconductor integrated circuit components (integrated circuit components 401-403) and all of the passive components (inductor components 501-503 and capacitor components 601, 602) are stacked in the same layer, and the thicknesses of the components are the same. Specifically, the second inductor component 502 and the first capacitor component 601 are stacked in the same layer, and the thicknesses of the second inductor component 502 and the first capacitor component 601 are the same.

[0094] According to the above configuration, since the thicknesses of the multiple components (second inductor component 502, first capacitor component 601) on the same layer are the same, the inclination of the stacked components can be reduced even if the number of stacked components is increased. Also, since the thickness of some of the components on the same layer is not unnecessarily increased, the stacked semiconductor package 1A can be made thinner. In this case, it is sufficient that the three-dimensional device has at least one semiconductor integrated circuit component and at least one passive component.

[0095] Preferably, a plurality of components among all the semiconductor integrated circuit components (integrated circuit components 401-403) and all the passive components (inductor components 501-503 and capacitor components 601, 602) are stacked on the top layer in the first direction D1, and at least two components among the plurality of components on the top layer have different thicknesses. Specifically, the third inductor component 503 and the second capacitor component 602 are stacked on the top layer, and the third inductor component 503 and the second capacitor component 602 have different thicknesses.

[0096] According to the above configuration, at least two components (third inductor component 503 and second capacitor component 602) among the multiple components on the top layer have different thicknesses, so that components of different thicknesses can be integrated on the top layer. Also, since no components are stacked above the top layer, a step of adjusting the thickness of the top layer is not required. In this case, it is sufficient for the three-dimensional device to have at least one semiconductor integrated circuit component and at least one passive component.

[0097] When passive components and semiconductor integrated circuit components are present on the top layer, it is preferable that the thickness of the passive components is thicker than that of the semiconductor integrated circuit components. Usually, the active area (area where the active layer is formed) of the semiconductor integrated circuit components is very thin, and the thickness of the passive components with low design accuracy is generally thick. Therefore, by making the passive components thicker, the volume increases, and it is possible to improve the performance while suppressing the footprint (planar area) of the entire package. Furthermore, when the passive components include an inductor component, the thickness of the inductor component is the thickest. Since the energy storage rate of the inductor component is generally smaller than that of the capacitor component, increasing the thickness of the inductor component to increase its volume contributes to reducing the footprint of the entire package. For example, the thickness of the semiconductor integrated circuit components on the top layer is 100 μm, the thickness of the capacitor component is 220 μm, and the thickness of the inductor component is 330 μm.

[0098] Preferably, the area of ​​the component closest to first substrate 210 in first direction D1 among all semiconductor integrated circuit components (integrated circuit components 401-403) and all passive components (inductor components 501-503 and capacitor components 601, 602) is larger than the area of ​​each of the other components. The area of ​​a component refers to the area of ​​a surface perpendicular to first direction D1 (planar area). Specifically, the area of ​​first integrated circuit component 401 closest to first substrate 210 is preferably larger than the area of ​​each of the other components (second and third integrated circuit components 402, 403, first to third inductor components 501-503, and first and second capacitor components 601, 602).

[0099] According to the above configuration, since the area (footprint) of the component closest to the first substrate 210 is the largest, misalignment of other components stacked on the component closest to the first substrate 210 can be absorbed, and a wide process margin can be secured for cutting other components. In this case, the three-dimensional device only needs to have at least one semiconductor integrated circuit component and at least one passive component.

[0100] More preferably, the areas of the semiconductor integrated circuit components and the passive components decrease in order along the first direction D1, which makes it possible to prevent misalignment of the components in the process of stacking the components and to ensure a process margin for cutting the components.

[0101] Preferably, the area of ​​at least one of all the passive components (inductor components 501-503 and capacitor components 601, 602) is smaller than the area of ​​at least one of all the semiconductor integrated circuit components (integrated circuit components 401-403). Specifically, the area of ​​each of the second inductor component 502 and the third inductor component 503 is smaller than the area of ​​each of the first to third integrated circuit components 401-403. The area of ​​each of the first capacitor component 601 and the second capacitor component 602 is smaller than the area of ​​each of the first to third integrated circuit components 401-403.

[0102] According to the above configuration, by stacking a small-area passive component on a semiconductor integrated circuit component, other functions can be added to the remaining space of the semiconductor integrated circuit component, thereby improving the integration density of the three-dimensional device. In this case, it is sufficient for the three-dimensional device to have at least one semiconductor integrated circuit component and at least one passive component.

[0103] Preferably, the passive components having a small area are capacitor components. Specifically, the area of ​​each of the first capacitor component 601 and the second capacitor component 602 is smaller than the area of ​​each of the first to third integrated circuit components 401 to 403. This makes it possible to provide a three-dimensional device with a high degree of integration efficiently. Capacitor components generally have a higher energy storage rate per volume than inductor components, and therefore the capacitor components are easier to miniaturize.

[0104] Preferably, the area of ​​at least one of all the passive components (inductor components 501-503 and capacitor components 601, 602) is larger than the area of ​​at least one of all the semiconductor integrated circuit components (integrated circuit components 401-403). Specifically, the area of ​​the first inductor component 501 is larger than the area of ​​the third integrated circuit component 403.

[0105] According to the above configuration, since the process node (design rule) of the passive components is looser than that of the semiconductor integrated circuit components, the manufacturing cost can be reduced by increasing the area of ​​the passive components. In this case, it is sufficient for the three-dimensional device to have at least one semiconductor integrated circuit component and at least one passive component.

[0106] Preferably, the passive component having a large area is an inductor component. This makes it possible to efficiently provide a highly integrated three-dimensional device. By increasing the area of ​​the inductor component, a desired circuit constant can be obtained.

[0107] (Second Modification) Fig. 9 is a simplified cross-sectional view showing a second modified example of a stacked semiconductor package. As shown in Fig. 9, a stacked semiconductor package 1B of the second modified example differs from the stacked semiconductor package 1A of Fig. 8 in the configuration of a three-dimensional device 300B, and includes other components in addition to the three-dimensional device 300B. The other configurations are the same as those of the first modified example, and description thereof will be omitted.

[0108] 9, the three-dimensional device 300B has one inductor component 501, one capacitor component 601, and one integrated circuit component 401. The inductor component 501, the capacitor component 601, and the integrated circuit component 401 are arranged side by side in a first direction D1. The capacitor component 601 corresponds to an example of a "first passive component" in the claims, and the inductor component 501 corresponds to an example of a "second passive component" in the claims.

[0109] A first main surface 501a of the inductor component 501 facing the capacitor component 601 and a first main surface 601a of the capacitor component 601 facing the inductor component 501 each include a flat surface. The flat surface of the inductor component 501 and the flat surface of the capacitor component 601 are bonded in a contacting state. This bonding is the direct bonding by each other's flat surfaces as described in the first embodiment. Similarly, the bonding between the capacitor component 601 and the integrated circuit component 401 is the direct bonding by each other's flat surfaces.

[0110] According to the above configuration, the flat surface of the inductor component 501 and the flat surface of the capacitor component 601 are joined in contact with each other, so that the thickness of the three-dimensional device 300B can be reduced, and the stacked semiconductor package 1B can be made thinner. In this case, the three-dimensional device only needs to have a plurality of passive components.

[0111] The stacked semiconductor package 1B has an integrated circuit component 400A for mounting and an inductor component 500A for mounting. Here, "for mounting" refers to a component that is not directly bonded by a flat surface. Specifically, the integrated circuit component 400A for mounting and the inductor component 500A for mounting are mounted on a first substrate 210. The integrated circuit component 400A for mounting and the inductor component 500A for mounting are connected to a first main surface 211 of the first substrate 210 via a first connecting member 5.

[0112] According to the above configuration, the same first main surface 211 of the first substrate 210 is provided with the integrated circuit component 400A and the inductor component 500A other than the three-dimensional device 300B, so that the integration density of the package can be increased and parasitic components can be suppressed.

[0113] <Second embodiment> (Configuration of stacked semiconductor package 1C) Fig. 10A is a simplified cross-sectional view showing a second embodiment of the stacked semiconductor package. Fig. 10B is a simplified plan view showing the second embodiment of the stacked semiconductor package. For convenience, an insulating member is omitted in Fig. 10B.

[0114] 10A and 10B, the stacked semiconductor package 1C of the second embodiment differs from the stacked semiconductor package 1 of Fig. 1 in the configuration of a three-dimensional device 300C, and includes other components in addition to the three-dimensional device 300C. The other configurations are the same as those of the first embodiment, and the description thereof will be omitted.

[0115] As shown in FIGS. 10A and 10B, the three-dimensional device 300C includes an integrated circuit component 401, an inductor component 501, a first capacitor component 601, a second capacitor component 602, a first insulating member 701, and a second insulating member 702.

[0116] Integrated circuit component 401, first capacitor component 601, and second capacitor component 602 are stacked on the same upper surface of inductor component 501. Bonding between integrated circuit component 401 and inductor component 501, bonding between first capacitor component 601 and inductor component 501, and bonding between second capacitor component 602 and inductor component 501 are performed by direct bonding via each other's flat surfaces as described in the first embodiment.

[0117] First insulating member 701 is provided on the upper surface of inductor component 501 so as to cover at least a portion of integrated circuit component 401, first capacitor component 601, and second capacitor component 602. This makes it possible for first insulating member 701 to protect the components from moisture and mechanical stress. Furthermore, by providing further wiring on first insulating member 701, the number of layers can be increased, enabling wiring to be routed and improving the freedom of circuit design.

[0118] The first insulating member 701 is made of, for example, epoxy resin, phenol resin, polyimide resin, liquid crystal polymer resin, etc., or a composite material containing inorganic filler in these resins, or an inorganic material such as Si, SiO2, or SiN formed by CVD or vapor deposition.

[0119] The second insulating member 702 is provided on the upper surface of the first insulating member 701. The second insulating member 702 is made of the same material as the first insulating member 701, for example.

[0120] The three-dimensional device 300C further includes an electrical connection portion 801 on the second main surface 302 of the three-dimensional device 300C. Specifically, the first main surface 301 is formed from the lower surface of the inductor component 501, and the second main surface 302 is formed from the upper surface of the second insulating member 702. The electrical connection portions 801 are provided so as to penetrate the second insulating member 702. The electrical connection portions 801 are, for example, external terminals. The electrical connection portions 801 are electrically connected to the first capacitor component 601 and the second capacitor component 602, respectively, through the via portions 802. The via portions 802 are provided in the first insulating member 701.

[0121] According to the above configuration, other components can be stacked on the electrical connection portion 801 while being electrically connected to the electrical connection portion, so that the number of layers can be increased, and the degree of freedom in stacking and the degree of freedom in circuit design can be improved. Note that the electrical connection portion 801 may be provided on at least one of the first main surface 301 and the second main surface 302.

[0122] Preferably, the stacked semiconductor package 1C further includes an integrated circuit component 400A for mounting. Specifically, the integrated circuit component 400A for mounting is mounted on the second insulating member 702. The integrated circuit component 400A for mounting is connected to the upper surface of the second insulating member 702 via an electrical connection portion 801. With this, since the integrated circuit component 400A other than the three-dimensional device 300C is provided, the integration degree of the package can be increased and parasitic components can be suppressed.

[0123] (Modification) Fig. 11 is a simplified cross-sectional view showing a modified example of a stacked semiconductor package. As shown in Fig. 11, a modified stacked semiconductor package 1D differs from the stacked semiconductor package 1C of Fig. 10A in the configuration of a three-dimensional device 300D. The other configurations are the same as those of the second embodiment, and the description thereof will be omitted.

[0124] 11, the three-dimensional device 300D differs from the three-dimensional device 300C in FIG. 10A in that it does not have a second capacitor component 602, but has a first conductive wiring 901 and a second conductive wiring 902. In other words, the three-dimensional device 300D has an integrated circuit component 401, an inductor component 501, a capacitor component 601, a first insulating member 701, a second insulating member 702, a plurality of first conductive wirings 901, and a plurality of second conductive wirings 902.

[0125] The first insulating member 701 is laminated in the same layer as the integrated circuit component 401 and the capacitor component 601. The first conductive wiring 901 penetrates the first insulating member 701. This improves the degree of freedom in circuit design. In addition, since the first conductive wiring 901 penetrates the first insulating member 701, the first conductive wiring 901 can be easily formed.

[0126] The first conductive wiring 901 is made of, for example, Cu or an alloy containing Cu. The first conductive wiring 901 preferably has a larger cross-sectional area than the FEOL (front-end-of-line) wiring of the semiconductor integrated circuit component. More preferably, the first conductive wiring 901 has a larger cross-sectional area than the BEOL (back-end-of-line) wiring of the semiconductor integrated circuit component. By using Cu, which is a relatively inexpensive material, as the material of the first conductive wiring 901 and using a rough process node for the first conductive wiring 901, the first conductive wiring 901 can be formed at low cost. The first conductive wiring 901 is equal to or greater than the thickness of the integrated circuit component 401 or the capacitor component 601, and is equal to or less than the thickness of the first insulating member 701.

[0127] Second conductive wiring 902 passes through inductor component 501 and is not connected to the inductor element of inductor component 501. The inductor element includes a coil. This allows electrical signals to be transmitted and received by second conductive wiring 902 without passing through the inductor element, thereby improving the degree of integration.

[0128] The material of the second through wiring 902 is, for example, the same material as the first conductive wiring 901. The second conductive wiring 902 preferably has a larger cross-sectional area than the FEOL wiring of the semiconductor integrated circuit component. More preferably, the second conductive wiring 902 has a larger cross-sectional area than the BEOL wiring of the semiconductor integrated circuit component. The second conductive wiring 902 has a thickness equal to or greater than the thickness of the inductor component 501. Note that the second conductive wiring does not have to pass through passive components other than the inductor component 501 and be connected to passive elements of the other passive components.

[0129] The first conductive wiring 901 is electrically connected to some of the second conductive wiring 902. The integrated circuit component 400A for mounting and the first substrate 210 are electrically connected via the first conductive wiring 901 and some of the second conductive wiring 902. The integrated circuit component 401 and the first substrate 210 are electrically connected via other second conductive wiring 902.

[0130] <Third embodiment> Fig. 12 is a simplified cross-sectional view showing a third embodiment of a stacked semiconductor package. As shown in Fig. 12, a stacked semiconductor package 1E of the third embodiment differs from the stacked semiconductor package 1 of Fig. 1 in the configuration of a three-dimensional device 300E and in the configuration in which a third substrate 230 is added. The other configurations are the same as those of the first embodiment, and the description thereof will be omitted.

[0131] 12, the three-dimensional device 300E has an integrated circuit component 401 and a capacitor component 601. The integrated circuit component 401 is stacked on the upper surface of the capacitor component 601. The integrated circuit component 401 and the capacitor component 601 are directly bonded to each other via their flat surfaces as described in the first embodiment.

[0132] The stacked semiconductor package 1E further includes a third substrate 230. The third substrate 230 is stacked in a first direction D1 with respect to the three-dimensional device 300E. A first main surface 231 of the third substrate 230 facing the three-dimensional device 300E and a second main surface 302 of the three-dimensional device 300E facing the third substrate 230 are spaced apart from each other and connected via a third connecting member 7. The third connecting member 7 is made of the same material as the first connecting member 5.

[0133] The third distance L3 between the first main surface 231 of the third substrate 230 and the second main surface 302 of the three-dimensional device 300E is greater than the second distance L2 between the first main surface 211 of the first substrate 210 and the first main surface 301 of the three-dimensional device 300E. This allows the circuit system to be enlarged, improving the degree of freedom in circuit design. The third distance L3 is determined in the same manner as the first distance L1 and the second distance L2. The third distance L3 is, for example, 300 μm.

[0134] The third substrate 230 has the same configuration as the second substrate 220. That is, the third substrate 230 has a lower design precision than the first substrate 210. The first main surface 231 of the third substrate 230 and the first main surface 221 of the second substrate 220 are connected via a fourth connecting member 8. An inductor component 500A for mounting and a capacitor component 600A for mounting are mounted on the second main surface 232 of the third substrate 230 via a fifth connecting member 9. The fifth connecting member 9 is made of the same material as the first connecting member 5. An integrated circuit component 400A for mounting and a capacitor component 600A for mounting are built into the third substrate 230.

[0135] Preferably, the three-dimensional device 300E further includes the electrical connection portion 801 of the second embodiment on each of the first main surface 301 and the second main surface 302 of the three-dimensional device 300E. This allows electrical signals to be transmitted and received from the upper surface and the lower surface of the three-dimensional device 300E, improving the degree of freedom in circuit design.

[0136] The present disclosure is not limited to the above-described embodiments, and design modifications are possible without departing from the scope of the present disclosure. For example, the respective characteristic points of the first to third embodiments may be combined in various ways.

[0137] <1> A first substrate; a three-dimensional device stacked in a first direction on the first substrate; a first connection member that connects the first substrate and the three-dimensional device; Equipped with the three-dimensional device has a plurality of components including semiconductor integrated circuit components and passive components stacked in the first direction; a first main surface of the first substrate facing the three-dimensional device and a first main surface of the three-dimensional device facing the first substrate are connected to each other via the first connection member in a spaced-apart state; A stacked semiconductor package, wherein a first main surface of the semiconductor integrated circuit component facing the passive component and a first main surface of the passive component facing the semiconductor integrated circuit component each include a flat surface, and the flat surface of the semiconductor integrated circuit component and the flat surface of the passive component are joined in contact with each other. <2> an area of ​​the flat surface of the semiconductor integrated circuit component is larger than half an area of ​​the first main surface of the semiconductor integrated circuit component, and an area of ​​the flat surface of the passive component is larger than half an area of ​​the first main surface of the passive component; <1> 2. The stacked semiconductor package according to claim 1 . <3> the flat surface of the semiconductor integrated circuit component and the flat surface of the passive component are made of an inorganic material; <1> or <2> 2. The stacked semiconductor package according to claim 1 . <4> the three-dimensional device includes a plurality of the semiconductor integrated circuit components; the plurality of semiconductor integrated circuit components are arranged side by side in the first direction or in a direction perpendicular to the first direction; <1> from <3> 13. The stacked semiconductor package according to claim 12 . <5> the three-dimensional device includes a plurality of the passive components; The plurality of passive components are arranged side by side in the first direction or in a direction perpendicular to the first direction. <1> from <4> 13. The stacked semiconductor package according to claim 12 . <6> Further, a second substrate and a second connection member are provided, the first substrate is stacked on the second substrate in the first direction; a second main surface of the first substrate facing the second substrate and a first main surface of the second substrate facing the first substrate are spaced apart from each other and connected to each other via the second connection member; a distance between the second main surface of the first substrate and the first main surface of the second substrate is greater than a distance between the first main surface of the first substrate and the first main surface of the three-dimensional device; <1> from <5> 13. The stacked semiconductor package according to claim 12 . <7> the three-dimensional device has at least one of the semiconductor integrated circuit components and at least one of the passive components; All of the semiconductor integrated circuit components and all of the passive components are stacked in the same layer, and the thicknesses of the components in the first direction are the same. <1> from <6> 13. The stacked semiconductor package according to claim 12 . <8> the three-dimensional device has at least one of the semiconductor integrated circuit components and at least one of the passive components; A plurality of components among all of the semiconductor integrated circuit components and all of the passive components are stacked on a top layer in the first direction, and thicknesses of at least two components among the plurality of components on the top layer in the first direction are different from each other. <1> from <6> 13. The stacked semiconductor package according to claim 12 . <9> the three-dimensional device has at least one of the semiconductor integrated circuit components and at least one of the passive components; an area of ​​a surface perpendicular to the first direction of a component that is closest to the first substrate in the first direction among all of the semiconductor integrated circuit components and all of the passive components is larger than an area of ​​a surface perpendicular to the first direction of each of the other components; <1> from <8> 13. The stacked semiconductor package according to claim 12 . <10> the three-dimensional device has at least one of the semiconductor integrated circuit components and at least one of the passive components; an area of ​​a surface perpendicular to the first direction of at least one of all of the passive components is smaller than an area of ​​a surface perpendicular to the first direction of at least one of all of the semiconductor integrated circuit components; <1> from <9> 13. The stacked semiconductor package according to claim 12 . <11> the three-dimensional device has at least one of the semiconductor integrated circuit components and at least one of the passive components; an area of ​​at least one of all of the passive components is greater than an area of ​​at least one of all of the semiconductor integrated circuit components; <1> from <10> 13. The stacked semiconductor package according to claim 12 . <12> At least one of the passive components is an inductor component; the inductor component has a surface area perpendicular to the first direction larger than that of at least one of the semiconductor integrated circuit components; <1> from <11> 13. The stacked semiconductor package according to claim 12 . <13> The three-dimensional device further comprises a second passive component; a first passive component and a second passive component among the passive components are arranged side by side in the first direction; a first main surface of the first passive component facing the second passive component and a first main surface of the second passive component facing the first passive component each include a flat surface, and the flat surface of the first passive component and the flat surface of the second passive component are joined in contact with each other. <1> from <12> 13. The stacked semiconductor package according to claim 12 . <14> The three-dimensional device further includes an insulating member that covers at least a portion of the semiconductor integrated circuit component and the passive component. <1> from <13> 13. The stacked semiconductor package according to claim 12 . <15> Further, a third substrate and a third connection member are provided, the third substrate is stacked in the first direction with respect to the three-dimensional device; a first main surface of the third substrate facing the three-dimensional device and a second main surface of the three-dimensional device facing the third substrate are spaced apart and connected via the third connection member; a distance between the first main surface of the third substrate and the second main surface of the three-dimensional device is greater than a distance between the first main surface of the first substrate and the first main surface of the three-dimensional device; <1> from <14> 13. The stacked semiconductor package according to claim 12 . <16> bonding a semiconductor integrated circuit component having a flat surface and a passive component having a flat surface with the flat surfaces in contact with each other to form a three-dimensional device; connecting a first main surface of the three-dimensional device and a first main surface of a first substrate via a connecting member while being spaced apart from each other; A manufacturing method of a stacked semiconductor package comprising: [Explanation of symbols]

[0138] 1, 1A-1E Stacked semiconductor package 3. Inductor Components 5, 6, 7 First, second, and third connecting members 10 Base 11b Bottom wiring 11t Top wiring 13 First through wiring 14 Second through-hole wiring 21 Inorganic layer 22 Insulators 110 Coil 210, 220, 230 First, second, and third substrates 211, 221, 231 First main surface 212, 222, 232 Second main surface 300, 300A-300E 3D Devices 301 First main surface 302 Second main surface 310 Semiconductor integrated circuit parts 311 First main surface 311a flat surface 312 Second main surface 320 Passive Components 321 First main surface 321a flat surface 322 Second main surface 401, 402, 403 First, second, and third integrated circuit components 501, 502, 503 First, second, and third inductor components 501a 1st principal surface 601, 602 First and second capacitor parts 601a First main surface 701, 702 First and second insulating members 801 Electrical connections 901, 902 1st and 2nd continuity wiring D1 1st direction L1, L2, L3 1st, 2nd, 3rd distance AX axis

Claims

1. A first substrate; a three-dimensional device stacked in a first direction on the first substrate; a first connection member that connects the first substrate and the three-dimensional device; Equipped with the three-dimensional device has a plurality of components including semiconductor integrated circuit components and passive components stacked in the first direction; a first main surface of the first substrate facing the three-dimensional device and a first main surface of the three-dimensional device facing the first substrate are connected to each other via the first connection member in a spaced-apart state; a first main surface of the semiconductor integrated circuit component facing the passive component and a first main surface of the passive component facing the semiconductor integrated circuit component each include a flat surface, and the flat surface of the semiconductor integrated circuit component and the flat surface of the passive component are joined in contact with each other; Further, a third substrate and a third connection member are provided, the third substrate is stacked in the first direction with respect to the three-dimensional device; a first main surface of the third substrate facing the three-dimensional device and a second main surface of the three-dimensional device facing the third substrate are spaced apart from each other and connected via the third connection member; A stacked semiconductor package, wherein a distance between the first main surface of the third substrate and the second main surface of the three-dimensional device is greater than a distance between the first main surface of the first substrate and the first main surface of the three-dimensional device.

2. 2. The stacked semiconductor package according to claim 1, wherein an area of ​​the flat surface of the semiconductor integrated circuit component is larger than half an area of ​​the first main surface of the semiconductor integrated circuit component, and an area of ​​the flat surface of the passive component is larger than half an area of ​​the first main surface of the passive component.

3. 2. The stacked semiconductor package according to claim 1, wherein said flat surface of said semiconductor integrated circuit component and said flat surface of said passive component are made of an inorganic material.

4. the three-dimensional device includes a plurality of the semiconductor integrated circuit components; 2. The stacked semiconductor package according to claim 1, wherein the plurality of semiconductor integrated circuit components are arranged side by side in the first direction or in a direction perpendicular to the first direction.

5. the three-dimensional device includes a plurality of the passive components; The stacked semiconductor package according to claim 1 , wherein the plurality of passive components are arranged side by side in the first direction or in a direction perpendicular to the first direction.

6. Further, a second substrate and a second connection member are provided, the first substrate is stacked on the second substrate in the first direction; a second main surface of the first substrate facing the second substrate and a first main surface of the second substrate facing the first substrate are spaced apart from each other and connected to each other via the second connection member; 2. The stacked semiconductor package of claim 1, wherein a distance between the second main surface of the first substrate and the first main surface of the second substrate is greater than a distance between the first main surface of the first substrate and the first main surface of the three-dimensional device.

7. the three-dimensional device has at least one of the semiconductor integrated circuit components and at least one of the passive components; all of the semiconductor integrated circuit components and all of the passive components are stacked in the same layer, and the thicknesses of the components in the first direction are the same; 2. The stacked semiconductor package according to claim 1.

8. the three-dimensional device has at least one of the semiconductor integrated circuit components and at least one of the passive components; 2. The stacked semiconductor package according to claim 1, wherein a plurality of components among all of the semiconductor integrated circuit components and all of the passive components are stacked in a top layer in the first direction, and the respective thicknesses in the first direction of at least two components among the plurality of components in the top layer are different.

9. the three-dimensional device has at least one of the semiconductor integrated circuit components and at least one of the passive components; 2. The stacked semiconductor package according to claim 1, wherein an area of ​​a surface perpendicular to the first direction of at least one of all of the passive components is smaller than an area of ​​a surface perpendicular to the first direction of at least one of all of the semiconductor integrated circuit components.

10. At least one of the passive components is an inductor component; The stacked semiconductor package according to claim 1 , wherein the inductor component has a surface area perpendicular to the first direction that is larger than that of at least one of the semiconductor integrated circuit components.

11. The three-dimensional device further comprises a second passive component; a first passive component and a second passive component among the passive components are arranged side by side in the first direction, 2. The stacked semiconductor package of claim 1, wherein a first main surface of the first passive component facing the second passive component and a first main surface of the second passive component facing the first passive component each include a flat surface, and the flat surface of the first passive component and the flat surface of the second passive component are joined in contact with each other.

12. The stacked semiconductor package according to claim 1 , wherein the three-dimensional device further comprises an insulating member covering at least a portion of the semiconductor integrated circuit component and the passive component.

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