Semiconductor Device

Abstract

To provide a semiconductor device for monitoring and measuring the voltage between the positive and negative electrodes of a battery and between the negative electrode or the positive electrode and ground.SOLUTION: A semiconductor device has a multi-chip structure divided into a first chip 10 that reduces (buckles) directly applied high voltage signals and a second chip 20 that processes signals from the reduced (buckled) signals via the first chip 10, and the second chip 20 has multiple operational amplifiers 1a and 1b. In addition to being able to detect the voltage between the positive and negative poles of the battery connected to the semiconductor device, the voltage between the negative pole and ground can be monitored or measured to enable state detection of the resistance of the insulation resistance.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a multi-chip type semiconductor device, and more particularly to a semiconductor device in which a high voltage is applied to lead terminals. [Background technology]

[0002] In hybrid and electric vehicles, the vehicle drive battery is configured to output a specified drive voltage, and the battery output voltage must be constantly monitored. For example, the vehicle drive battery in a hybrid vehicle has an output voltage of about 200V, which is further boosted to about 500V. Therefore, a voltage monitoring circuit is required to monitor for abnormal voltages. In recent years, there has also been a demand for high-voltage monitoring circuits that can monitor for abnormal voltages exceeding 1000V.

[0003] 7 shows an example of a motor drive device equipped with a voltage detection circuit. Motor drive device 100 is configured to boost (e.g., to 600 V) a DC voltage (e.g., 200 V) output from a high-voltage battery B separated from the vehicle body by an insulation resistor using a boost converter 101, and convert the boosted voltage via a smoothing capacitor 102 to a three-phase AC voltage for driving a motor using an inverter circuit 103, and supply the voltage to a motor M for driving a vehicle. This type of motor drive device is described in Patent Document 1, for example.

[0004] The voltage detection circuit 200 detects the voltage between the positive and negative electrodes of a battery B. In general, the voltage detection circuit 200 can be configured with an operational amplifier 201 and resistive elements 202a to 202e as shown in Fig. 8, and can obtain a detection signal of the voltage between the positive and negative electrodes of a battery connected between terminals B1 and B2 from a terminal OUT. The applicant of the present application has also disclosed a technology for configuring this type of voltage detection circuit with a semiconductor device (Patent Document 2).

[0005] Incidentally, when detecting the voltage of a vehicle battery using this type of voltage detection circuit 200, the voltage detection circuit 200 including the battery is electrically isolated from the vehicle body, which is the ground reference potential point, by an insulation resistor, and can be considered as a configuration in which insulation resistors P1 and P2, ideally having infinite resistance values, are connected as shown in Fig. 9. In such a configuration, if the insulation resistors P1 and P2 are not maintained in a high resistance state, there is a risk of malfunction of peripheral circuits or electric shock accidents. Therefore, it is necessary to detect the state in which the insulation resistors are maintained in a high resistance state. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2009-201192 A [Patent Document 2] Patent No. 6541223 Summary of the Invention [Problem to be solved by the invention]

[0007] The semiconductor device previously proposed by the applicant of the present application was capable of measuring the voltage between the positive and negative electrodes of a battery, but was unable to measure the voltage between the negative electrode and ground or the voltage between the positive electrode and ground. The object of the present invention is to provide a semiconductor device that can monitor and measure the voltage between the positive electrode and negative electrode of a battery, and between the negative electrode or positive electrode and ground. [Means for solving the problem]

[0008] In order to achieve the above object, the invention according to claim 1 of the present application provides a semiconductor device in which a first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, each chip electrode is connected by wire to each other and each chip electrode is connected to a lead terminal for external extraction, and the semiconductor device is sealed with a sealing resin, the lead terminals constitute a first lead row and a second lead row made up of a plurality of lead terminals arranged opposite each other with the die pad in between, and the first chip is mainly composed of a resistance element. the resistor element includes a first voltage dividing resistor string consisting of a first resistor element and a second resistor element, a second voltage dividing resistor string consisting of a third resistor element and a fourth resistor element, and a feedback resistor consisting of a fifth resistor element; the second chip has an operational amplifier as a main component and includes a first operational amplifier and a second operational amplifier; the lead terminal of the first lead string is composed of two lead terminals, one of the lead terminals of the first lead string being one of two resistor chip electrodes formed on one side of the rectangular first chip on the side of the first lead string; the other lead terminal of the first lead string is connected to the other of the two resistor chip electrodes which is connected to one end of the second voltage-dividing resistor string; and among other resistor chip electrodes arranged on another side opposite to the one side from the two resistor chip electrodes, a resistor chip electrode connected to a first series connection point which is a connection point between the first resistor element and the second resistor element which outputs a first divided voltage of the first voltage-dividing resistor string; a resistor chip electrode connected to a second series connection point, which is a connection point between the third resistor element and the fourth resistor element, which outputs a second divided voltage of the voltage-dividing resistor string, is connected to an operational amplifier chip electrode connected to a non-inverting input terminal and an inverting input terminal of the first operational amplifier among operational amplifier chip electrodes arranged on one side of the first chip formed on the rectangular second chip, and resistor chip electrodes connected to the other end of the first voltage-dividing resistor string and the other end of the second voltage-dividing resistor string, which are connected to a reference voltage, are connected to lead terminals of the second lead string;Among the op-amp chip electrodes arranged on one side of the first chip side formed on the second chip, resistor chip electrodes connected to both ends of the feedback resistor are connected between an op-amp chip electrode connected to an output terminal of the first op-amp and an op-amp chip electrode connected to the inverting input terminal of the first op-amp, a resistor chip electrode connected to the first series connection point is connected to an op-amp chip electrode connected to a non-inverting input terminal of the second op-amp among the op-amp chip electrodes arranged on one side of the first chip side formed on the second chip, and another op-amp chip electrode including an op-amp chip electrode connected to an output terminal of the second op-amp connected to the inverting input terminal of the second op-amp is connected to a lead terminal of the second lead row, a voltage applied to a lead terminal of the first lead string is divided by the first voltage dividing resistor string and the second voltage dividing resistor string, the first divided voltage is output to a non-inverting input terminal of the first operational amplifier, the second divided voltage is output to an inverting input terminal of the first operational amplifier, an output signal processed by the first operational amplifier is output from a lead terminal of the second lead string, the first divided voltage is output to a non-inverting input terminal of the second operational amplifier, and an output signal processed by the second operational amplifier is output from a lead terminal of the second lead string; the two lead terminals of the first lead string are spaced apart from each other by a dimension sufficient to withstand the voltage applied between the lead terminals; and the sealing resin is filled at least between the two lead terminals of the first lead string.

[0009] The invention of claim 2 of the present application is characterized in that, in the semiconductor device described in claim 1, auxiliary wiring is arranged on the surface of the first chip facing the second chip, or on the surface of the second chip facing the first chip, and the non-inverting input terminal of the first operational amplifier and the non-inverting input terminal of the second operational amplifier are connected via the auxiliary wiring.

[0010] The invention of claim 3 of the present application is characterized in that, in a semiconductor device described in either claim 1 or claim 2, any lead terminal of the second lead row and the resistor chip electrode or the operational amplifier chip electrode are connected via a relay chip mounted on the die pad.

[0011] The invention of claim 4 of the present application is characterized in that, in a semiconductor device described in either claim 1 or claim 2, any lead terminal of the second lead row and the resistor chip electrode or the operational amplifier chip electrode are connected via a relay chip equipped with an ESD protection element mounted on the die pad. Effect of the Invention

[0012] The semiconductor device of the present invention can monitor or measure the voltage between the positive and negative electrodes of a battery, as well as the voltage between the negative electrode and ground or the voltage between the positive electrode and ground, which is highly effective in reducing the size of in-vehicle components. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is a block diagram of a voltage detection circuit of the semiconductor device of the present invention. [Diagram 2] 5 is an explanatory diagram of voltage detection in the semiconductor device of the present invention. [Diagram 3] FIG. 1 is an explanatory diagram of a semiconductor device according to a first embodiment of the present invention. [Figure 4] FIG. 1 is an explanatory diagram of a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention. [Diagram 5] FIG. 4 is an explanatory diagram of a semiconductor device according to a second embodiment of the present invention. [Figure 6] FIG. 11 is an explanatory diagram of a semiconductor device according to a third embodiment of the present invention. [Figure 7] FIG. 1 is an explanatory diagram of a general motor drive device. [Figure 8] FIG. 1 is an explanatory diagram of a general voltage detection circuit. [Figure 9] FIG. 1 is an explanatory diagram of a general voltage detection circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The semiconductor device according to the present invention is a semiconductor device to which a high voltage can be applied. Specifically, the semiconductor device can apply a high voltage of about 1000V, and has a multi-chip structure divided into a first chip that reduces (steps down) the high voltage signal directly applied, and a second chip that processes the reduced (stepped down) signal that has passed through the first chip. In particular, the present invention is configured to include a plurality of operational amplifiers in the second chip, and is configured to detect not only the voltage between the positive and negative electrodes of a battery connected to the semiconductor device of the present invention, but also the voltage between the negative electrode and ground (vehicle body) and the voltage between the positive electrode and ground (vehicle body) to detect a decrease in the resistance value of an insulation resistor. Hereinafter, an embodiment of the present invention will be described in detail. EXAMPLES

[0015] An embodiment of the present invention will be described taking as an example a semiconductor device capable of detecting a high voltage exceeding 1000V and a decrease in the resistance value of an insulation resistor. Fig. 1 is a block diagram of a voltage detection circuit of a semiconductor device according to the present invention.

[0016] As shown in Fig. 1, the series-connected resistor elements 2a and 2b (corresponding to a first voltage-dividing resistor string) are elements that divide the high voltage on the negative side of the battery, with terminal B1 connected to the negative electrode of the battery and the other end connected to a reference voltage (VREF). The series connection point N1 (corresponding to a first series connection point) of the resistor elements 2a and 2b is connected to the non-inverting input terminal of the first operational amplifier 1a. Here, since the first chip 10 on which the resistor elements are formed and the second chip 20 on which the operational amplifier is formed are each composed of separate chips, the series connection point N1 of the resistor elements 2a and 2b and the non-inverting input terminal of the operational amplifier 1a are connected by a wire 3.

[0017] On the other hand, the series-connected resistor elements 2c and 2d (corresponding to a second voltage-dividing resistor string) are elements for dividing the high voltage on the positive side of the battery, with terminal B2 connected to the positive electrode of the battery and the other end connected to a reference voltage (VREF). A series connection point N2 (corresponding to a second series connection point) of the resistor elements 2c and 2d is connected to the inverting input terminal of the first operational amplifier 1a. The series connection point N2 of the resistor elements 2c and 2d is connected to the inverting input terminal of the first operational amplifier 1a by a wire 3.

[0018] The resistor element 2e is a feedback resistor for determining the amplification gain of the first operational amplifier 1a, and one end of the resistor element 2e is connected to the inverting input terminal of the first operational amplifier 1a, and the other end is connected to the output terminal of the first operational amplifier 1a by wires 3. The output terminal OUT of the first operational amplifier 1a outputs an output signal corresponding to the voltage between the positive and negative poles of the battery connected between terminals B1 and B2. This terminal OUT is connected to a control circuit (not shown), and the control circuit outputs a control signal for controlling the operation of the boost converter 101 and inverter circuit 103 shown in FIG. 7, thereby controlling the drive of the motor M.

[0019] The series connection point N1 of the resistor elements 2a and 2b is connected to the non-inverting input terminal of the second operational amplifier 1b. The inverting input terminal of the second operational amplifier 1b is connected to the output terminal of the second operational amplifier 1b, and the output terminal VNOUT of the second operational amplifier 1b outputs an output signal corresponding to the voltage between the negative pole of the battery connected to terminal B1 and the reference voltage (VREF).

[0020] More specifically, as shown in FIG. 2, battery B is connected between terminal B1 and terminal B2. When insulation resistance P1 between the negative pole (terminal B1) of battery B and ground (GND) is maintained normally, the resistance value R(P1) of insulation resistance P1 between them is very large, ideally approaching infinity. On the other hand, when insulation resistance P1 between the negative pole of battery and ground potential is abnormal, the resistance value R(P1) becomes small. Similarly, when insulation resistance P2 between the positive pole (terminal B2) of battery B and ground (GND) is maintained normally, the resistance value R(P2) of insulation resistance P2 between them is very large, and when the insulation state is abnormal, the resistance value R(P2) becomes small.

[0021] For example, in Figure 2, the voltage VBATT of battery B is 1000V, and the insulation resistance to the ground potential is normally maintained. If the resistance R(P1) of insulation resistor P1 is 9MΩ, and the resistance P(P2) of insulation resistor P2 is 9MΩ, the voltage V(N) of the negative electrode and the voltage V(P) of the positive electrode of battery B are as follows: V(N)=-R(P1) / {R(P1)+R(P2)}×VBATT=-500V V(P)=+R(P2) / {R(P1)+R(P2)}×VBATT=+500V It becomes.

[0022] If the insulation resistance P1 deteriorates and the resistance R(P1) falls to 1 MΩ, the negative electrode voltage V(N) and the positive electrode voltage V(P) of battery B will be as follows: V(N)=-R(P1) / {R(P1)+R(P2)}×VBATT=-100V V(P)=+R(P2) / {R(P1)+R(P2)}×VBATT=+900V It becomes.

[0023] Similarly, if the insulation resistance of the insulation resistor P2 deteriorates and the resistance value R(P2) falls to 1 MΩ, the negative electrode voltage V(N) and the positive electrode voltage V(P) of the battery B will be as follows: V(N)=-R(P1) / {R(P1)+R(P2)}×VBATT=-900V V(P)=+R(P2) / {R(P1)+R(P2)}×VBATT=+100V It becomes.

[0024] When the resistance values ​​of insulation resistors P1 and P2 decrease in this way, the voltage V(N) of the negative electrode and the voltage V(P) of the positive electrode of battery B change. Therefore, in the example shown in Fig. 2, the resistance state of insulation resistors P1 and P2 is detected by detecting the change in voltage V(N) (voltage at terminal B1). More specifically, the change in voltage V(N1) at node N1 is detected from the output voltage VNOUT at output terminal VNOUT.

[0025] Here, the voltage V(N1) of the node N1 can be expressed as follows: V(N1) = VNOUT =R(2a) / {R(2a)+R(2b)}×VREF+R(2b) / {R(2a)+R(2b)}×V(N) In this way, it can be seen that the output voltage VNOUT at the output terminal VNOUT becomes a signal that corresponds to the voltage V(N) of the negative electrode of the battery B.

[0026] Since the output voltage VNOUT, the reference voltage VREF, the resistance value R(2a) of the first resistive element, and the resistance value R(2b) of the second resistive element are known, the voltage V(N) of the negative electrode of battery B can be calculated using a calculation device (not shown) as follows: V(N)=[1+{R(2A) / R(b)}]×VNOUT-R(2a) / R(2b)×VREF

[0027] As explained above, when the resistance value of insulation resistor P1 decreases, the voltage V(N) increases, and when the resistance value of insulation resistor P2 decreases, the voltage V(N) decreases. Therefore, by monitoring the output signal of terminal VNOUT of the semiconductor device of the present invention, it is possible to easily detect the state of the insulation resistance between the negative electrode (terminal B1) of battery B and ground (GND) and the state of the insulation resistance between the positive electrode (terminal B2) of battery B and ground (GND).

[0028] Furthermore, if necessary, the voltage V(P) of the positive electrode of battery B can be obtained from the output signal of terminal OUT, which is the output signal of the second operational amplifier, and the resistance value R(P1) of insulation resistor P1 and the resistance value R(P2) of insulation resistor P2 can be calculated.

[0029] In the above explanation, an example was given in which the negative pole of battery B was connected to terminal B1 and the positive pole of battery B was connected to terminal B2. However, even if battery B is connected in reverse, it is possible to similarly detect the connection state of the positive or negative pole of battery B to ground (GND).

[0030] In this way, by monitoring the voltage of the output terminal VNOUT of the second operational amplifier 1b, it is possible to detect whether the insulation resistance between the negative electrode of the battery and the ground is normal or whether the insulation resistance between the negative electrode of the battery and the ground or between the positive electrode of the battery and the ground is abnormal. The output terminal VNOUT can be connected to a control circuit (not shown) and configured to perform a predetermined control.

[0031] The first chip 10 equipped with the resistance element of the present invention consists of a resistance element (so-called thin film resistance element) that can be formed in a normal semiconductor device manufacturing process, and for example, when resistance element 2a is formed as 36 MΩ, resistance element 2b as 90 kΩ, resistance element 2c as 36 MΩ, resistance element 2d as 180 kΩ, and resistance element 2e as 180 kΩ, the size of the first chip can be formed to be 3.0 mm x 1.5 mm.

[0032] Fig. 3 shows a schematic diagram of the connection state when the voltage detection circuit described in Fig. 1 is mounted on a lead frame to form the circuit using a first chip 10 consisting of a resistive element and a second chip 20 consisting of an operational amplifier. The first chip 10 has auxiliary wiring 4 arranged thereon to facilitate connection by wire 3. The wire 3 connects the resistor chip electrode formed on the first chip 10, the operational amplifier chip electrode formed on the second chip 20, and the lead terminal. Details will be described later.

[0033] 3, a first chip 10 on which a resistive element is formed and a second chip 20 on which an operational amplifier is formed are mounted on a die pad 5. This lead frame has two lead terminals L1, L2 (corresponding to a first lead row) on the left side of the drawing, and seven lead terminals L4 to L10 and two suspension leads L3, L11 (corresponding to a second lead row) of the die pad 5 on the right side of the drawing.

[0034] In the example described in FIG. 2, the lead terminal L1 is connected to the negative electrode of the battery, and the lead terminal L2 is connected to the positive electrode of the battery. One end of the series circuit of the resistive element 2a and the resistive element 2b is connected to the lead terminal L1, and the other end is connected to a predetermined reference potential from the lead terminal L10. The connection point of the resistive element 2a and the resistive element 2b is connected to the non-inverting input terminal of the first operational amplifier 1a formed on the second chip 20 by using the wire 3. Similarly, the series circuit of the resistive element 2c and the resistive element 2d is connected to the lead terminal L2, and the other end is connected to the reference potential from the lead terminal L10, and the connection point of the resistive element 2c and the resistive element 2d is connected to the inverting input terminal of the first operational amplifier 1a.

[0035] The output terminal of the first operational amplifier 1a formed on the second chip 20 is connected to one end of a resistive element 2e formed on the first chip 10 by a wire 3. The other end of this resistive element 2e is connected to the connection point between resistive elements 2c and 2d, and is also connected to the inverting input terminal of the first operational amplifier 1a formed on the second chip by using a wire 3, so that the resistive element 2e serves as a feedback resistor for the first operational amplifier 1a.

[0036] Furthermore, the connection point between the resistor element 2a and the resistor element 2b is connected to the non-inverting input terminal of the second operational amplifier 1b formed on the second chip 20 by using a wire 3. In the example shown in FIG. 3, the connection point between the resistor element 2a and the resistor element 2b is also connected to the non-inverting terminal of the first operational amplifier 1a, and in order to avoid contact with the wire 3 for this connection, the connection is made via an auxiliary wiring 4 formed separately on the first chip 10. It is to be noted that, if the auxiliary wiring is formed on the second chip instead of on the first chip 10, and the non-inverting input terminal of the first operational amplifier and the non-inverting input terminal of the second operational amplifier are connected by the auxiliary wiring, the number of connections by the wire 3 can be reduced. The output terminal of the second operational amplifier 1b is connected to the inverting input terminal of the second operational amplifier 1b and is also connected to a lead terminal L8.

[0037] The second chip 20 has power supply terminals for the first operational amplifier 1a and the second operational amplifier 1b formed thereon, with the power supply V+ being connected to the lead terminal L5 and the power supply V- being connected to the lead terminal L9, and the power supply voltage being supplied from each lead terminal.

[0038] The output terminal of the first operational amplifier 1a can be directly connected to the lead terminal L4 by a wire 3, but in order to avoid contact with the wire 3 connecting the power supply V+ of the first operational amplifier 1a and the second operational amplifier 1b to the lead terminal L5, the output terminal is connected to the lead terminal L4 by the wire 3 via an auxiliary wiring 4 separately formed on the first chip 10.

[0039] Furthermore, lead terminals L1 and L2 to which a high voltage is applied are spaced apart by a predetermined distance according to the voltage applied to each lead terminal in order to ensure a predetermined creepage distance. In this embodiment, since the voltage applied to the first lead row is greater than the voltage applied to the second lead row, the distance between lead terminals L1 and L2 of the first lead row is set wider than the distance between the lead terminals of the second lead row.

[0040] Furthermore, lead terminal L1 is not only positioned to maintain a creepage distance from lead terminal L2, but is also positioned at a predetermined distance from the other lead terminals L4 to L10. Similarly, lead terminal L2 is positioned at a predetermined distance from the other lead terminals L4 to L10. Similarly, to maintain a creepage distance, suspension leads L3 and L11 of die pad 5 are also positioned on the right side of the drawing (the second lead row side) as shown in FIG.

[0041] Furthermore, in order to prevent discharge between lead terminals L1 and L2 exposed to the outside from the resin-sealed semiconductor device, a resin layer 6 corresponding to the thickness of the lead terminals is filled between the lead terminals. The formation of this resin layer 6 is performed at the same time as the resin sealing of the semiconductor device body, so that the resin layer 6 is also formed between the lead terminals on the second lead row side as shown in FIG.

[0042] When a higher voltage is applied, it is preferable to have a structure in which the die pad 5 is not exposed from the semiconductor device body. Fig. 4 is a diagram showing a schematic cross-sectional structure of a semiconductor device suitable for when a higher voltage is applied. As shown in Fig. 4, by processing the suspension leads so that the back surface of the die pad 5 is not exposed from the sealing resin, it is possible to easily seal the die pad 5 in the semiconductor device body 7.

[0043] 3, the lead terminals L6 and L7 are not connected, but may be used to realize a structure that does not use the auxiliary wiring 4. Of course, it is also possible to make a semiconductor device without these unconnected lead terminals. EXAMPLES

[0044] Next, a second embodiment will be described. In the above-mentioned first embodiment, the resistor chip electrodes formed on the first chip 10 and the lead terminals of the second lead row are directly connected by wires 3. If the wires 3 are long like this, pressure may be applied to the wires 3 during resin sealing, causing problems such as contact with other wires. Therefore, in this embodiment, it is possible to connect the resistor chip electrodes formed on the first chip 10 and the lead terminals L4, L10 of the second lead row via a relay chip 30 as shown in FIG. 5.

[0045] The relay chip 30 can have a structure in which auxiliary wiring 4 similar to the auxiliary wiring 4 formed on the first chip 10 is formed as shown in Fig. 5. Specifically, the relay chip 30 has a structure in which the auxiliary wiring 4 and chip electrodes for connection are formed on both ends of the auxiliary wiring 4 on the surface of the relay chip 30. By providing the auxiliary wiring 4, the length of the wire 3 is shortened, and it is possible to prevent the occurrence of defects such as contact with other wires. EXAMPLES

[0046] Next, a third embodiment will be described. The relay chip 30 is not limited to being used only for connecting the first chip 10 and the lead terminals of the second lead row. For example, as shown in FIG. 6, in addition to connecting the first chip 10 and the lead terminals L4, L10 of the second lead row via the relay chip 30 as in the second embodiment described above, the second chip 20 and the lead terminals of the second lead row can also be connected via the relay chip 30.

[0047] In order to protect the internal circuit of the semiconductor device from surge voltages such as static electricity, it is desirable to provide an ESD protection element as shown in FIG. 6. Although it is easy to form an ESD protection element on the second chip 20 at the same time as forming the first operational amplifier 1a and the second operational amplifier 1b, a thick insulating film is formed on the surface of the first chip 10 since a high voltage is applied to the first chip 10. Specifically, while the oxide film formed on the surface of a general semiconductor device is about 0.7 μm, the semiconductor device of the present invention, to which a high voltage exceeding 1000 V is applied, needs to form a thick oxide film of 5 μm or more. Therefore, if an ESD protection element is formed on the semiconductor substrate under the oxide film, it is necessary to remove the thick oxide film to expose the ESD protection element.

[0048] Therefore, the ESD protection element 8 is formed on the relay chip 30. Such relay chip 30 can be formed by a general semiconductor device manufacturing process, so there is no need to make the oxide film formed on its surface thick, making it suitable for forming the ESD protection element 8. In the semiconductor device having the structure shown in Fig. 6, even if a surge voltage is applied to the lead terminal L10 of the second lead row, the ESD protection element 8 can prevent damage to the resistance element of the first chip 10.

[0049] In the above second and third embodiments, the auxiliary wiring 4 can also be formed on the second chip instead of on the first chip 10, and the auxiliary wiring 4 can connect the non-inverting input terminal of the first operational amplifier and the non-inverting input terminal of the second operational amplifier. [Explanation of symbols]

[0050] 1a: first operational amplifier, 1b: second operational amplifier, 2a to 2e: resistive element, 3: wire, 4: auxiliary wiring, 5: die pad, 6: resin layer, 7: semiconductor device body, 8: ESD protection element, 100: motor drive device, 101: boost converter, 102: smoothing capacitor, 103: inverter circuit, 200: voltage detection circuit, 201: operational amplifier, 202a to 202e: resistance elements

Claims

1. A semiconductor device in which a first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, each chip electrode is connected to a lead terminal for external extraction by wires, and the semiconductor device is sealed with a sealing resin, the lead terminals constitute a first lead row and a second lead row each consisting of a plurality of lead terminals arranged opposite to each other with the die pad interposed therebetween; the first chip has a resistor element as a main component, the resistor element including a first voltage dividing resistor string including a first resistor element and a second resistor element, a second voltage dividing resistor string including a third resistor element and a fourth resistor element, and a feedback resistor including a fifth resistor element; The second chip has an operational amplifier as a main component, and includes a first operational amplifier and a second operational amplifier; the lead terminal of the first lead row is composed of two lead terminals, one of two resistor chip electrodes formed on one side of the rectangular first chip toward the first lead row, the resistor chip electrode being connected to one end of the first voltage-dividing resistor string, and the other lead terminal of the first lead row is connected to the other of the two resistor chip electrodes, the resistor chip electrode being connected to one end of the second voltage-dividing resistor string; Among other resistor chip electrodes arranged on another side opposite to the one side of the two resistor chip electrodes, a resistor chip electrode connected to a first series connection point which is a connection point between the first resistor element and the second resistor element, which outputs a first divided voltage of the first voltage-dividing resistor string, and a resistor chip electrode connected to a second series connection point which is a connection point between the third resistor element and the fourth resistor element, which outputs a second divided voltage of the second voltage-dividing resistor string, are connected to operational amplifier chip electrodes connected to a non-inverting input terminal and an inverting input terminal of the first operational amplifier among operational amplifier chip electrodes arranged on one side of the first chip formed on the rectangular second chip, respectively, and resistor chip electrodes connected to the other end of the first voltage-dividing resistor string and the other end of the second voltage-dividing resistor string, which are connected to a reference voltage, are connected to lead terminals of the second lead string; among the op amp chip electrodes arranged on one side of the first chip side formed on the second chip, resistor chip electrodes connected to both ends of the feedback resistor are connected between an op amp chip electrode connected to the output terminal of the first op amp and an op amp chip electrode connected to the inverting input terminal of the first op amp, a resistor chip electrode connected to the first series connection point is connected to an op amp chip electrode connected to a non-inverting input terminal of the second op amp among the op amp chip electrodes arranged on one side of the first chip side formed on the second chip, and another op amp chip electrode including an op amp chip electrode connected to the output terminal of the second op amp connected to the inverting input terminal of the second op amp is connected to a lead terminal of the second lead row, dividing a voltage applied to a lead terminal of the first lead string by the first voltage dividing resistor string and the second voltage dividing resistor string, outputting the first divided voltage to a non-inverting input terminal of the first operational amplifier, outputting the second divided voltage to an inverting input terminal of the first operational amplifier, outputting an output signal signal processed by the first operational amplifier from a lead terminal of the second lead string, outputting the first divided voltage to the non-inverting input terminal of the second operational amplifier, and outputting an output signal signal signal processed by the second operational amplifier from a lead terminal of the second lead string; the two lead terminals of the first lead row are spaced apart from each other by a distance sufficient to withstand a voltage applied between the lead terminals; A semiconductor device, wherein the sealing resin is filled between at least two lead terminals of the first lead row.

2. 2. The semiconductor device according to claim 1, Auxiliary wiring is disposed on a surface of the first chip facing the second chip, or on a surface of the second chip facing the first chip; a non-inverting input terminal of the first operational amplifier and a non-inverting input terminal of the second operational amplifier are connected to each other via the auxiliary wiring.

3. 3. The semiconductor device according to claim 1, A semiconductor device characterized in that any one of the lead terminals of the second lead row and the resistor chip electrode or the operational amplifier chip electrode are connected via a relay chip mounted on the die pad.

4. 3. The semiconductor device according to claim 1, A semiconductor device characterized in that any one of the lead terminals of the second lead row and the resistor chip electrode or the operational amplifier chip electrode are connected via a relay chip having an ESD protection element mounted on the die pad.

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