Comparator, photoelectric conversion device, and equipment

Abstract

To reduce kickback to an input of a comparator.SOLUTION: A comparator in an embodiment comprises: a first differential transistor and a second differential transistor that form a differential pair; a first load transistor and a second load transistor that are provided in correspondence with the first differential transistor and the second differential transistor; a first cascode transistor that is cascode-connected between the first differential transistor and the first load transistor; and an amplitude limiting element that limits the amplitude of an output signal in an output node between the first load transistor and the first cascode transistor.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a comparator, a photoelectric conversion device, and an instrument. [Background technology]

[0002] Comparators including differential amplifier circuits are used in various devices. The comparator described in Cited Document 1 includes a pair of differential transistors, a pair of load transistors, and one or a pair of cascode transistors cascode-connected to the differential transistors. The cascode transistors can reduce noise by functioning as an isolator. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-90305 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the cascode transistors are in a linear operating state, the potential fluctuation of the main node of the differential transistor increases, causing a problem of increased kickback to the input of the comparator.

[0005] The present invention has been made in consideration of the above-mentioned problems, and has an object to reduce kickback to the input of a comparator. [Means for solving the problem]

[0006] A comparator disclosed in this specification includes a first differential transistor and a second differential transistor forming a differential pair, a first load transistor and a second load transistor provided corresponding to the first differential transistor and the second differential transistor, respectively, a first cascode transistor cascode-connected between the first differential transistor and the first load transistor, and an amplitude limiting element that limits an amplitude of an output signal at an output node between the first load transistor and the first cascode transistor. In the first cascode transistor, when a voltage between the drain and source is Vds, a voltage between the gate and source is Vgs, and a threshold voltage is Vth, the formula Vds>Vgs-Vth is satisfied; and when a gate length of the first cascode transistor is L, a drain current is I, a mobility is μ, a gate oxide film capacitance per unit area is Cox, and a gate width is W,

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[0007] According to the present invention, it is possible to reduce the kickback to the input of the comparator. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram of an imaging device according to a first embodiment. [Diagram 2] FIG. 2 is an equivalent circuit diagram of a pixel in the first embodiment. [Diagram 3] 4 is an equivalent circuit diagram of a comparator in the first embodiment. [Figure 4] 4 is a timing chart illustrating an operation of a comparator in the first embodiment. [Diagram 5] FIG. 11 is an equivalent circuit diagram of a comparator in the second embodiment. [Figure 6] 13 is a timing chart illustrating an operation of a comparator in the third embodiment. [Figure 7] FIG. 13 is an equivalent circuit diagram of a comparator in the fourth embodiment. [Figure 8] FIG. 13 is an equivalent circuit diagram of a comparator in the fifth embodiment. [Figure 9] FIG. 13 is a block diagram of an apparatus according to a sixth embodiment. [Figure 10] FIG. 13 is a block diagram of an apparatus according to a seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiments described below. For example, a part of the configuration of any of the following embodiments may be added to another embodiment, or may be replaced with a part of the configuration of another embodiment.

[0010] [First embodiment] 1 is a block diagram of an image pickup device according to the present embodiment. The image pickup device is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, and includes a pixel section 1, a vertical scanning circuit 2, comparators 3a and 3b, reference signal generating circuits 4a and 4b, counters 5a and 5b, first memories 6a and 6b, second memories 7a and 7b, output circuits 8a and 8b, signal lines 11a and 11b, and current sources 12a and 12b.

[0011] The pixel section 1 includes a plurality of pixels 10 arranged in a two-dimensional array, and each pixel 10 includes a photoelectric conversion section that generates and accumulates a signal charge according to the amount of received light. In this specification, the row direction refers to the horizontal direction in the drawing, and the column direction refers to the vertical direction in the drawing. A microlens and a color filter may be arranged on the pixel 10. The color filters are, for example, primary color filters of red (R), blue (B), and green (Gr, Gb), and are arranged on each pixel 10 according to a Bayer array. Some of the pixels 10 are shielded from light as OB pixels (optical black pixels). The plurality of pixels 10 may include a ranging row in which focus detection pixels that output pixel signals for focus detection are arranged, and a plurality of imaging rows in which imaging pixels that output pixel signals for generating an image are arranged. Signal lines 11a and 11b are arranged for each column of the pixels 10, and the pixels 10 in the same column output pixel signals to the common signal lines 11a and 11b. In this embodiment, the signal lines 11a in the odd columns and the signal lines 11b in the even columns may be connected to different circuits. That is, the pixels 10 in the odd columns are read out by the comparator 3a, the reference signal generating circuit 4a, the counter 5a, the first memory 6a, the second memory 7a, and the output circuit 8a via the signal line 11a. The pixels 10 in the even columns are read out by the comparator 3b, the reference signal generating circuit 4b, the counter 5b, the first memory 6b, the second memory 7b, and the output circuit 8b via the signal line 11b. The number of signal lines arranged for the pixels 10 in one column is not limited to one, and may be multiple, such as 2 to 24.

[0012] The vertical scanning circuit 2 is composed of a shift register, a gate circuit, a buffer circuit, etc., and outputs control signals to the pixels 10 based on a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc., to drive the pixels 10 for each row. Current sources 12a and 12b are connected to signal lines 11a and 11b, and function as load circuits for the pixels 10.

[0013] The comparators 3a and 3b are each composed of a differential amplifier circuit or the like, and a pixel signal is input to an inverting input node, and a reference signal RAMP is input to a non-inverting input node. The comparators 3a and 3b compare the reference signal RAMP with the pixel signal, and output a comparison signal representing the comparison result from an output node.

[0014] The reference signal generating circuits 4a and 4b generate a reference signal (ramp signal) RAMP whose voltage changes depending on time. The reference signal generating circuits 4a and 4b can be configured using various methods such as a capacitive charging and discharging method, a DAC method, and a current steering method. The reference signal RAMP may be not only an upslope where the voltage increases with time, but also a downslope where the voltage decreases with time. The reference signal RAMP may include a plurality of slope waveforms with different voltage change rates per unit time.

[0015] The counters 5a and 5b count up or down in synchronization with the reference signal RAMP. The counters 5a and 5b start counting clock pulses at the same time as the reference signal RAMP of the reference signal generating circuits 4a and 4b starts to change in voltage, and output a count signal. The count signal is supplied to the first memories 6a and 6b. It is also possible to provide a counter for each column of the signal lines 11a and 11b, and supply a common clock pulse to each counter.

[0016] The first memories 6a and 6b receive the comparison results from the comparators 3a and 3b and the count values ​​from the counters 5a and 5b, and latch the count values ​​at the timing when the comparison results are inverted. The count values ​​held in the first memories 6a and 6b represent values ​​obtained by analog-to-digital conversion of the pixel signals. The second memories 7a and 7b can further hold the count values ​​transferred from the first memories 6a and 6b. The first memories 6a and 6b and the second memories 7a and 7b can hold the count values ​​at the time of resetting the pixel 10 and the count values ​​based on the photoelectric conversion of the pixel 10, respectively. The output circuits 8a and 8b can include a horizontal scanning circuit and a signal processing circuit. The horizontal scanning circuit includes a decoder and a shift register, and sequentially reads out the count values ​​held in the first memories 6a and 6b and the second memories 7a and 7b, and outputs them to the signal processing circuit. The signal processing circuit includes a digital signal processor, and performs digital signal processing such as digital gain, digital correlated double sampling, digital offset, and linearity correction. The signal processing circuit also includes a serial output circuit of the LVDS (Low Voltage Differential Signaling) system, and outputs the processed digital signal to the outside of the imaging device at high speed and with low power consumption.

[0017] FIG. 2 is an equivalent circuit diagram of a pixel 10 in this embodiment. The pixel 10 includes a photoelectric conversion unit 100, a transfer transistor 101, a floating diffusion region 102, an amplifying transistor 103, a selection transistor 104, and a reset transistor 105. The following description shows an example in which the transistors constituting the pixel 10 are N-channel MOS transistors. The photoelectric conversion unit 100 is composed of, for example, a photodiode, and performs photoelectric conversion by incident light and accumulation of electric charge. Note that the photoelectric conversion unit 100 is not limited to a photodiode, and may be made of any material that generates a photoelectric effect. The number of photoelectric conversion units 100 per pixel 10 is also not limited, and two, four, or more photoelectric conversion units 100 may be provided so as to share one microlens. Furthermore, by configuring an embedded photodiode, dark current noise can be reduced. The photoelectric conversion unit 100 is provided with a microlens, and light collected by the microlens is incident on the photoelectric conversion unit 100.

[0018] The transfer transistor 101 is provided corresponding to the photoelectric conversion unit 100, and a control signal TX is applied to the gate of the transfer transistor 101 from the vertical scanning circuit 2. When the control signal TX becomes high level, the transfer transistor 101 is turned on (conductive state), and the signal charge accumulated in the photoelectric conversion unit 100 is transferred to a floating diffusion region 102 formed in the gate of the amplification transistor 103. When the control signal TX becomes low level, the transfer transistor 101 is turned off (non-conductive state). The floating diffusion region 102 converts the signal charge into a voltage, and the amplification transistor 103 outputs a signal voltage according to the gate voltage from the source to the signal lines 11a and 11b via the selection transistor 104. The drain of the amplification transistor 103 is connected to a power supply VDD.

[0019] The source of the reset transistor 105 is connected to the floating diffusion region 102, the drain is connected to a power supply VDD, and a control signal RES is applied to the gate from the vertical scanning circuit 2. When the control signal RES becomes high level, the reset transistor 105 is turned on, and the voltage of the power supply VDD is supplied to the floating diffusion region 102. The selection transistor 104 is provided between the amplification transistor 103 and signal lines 11a and 11b, and a control signal SEL is applied to the gate of the selection transistor 104 from the vertical scanning circuit 2. When the control signal SEL becomes high level, the amplification transistor 103 and the signal lines 11a and 11b are electrically connected. Current sources 12a and 12b are connected to the signal lines 11a and 11b, and the current sources 12a and 12b supply a constant bias current to the source of the amplification transistor 103 via the signal lines 11a and 11b.

[0020] 2, a plurality of selection transistors may be provided in each pixel 10. Furthermore, an additional capacitance may be provided in the floating diffusion region, and the capacitance of the floating diffusion region may be selectable.

[0021] 3 is a block diagram of a comparator in this embodiment. The comparator 3 (3a, 3b) includes a current source 300, a first differential transistor 301 of N-channel MOS, a second differential transistor 302 of N-channel MOS, a first load transistor 311 of P-channel MOS, a second load transistor 312 of P-channel MOS, a first cascode transistor 321 of N-channel MOS, a second cascode transistor 322 of N-channel MOS, an amplitude limiting transistor 330 of P-channel MOS, a source follower transistor 370 of P-channel MOS, and a current source 371.

[0022] The differential transistors 301 and 302 form a differential pair. A reference signal RAMP is input to the gate of the differential transistor 301, and a pixel signal is input to the gate of the differential transistor 302. The sources of the differential transistors 301 and 302 are each connected to the ground line GND via a current source 300.

[0023] The load transistors 311 and 312 form a pair and are provided corresponding to the differential transistors 301 and 302. The load transistors 311 and 312 form a current mirror circuit, and the gates of the load transistors 311 and 312 are connected to each other and to the drain of the load transistor 312. The sources of the load transistors 311 and 312 are connected to a power supply VDD.

[0024] The cascode transistors 321 and 322 form a pair and are arranged between the differential transistors 301 and 302 and the load transistors 311 and 312, respectively. That is, the source of the cascode transistor 321 is connected to the drain of the differential transistor 301, and the drain of the cascode transistor 321 is connected to the drain of the load transistor 311. Similarly, the source of the cascode transistor 322 is connected to the drain of the differential transistor 302, and the drain of the cascode transistor 322 is connected to the drain of the load transistor 312. A predetermined bias voltage Vbias is applied to the gates of the cascode transistors 321 and 322.

[0025] The limiting transistor 330 is provided at the output of the differential stage, that is, at the output node A between the load transistor 311 and the cascode transistor 321. The gate and drain of the limiting transistor 330 are connected to the drain of the load transistor 311, and the source of the limiting transistor 330 is connected to the power supply VDD. The limiting transistor 330 prevents the cascode transistor 321 from entering a linear operating state by limiting the amplitude at the output node A. This suppresses the potential fluctuation of the drain of the differential transistor 301, making it possible to reduce kickback to the input of the comparator 3.

[0026] The source follower transistor 370 is provided at the output node A of the differential stage. The gate of the source follower transistor 370 is connected to the output node A, and the source of the source follower transistor 370 is connected to a power supply VDD. The drain of the source follower transistor 370 is connected to a ground line GND via a current source 371, and is capable of outputting a signal OUT.

[0027] 4 is a timing chart showing the operation of the comparator in this embodiment, and shows potential changes of the reference signal RAMP, the pixel signal, the output node A, and the drain 301d and source 301s of the differential transistor 301. The solid line graph shows the operation in this embodiment, and the dashed line graph shows the operation of a comparative example in which the amplitude limiting transistor 330 is not provided.

[0028] First, the operation of the comparative example will be described. Between times t1 and t2, the potential of the reference signal RAMP is higher than the potential of the pixel signal, and a current flows through the differential transistor 301. The potential of the drain 301d of the differential transistor 301 and the potential of the output node A of the differential stage drop close to the potential of the source 301s.

[0029] At time t2, the potential of the reference signal RAMP starts to decrease, and the current in the differential transistor 301 also starts to decrease. From time t2 to t3, the cascode transistor 321 operates linearly, and the potential of the drain 301d of the differential transistor 301 increases together with the potential of the output node A of the differential stage. Here, parasitic capacitance exists between the gate and drain of the differential transistor 301. Therefore, the potential fluctuation of the drain 301d causes the potential fluctuation of the gate via the parasitic capacitance, which interferes with the reference signal RAMP, and may increase the kickback to the input of the comparator 3.

[0030] After time t3, when the potential difference between the output node A of the differential stage and the drain 301d, i.e., the drain-source voltage Vds of the cascode transistor 321, becomes large enough to saturate the cascode transistor 321, the potential of the drain 301d becomes substantially constant. In other words, even if the potential of the output node A of the differential stage changes, the potential of the drain 301d does not change.

[0031] Next, the operation of this embodiment will be described. At times t1 to t2, a current flows through the differential transistor 301, and the potential of the output node A of the differential stage drops. Since the amplitude limiting transistor 330 is provided at the output node A, the drop in the potential of the output node A is suppressed by the amplitude limiting transistor 330. At this time, the potential of the output node A can be determined by the gate-source voltage Vgs of the amplitude limiting transistor 330. In this embodiment, the potential of the output node A and the potential of the drain 301d are higher than the respective potentials in the comparative example. The voltage between the drain and source of the cascode transistor 321 becomes large enough for the cascode transistor 321 to perform a saturated operation. At this time, in the cascode transistor 321, the drain-source voltage Vds, the gate-source voltage Vgs, and the threshold voltage Vth can satisfy the following formula (1). Vds>V gs -V th (1)

[0032] From time t2 to t3, as the potential of the reference signal RAMP decreases, the potential of the output node A increases, but the cascode transistor 321 maintains a saturated operation state (equation (1)), and the potential of the drain 301d of the differential transistor 301 remains constant. Therefore, even if a parasitic capacitance exists between the gate and drain of the differential transistor 301, the potential fluctuation of the gate is reduced, and interference with the reference signal RAMP can be suppressed. Even after time t3, the cascode transistor 321 maintains a saturated operation state, and the potential of the drain 301d remains constant. It is desirable that the above-mentioned equation (1) is satisfied over the range from the minimum value to the maximum value of the output signal at the output node A.

[0033] In this embodiment, by providing the amplitude limiting transistor 330, it is possible to prevent the cascode transistor 321 from entering a linear operation state, and to reduce kickback to the input node of the comparator 3. In particular, when the load transistors 311 and 312 of the current mirror are provided, the lower limit of the output node A of the differential stage falls close to the potential of the sources of the differential transistors 301 and 302, and the cascode transistor 321 is more likely to operate linearly. Even in such a case, the amplitude limiting transistor 330 in this embodiment effectively suppresses the linear operation of the cascode transistor 321, and it is possible to reduce kickback to the input of the comparator 3.

[0034] In the present embodiment, the amplitude limiting element is described by taking the amplitude limiting transistor 330 as an example, but the amplitude limiting element may be a diode element, a clip circuit, or the like.

[0035] [Second embodiment] Next, the comparator and the imaging device according to the second embodiment will be described, focusing on the configurations that differ from those of the first embodiment.

[0036] 5 is a block diagram of the comparator in this embodiment. In this embodiment, in addition to the amplitude limiting transistor 330, a transistor 332 is provided. The transistor 332 is a P-channel MOS and pairs with the amplitude limiting transistor 330. The gate and drain of the transistor 332 are connected to the drain and gate of the load transistor 312, and the source of the transistor 332 is connected to the power supply VDD.

[0037] In the first embodiment, when the power supply voltage fluctuates due to a disturbance, the voltage at the output node A of the differential stage may fluctuate due to the amplitude limiting transistor 330. In this embodiment, the transistor 332 generates a potential fluctuation also at the gates of the load transistors 311 and 312, making it possible to cancel the effect of the power supply voltage fluctuation at the output node A.

[0038] Also in this embodiment, the amplitude limiting transistor 330 effectively suppresses the linear operation of the cascode transistor 321, and the kickback to the input of the comparator 3 can be reduced.

[0039] [Third embodiment] Next, a description will be given of a comparator and an imaging device in the third embodiment. The configuration of the comparator in this embodiment is similar to that in the second embodiment, but in this embodiment, a description will be given of desirable circuit constants.

[0040] As described above, by saturating the cascode transistor 321, the kickback to the input of the comparator 3 can be reduced. In order for the cascode transistor 321 to operate in saturation, it is desirable that the above formula (1) be satisfied. Moreover, formula (1) can be expressed as the following formula (2).

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[0041] In formula (2), L represents the gate length, I represents the drain current, μ represents the mobility, Cox represents the gate oxide film capacitance per unit area, and W represents the gate width. By shortening the gate length L, the drain-source voltage Vds required for the saturation operation of the cascode transistor 321 can be suppressed. For example, by making the gate length L of the cascode transistor 321 shorter than the gate length L of the differential transistor 301, the drain-source voltage Vds of the cascode transistor 321 can be suppressed. The differential transistor 302 and the cascode transistor 322 can be configured in the same manner as the differential transistor 301 and the cascode transistor 321.

[0042] 6 is a timing chart showing the operation of the comparator in this embodiment, and shows potential changes of the reference signal RAMP, the pixel signal, the output node A, and the drain 301d and source 301s of the differential transistor 301. The solid line graph shows the operation in this embodiment, and the dashed line graph shows the operation of a comparative example in which the cascode transistor 321 is not provided.

[0043] First, the operation of the comparative example will be described. Between times t1 and t2, the potential of the output node A of the differential stage drops. Here, if the cascode transistors 321 and 322 are not provided, there is no need to ensure the drain-source voltage Vds of the cascode transistors 321 and 322. Therefore, the potential of the output node A can be lowered without limiting the amplitude of the output node A of the differential stage by the amplitude-limiting transistor 330. Between times t2 and t3, it can be confirmed that the potential of the output node A of the differential stage rises from a sufficiently low potential, and the rate of change of the potential, i.e., the slew rate (slope), becomes large.

[0044] On the other hand, when the cascode transistors 321 and 322 are provided, the voltage drop of the output node A of the differential stage is suppressed by the amplitude limiting transistor 330 at times t1 to t2, and the drain-source voltage Vds of the cascode transistor 321 is in a saturated operation state. In this embodiment, the gate length L of the cascode transistor 321 is configured to be shorter than the gate length L of the differential transistor 301. Therefore, the drain-source voltage Vds for the saturated operation of the cascode transistor 321 can be reduced, and the voltage of the output node A of the differential stage can be reduced. At times t2 to t3, the slew rate of the voltage of the output node A can be sufficiently increased, and high-speed operation can be realized. Therefore, according to this embodiment, it is possible to increase the slew rate of the output signal while avoiding the linear operation of the cascode transistor 321.

[0045] In the present embodiment, the gate length L of the cascode transistor 321 is set shorter than the gate length L of the differential transistor 301, but the constants other than the gate length L in the formula (2) may be changed as appropriate. For example, the gate width W may be increased to set the drain-source voltage Vds small while keeping the cascode transistor 321 in a saturated operation state.

[0046] [Fourth embodiment] Next, the comparator and the imaging device according to the fourth embodiment will be described, focusing on the configurations that differ from those of the second embodiment.

[0047] FIG. 7 is a block diagram of the comparator in this embodiment. In this embodiment, the gates of the cascode transistors 321 and 322 are connected to the power supply VDD, as is the source of the amplitude limiting transistor 330. When the power supply voltage drops, the potential of the output node A of the differential stage is lowered by the amplitude limiting transistor 330. The potential of the drain of the cascode transistor 321 drops, and the cascode transistor 321 can enter a linear operation state. In this embodiment, the potential of the gate of the cascode transistor 321 drops together with the power supply voltage, and the gate-source voltage Vgs of the cascode transistor 321 also becomes smaller. For this reason, the above-mentioned formula (1), i.e., [Vds>V gs -V th ] is also reduced, and the cascode transistor 321 can maintain a saturated operation state. Therefore, according to this embodiment, even when the power supply voltage is reduced, the linear operation of the cascode transistor 321 can be effectively suppressed, and the kickback to the input of the comparator 3 can be reduced.

[0048] [Fifth embodiment] The comparator is not limited to the above embodiment and may have various configurations. The following describes this embodiment, focusing on the configuration that differs from the fourth embodiment.

[0049] 8 is an equivalent circuit diagram of the comparator in this embodiment. The comparator 3 in FIG. 8 may further include a first capacitance 341, a second capacitance 342, a first switch 351, a second switch 352 for auto-zero operation, and an amplifier 372 for the reference signal RAMP. The amplifier 372 functions as a buffer amplifier for the reference signal RAMP, and may be configured by, for example, a source follower circuit. By providing the amplifier 372, it is possible to prevent the potential fluctuation at the gate of the differential transistor 301 from affecting the other comparators 3. An amplifier may also be provided at the gate of the differential transistor 302.

[0050] The capacitors 341 and 342 are connected in series to the gates of the differential transistors 301 and 302, respectively. A reference signal RAMP output from the amplifier 372 is input to the gate of the differential transistor 301 via the capacitor 341. In addition, a pixel signal is input to the gate of the differential transistor 302 via the capacitor 342. The switch 351 makes the gate of the differential transistor 301 and the drain of the load transistor 311 conductive or non-conductive, and the switch 352 makes the gate of the differential transistor 302 and the drain of the load transistor 312 conductive or non-conductive. The switches 351 and 352 are controlled to be turned on or off by a control signal CRES1, and can compensate for the offset of the potential of each gate of the differential transistors 301 and 302 to realize an auto-zero operation.

[0051] In this embodiment as well, it is possible to prevent the cascode transistor 321 from entering a linear operating state, and to reduce the kickback to the input node of the comparator 3.

[0052] [Sixth embodiment] The solid-state imaging device according to the above-described embodiment can be applied to various devices. Examples of the devices include digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and surveillance cameras. Fig. 9 shows a block diagram of a digital still camera as an example of the device.

[0053] The device 7 shown in FIG. 9 includes a barrier 706, a lens 702, an aperture 704, an imaging device 70 (an example of a photoelectric conversion device), a signal processing unit (processing device) 708, a timing generating unit 720, an overall control / calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, the lens 702, and the aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens, and the lens 702 forms an optical image of a subject on the imaging device 70. The aperture 704 varies the amount of light passing through the lens 702. The imaging device 70 is configured as in the above-mentioned embodiment, and converts the optical image formed by the lens 702 into image data (image signal). Here, it is assumed that an AD (analog-digital) conversion unit is formed on the semiconductor substrate of the imaging device 70. The signal processing unit 708 performs various corrections on the imaging data output from the imaging device 70 and compresses the data. The timing generating unit 720 outputs various timing signals to the imaging device 70 and the signal processing unit 708. The overall control and calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to the recording medium 714, and the recording medium 714 is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer or the like. Timing signals and the like may be input from outside the device. The device 7 may further include a display device (monitor, electronic viewfinder, etc.) that displays information obtained by the photoelectric conversion device. The device includes at least a photoelectric conversion device. Furthermore, the device includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. The mechanical device is a movable part (for example, a robot arm) that operates by receiving a signal from the photoelectric conversion device.

[0054] In this embodiment, the imaging device 70 and the AD conversion unit are provided on different semiconductor substrates, but the imaging device 70 and the AD conversion unit may be formed on the same semiconductor substrate. Also, the imaging device 70 and the signal processing unit 708 may be formed on the same semiconductor substrate.

[0055] Moreover, each pixel may include a first photoelectric conversion unit and a second photoelectric conversion unit. The signal processing unit 708 may be configured to process a pixel signal based on the charge generated in the first photoelectric conversion unit and a pixel signal based on the charge generated in the second photoelectric conversion unit, and to acquire distance information from the imaging device 70 to the subject.

[0056] [Seventh embodiment] FIG. 10(a) and FIG. 10(b) are block diagrams of devices related to the vehicle-mounted camera in this embodiment. The device 8 has the imaging device 80 (an example of a photoelectric conversion device) of the above-mentioned embodiment and a signal processing device (processing device) that processes a signal from the imaging device 80. The device 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the imaging device 80, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the device 8. The device 8 also has a distance measurement unit 803 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0057] The device 8 is connected to a vehicle information acquisition device 810, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. In addition, the device 8 is connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 804. In addition, the device 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the judgment result of the collision judgment unit 804. For example, when the judgment result of the collision judgment unit 804 indicates that there is a high possibility of a collision, the control ECU 820 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm such as a sound, displaying alarm information on a screen of a car navigation system, etc., and applying vibrations to a seat belt or steering wheel. The device 8 functions as a control means that controls the operation of controlling the vehicle as described above.

[0058] In this embodiment, the surroundings of the vehicle, for example the front or rear, are imaged by the device 8. FIG. 10(b) shows the device when imaging the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810, which serves as an imaging control means, sends instructions to the device 8 or the imaging device 80 to perform the operations described in the first to seventh embodiments. This configuration can further improve the accuracy of distance measurement.

[0059] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the device is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present invention can be applied to devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, in addition to moving bodies.

[0060] [Other embodiments] The present invention is not limited to the above-described embodiments and can be modified in various ways. For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of any of the embodiments is replaced with another embodiment, is also an embodiment of the present invention.

[0061] In the above embodiment, a pair of cascode transistors 321, 322 are provided, but only the cascode transistor 321 on the output node A side may be provided.

[0062] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0063] 10 pixels 3a, 3b comparator 301, 302 Differential transistor 311, 312 Load transistor 321, 322 Cascode transistor 330 Amplitude limiting transistor

Claims

1. a first differential transistor and a second differential transistor forming a differential pair; a first load transistor and a second load transistor provided corresponding to the first differential transistor and the second differential transistor, respectively; a first cascode transistor cascode-connected between the first differential transistor and the first load transistor; an amplitude limiting element for limiting the amplitude of an output signal at an output node between the first load transistor and the first cascode transistor; Equipped with In the first cascode transistor, when the voltage between the drain and the source is Vds, the voltage between the gate and the source is Vgs, and the threshold voltage is Vth, Vds>Vgs-Vth The formula is satisfied, In the first cascode transistor, when the gate length is L, the drain current is I, the mobility is μ, the gate oxide film capacitance per unit area is Cox, and the gate width is W, [0010] The formula is satisfied, A comparator, wherein the gate length L of the first cascode transistor is shorter than the gate length of the first differential transistor.

2. A differential pair including a first differential transistor and a second differential transistor; a first load transistor and a second load transistor provided corresponding to the first differential transistor and the second differential transistor, respectively; a first cascode transistor cascode-connected between the first differential transistor and the first load transistor; an amplitude limiting element for limiting the amplitude of an output signal at an output node between the first load transistor and the first cascode transistor; Equipped with In the first cascode transistor, when the voltage between the drain and the source is Vds, the voltage between the gate and the source is Vgs, and the threshold voltage is Vth, Vds>Vgs-Vth The formula is satisfied, In the first cascode transistor, when the gate length is L, the drain current is I, the mobility is μ, the gate oxide film capacitance per unit area is Cox, and the gate width is W, [0025] The formula is satisfied, A comparator, wherein the gate width W of the first cascode transistor is greater than the gate width of the first differential transistor.

3. 3. The comparator according to claim 1, wherein the amplitude limiting element is an amplitude limiting transistor, the gate and drain of the amplitude limiting transistor being connected to the output node.

4. 4. The comparator according to claim 3, wherein a predetermined bias voltage is applied to the gate of said first cascode transistor.

5. 5. A comparator as claimed in claim 3, wherein the gate of said first cascode transistor is connected to the source of said limiting transistor.

6. 6. The comparator according to claim 3, wherein the sources of the first load transistor, the second load transistor and the amplitude limiting transistor are connected to a power supply.

7. 7. The comparator according to claim 3, further comprising a second cascode transistor cascode-connected between the second differential transistor and the second load transistor.

8. 8. The comparator of claim 7, wherein the gate of the first cascode transistor and the gate of the second cascode transistor are connected together.

9. Further comprising another transistor paired with the amplitude limiting transistor, a source of the other transistor is connected to a source of each of the first load transistor, the second load transistor, and the amplitude limiting transistor; 9. The comparator according to claim 3, wherein the gate and drain of the other transistor are connected to the drain of the second load transistor.

10. 10. The comparator according to claim 1, wherein the formula (Vds>Vgs-Vth) is satisfied over the range from the minimum value to the maximum value of the output signal.

11. a first capacitance connected in series to the gate of the first differential transistor; a second capacitance connected in series to the gate of the second differential transistor; a first switch that connects the gate of the first differential transistor and the drain of the first load transistor to each other, or to each other; 11. The comparator according to claim 3, further comprising a second switch that connects or disconnects the gate of the second differential transistor and the drain of the second load transistor.

12. 12. The comparator according to claim 3, wherein a signal is input to the gate of the first differential transistor via a buffer amplifier.

13. A comparator according to any one of claims 1 to 12; A plurality of pixels arranged in an array and outputting pixel signals in response to incident light; a reference signal generating circuit that generates a reference signal whose voltage changes depending on time; Equipped with The photoelectric conversion device according to claim 1, wherein the comparator outputs a signal representing a result of comparison between the pixel signal and the reference signal.

14. The photoelectric conversion device according to claim 13 ; an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; A storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

15. The pixel includes a plurality of photoelectric conversion units, The device according to claim 14 , wherein the processing device processes the pixel signals generated by each of the plurality of photoelectric conversion units, and obtains distance information from the photoelectric conversion unit to a subject.

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