Automated transistor-level placement for integrated circuit design.

Abstract

In some embodiments, a computer-implemented method for designing an integrated circuit using transistor placement optimization is provided. A computing system receives a specification for the integrated circuit. The specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors. The computing system determines an initial position and orientation on a canvas for each transistor in the plurality of transistors. The computing system uses an objective function based at least in part on the initial positions and orientations of the plurality of transistors to generate a coarse placement having globally optimized positions and orientations of the plurality of transistors. The computing system uses local refinement techniques to optimize the coarse placement to generate a fine placement, and uses routing techniques to generate a routing for the fine placement to generate a completed design.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Patent Application No. 17 / 957,621, filed September 30, 2022, and U.S. Provisional Application No. 63 / 310,675, filed February 16, 2022, the contents of both of which are incorporated herein by reference.

[0002] The present disclosure relates generally to techniques of integrated circuit design, and more particularly, but not exclusively, to iterative optimization of transistor placement in an integrated circuit layout. [Background technology]

[0003] Traditional approaches to integrated circuit design include a rules-based placement engine, which refers to one or more software applications that determine optimal or near-optimal placement of standard cells or hard macros, rather than individual transistors. In the context of integrated circuit design, a standard cell represents a group of transistors and interconnect structures that provide a Boolean logic function (AND, OR, XOR, XNOR, inverter, etc.) or a memory function (flip-flop or latch). Similarly, a "hard macro" refers to a block-level placement of transistors that has been pre-verified (e.g., in terms of design rules) for a given semiconductor manufacturing process. Thus, traditional transistor placement operates at a hierarchical level above individual transistors, where each object to be placed is either a standard cell or a hard macro, and each net represents a logical connection between various input / output pins associated with an object (cell or macro) or input / output of the design, rather than an individual transistor. Thus, individual transistors are placed relative to the placement of their respective standard cells or macros. Furthermore, for transistors that do not host connections outside of the standard cells or macros, the net routing has already been determined.

[0004] Analytical formulations such as quadratic and nonlinear programming have become mainstream solutions within commercial toolchains for dealing with standard cell-based designs. The focus on standard cell or hard macro-level placement leaves unmet the need for formulations that directly and automatically facilitate design at the transistor level. Transistor-level placement has been considered for standard cell and hard macro layouts, where standard cells are typically relatively small (<100) in terms of transistor count, object count, and / or net count. Yet, conventional techniques for rule-based placement engines have largely ignored analytical formulations in favor of graph-based search or combinatorial solvers. Thus, there remains a need for a transistor-level placement engine for integrated circuit design that is configured to optimize individual transistor placements with respect to one or more analytical objectives and that can operate automatically (e.g., without human intervention). Summary of the Invention [Means for solving the problem]

[0005] In some embodiments, a computer-implemented method for designing an integrated circuit using transistor placement optimization is provided. A computing system receives a specification for the integrated circuit. The specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors. The computing system determines an initial position and orientation on a canvas for each transistor in the plurality of transistors. The computing system uses an objective function based at least in part on the initial positions and orientations of the plurality of transistors to generate a coarse placement having globally optimized positions and orientations of the plurality of transistors. The computing system uses a local refinement technique to optimize the coarse placement to generate a fine placement. The computing system uses a routing technique to generate a routing for the fine placement to generate a completed design. The computing system stores the completed design in a layout data store.

[0006] In some embodiments, a non-transitory computer-readable medium having computer-executable instructions stored thereon is provided, the instructions, in response to execution by one or more processors of the computing system, causing the computing system to perform operations for designing an integrated circuit using transistor placement optimization, the operations including receiving, by the computing system, a specification for the integrated circuit, the specification including a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors, determining, by the computing system, an initial position and orientation on a canvas for each transistor in the plurality of transistors, using, by the computing system, an objective function based at least in part on the initial positions and orientations of the plurality of transistors to generate a coarse placement having globally optimized positions and orientations of the plurality of transistors, using, by the computing system, local refinement techniques to optimize the coarse placement to generate a fine placement, using routing techniques to generate a routing for the fine placement to generate a completed design, and storing, by the computing system, the completed design in a layout data store.

[0007] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, in which like reference numerals refer to like parts throughout the various views unless otherwise specified. Where appropriate, not every instance of an element has been labeled to avoid cluttering the drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles being described. [Brief description of the drawings]

[0008] [Figure 1] 2 is a schematic diagram of an NMOS and PMOS transistor according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic diagram of a transistor placement matrix according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is a block diagram illustrating aspects of a non-limiting exemplary embodiment of a layout computing system according to various aspects of the present disclosure. [Figure 4] 1 is a flow chart illustrating a non-limiting exemplary embodiment of a method for laying out a plurality of transistors for fabricating an integrated circuit in accordance with various aspects of the present disclosure. [Diagram 5] 1 is a schematic diagram of a non-limiting exemplary embodiment of a canvas after an initial position of a transistor has been determined, in accordance with various aspects of the present disclosure. [Figure 6] 1 illustrates a non-limiting exemplary embodiment of a procedure for generating a rough layout using analysis techniques, in accordance with various aspects of the present disclosure. [Figure 7] FIG. 2 is a schematic diagram of a non-limiting exemplary embodiment of a layout in a discrete coordinate space, in accordance with various aspects of the present disclosure. [Figure 8] 4 is a flow chart illustrating a non-limiting exemplary embodiment of a procedure for generating a rough layout using a simulated annealing technique, in accordance with various aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Embodiments of the computer-implemented method for transistor-level object placement described herein provide greater flexibility and control over transistor placement in integrated circuit layouts compared to standard cell and hard macro-based approaches, resulting in improved optimization of custom integrated circuits at the level of individual or arbitrary groupings of transistors.

[0010] 1 is a schematic diagram of NMOS and PMOS transistors according to an embodiment of the present disclosure. Transistor placement techniques can be implemented automatically and can include large-scale transistor-level placement techniques to achieve a globally optimized solution. In such a formulation, it can be assumed that each object can be a transistor or any group of transistors (rather than being restricted to functional or manufacturable groupings), and each net represents a logical connection between various input / output pins associated with a transistor or group of transistors or inputs / outputs of the design.

[0011] As shown in FIG. 1, the transistors are multi-terminal devices, such as the three-terminal NMOS and PMOS transistors shown. As part of the design, each terminal of the transistor is connected to a respective net, such as n1, n2, ... n5. In some embodiments, an individual net may be connected to multiple transistors, as shown by n2. In this manner, a group of n transistors may be associated with a number of nets, from n to 3n. The groups of transistors, as opposed to standard cells or hard macros, may describe a hierarchical optimization strategy that segments a transistor placement matrix (e.g., the transistor placement matrix of FIG. 2) into smaller groups, for example, for parallelization or optimization of computational resources (e.g., in the context of distributed computing systems, graphical processing units (GPUs), or other parallel computing resources).

[0012] As shown, material properties of individual transistors can also inform the placement decisions described with reference to Figure 2. For example, transistors can be N-type or P-type (e.g., NMOS or PMOS), and these two types of transistors can be used in a single integrated circuit to create a CMOS integrated circuit. As shown in Figure 2, transistors of a given type can be confined to one or more particular regions of the transistor placement matrix.

[0013] 2 is a schematic diagram of a transistor placement matrix according to an embodiment of the present disclosure. A transistor placement matrix is ​​an example of a discretized data structure that organizes a set of transistors according to coordinates in one or more dimensions and / or sub-dimensions (sub-dimensions refer to coded dimensions that constrain the placement of a given transistor to a subset of coordinates) of a coordinate space. The coordinate space can then be mapped to a physical space on a CMOS substrate as part of the fabrication of a semiconductor integrated circuit. Thus, by optimizing the placement of transistors in this discretized coordinate space, the layout of transistors and nets in the integrated circuit can be improved with respect to one or more objectives.

[0014] As shown, the transistor placement matrix can correspond to a discretized Cartesian coordinate space (e.g., a quantized xy space). In this scheme, any i-th transistor is (x i ,y i As shown, one set of transistors may include an NMOS 202 with coordinates (0,0) shown in solid lines and a PMOS 204 with coordinates (3,2) shown in dashed lines.

[0015] Optimizing the locations of a set of transistors in a transistor placement matrix can help improve the performance, reliability, cost, and manufacturability of the resulting integrated circuit. However, typical transistor-level optimization techniques use combinatorial methods that do not scale when the total number of transistors is small (e.g., on the order of 100 transistors), which is perhaps one of the reasons why optimization techniques have not been widely applied in the past at the transistor level rather than at the low-count cell level. Although optimization techniques can still be used on small partitions of the transistor placement matrix, it is unlikely that a globally optimal solution will be found unless the entire transistor placement matrix is ​​considered at once.

[0016] In an embodiment of the present disclosure, an optimization technique is provided that can be efficiently applied to all components specified in the netlist to generate an optimal rough layout in a discretized placement matrix (instead of requiring operations on smaller partitions). The rough layout may then be partitioned and processed using conventional methods to create an optimal layout for providing to a fabrication system. A better overall layout is achieved by first creating the rough layout using techniques that consider an optimal solution for the entire layout before optimizing the partitions.

[0017] FIG. 3 is a block diagram illustrating aspects of a non-limiting exemplary embodiment of a layout computing system according to various aspects of the disclosure. The illustrated layout computing system 310 may be implemented by any computing device or collection of computing devices, including, but not limited to, one or more of a desktop computing device, a laptop computing device, a mobile computing device, a server computing device, a computing device of a cloud computing system, and / or combinations thereof. The layout computing system 310 is configured to receive a netlist specifying a plurality of components and optimize a layout of the components in the netlist. In some embodiments, the layout computing system 310 may provide a user interface that enables manual modification of the optimized layout. In some embodiments, the layout computing system 310 may provide the optimized layout to a fabrication system for fabricating the represented integrated circuit.

[0018] As shown, the layout computing system 310 includes one or more processors 302 , one or more communication interfaces 304 , a layout data store 308 , and a computer-readable medium 306 .

[0019] In some embodiments, the processor 302 may include any suitable type of general-purpose computer processor. In some embodiments, the processor 302 may include one or more special-purpose computer processors or AI accelerators optimized for specific computing tasks, including, but not limited to, a graphical processing unit (GPU), a visual processing unit (VPT), ​​and a tensor processing unit (TPU).

[0020] In some embodiments, communication interface 304 includes one or more hardware and / or software interfaces suitable for providing a communications link between components. Communication interface 304 may support one or more wired communication technologies (including but not limited to Ethernet, FireWire, and USB), one or more wireless communication technologies (including but not limited to Wi-Fi, WiMAX, Bluetooth, 2G, 3G, 4G, 5G, and LTE), and / or combinations thereof.

[0021] As shown, the computer-readable medium 306 stores logic that, in response to execution by the one or more processors 302, causes the layout computing system 310 to provide a layout management engine 312, an analytical layout engine 314, a simulated annealing layout engine 316, and a user interface engine 318.

[0022] As used herein, a "computer-readable medium" refers to a removable or non-removable device implementing any technology capable of storing information in a volatile or non-volatile manner to be read by a processor of a computing device, including, but not limited to, a hard drive, a flash memory, a solid-state drive, a random access memory (RAM), a read-only memory (ROM), a CD-ROM, a DVD or other disk storage device, a magnetic cassette, a magnetic tape, and a magnetic disk storage device.

[0023] In some embodiments, the layout management engine 312 is configured to receive the netlist and manage the layout optimization process performed by other components of the layout computing system 310 prior to storing the optimized layout in the layout data store 308. In some embodiments, the user interface engine 318 is configured to generate a visual presentation of the optimized layout stored in the layout data store 308 and to receive and process manual adjustments to the optimized layout.

[0024] In some embodiments, the analysis layout engine 314 is configured to generate a rough layout using analysis techniques. In some embodiments, the simulated annealing layout engine 316 is configured to generate a rough layout using simulated annealing techniques. Because analysis and simulated annealing techniques are alternatives, in some embodiments, only one or the other of the analysis layout engine 314 and the simulated annealing layout engine 316 may be present.

[0025] The composition of each of these components is further described below.

[0026] As used herein, an "engine" refers to logic embodied in hardware or software instructions that may be written in one or more programming languages, including, but not limited to, C, C++, C#, COBOL, JAVA™, PHP, Perl, HTML, CSS, JavaScript, VBScript, ASPX, Go, and Python. An engine may be compiled into an executable program or written in an interpreted programming language. A software engine may be called from other engines or from itself. In general, an engine as described herein refers to a logical module that may be merged with other engines or split into sub-engines. An engine may be implemented by logic stored in any type of computer-readable medium or computer storage device, and stored and executed in one or more general-purpose computers, thus creating an engine or a special-purpose computer configured to provide its functionality. An engine may be implemented by logic programmed into an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or another hardware device.

[0027] As used herein, a "data store" refers to any suitable device configured to store data for access by a computing device. One example of a data store is a reliable, high-speed relational database management system (DBMS) running on one or more computing devices and accessible over a high-speed network. Another example of a data store is a key-value store. However, any other suitable storage technique and / or device capable of quickly and reliably providing stored data in response to a query may be used, and the computing devices may be accessible locally rather than over a network, or may be provided as a cloud-based service. A data store may also include data stored in an organized manner on a computer-readable storage medium, such as a hard disk drive, flash memory, RAM, ROM, or any other type of computer-readable storage medium. Those skilled in the art will recognize that the separate data stores described herein may be combined into a single data store and / or the single data store described herein may be separated into multiple data stores without departing from the scope of the present disclosure.

[0028] 4 is a flow chart illustrating a non-limiting exemplary embodiment of a method for laying out a plurality of transistors for fabricating an integrated circuit according to various aspects of the present disclosure. Method 400 optimizes the overall transistor layout using analytical or simulated annealing techniques to generate a rough placement that is more globally optimized than was possible using previous techniques and is then partitioned to generate a finished design suitable for fabrication.

[0029] From a start block, the method 400 proceeds to block 402 where the layout management engine 312 of the layout computing system 310 receives a specification for an integrated circuit including a netlist. In some embodiments, the netlist entries include information about the transistors in the integrated circuit, including, but not limited to, an identification of the type of each transistor (e.g., NMOS or PMOS) and the nets connected to each terminal of each transistor. In some embodiments, the specification may also identify additional characteristics of the integrated circuit, including, but not limited to, the footprint of the integrated circuit and physical restrictions on various portions of the footprint (e.g., areas where only NMOS transistors may be placed, and areas where only PMOS transistors may be placed, etc.). In some embodiments, the specification includes a transistor list and the nets are included as metadata in the list. In some embodiments, the specification may be, include, or be included in a data structure, such as an integrated circuit configuration file.

[0030] In block 404, the layout management engine 312 determines initial positions on a canvas for the transistors in the netlist. In some embodiments, the size and / or dimensions of the canvas may be determined by information provided by the specification. The initial positions on the canvas may be specified in a continuous coordinate system (e.g., the horizontal and vertical coordinates of each transistor may be specified with real values ​​instead of or in addition to integer values). In some embodiments, the initial positions may be randomly distributed across the canvas, randomly distributed with weighting applied to transistors connected to matching nets, the output of another type of optimization, or distributed using other suitable techniques.

[0031] 5 is a schematic diagram of a non-limiting exemplary embodiment of a canvas after the initial locations of the transistors have been determined, according to various aspects of the disclosure. As shown, NMOS transistors (shown in solid lines) and PMOS transistors (shown in dashed lines) are randomly placed across the canvas 502. Also shown, the transistors are placed using a continuous coordinate system, as evidenced by the overlapping horizontal and vertical locations. The initial locations may or may not be valid locations from a manufacturability perspective, but serve as initial states for subsequent optimization.

[0032] Returning to FIG. 4, the method 400 then proceeds to subroutine block 406 where the layout management engine 312 provides a canvas to the analytical layout engine 314 of the layout computing system 310 or the simulated annealing layout engine 316 of the layout computing system 310 to generate a rough placement including optimizing the orientation of the transistors. One aspect of the layout of transistors compared to the layout of other types of components (e.g., cells) is that a three-terminal transistor can be placed in one of at least two orientations. For example, in FIG. 1, the left terminal of the NMOS transistor coupled to net N1 may be the source terminal and the right terminal of the NMOS transistor coupled to net N3 may be the drain terminal. However, when laying out this transistor, it may be flipped so that the drain terminal coupled to N3 is placed on the left and the source terminal coupled to N1 is placed on the right. In an embodiment of the present disclosure, in addition to considering the position, the optimization to generate the rough placement may consider flipping one or more transistors to improve the overall layout.

[0033] In some embodiments, the rough placement is in a discretized coordinate system (e.g., the horizontal and vertical coordinates of each transistor are specified with integer values) rather than the continuous coordinate system used for the initial placement. Because the discretized coordinate system may be used as input in future steps of method 400 (including but not limited to a fabrication system), procedures performed in subroutine block 406 may convert from the continuous coordinate system to the discretized coordinate system to generate the rough placement to enable later operations of method 400.

[0034] A non-limiting exemplary embodiment of a suitable procedure performed by the analysis layout engine 314 to generate a rough placement using analysis techniques is shown in Figure 6. A non-limiting exemplary embodiment of a suitable procedure performed by the simulated annealing layout engine 316 to generate a rough placement using simulated annealing techniques is shown in Figure 8. Both exemplary procedures are described in further detail below.

[0035] At block 408, the layout management engine 312 partitions and optimizes the coarse placement to generate a fine placement. In some embodiments, the partitions may be optimized using one or more conventional techniques applied to transistor-level optimization, including, but not limited to, general combinatorial search schemes, including, but not limited to, Satisfiability Modulo Theory (SMT), Mixed Integer Programming (MIP), graph search, branch and bound, and dynamic programming. The optimization factors of power, performance, and area may be approximated by other objectives, including, but not limited to, interconnect length and diffusion sharing.

[0036] At block 410, the layout management engine 312 routes the fine placement to generate a completed design. Any suitable router may be used, including but not limited to a maze router, a line probe router, a pattern router, a channel router, or a gridless router, and any suitable routing technique may be used, including but not limited to a rip-up and re-route technique or an iterative refinement routing method. Techniques for routing the fine placement to generate a completed design are known to those skilled in the art and will not be described in further detail herein for the sake of brevity.

[0037] Because determining the location of transistors and determining the routing of connections between transistors are two objectives of method 400, for clarity, placement and routing are described as separate tasks in blocks 406-410. However, placement and routing are considered to be related separate aspects of a single problem of integrated circuit design that may affect each other. Thus, in some embodiments, the placement step may be followed by a routing step, which may then be followed by one or more other iterations of the placement step (e.g., if the initial placement is determined to be non-routable in the routing step). Furthermore, in some embodiments, the placement and routing problems are considered simultaneously by a combinatorial optimization apparatus, and at least some blocks of the integrated circuit are placed and routed simultaneously.

[0038] At block 412, the layout management engine 312 stores the completed design in the layout data store 308 of the Layout Computing System 310. In some embodiments, the layout management engine 312 may not store the completed design in the layout data store 308, but instead immediately pass it on to other components of the Layout Computing System 310. However, by storing the completed design in the layout data store 308, the Layout Computing System 310 may be able to update or reuse the completed design without having to repeat the optimization steps described above.

[0039] In block 414, the user interface engine 318 of the layout computing system 310 presents the completed design, receives one or more manual updates to the completed design, and stores the updated design in the layout data store 308. Often, it may be desired to make manual adjustments to the completed design. For example, a user may wish to add one or more components to the completed design, remove one or more components from the completed design, add input or output ports or vias to the completed design to enable the resulting integrated circuit to communicate with other devices, adjust the position of one or more components to enhance interoperability with other devices, and / or make various other types of changes. In some embodiments, the user interface engine 318 receives an indication of such changes and responsively adjusts the completed design while ensuring that any design rules are met.

[0040] In some embodiments, the user interface may include an interactive and / or searchable transistor map that can be used to identify connected or otherwise grouped (e.g., into a Boolean logic function) transistors that would traditionally be replaced in a mapping to a cell representation. As such, the user interface may include a search tool configured to query the completed design and return a subset of transistors and / or nets according to a query term. The user interface may update the presentation of the transistor map to visually highlight the subset of transistors and / or nets that match the query term. Additionally or alternatively, the user interface may also include data or information useful to a user of the environment, such as values ​​of objective / loss functions as a function of the number of iterations to determine convergence, qualitative or quantitative determinations of convergence, etc. Similarly, the layout management engine 312 may interact with the user interface to facilitate at least partial manual input regarding one or more transistors. For example, between iterations of an automatic correction, a user may insert additional transistors, remove transistors, modify the netlist, manually reconfigure the coordinates and / or orientation of transistors, and / or add soft or hard region fences around groups of transistors.

[0041] At block 416, the layout management engine 312 provides the design from the layout data store 308 to a fabrication system for fabricating the integrated circuit. Any type of fabrication system capable of fabricating an integrated circuit may be used, including, but not limited to, a photolithography system.

[0042] The method 400 then proceeds to an end block and ends.

[0043] 6 illustrates a non-limiting exemplary embodiment of a procedure for generating a rough layout using analytical techniques in accordance with various aspects of the present disclosure. In procedure 600, analytical techniques exploit differentiability of operations on a continuous coordinate space to optimize the locations of transistors, and then transform the locations in the continuous coordinate space to locations in a discrete coordinate space for use by further operations of calling method 400.

[0044] From a start block, the procedure 600 proceeds to block 602 where the analytical layout engine 314 performs an optimization of transistor locations in continuous coordinate space using a loss function that may include a term for transistor orientation.

[0045] In some embodiments, the optimization minimizes the value of a loss function (also referred to as an objective function) by perturbing the design points (e.g., the positions of the transistors in a continuous coordinate space) until a minimum of values ​​is found (or a predetermined number of iterations are performed). In some embodiments, perturbing the design points includes flipping the orientation of one or more transistors. In some embodiments, the loss function may include a term that represents the orientation of one or more transistors. Subsequent design points may be found using any suitable optimization technique, including, but not limited to, gradient descent, genetic algorithms, and combinations thereof. The use of a continuous coordinate space at this point in the procedure 600 allows iterative techniques such as gradient descent to be used effectively even if the positions in the continuous coordinate space are not available for fabrication.

[0046] The loss function may include one or more terms as a convergence objective. An example of a convergence objective for optimization is the weighted sum of half-period wire lengths (HPWLs). In terms of weighting coefficients, w ij is defined as the weight of the net, and the weighted sum of HPWL is Σw ij *(|x i -x j |+|y i -y j|), which may be approximated using quadratic equations or other non-linear objectives (e.g., distances may be constrained to straight line routing rules, the shortest straight line path may be used, curve rules incorporating manufacturability constraints on radius of curvature may also be included, etc.). Additional or alternative convergence objectives include, but are not limited to, interconnect length, transistor density, routability, timing, power, manufacturability, among others.

[0047] The objectives can be used to estimate power, performance, and area optimization factors. ij may be net-specific for a given net connecting transistors "i" and "j". In some embodiments, a given net may connect more than two transistors. Thus, the weighting factor w ijk may be defined for a net connected to three transistors, and is logically extended to nets connecting more than three transistors. In some embodiments, transistor-specific weighting is applied, where a given transistor "i" may be assigned a weight that makes it have relatively more or less influence on the overall placement of the set of transistors. For example, if transistor density is used as the objective function, then individual transistors may be assigned respective weights w i can be given.

[0048] In some embodiments, the weight w i is the density function d that defines the numerical probability that a transistor will be placed in a given matrix space. i It can be defined in terms of the density function d i Also, the transistor t i may depend at least in part on the number of transistors in a given interval of (e.g., the number of transistors t increases as the density of transistors in a given area of ​​the placement matrix increases). i (so that the probability of placing a

[0049] In some embodiments, one or more constraints may be applied to prevent the transistor placement matrix from converging to a non-physical solution (e.g., two different transistors occupying the same physical space). For example, transistors may be assigned a size in coordinate space and / or an exclusion radius in coordinate space (e.g., a zero-dimensional size with an exclusion radius of (1,1)), where the term "exclusion radius" refers to the spacing around a given transistor "i" within which no other transistor "j" is allowed. The spacing may be defined in spatial dimensions (e.g., physical terms in a two-dimensional plane) or in coordinate space (e.g., indexical terms for the coordinates of the transistor). In an illustrative example, transistor t i can be given an exclusion radius of two grid intervals in xy space, and the second transistor t j are not assigned coordinates that are more than two units away from the location of the transistor. In some embodiments, each transistor in a set of transistors may be assigned the same size, corresponding to the physical state of the transistor in the fabricated integrated circuit. In some embodiments, the transistors are assigned different sizes and / or exclusion distances.

[0050] As an approach to reducing the computational complexity of applying constraints, the objective function (e.g., the HPWL described above) can be modified to include a penalty term. For example, constraints on physical space (e.g., no-overlapping transistor rules) can be relaxed into the objective function using a penalty term. Similarly, a local refinement step can be included to optimize transistor placement, e.g., as part of optimizing power, performance, and / or area. In an illustrative example, a subset of transistors can be moved or otherwise shifted as part of reducing the overall area of ​​an integrated circuit containing thousands of transistors.

[0051] Once the optimal location and orientation is determined by the optimization technique in block 602, procedure 600 then converts the location from a continuous coordinate space to a discrete coordinate space. Thus, procedure 600 proceeds to block 604 where analysis layout engine 314 sorts the transistors horizontally and vertically in the continuous coordinate space. To do so, analysis layout engine 314 may compare the locations of the transistors to each other and create two lists: a first list in which the transistors are sorted in order based on their location on the horizontal axis, and a second list in which the transistors are sorted in order based on their location on the vertical axis. Additional lists may be used if there are more or fewer dimensions at the location.

[0052] At block 606, the analysis layout engine 314 generates a preliminary discrete layout by arranging the transistors in rows of the discrete coordinate space according to a vertical sorting and arranging the transistors in columns of the discrete coordinate space according to a horizontal sorting. In some embodiments, the analysis layout engine 314 may determine the number of available rows in the discrete coordinate space and determine the number of transistors to be placed in each row to distribute the transistors evenly across the rows and the number of transistors to be placed in each column to distribute the transistors evenly across the columns. The analysis layout engine 314 then processes the list of transistors sorted by vertical position to place the transistors in rows (e.g., if three transistors are to be placed in each row, the first three transistors in the list are assigned to the first row, the next three transistors in the list are assigned to the second row, and so on), and then similarly processes the list of transistors sorted by horizontal position to place the transistors in columns (e.g., if five transistors are to be placed in each column, the first five transistors in the list are placed in the first column, the next five transistors in the second column, and so on). In some embodiments, certain locations may be limited to certain types of transistors (e.g., PMOS vs. NMOS), so placement at this point may take these constraints (and / or other fabrication constraints) into account.

[0053] 7 is a schematic diagram of a non-limiting, exemplary embodiment of a layout in a discrete coordinate space according to various aspects of the disclosure. In layout 702, the canvas is divided into separate rows and columns. The rows include pairs of rows in which only PMOS transistors (shown in dashed lines) may be placed, and pairs of rows in which only NMOS transistors (shown in solid lines) may be placed. The operation of block 606 distributed the transistors into discrete locations defined by the rows and columns.

[0054] Returning to FIG. 6, in block 608, the analytical layout engine 314 converts the preliminary discrete layout into a rough layout using a combinatorial optimizer that may consider transistor orientations. To complete the combinatorial optimization in a reasonable time, the discrete coordinate space can be partitioned into smaller areas, similar to conventional techniques. Even if combinatorial optimization techniques are applied to smaller partitions of a large layout problem to reduce the problem to a reasonable size, previous techniques do not first apply the above-mentioned global optimization, and therefore cannot be used to layout a large number of individual transistors in an integrated circuit design, since the partitioned optimization has no effect on the overall design. Those skilled in the art are familiar with applying combinatorial techniques to small partitions of an integrated circuit design, and for the sake of brevity, further details of these operations will not be described herein.

[0055] The procedure 600 then proceeds to an end block and returns control to the caller.

[0056] 8 is a flow chart illustrating a non-limiting exemplary embodiment of a procedure for generating a rough layout using a simulated annealing technique in accordance with various aspects of the present disclosure. Procedure 800 uses a simulated annealing technique that can efficiently operate on a discrete coordinate space to optimize transistor locations.

[0057] From a start block, the procedure 800 proceeds to block 802, where the simulated annealing layout engine 316 transforms the initial locations of the transistors into a discrete coordinate space. In some embodiments, the initial locations may be transformed from a continuous coordinate space to a discrete coordinate space using a sorting technique such as that described in blocks 604-606 of FIG. 6. In some embodiments, the initial locations may be provided directly in the discrete coordinate space.

[0058] In block 804, the simulated annealing layout engine 316 uses a simulated annealing technique to optimize the locations of transistors in the discrete coordinate space to create a preliminary discrete layout, where the simulated annealing technique moves may include changing the orientation of the transistors. In the simulated annealing technique, a loss function similar to that described in block 602 may be optimized, but instead of using a gradient technique to perturb the design point, iterations are performed in which one or more neighbors of the current state are evaluated using the loss function, and a probabilistic decision is made to determine whether to move to a neighboring state or remain in the current state. The neighbors are determined by changing the location of one or more transistors, and may also include changing the orientation of one or more transistors.

[0059] The simulated annealing layout engine 316 converts the preliminary discrete layout to a coarse layout using a combinatorial optimizer, at block 806. As in block 608, conventional partitioning and combinatorial optimization techniques can be used to convert the preliminary discrete layout to a coarse layout.

[0060] The procedure 800 then proceeds to an end block and returns control to the caller.

[0061] As part of the techniques described herein, analytical formulations for standard cell-based placement can be adapted to transistor-level placement. For example, orientation, grouping, routability constraints, and / or weighting per group can be implemented to allow flexibility in transistor placement. In contrast to the standard cell hierarchy traditionally applied in industry, transistor-level placement improves the optimization process by decoupling transistor locations from Boolean logic function groupings. In this way, local deviations from optimal placement can be balanced against overall improvements to the overall placement of transistors. In contrast, traditional tools are limited to placing standard cells rather than transistors, limiting flexibility regarding placement of individual transistors at the scale of integrated circuits, thereby prioritizing cell-scale optimization over IC-scale optimization. Thus, direct placement of transistors at the scale of over 1000 transistors was previously rare and manual.

[0062] In the foregoing description, numerous specific details are set forth to provide a thorough understanding of various embodiments of the present disclosure. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

[0063] Throughout this specification, reference to "one embodiment" or "one embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0064] The order in which some or all of the blocks appear in each method flowchart is not intended to be considered limiting: rather, one of ordinary skill in the art having the benefit of this disclosure will understand that operations associated with some of the blocks may be performed in various orders not shown, or in parallel.

[0065] The processes described above are described in terms of computer software and hardware. The techniques described may comprise machine-executable instructions embodied in a tangible or non-transitory machine (e.g., computer) readable storage medium, which, when executed by a machine, causes the machine to perform the described operations. In addition, the processes may also be embodied in hardware, such as an application specific integrated circuit ("ASIC").

[0066] The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments and examples for the invention have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications are possible within the scope of the invention.

[0067] These modifications can be made to the present invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed herein. Rather, the scope of the invention shall be determined entirely by the following claims, which shall be construed in accordance with established principles of claim interpretation. [Explanation of symbols]

[0068] 202 NMOS 204 PMOS 302 Processor 304 Communication Interface 306 Computer-readable medium 308 Layout Data Store 310 Layout Computing System 312 Layout Management Engine 314 Analysis and Layout Engine 316 Simulated Annealing Layout Engine 318 User Interface Engine 400 ways 502 Canvas 600 steps 702 Layout 800 Procedures

Claims

1. 1. A computer-implemented method for designing an integrated circuit using transistor placement optimization, comprising: receiving, by a computing system, a specification for the integrated circuit, the specification including a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors; determining, by the computing system, an initial position and orientation on a canvas of each transistor in the plurality of transistors; generating, by the computing system, a rough placement having globally optimized positions and orientations of the plurality of transistors using an objective function based at least in part on the initial positions and orientations of the plurality of transistors; optimizing, by the computing system, the coarse configuration to generate a fine configuration using local refinement techniques; generating, by the computing system, routing for the fine placement using routing techniques to generate a completed design; storing, by the computing system, the completed design in a layout data store; 4. A computer-implemented method comprising:

2. The computer-implemented method of claim 1 , further comprising providing the completed design to a fabrication system for fabrication of the integrated circuit.

3. generating a user interface based on at least one of the coarse layout, the fine layout, and the final design; receiving, via the user interface, a query including one or more query terms; updating the user interface to visually highlight at least one of a subset of transistors or a subset of nets that match the query terms; The computer-implemented method of claim 1 , further comprising:

4. receiving instructions via the user interface to add transistors, remove transistors, modify the netlist, modify transistor positions, modify transistor orientations, or add region fences around groups of transistors; updating at least one of the coarse layout, the fine layout, and the completed design based on the instructions; The computer-implemented method of claim 3 , further comprising:

5. generating the coarse placement having globally optimized positions and orientations of the plurality of transistors using the objective function; optimizing positions of the plurality of transistors in a continuous coordinate space using analytical techniques; creating a preliminary discrete layout by transforming the optimized positions of the plurality of transistors in the continuous coordinate space to positions in a discrete coordinate space; 2. The computer-implemented method of claim 1, comprising:

6. transforming the optimized positions of the plurality of transistors in the continuous coordinate space to positions in the discrete coordinate space; creating a sorted list of the plurality of transistors for each dimension of the canvas, the sorted list being arranged by the location in the corresponding dimension of the optimized position of each transistor; placing the plurality of transistors in the discrete coordinate space according to the sorted list; 6. The computer-implemented method of claim 5, comprising:

7. The computer-implemented method of claim 5 , wherein the analysis technique comprises a gradient descent technique.

8. generating a rough placement having globally optimized positions and orientations of the plurality of transistors using the objective function; optimizing the locations of the plurality of transistors in a discrete coordinate space using simulated annealing techniques; 2. The computer-implemented method of claim 1, comprising:

9. 10. The computer-implemented method of claim 8, wherein at least one move of the simulated annealing technique includes modifying an orientation of at least one transistor.

10. 2. The computer-implemented method of claim 1, wherein the objective function comprises a weighted half-perimeter wire length (HPWL) function.

11. 1. A computer-readable storage medium having stored thereon computer-executable instructions that, upon execution by one or more processors of a computing system, cause the computing system to perform operations for designing an integrated circuit using transistor placement optimization, the operations comprising: receiving, by the computing system, a specification for the integrated circuit, the specification including a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors; determining, by the computing system, an initial position and orientation on a canvas of each transistor in the plurality of transistors; generating, by the computing system, a rough placement having globally optimized positions and orientations of the plurality of transistors using an objective function based at least in part on the initial positions and orientations of the plurality of transistors; optimizing, by the computing system, the coarse constellation to generate a fine constellation using local refinement techniques; generating, by the computing system, routing for the fine placement using routing techniques to generate a completed design; storing, by the computing system, the completed design in a layout data store; 23. A computer-readable storage medium comprising:

12. 12. The computer-readable storage medium of claim 11, wherein the operations further comprise providing the completed design to a fabrication system for fabrication of the integrated circuit.

13. The operation, generating a user interface based on at least one of the coarse layout, the fine layout, and the completed design; receiving, via the user interface, a query including one or more query terms; updating the user interface to visually highlight at least one of a subset of transistors or a subset of nets that match the query terms; 12. The computer-readable storage medium of claim 11, further comprising:

14. The operation, receiving instructions via the user interface to add transistors, remove transistors, modify the netlist, modify transistor positions, modify transistor orientations, or add region fences around groups of transistors; updating at least one of the coarse layout, the fine layout, and the completed design based on the instructions; 14. The computer-readable storage medium of claim 13, further comprising:

15. generating the coarse placement having globally optimized positions and orientations of the plurality of transistors using the objective function; optimizing positions of the plurality of transistors in a continuous coordinate space using analytical techniques; creating a preliminary discrete layout by transforming the optimized positions of the plurality of transistors in the continuous coordinate space to positions in a discrete coordinate space; 12. The computer-readable storage medium of claim 11, comprising:

16. transforming the optimized positions of the plurality of transistors in the continuous coordinate space to positions in the discrete coordinate space; creating a sorted list of the plurality of transistors for each dimension of the canvas, the sorted list being arranged by the location in the corresponding dimension of the optimized position of each transistor; arranging the plurality of transistors in the discrete coordinate space according to the sorted list; 16. The computer-readable storage medium of claim 15, comprising:

17. 16. The computer-readable storage medium of claim 15, wherein the analysis technique comprises a gradient descent technique.

18. generating a rough placement having globally optimized positions and orientations of the plurality of transistors using the objective function; optimizing the locations of the plurality of transistors in a discrete coordinate space using a simulated annealing technique; 12. The computer-readable storage medium of claim 11, comprising:

19. 20. The computer-readable storage medium of claim 18, wherein at least one move of the simulated annealing technique includes modifying an orientation of at least one transistor.

20. 12. The computer-readable storage medium of claim 11, wherein the objective function comprises a weighted half-perimeter wire length (HPWL) function.

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