SYSTEM AND METHOD FOR INCREASING POWER DURING LOW FREQUENCY CYCLES USING BINNING - Patent application

Abstract

A method for achieving uniformity in etch rate is described. The method includes receiving a voltage signal from an output of a matching unit and determining a positive crossing point and a negative crossing point of the voltage signal for each cycle of the voltage signal. The negative crossing point of each cycle is contiguous with the positive crossing point of the cycle. The method further includes dividing a time interval of each cycle of the voltage signal into a plurality of bins. For one or more of the plurality of bins associated with the positive crossing point or one or more of the plurality of bins associated with the negative crossing point, the method includes adjusting the frequency of a radio frequency generator to achieve uniformity in etch rate.

Description

[Technical field]

[0001] The present embodiment relates to a system and method that uses binning to increase power during low frequency cycles. [Background technology]

[0002] The plasma tool includes a radio frequency generator (RFG), an impedance match network, and a plasma chamber. The RFG generates power that is provided to the plasma chamber through the impedance match network. When power is provided, a process gas is supplied to the plasma chamber for processing a wafer placed in the plasma chamber. When the process gas is supplied, a plasma is generated in the plasma chamber. The wafer is etched by the generated plasma.

[0003] It is in this context that the embodiments described in this disclosure arise.

[0004] The background description provided herein is intended to provide a general overview of the contents of the present disclosure. Work by the currently named inventors within the scope of what is described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, either expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0005] The embodiments of the present disclosure provide a system, an apparatus, a method, and a computer program for increasing power during low frequency cycles using binning. It should be understood that the embodiments can be implemented by various means, such as a process, an apparatus, a system, a device, or a method on a computer readable medium. Some embodiments are described below.

[0006] A low frequency (LF) radio frequency (RF) generator and a high frequency (HF) RF generator are used to process a substrate. The LF RF generator and the HF RF generator generate RF signals that are used to generate a plasma and a plasma sheath in a plasma chamber. The voltage of the plasma sheath cycles between a low level and a high level. During periods when the plasma sheath is at a low level, a first voltage of the plasma sheath generated by the HF RF generator has a greater effect on a second voltage of the plasma sheath generated by the LF RF generator. This effect is greater than the effect of the first voltage on the second voltage during periods when the plasma sheath is at a high level. As this effect increases, uniformity becomes less controllable when processing the substrate. The systems and methods described herein facilitate achieving uniformity during periods of increased effect.

[0007] Some advantages of the systems and methods described herein include achieving a level of uniformity in the processing of a substrate, such as an etch rate or a deposition rate of the substrate. The level of uniformity is achieved by dividing a portion of a + cycle of the voltage measured at the output of the impedance matching circuit into a predetermined number of bins. For example, the portion of the cycle between a positive crossing point of the cycle and a negative crossing point of the cycle is divided into a predetermined number of bins. For each bin, the frequency of the HF RF generator is controlled to control the power delivered by the HF RF generator. For example, the frequency of the HF RF generator is increased or decreased to increase the delivered power. By controlling the frequency over a predetermined number of bins, the HF RF generator can be precisely controlled to achieve the level of uniformity.

[0008] In one embodiment, a method for achieving uniformity in etch rate is described. The method includes receiving a voltage signal from an output of a match unit and determining a positive cross point and a negative cross point of the voltage signal for each cycle of the voltage signal. The negative cross point of each cycle is contiguous with the positive cross point of the cycle. The method further includes dividing a time interval of each cycle of the voltage signal into a number of bins. For one or more of the number of bins associated with the positive cross points or one or more of the number of bins associated with the negative cross points, the method includes adjusting a frequency of a radio frequency generator to achieve uniformity in etch rate.

[0009] In one embodiment, a method for achieving uniformity in etch rate is described. The method includes receiving a voltage signal from an output of a matching section and determining a positive cross point and a negative cross point of the voltage signal for each cycle of the voltage signal. The negative cross point of each cycle is contiguous with the positive cross point of the cycle. The method further includes dividing a time interval of each cycle of the voltage signal into a plurality of bins, the time interval beginning at a time proximate to the positive cross point and ending at a time proximate to the negative cross point. For one or more of the plurality of bins, the method includes adjusting a frequency of a radio frequency generator to achieve uniformity in etch rate.

[0010] In one embodiment, a controller is described that achieves uniformity in the etch rate. The controller includes a processor that receives a voltage signal from an output of a matching unit. The processor determines a positive crossing point and a negative crossing point of the voltage signal for each cycle of the voltage signal. The negative crossing point of each cycle is contiguous with the positive crossing point of the cycle. The processor divides a time interval of each cycle of the voltage signal into a number of bins, the time interval beginning at a time proximate to a positive crossing point and ending at a time proximate to a negative crossing point. For one or more of the number of bins, the processor adjusts a frequency of a radio frequency generator to achieve uniformity in the etch rate. The controller includes a memory device coupled to the processor.

[0011] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0012] The embodiments may be best understood by reference to the following description taken in conjunction with the accompanying drawings.

[0013] [Figure 1A] 1 is an embodiment of a graph for illustrating plasma sheath voltage versus time.

[0014] [Figure 1B-1] 1B is an embodiment of a graph to illustrate the voltages applied to the radio frequency (RF) rods of the RF transmission line to achieve the voltages shown in FIG. 1A at the plasma sheath.

[0015] [Figure 1B-2] This is a continuation of the graph in Figure 1B-1.

[0016] [Figure 1C] 1B is an embodiment of the graph of FIG. 1A.

[0017] [Figure 1D-1] 13 is one embodiment of a graph to illustrate binning around a positive intersection.

[0018] [Figure 1D-2] This is a continuation of the graph in Figure 1D-1.

[0019] [Diagram 2] 1 illustrates an embodiment of a plasma system to illustrate application of a high frequency (HF) RF generator operating frequency to multiple bins.

[0020] [Figure 3A] 1 is a schematic diagram of one embodiment of a system for illustrating the operation of an HF RF generator.

[0021] [Figure 3B] 1 is an embodiment of a graph plotting logic levels versus time of a digital pulse signal.

[0022] [Figure 3C] 4 is an embodiment of a graph plotting logic levels versus time for another digital pulse signal.

[0023] [Figure 4] 1 is a schematic diagram of one embodiment of a system to illustrate control of an auxiliary capacitor of an impedance matching circuit (IMC) for modifying the frequency in the high frequency range to control the power delivered by an HF RF generator.

[0024] [Diagram 5] 13 is one embodiment of a graph illustrating the change in uniformity in etch rate when high frequency values ​​for pre-stored number bins are applied.

[0025] [Figure 6A] 2 is an embodiment of the graph of FIG. 1.

[0026] [Figure 6B] 11 is an embodiment of a graph to illustrate increased delivered power by applying high frequency values ​​to a pre-stored number of bins. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In the following embodiments, a system and method for increasing power during low frequency cycles using binning is described. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well known operations have not been described in detail in order to not unnecessarily obscure the present embodiments.

[0028] FIG. 1A illustrates an embodiment of a graph 100 showing plasma sheath voltage (V) versus time t. The plasma sheath is a lower plasma sheath that is formed closer to the powered electrode, which is the lower electrode, than the upper plasma sheath. The upper plasma sheath is formed closer to the upper electrode than the lower plasma sheath. Graph 100 plots plasma sheath voltage on the Y-axis and time t on the X-axis. Graph 100 includes a plot 102 of a first portion of the plasma sheath voltage, the first portion being created as a result of a radio frequency (RF) signal generated by a low frequency (LF) RF generator. An example of an LF RF generator is provided below. Plot 102 is shown using a solid line. Graph 100 further includes a plot 104 of a second portion of the plasma sheath voltage, the second portion being created based on an RF signal generated by a high frequency (HF) RF generator. An example of an HF RF generator is provided below. Plot 104 is shown using a dotted line.

[0029] As shown in FIG. 1A, plot 102 periodically cycles between a low voltage level V1 and a high voltage level V2. An example of the low voltage level V1 is a low voltage point, such as a low voltage swing, and an example of the high voltage level V2 is a high voltage point, such as a high voltage swing. Plot 102 remains at a level that is approximately the low voltage level V1 from time t0 to time t1, transitions from the level at time t1 to a high voltage level V2 between times t1 and t2, and transitions from the high voltage level V2 to a level that is approximately the low voltage level V1 at time t2. Plot 102 also remains at a level that is approximately the low voltage level V1 from approximately time t2 to time t3, transitions from the level at time t3 to a high voltage level V2 between times t3 and t4, and reaches a level that is approximately the low voltage level V1 at approximately time t4. An example of a level that is approximately the low voltage level V1 is a level that is within a predetermined range, such as within ±10%, from the low voltage level V1.

[0030] Note that between time t1 and time t2, plot 102 is either transitioning between low voltage level V1 and high voltage level V2 or is at high voltage level V2. Due to the high voltage level V2, the plasma sheath becomes thicker and the effect of the second part of the plasma sheath voltage (plot 104) on the first part of the plasma sheath voltage (plot 102) becomes smaller. When the second part of the voltage affects the first part during time t1 and time t2, the plasma sheath voltage reaches a maximum voltage point, such as a maximum voltage amplitude. The maximum voltage point is the highest among all the plasma sheath voltage amplitudes during time t1 and time t3. Due to the smaller effect, generally, a uniformity level in the etch rate across the surface of the substrate is achieved. Also, the control of the impedance matching network is sufficient between time t1 and time t2 to minimize the power reflected from the plasma chamber through the impedance matching network back to the LF and HF RF generators. However, between time t2 and time t3, the voltage level is maintained at approximately the low voltage level V1. Between time t2 and time t3, due to the low voltage level V1, the plasma sheath becomes thinner and the effect of the second portion of the plasma sheath voltage (plot 104) on the first portion of the plasma sheath voltage (plot 102) becomes greater. When the second portion of the voltage affects the first portion during time t2 and time t3, the plasma sheath voltage reaches a minimum voltage point, such as a minimum voltage amplitude. The minimum voltage point is the lowest of the total plasma sheath voltage amplitude during time t1 and time t3. As a result of the greater effect, the uniformity in the etch rate decreases. For example, the RF signal output from the HF RF generator causes harmonics in the plasma chamber, which cause standing waves. The standing waves decrease the uniformity in the etch rate.

[0031] FIG. 1B-1 is an embodiment of a graph 110 to show a voltage 112 applied to a radio frequency (RF) rod of an RF transmission line to achieve the voltage shown in FIG. 1A at the plasma sheath. FIG. 1B-2 is a continuation of the graph 110. The graph 110 plots a voltage 112 measured by a sensor coupled to the output of an impedance matching circuit (IMC) described with respect to FIG. 2. The voltage 112 is plotted against the time t shown in FIG. 1A. The voltage 112 is plotted on the Y-axis and the time t is plotted on the X-axis. The voltage 112 is a voltage signal that repeats over multiple cycles, such as cycle 1 and cycle 2. Cycle 2 is consecutive to cycle 1. As an example, the voltage signal of the graph 110 is a sinusoidal signal.

[0032] The voltage 112 has or is applied with a direct current (DC) offset 114. The DC offset 114 is applied by an impedance matching circuit and a blocking capacitor (not shown) in the plasma systems described herein.

[0033] The voltage 112 has a positive intersection point for each cycle of the voltage 112 and a negative intersection point for each cycle of the voltage 112. For example, the voltage 112 has a positive intersection point 122 during cycle 1 and a negative intersection point 124a during cycle 1. The positive intersection point of each cycle of the voltage 112 is consecutive with the negative intersection point of the cycle. For example, there are no other intersection points between the positive intersection point 122 and the negative intersection point 124a of cycle 1. Positive and negative intersection points are described further below.

[0034] A negative intersection of a cycle is at the beginning of the cycle and at the edge of the cycle. For example, cycle 1 has a negative intersection 124a that indicates the beginning of cycle 1 and another negative intersection 124b that indicates the end of cycle 1. The other negative intersection 124b, which is consecutive to the positive intersection 122 of cycle 1, belongs to cycle 1 of the voltage 112. The other negative intersection 124b is at the edge of cycle 1. Also, the negative intersection 124b at the end of cycle 1 belongs to cycle 2 as well.

[0035] Each cycle of the voltage 112 is divided into a number of bins, such as segments or sections or divided time intervals, by a processor, described below with reference to FIG. 2. For example, the first half 112A of the period of cycle 1 is divided into bins 1m, 2m, etc., into bins Mm, where M is an integer and m is a variable that indicates the first half of each cycle of the voltage 112. The second half 112B of the period of cycle 1 is divided into bins Nn, 1n, 2n, etc., where N is an integer and n is a variable that indicates the second half of each cycle of the voltage 112. As another example, referring to FIG. 1B-2, the first half of the period of cycle 2 is divided into bins Mm, 1m, 2m, etc., and the second half of the period of cycle 2 is divided into bins Nn, 1n, 2n, etc.

[0036] Each bin of cycle 1 has the same duration or time interval. For example, bin 1m of cycle 1 extends from time tNn at the end of cycle 0 to time t1m of cycle 1, bin 2m of cycle 1 extends from time t1m of cycle 1 to time t2m of cycle 1, and bin Mm of cycle 1 extends from time t(M-1)m to time tMm of cycle 1. Cycle 1 is continuous with cycle 0 of the voltage 112. The time interval between time Nn of cycle 0 and time t1m of cycle 1 is equal to the time interval between time t1m of cycle 1 and time t2m of cycle 1, and is equal to the time interval between time t(M-1)m of cycle 1 and time tMm of cycle 1. Similarly, cycle 1 bin 1n spans from cycle 1 time tMm to cycle 1 time t1n, cycle 1 bin 2n spans from cycle 1 time t1n to cycle 1 time t2n, and bin Nn spans from cycle 1 time t(N-1)n to time tNn, the end of cycle 1 and the beginning of cycle 2. The time interval between cycle 1 time tMm and cycle 1 time t1n is equal to the time interval between cycle 1 time t1n and cycle 1 time t2n, which is equal to the time interval between cycle 1 time t(N-1)n and time tNn, the end of cycle 1 and the beginning of cycle 2.

[0037] Similarly, each bin of each remaining cycle, such as cycle 2 of the voltage 112, has the same duration or time interval. For example, bin 1m of cycle 2 extends from cycle 2 time tNn to cycle 2 time t1m, bin 2m of cycle 2 extends from cycle 2 time t1m to cycle 2 time t2m, and bin Mm of cycle 2 extends from cycle 2 time t(M-1)m to cycle 2 time tMm. Similarly, bin 1n of cycle 2 extends from cycle 2 time tMm to cycle 2 time t1n, bin 2n of cycle 2 extends from cycle 2 time t1n to cycle 2 time t2n, and bin Mm extends from cycle 2 time t(N-1)n to time tNn, which is the end of cycle 2 and the beginning of cycle 3 of the voltage 112. Cycle 3 is continuous with cycle 2 of the voltage 112.

[0038] As shown by plot 102 and voltage 112 in FIGS. 1A, 1B-1 and 1B-2, during the time period between time t1 and time t2 when voltage 112 is high, e.g., significantly negative, the voltage of the plasma sheath increases. Also, during the time period between time t2 and time t3 when voltage 112 is low, e.g., less positive or less negative, the voltage of the plasma sheath decreases. As an example, the large amount of voltage 112 is more negative than the small amount of voltage 112. To explain, the large amount of voltage 112 has a larger negative amplitude than the amplitude of the small amount of voltage 112. To explain further, the large amount of voltage 112 does not have a positive potential, and the small amount of voltage 112 has a positive potential. The low voltage 112 has a relatively positive amount of power associated with the low voltage, P 正 The relatively positive amount of power during the period between time t2 and time t3 is more positive than the amount of power based on voltage 112 between time t1 and time t2. The amount of power between time t1 and time t2 is relatively negative compared to the amount of power between time t2 and time t3. The relatively negative amount of power between time t1 and time t2 corresponds to P 負 It is shown as:

[0039] Additionally, the voltage 112 between time t1 and time t2 corresponds to a high voltage duty cycle (HVDC) of the voltage 112, and the voltage 112 between time t2 and time t3 corresponds to a low voltage duty cycle (LVDC) of the voltage 112. The high voltage is more negative than the low voltage.

[0040] As further shown by plot 102 and voltage 112 in Figures 1A, 1B-1, and 1B-2, the second half of each cycle of voltage 112 coincides with a period during which the plasma sheath voltage is low compared to the plasma sheath voltage during the first half of the cycle, and the first half of each cycle of voltage 112 coincides with a period during which the plasma sheath voltage is high compared to the plasma sheath voltage during the second half of the cycle. For example, the second half 112B coincides with the period between time t2 and time t3 during which the plasma sheath voltage is low compared to the plasma sheath voltage during the first half 112A, and the first half 112A coincides with the period between time t1 and time t2 during which the plasma sheath voltage is high compared to the plasma sheath voltage during the second half 112B. More specifically, the period between time t1 and time t2 of plot 102 falls within the period during which the first half 112A of cycle 1 of voltage 112 occurs, and a majority of the period between time t2 and time t3 of plot 102 falls within the period during which the second half 112B of cycle 1 of voltage 112 occurs.

[0041] During each bin of the first half 112A of cycle 1, the processor determines an operating frequency of the HF RF generator to control the amount of power delivered at the output of the HF RF generator. For example, during the time interval of bin 1m of cycle 1, the processor determines an operating frequency of the HF RF generator at which the amount of power delivered at the output of the HF RF generator is increased, decreased, or maintained to achieve a predetermined uniformity level. The amount of power delivered is increased, decreased, or maintained compared to the amount of power delivered at the output of the HF RF generator during bin 1m of the previous cycle, such as cycle 0 of the voltage 112. As another example, during the time interval of bin 2m of cycle 1, the processor determines an operating frequency of the HF RF generator at which the amount of power delivered at the output of the HF RF generator is increased, decreased, or maintained compared to the amount of power delivered at the output of the HF RF generator during bin 2m of the previous cycle, such as cycle 0 of the voltage 112.

[0042] During cycle 2 of the voltage 112, the processor applies a pre-determined operating frequency during the first half of cycle 1 of the voltage 112. For example, the processor increases or decreases the operating frequency of the HF RF generator during bin 1m of cycle 2 to achieve the pre-determined frequency during bin 1m of cycle 1. As another example, the processor increases or decreases the operating frequency of the HF RF generator during bin 2m of cycle 2 to achieve the pre-determined frequency during bin 2m of cycle 1.

[0043] Similarly, during each bin of the second half 112B of cycle 1, the processor determines an operating frequency of the HF RF generator to control the amount of power delivered at the output of the HF RF generator. For example, during a time interval of bin 1n of cycle 1, the processor determines an operating frequency of the HF RF generator at which the amount of power delivered at the output of the HF RF generator is increased, decreased, or remains the same. The amount of power delivered is increased, decreased, or maintained compared to the amount of power delivered at the output of the HF RF generator during bin 1n of the previous cycle, such as cycle 0 of the voltage 112. As another example, during a time interval of bin 2n of cycle 1, the processor determines an operating frequency of the HF RF generator at which the amount of power delivered at the output of the HF RF generator is increased, decreased, or remains the same. The amount of power delivered is increased, decreased, or maintained compared to the amount of power delivered at the output of the HF RF generator during bin 2n of the previous cycle, such as cycle 0 of the voltage 112.

[0044] During cycle 2 of the voltage 112, the processor applies a pre-determined operating frequency during the second half 112B of cycle 1 of the voltage 112. For example, the processor increases or decreases the operating frequency of the HF RF generator during bin 1n of cycle 2 to achieve the pre-determined frequency during bin 1n of cycle 1. As another example, the processor increases or decreases the operating frequency of the HF RF generator during bin 2n of cycle 2 to achieve the pre-determined frequency during bin 2n of cycle 1.

[0045] Note that it is beneficial to control the operating frequency during the second half of cycle 2 as compared to the first half of cycle 2. This is because the lower voltage at the plasma sheath between times t2 and t3 results in a decrease in uniformity in the etch rate. By controlling the operating frequency during the second half of cycle 2, the delivered power at the output of the HF RF generator is increased, resulting in increased uniformity.

[0046] In one embodiment, the first half 112A of the cycle 1 period is divided into a different number of bins than the second half 112B of the cycle 1 period. For example, the first half 112A of the cycle 1 period is divided into 10 bins and the second half 112B of the cycle 1 period is divided into 15 bins.

[0047] In one embodiment, after cycle 1 of the voltage 112, the processor controls the operating frequency of the HF RF generator during the second half of each cycle, such as cycle 2 and 3, but does not control the operating frequency of the HF RF generator during the first half of the cycle of the voltage 112. For example, the processor controls the operating frequency during the second half of cycle 2, but does not control the frequency during the first half of cycle 2. To explain, if the processor ignores the predetermined uniformity level, the processor does not control the operating frequency. To explain further, the processor does not target the predetermined uniformity level while adjusting the operating frequency. To explain another way, the processor does not modify the operating frequency because it does not control the operating frequency.

[0048] In one embodiment, the processor controls the operating frequency of the HF RF generator during the first half of each cycle of the voltage 112, but does not control the operating frequency of the HF RF generator during the second half of the cycle. For example, the processor controls the operating frequency of the HF RF generator during the first half 112A of cycle 1 of the voltage 112, but does not control the operating frequency of the HF RF generator during the second half 112B of cycle 1 of the voltage 112. As another example, the processor controls the operating frequency of the HF RF generator during the first half 112A of cycle 2 of the voltage 112, but does not control the operating frequency of the HF RF generator during the second half 112B of cycle 2 of the voltage 112.

[0049] In one embodiment, the processor determines an operating frequency of the HF RF generator for a bin of the voltage 112 during multiple cycles of the voltage 112 and applies the operating frequency during a subsequent cycle of the voltage 112. The subsequent cycle is consecutive with the multiple cycles of the voltage 112. For example, the processor determines an operating frequency of the HF RF generator during bin 1n of multiple cycles, such as cycles 1 and 2 of the voltage 112, and controls the HF RF generator to achieve the same operating frequency during bin 1n of cycle 3 of the voltage 112. Cycle 3 is consecutive with cycle 2.

[0050] Note that in one embodiment, the operating frequency of the HF RF generator is changed for the same bins after the first set of cycles of the voltage 112, and this change in operating frequency is calculated based on achieving a level of uniformity. Once the frequency is changed, the processor keeps the frequency unchanged for the same bins for the second set of cycles. The first set of cycles precedes the second set of cycles.

[0051] In one embodiment, the processor applies the operating frequency of the HF RF generator determined for a bin during a cycle of the voltage 112 to the same bin during multiple consecutive cycles of the voltage 112. For example, the processor applies the operating frequency of the HF RF generator determined for bin 1 n during cycle 1 of the voltage 112 to bin 1 n during cycles 2 and 3 of the voltage 112.

[0052] In one embodiment, the processor determines an operating frequency of the HF RF generator for a bin during a cycle of the voltage 112 and then applies the determined operating frequency to the bin during the same cycle. For example, the operating frequency is determined during a portion of bin In of cycle 1 and applied during the remaining portion of bin In of cycle 1.

[0053] In one embodiment, no DC offset 114 is applied to the voltage 112, and the voltage 112 oscillates about the X-axis along which time t is plotted. For example, the voltage of the DC offset 114 is zero.

[0054] Although the voltage 112 shown in FIG. 1B-1 is a sinusoidal waveform or envelope, in one embodiment, the voltage 112 has another shape, for example, a sawtooth shape, or a pulse shape, or any arbitrary shape.

[0055] FIG. 1C is an embodiment of a graph 100.

[0056] FIG. 1D-1 is an embodiment of a graph 120 to show binning around a positive intersection 122 of a cycle of the voltage 112. FIG. 1D-2 is a continuation of the graph 120. A positive intersection is a point of intersection of the voltage 112 from a more negative potential on one side of the DC offset 114 to a less negative potential on the other side of the DC offset 114. As an example, a positive intersection is a time point where the value of the voltage 112 matches the potential of the DC offset 114 and the voltage 112 transitions from a more negative potential to a less negative potential. The positive intersection 122 occurs at or about time tMm during each cycle of the voltage 112. An example of a time that is about time tMm is a time that is within a pre-set range, such as ±10%, from time tMm. The graph 120 plots the voltage 112 versus time t. The voltage 112 is plotted on the Y-axis of the graph 120 and the time t is plotted on the X-axis of the graph 120.

[0057] A negative crossing point, such as negative crossing point 124a or 124b, is a crossing point of voltage 112 that goes from a less negative potential on one side of DC offset 114 to a more negative potential on the other side of DC offset 114. As an example, a negative crossing point is a point in time where the value of voltage 112 matches the potential of DC offset 114 and voltage 112 transitions from a less negative potential to a more negative potential. A negative crossing point, such as negative crossing point 124a or 124b, occurs at or about time tNn during each cycle of voltage 112. An example of a time that is about time tNn is a time that is within a pre-set range, such as ±10%, of time tNn.

[0058] The voltage 112 is divided into bins 1m to 1n in the same manner as above, except that bins 1m to 1n are offset along the X-axis such that bin 1n of each cycle of the voltage 112 spans before and after the positive intersection 122 of the cycle, and bin 1m of the cycle spans before and after a negative intersection, such as 124a or 124b of the cycle. For example, bins 1m to 1n are shifted to the left compared to bins 1m to 1n shown in FIG. 1B-1. Bin 1m begins at time tRr of a previous cycle, such as cycle 0, and ends at time t1q of a current cycle, such as cycle 1, where R is an integer and r is a variable indicating the second half of each cycle of the voltage 112. Time tNn of the current cycle is between time tRr of the previous cycle and time t1q of the current cycle. The previous cycle precedes the current cycle. Also, bin 1n begins at current cycle time tQq and ends at current cycle time t1r, where Q is an integer and q is a variable that indicates the first half of each cycle of the voltage 112. Current cycle time tMm is between current cycle time tQq and current cycle time t1r.

[0059] Graph 120 plots voltage 112 versus time t. Instead of binning each cycle of voltage 112 (FIG. 1B-1), such as dividing bins 1m through Nn such that bin 1m begins at the negative crossing point of the cycle and bin Nn ends at the positive crossing point of the cycle, the processor divides a cycle of voltage 112 into bins 1m through Nn such that bin 1n spans a first predetermined interval before positive crossing point 122 and a second predetermined interval after positive crossing point 122, and bin 1m spans a third predetermined interval before negative crossing point 124a and a fourth predetermined interval after negative crossing point 124a.

[0060] That is, the positive intersection 122 and the negative intersection 124a do not occur at the edge of the bin (i.e., either the beginning or the end), but instead occur at the center portion of the bin. For example, the processor divides the time interval around the negative intersection 124a of cycle 1 to generate bin 1m of cycle 1. Explained, bin 1m of cycle 1 spans from a third predetermined time interval before time tNn of cycle 1, where the negative intersection 124a occurs, to a fourth predetermined time interval after time tNn. Time tRr is in the third predetermined time interval before time tNn and falls within cycle 0 of the voltage 112, and time t1q is in the fourth predetermined time interval after time tNn and falls within cycle 1 of the voltage 112. In one explanation, the third predetermined time interval is equal to the fourth predetermined time interval. In another explanation, the third predetermined time interval is greater than or less than the fourth predetermined time interval. As yet another alternative, each of the first, second, third, and fourth predetermined time intervals are equal. The processor determines an operating frequency of the HF RF generator for bin 1m and controls the operating frequency of the HF RF generator to achieve the determined operating frequency during bin 1m of cycle 2 of the voltage 112.

[0061] As another example, instead of dividing the first half 112A of cycle 1 of the voltage 112 into a preset number of bins 1m to Mm using the positive intersection 122 and the negative intersection 124a as the two ends, the processor divides a portion of cycle 0, the first half 112A of cycle 1, and a portion of the second half 112B of cycle 1 of the voltage 112 into a preset number of bins 1m to 1n. To explain, instead of ending bin Mm at time tMm, which is the end of the first half 112A of cycle 1, bin 1n starts at a first predetermined interval before time tMm and ends at a second predetermined interval after time tMm. In this explanation, the first predetermined time interval is equal to the second predetermined time interval. As another explanation, the first predetermined time interval is greater than or less than the second predetermined time interval. Bin 1n starts at time tQq and ends at time t1r. Time t1r is within cycle 1 and time tQq is within cycle 1. Additionally, time tQq occurs after time t(M-1)m (FIG. 1B-1) of cycle 1, and time t1r occurs before time t1n (FIG. 1B-1) of cycle 1. Because time tQq occurs after time t(M-1)m (FIG. 1B-1) and time t1r occurs before time t1n, the positive intersection 122 occurs during the bin, instead of at the beginning or end of the bin.

[0062] This allows the processor to control the operating frequency of the HF RF generator during the time interval in which positive crossing 122 occurs. For example, having determined the operating frequency of the HF RF generator for bin 1n of cycle 1, the processor applies that operating frequency during bin 1n of cycle 2 of the voltage 112. Bin 1n of cycle 2 extends from time tQq of cycle 2 to time t1r of cycle 2. During bin 1n of cycle 2 of the voltage 112, positive crossing 122 occurs and the operating frequency of the HF RF generator is controlled by the processor 214 at the positive crossing 112.

[0063] As another example, instead of dividing the second half 112B of cycle 1 of the voltage 112 into a preset number of bins 1n to Nn such that bin 1n begins at the positive crossing point 122 of cycle 1 and bin Nn ends at the negative crossing point 124b of cycle 2, the processor divides a portion of the first half 112A of cycle 1, the second half 112B of cycle 1, and a portion of the first half 112A of cycle 2 of the voltage 112 into a preset number of bins 1n to Nn. Illustratively, bin 1n begins at a first predetermined interval before time tMm and ends at a second predetermined interval after time tMm.

[0064] In a similar manner, the processor divides the time interval around the negative crossing point 124b of cycle 2 to generate bin 1m of cycle 2. As an example, bin 1m of cycle 2 spans from a third predetermined time interval before time t in cycle 1 at which the negative crossing point 124b occurs, to a fourth predetermined time interval after time t.

[0065] FIG. 2 is an embodiment of a plasma system 200 for illustrating application of an operating frequency of an HF RF generator to multiple bins. The plasma system 200 includes an LF RF generator, an HF RF generator, an impedance matching circuit (IMC) 202, a host computer 212, a plasma chamber 220, a voltage sensor 204, a control system 222, and a power sensor 224. The LF RF generator is a radio frequency generator operating in a low frequency range, e.g., in the kilohertz (kHz) frequency range. For example, the LF RF generator is a 400 kHz RF generator having a frequency tuning range of 330 kHz to 440 kHz. As another example, the LF RF generator is a 100 kHz RF generator having a frequency tuning range of 50 kHz to 150 kHz. The HF RF generator is a radio frequency generator operating in a high frequency range, e.g., in the megahertz (MHz) frequency range. As an example, the HF RF generator is a 60 MHz RF generator having a frequency tuning range of 54 MHz to 63 MHz. As another example, the HF RF generator operates at a frequency in the range of 20 MHz to 30 MHz, or at a frequency in the range of 12 MHz to 14 MHz, or at a frequency in the range of 1 MHz to 3 MHz.

[0066] An example of the IMC 202 is a network of electrical components such as capacitors and inductors. For example, the IMC 202 includes a plurality of inductors and a plurality of capacitors, and the inductors and capacitors are coupled to each other. Examples of the capacitors include fixed capacitors and variable capacitors, and examples of the inductors include fixed inductors and variable inductors. The IMC 202 has two branch circuits including a first branch circuit and a second branch circuit.

[0067] The host computer 212 includes a processor 214 and a memory device 216. The processor 214 is coupled to the memory device 216. By way of example, the processor may be a controller, or an application specific integrated circuit (ASIC), or a programmable logic device (PLD), or a central processing unit (CPU), or a microcontroller, or a microprocessor, and these terms are used interchangeably herein. Examples of memory devices used herein include random access memory (RAM), read only memory (ROM), and combinations thereof.

[0068] An example of the control system 222 is a combination of a drive system and a motor system. The drive system includes one or more drive devices, such as one or more transistors, and the motor system includes one or more motors, such as one or more electric motors. The drive system is coupled to the motor system, which is coupled to the IMC 202 through one or more connections, such as one or more rods or a combination of multiple rods and one or more gears. For example, the electric motor is coupled to the plates of a capacitor of the IMC 202 through two rods and gears, and the gear is coupled between the two rods.

[0069] The processor 214 is coupled to the LF RF generator via a transfer cable 236 A and to the HF RF generator via another transfer cable 236 B. As an example, the processor 214 is connected to a digital signal processor (DSP) of the LF RF generator via the transfer cable 236 A and to a DSP of the HF RF generator via the transfer cable 236 B. Examples of transfer cables include a serial transfer cable, a parallel transfer cable, and a universal serial bus (USB) cable.

[0070] The processor 214 is also coupled to the voltage sensor 204 via a transfer cable 236C and to the power sensor 224 via a transfer cable 236D. The processor 214 is also coupled to the drive system of the control system 222.

[0071] The plasma chamber 106 is a capacitively coupled plasma (CCP) chamber and includes a chuck 226 and an upper electrode 228. The upper electrode 228 has a lower surface opposite an upper surface of the chuck 226. An example of the chuck 226 is an electrostatic chuck (ESC). The chuck 226 includes a lower electrode made of a metal, such as aluminum or an aluminum alloy. The upper electrode 228 is coupled to ground potential and is made of silicon.

[0072] The output 230A of the LF RF generator is coupled to an input 232A of the IMC 202 via an RF cable 234A. The input 232A is coupled to a first branch of the IMC 202. The output 230B of the HF RF generator is coupled to another input 232B of the IMC 202 via another RF cable 234B. The input 232B is coupled to a second branch of the IMC 202. The first and second branches of the IMC 202 are coupled to each other at a junction, which is coupled to an output 206 of the IMC 202. As an example, the output 206 is an output port of a housing or enclosure of the IMC 202, and the RF transmission line 210 extends from the output port to the outside of the matching section. The output 206 of the IMC 202 is coupled to a lower electrode of the chuck 226 via the RF transmission line 210 and an input 208 of the plasma chamber 220. The input 208 is a point on the RF transmission line 210. To explain, the input 208 is a port in the housing or enclosure of the plasma chamber 220 from which the RF transmission line extends into the housing or enclosure. Examples of the RF transmission line 210 include an RF rod and an RF cylinder. The RF rod is coupled to an RF cylinder located in the plasma chamber. The RF rod is surrounded by an RF tunnel of the RF transmission line 210 and an RF sheath of the RF transmission line 210. The RF sheath surrounds the RF tunnel, and the RF tunnel includes an insulator material to insulate the RF rod from the RF sheath.

[0073] The power sensor 224 is coupled to the output 230B of the HF RF generator and the voltage sensor 204 is coupled to the output 206 of the IMC 202. For example, the power sensor 224 is coupled to the output 230B of the HF RF generator HF power supply and the voltage sensor 204 is coupled to the junction of the first and second branches of the IMC 202. The power sensor 224 measures the delivered power, which is the difference between the power delivered at output 230B and the power reflected to output 230B. The power reflected to output 230B is reflected from the plasma chamber 220, through the RF sheath and housing of the IMC 202, the RF sheath of the RF cable 234B, and to the output 230B to the HF RF generator.

[0074] The processor 214 provides parameter setpoints, such as frequency and power, to the LF RF generator via transmission cable 236A and parameter setpoints to the HF RF generator via transmission cable 236B. Upon receiving the parameter setpoints, the LF RF generator generates an RF signal 218A and transmits the RF signal 218A to the first branch via output 230A, RF cable 234A, and input 232A. Similarly, upon receiving the parameter setpoints, the HF RF generator generates an RF signal 218B and transmits the RF signal 218B to the second branch via output 230B, RF cable 234B, and input 232B.

[0075] The first branch of the IMC 202 matches the impedance of a load coupled to the output 206 with the impedance of a source coupled to the input 232A and outputs a first modified RF signal at a connection to the IMC 202. Examples of loads coupled to the output 206 include RF transmission line 210 and plasma chamber 220. Examples of sources coupled to the input 232A include RF cable 234A and an LF RF generator. Similarly, the second branch of the IMC 202 matches the impedance of a load coupled to the output 206 with the impedance of a source coupled to the input 232B and outputs a second modified RF signal at a connection to the IMC 202. Examples of sources coupled to the input 232B include RF cable 234B and an HF RF generator. The first modified RF signal and the second modified RF signal are combined, such as summed, at a connection to the IMC 202 to output a modified RF signal 238 at a connection.

[0076] The modified RF signal 238 is provided from the connection point to an output 206 and further provided via an RF transmission line 210 to a lower electrode of the chuck 226. In addition to providing power of the modified RF signal 238 to the lower electrode of the chuck 226, one or more process gases, such as an oxygen-containing gas or a fluorine-containing gas, are provided to the plasma chamber 220 to strike or sustain a plasma in the plasma chamber 220 for processing a substrate S disposed on an upper surface of the chuck 226. Examples of substrates S include semiconductor wafers and substrate stacks.

[0077] While the modified RF signal 238 is provided to the lower electrode, the voltage sensor 204 measures the voltage 112 (FIGS. 1B-1 and 1D-1) at the output 206 to generate a measurement of the voltage 112, which is provided to the processor 214 via the transfer cable 236C. Additionally, the voltage sensor 204 provides the processor 214 with the time at which the measurement was made via the transfer cable 236C. Upon receiving the measurement of the voltage 112 and the time at which the measurement was made, the processor 214 identifies the positive and negative crossing points of each cycle of the voltage 112 and divides the voltage 112 into bins 1m to Nm. For example, the processor 214 determines or identifies from the measurement a time at which the voltage 112 is at a predetermined value, such as the value of the DC offset 114 (FIG. 1B-1) or a value of zero with no DC offset at all. The processor 214 further determines from the measurement that the value of the voltage 112 increases at a time after the voltage 112 is at the predetermined value compared to a time before the voltage 112 is at the predetermined value. To illustrate, the processor 214 determines that the value of the voltage 112 in the time interval between time tMm and time t1n (FIG. 1B-1) is greater than the value of the voltage 112 in the time interval between time t(M-1)m and time tMm (FIG. 1B-1). To illustrate another example, the processor 214 determines that the value of the voltage 112 in the time interval between time tMm and time t1r (FIG. 1D-1) is greater than the value of the voltage 112 in the time interval between time tQq and time tMm (FIG. 1D-1). When the processor 214 determines that the value of the voltage 112 increases after the voltage 112 is at the predetermined value compared to the time before the voltage 112 is at the predetermined value, the processor 214 determines that the time at which the predetermined value occurs is a positive intersection.

[0078] As another example, the processor 214 determines or identifies from the measurements a time when the voltage 112 is at a predetermined value, such as the value of the DC offset 114 (FIG. 1B-1) or a value of zero with no DC offset at all. The processor 214 further determines from the measurements that the value of the voltage 112 is decreased at a time after the voltage 112 is at the predetermined value compared to a time before the voltage 112 is at the predetermined value. Illustratively, the processor 214 determines that the value of the voltage 112 in the time interval between times tNn and t1m (FIG. 1B-1) is less than the value of the voltage 112 in the time interval between times t(N-1)n and tNn (FIG. 1B-1).

[0079] Alternatively, the processor 214 determines that the value of the voltage 112 in the time interval between times tNn and t1q (FIG. 1D-1) is less than the value of the voltage 112 in the time interval between times tRr and tNn (FIG. 1D-1). If the processor 214 determines that the value of the voltage 112 is decreasing after the voltage 112 is at the predetermined value compared to the time before the voltage 112 is at the predetermined value, the processor 214 determines that the time at which the predetermined value occurs is a negative intersection point.

[0080] As another example, the processor 214 divides the time interval of the second half 112B of each cycle of the voltage 112 (FIGS. 1B-1 and 1D-1) into bins 1n to Nn. To explain, the processor 214 divides the time interval from time tMm to time tNn into bins 1n to Nn (see FIG. 1B-1) such that bin 1n begins at the positive intersection 122 and bin Nn ends at the negative intersection 124b. To explain, the processor 214 divides the time interval from time tQq (FIG. 1D-1) to time tRr into bins 1n to Nn, where R is an integer. Time tQq is close to time tMm of the positive intersection 122 of cycle 1, and time tRr is close to time tNn of the negative intersection 124b of cycle 2 (FIG. 1D-1). For example, time tQq is within a predetermined range from time tMm of positive crossing 122 in cycle 1, and time tRr is within a predetermined range from time tNn of negative crossing 124b in cycle 2. The predetermined ranges associated with each crossing of voltage 112 are stored in memory device 216. In this example, processor 214 does not divide the time interval of the first half 112A of each cycle of voltage 112 (FIGS. 1B-1 and 1D-1) into bins 1m through Mm.

[0081] As yet another example, the processor 214 divides the time interval of the first half 112A of each cycle of the voltage 112 into bins 1m to Mm. In this example, the processor 214 does not divide the time interval of the second half 112B of each cycle of the voltage 112 into bins 1n to Nn. To explain, the processor 214 divides the time interval from time tNn to time tMm into bins 1m to Mm (FIG. 1B-1) such that bin 1m begins at the negative intersection 124a and bin Mm ends at the positive intersection 122. To explain another way, the processor 214 divides the time interval from time tRr (FIG. 1D-1) to time tQq into bins 1m to Mm. Time tRr is close to time tNn of the negative intersection 124a of cycle 1, and time tQq is close to time tMm (FIG. 1D-1) of the positive intersection 122 of cycle 1. For example, time tRr is within a predetermined range from time tNn of negative intersection 124a of cycle 1, and time tQq is within a predetermined range from time tMm of positive intersection 122 of cycle 1. In this example, processor 214 does not divide the time interval of the second half 112B of each cycle of voltage 112 (FIGS. 1B-1 and 1D-1) into bins 1n through Nn.

[0082] As yet another example, the processor 214 divides the time interval of each cycle of the voltage 112 into bins 1m to Nn. Explaining, the processor 214 identifies the negative crossing point 124a (FIG. 1D-1) of cycle 1 of the voltage 112 from the measurements, and identifies the consecutive negative crossing point 124b (FIG. 1D-1) of cycle 1 or cycle 2 of the voltage 112 from the measurements. The processor 214 determines the period taken by the voltage sensor 204 to obtain the measurements between the two consecutive negative crossing points 124a and 124b. The processor 214 divides the period into a predetermined number of time intervals to generate bins 1m to Nn. The period for obtaining the measurements of the voltage 112 for each cycle of the voltage 112 is transmitted from the voltage sensor 204 to the processor 214 via the transmission cable 236C along with the measurements. The predetermined number of time intervals are stored in memory device 216 and received as input from a user via a user interface including an input device such as a mouse, keyboard, or keypad, a display device, a display screen, or a combination thereof. The input device is coupled to processor 214. As another example, processor 214 divides a portion of the time intervals of each cycle of voltage 112 into a pre-stored number of bins. An example of a pre-stored number of bins is provided below.

[0083] The processor 214 also receives the measurements of the delivered power from the power sensor 224 via the transfer cable 236D, and the time at which the measurements were made by the power sensor 224. The time at which the measurements of the delivered power were taken by the power sensor 224 for each cycle of the voltage 112 are transmitted from the power sensor 224 to the processor 214 along with the measurements via the transfer cable 236D. To generate the measurements of the delivered power, the delivered power at the output 230B is measured by the power sensor 224. The processor 214 associates the measurements of the delivered power with bins 1m to Nn. For example, the processor 214 determines that a first set of measurements or a first measurement of the delivered power corresponds to a period of bin 1n, and a second set of measurements or a second measurement of the delivered power corresponds to a period of bin 2n. The measurements of the delivered power include one value of the delivered power, and the set of measurements of the delivered power include multiple values ​​of the delivered power. When multiple values ​​for the delivered power are received during a bin, the processor 214 calculates the average or median of those values ​​to determine a single measure of the delivered power for that bin.

[0084] For each of the pre-stored number of bins from bin 1m to Nn, processor 214 determines a frequency level, which is a quantity of the operating frequency of the HF RF generator, to achieve a predetermined level UNFM, such as a uniform value or a range of continuous values. For example, processor 214 determines that increasing the frequency level of the HF RF generator from a setpoint value to level HF1m during bin 1m will increase the transmit power from a measured level, such as a measured value for bin 1m, to level PR1m for bin 1m to further achieve level UNFM. The measured level of transmit power for bin 1m is received from power sensor 224 in the manner described above. Processor 214 controls the HF RF generator during bin 1m of cycle 1 of voltage 112 to achieve the frequency level HF1m, and receives a measured value of power level PR1m from power sensor 224 and determines that increasing the frequency level from a setpoint value to level HF1m will increase the transmit power from a measured level to level PR1m. The delivered power is increased to a level PR1m to achieve or exceed the uniformity level UNFM. The correspondence between the levels PR1m and UNFM is stored in a table 240 in the memory device 216. The processor 214 stores the determined frequency level as corresponding to bin HF1m in the table 240.

[0085] As another example, the processor 214 determines that increasing the frequency level of the HF RF generator from the setpoint value to level HF1m during bin 1m will cause the transmitted power to be decreased from the measured level for bin 1m to level PR1m for bin 1m instead of increased.

[0086] As yet another example, the processor 214 determines that instead of increasing the frequency level of the HF RF generator, it will decrease the frequency level from the setpoint value during bin 1m to a level HF1m, thereby increasing the transmitted power from the measured level for bin 1m to a level PR1m for bin 1m.

[0087] As yet another example, the processor 214 determines that lowering the frequency level of the HF RF generator from the setpoint value to level HF1m during bin 1m will cause the transmitted power to be decreased from the measured level for bin 1m to level PR1m for bin 1m instead of increased.

[0088] Similarly, as another example, the processor 214 determines that increasing the frequency level of the HF RF generator from HF1m in bin 1m to level HF2m will increase the delivered power from the measured level for bin 2m to level PR2m for bin 2m to further achieve level UNFM. The measured level of the delivered power for bin 2m is received from the power sensor 224 in the manner described above. The processor 214 controls the HF RF generator during bin 2m of cycle 1 of the voltage 112 to achieve the frequency level HF2m, and receives a measured value of the power level PR2m from the power sensor 224 to determine that increasing the frequency level to level HF2m will increase the delivered power from the measured level to level PR2m. The delivered power is increased to level PR2m to achieve level UNFM of uniformity. The correspondence between the levels PR2m and UNFM is stored in a table 240 in the memory device 216. The processor 214 stores the determined frequency level HF2m as corresponding to bin 2m in the table 240.

[0089] As another example, the processor 214 determines that increasing the frequency level of the HF RF generator from level HF1m to level HF2m during bin 2m would cause the transmitted power to be decreased from the measured level for bin 2m to level PR2m for bin 2m instead of increased.

[0090] As yet another example, the processor 214 determines that instead of increasing the frequency level of the HF RF generator, lowering it to a level HF2m during bin 2m would increase the transmitted power from the measured level for bin 2m to a level PR2m for bin 2m.

[0091] As yet another example, the processor 214 determines that lowering the frequency level of the HF RF generator to a level HF2m during bin 2m would cause the transmitted power to be decreased from the measured level for bin 2m to a level PR2m for bin 2m instead of increased.

[0092] As another example, the processor 214 determines that increasing the frequency level of the HF RF generator to a level HFMm during bin Mm will increase the delivered power from a measured level for bin Mm to a level PRMm for bin Mm to further achieve the level UNFM. The frequency level is increased from a frequency level HF(M-1)m for bin (M-1)m to a level HFMm. A measured level of the delivered power for bin Mm is received from the power sensor 224 in the manner described above. The processor 214 controls the HF RF generator during bin Mm of cycle 1 of the voltage 112 to achieve the frequency level HFMm, and receives a measured value of the power level PRMm from the power sensor 224 to determine that increasing the frequency level to the level HFMm will increase the delivered power from a measured level to the level PRMm. The delivered power is increased to the level PRMm to achieve the uniformity level UNFM. The correspondence between the levels PRMm and the levels UNFM is stored in the table 240. The processor 214 stores the determined frequency level HFMm as corresponding to bin Mm in the table 240.

[0093] As another example, the processor 214 determines that increasing the frequency level of the HF RF generator from frequency level HF(M-1)m to level HFMm during bin Mm will cause the transmitted power to be decreased, instead of increased, from the measured level for bin Mm to a level PRMm for bin Mm.

[0094] As yet another example, the processor 214 determines that lowering the frequency level of the HF RF generator to a level HFMm during bin Mm, instead of increasing it, would increase the transmitted power from the measured level for bin Mm to a level PRMm for bin Mm.

[0095] As yet another example, the processor 214 determines that lowering the frequency level of the HF RF generator to a level HFMm during bin Mm would cause the transmitted power to be decreased from the measured level for bin Mm to a level PRMm for bin Mm instead of increased.

[0096] As yet another example, the processor 214 determines that increasing the frequency level of the HF RF generator from level HFMm to level HF1n during bin 1n will increase the delivered power from the measured level for bin 1n to level PR1n for bin 1n to further achieve level UNFM. The measured level of the delivered power for bin 1n is received from the power sensor 224 in the manner described above. The processor 214 controls the HF RF generator during bin 1n of cycle 1 of the voltage 112 to achieve the frequency level HF1n, and receives a measured value of the power level PR1n from the power sensor 224 to determine that increasing the frequency level to level HF1n will increase the delivered power from the measured level to level PR1n. The delivered power is increased to level PR1n to achieve the uniformity level UNFM. The correspondence between the levels PR1n and the levels UNFM is stored in a table 242 in the memory device 216. The processor 214 stores the determined frequency level HF1n as corresponding to bin 1n in the table 242.

[0097] As another example, the processor 214 determines that increasing the frequency level of the HF RF generator from frequency level HFMm to level HF1n during bin 1n will cause the transmitted power to be decreased from the measured level for bin 1n to level PR1n for bin 1n instead of increased.

[0098] As yet another example, the processor 214 determines that instead of increasing the frequency level of the HF RF generator, lowering it to a level HF1n during bin 1n would increase the transmitted power from the measured level for bin 1n to a level PR1n for bin 1n.

[0099] As yet another example, the processor 214 determines that lowering the frequency level of the HF RF generator to a level HF1n during bin 1n will cause the transmitted power to be decreased from the measured level for bin 1n to a level PR1n for bin 1n instead of increased.

[0100] Similarly, as another example, the processor 214 determines that increasing the frequency level of the HF RF generator from level HF1n to level HF2n during bin 2n will increase the delivered power from the measured level for bin 2n to level PR2n for bin 2n to further achieve level UNFM. The measured level of the delivered power for bin 2n is received from the power sensor 224 in the manner described above. The processor 214 controls the HF RF generator during bin 2n of cycle 1 of the voltage 112 to achieve the frequency level HF2n, and receives a measured value of the power level PR2n from the power sensor 224 to determine that increasing the frequency level to level HF2n will increase the delivered power from the measured level to level PR2n. The delivered power is increased to level PR2n to achieve the uniformity level UNFM. The correspondence between the levels PR2n and the levels UNFM is stored in a table 242 in the memory device 216. The processor 214 stores the determined frequency level HF2n as corresponding to bin 2n in the table 240.

[0101] As another example, the processor 214 determines that increasing the frequency level of the HF RF generator from frequency level HF1n to level HF2n during bin 2n will cause the transmitted power to decrease, instead of increase, from the measured level for bin 2n to level PR2n for bin 2n.

[0102] As yet another example, the processor 214 determines that instead of increasing the frequency level of the HF RF generator, lowering it to a level HF2n during bin 2n would increase the transmitted power from the measured level for bin 2n to a level PR2n for bin 2n.

[0103] As yet another example, the processor 214 determines that lowering the frequency level of the HF RF generator to a level HF2n during bin 2n will cause the transmitted power to be decreased from the measured level for bin 2n to a level PR2n for bin 2n instead of increased.

[0104] As another example, the processor 214 determines that increasing the frequency level of the HF RF generator to a level HFNn during bin Nn will increase the transmit power from a measured level for bin Nn to a level PRNn for bin Nn. To further achieve the level UNFM, the frequency level is increased from a frequency level HF(N-1)n for bin (N-1)n to a level HFNn for bin Nn. The measured level of the transmit power for bin Nn is received from the power sensor 224 in the manner described above. The processor 214 controls the HF RF generator during bin Nn of cycle 1 of the voltage 112 to achieve the frequency level HFNn, and receives a measured value of the power level PRNn from the power sensor 224, and determines that increasing the frequency level to a level HFNn will increase the transmit power from a measured level to a level PRNn. The transmit power is increased to a level PRNn to achieve the level UNFM of uniformity. The correspondence between the level PRNn and the level UNFM is stored in the table 240. The processor 214 stores the determined frequency level HFNn as corresponding to bin Nn in the table 240.

[0105] As another example, the processor 214 determines that increasing the frequency level of the HF RF generator from frequency level HF(N-1)n to level HFNn during bin Nn will cause the transmitted power to decrease, instead of increase, from the measured level for bin Nn to level PRNn for bin Nn.

[0106] As yet another example, the processor 214 determines that lowering the frequency level of the HF RF generator to a level HFNn during bin Nn, instead of increasing it, would increase the transmitted power from the measured level for bin Nn to a level PRNn for bin Nn.

[0107] As yet another example, the processor 214 determines that lowering the frequency level of the HF RF generator to a level HFNn during bin Nn will cause the transmitted power to be decreased from the measured level for bin Nn to a level PRNn for bin Nn instead of increased.

[0108] In one embodiment, the uniformity level is achieved when a predetermined value of uniformity is reached or when a value within a preset range of the predetermined value of uniformity is reached. An example of the preset range is a range of ±5% from the predetermined value. The preset range and the predetermined value of uniformity are stored in memory device 216.

[0109] Examples of uniformity include the uniformity of the etch rate across the surface of the substrate, or the uniformity of the deposition rate across the surface of the substrate. As one example, the uniformity level is a statistical value, such as the average or median etch rate across the surface of the substrate. As another example, the uniformity level is a maximum or minimum value of all etch rates across the surface of the substrate.

[0110] An example of a pre-stored number of bins out of bins 1m through Nn includes bin numbers 1m through Mm for the first half 112A of cycle 1 of voltage 112.

[0111] Another example of a pre-stored number of bins out of bins 1m through Nn includes bin numbers 1n through Nn for the second half 112B of cycle 1 of voltage 112.

[0112] Yet another example of the pre-stored number of bins includes one or more, such as all of bins 1m through Nn of the cycles of the voltage 112.

[0113] Yet another example of the pre-stored number of bins out of bins 1m through Nn includes bin numbers 1n through Nn for the first quarter of cycle 1 or the second quarter of cycle 1 or the third quarter of cycle 1 or the fourth quarter of cycle 1 of voltage 112. The second quarter of cycle 1 is contiguous with the first quarter of cycle 1. Similarly, the third quarter of cycle 1 is contiguous with the second quarter of cycle 1 and the fourth quarter of cycle 1 is contiguous with the third quarter of cycle 1.

[0114] Another example of the pre-stored number of bins includes a predetermined number of bins associated with the positive intersection 122. To explain, the predetermined number of bins associated with the positive intersection 122 includes bin 1n (FIGS. 1B-1 and 1D-1) or bin Mm (FIG. 1B-1) that includes time tMm of the positive intersection 122.

[0115] As another explanation, the predetermined number of bins associated with the positive intersection 122 includes bin In or bin Mm (FIG. 1B-1) and a preset number of additional bins adjacent to bin In or bin Mm. The preset number of additional bins are stored in the memory device 216. As an example, bins 2n and Mm are adjacent to bin In (FIG. 1B-1), and bins (M-1)m and In are adjacent to bin Mm (FIG. 1B-1).

[0116] As another example, bin 2n, bin 3n (FIG. 1B-1), bin (M-1)m, and Mm are adjacent to bin 1n (FIG. 1B-1), and bin (M-2)m (FIG. 1B-1), bin (M-1)m, and bins 1n and 2n (FIG. 1B-1) are adjacent to bin Mm. One or more bins are adjacent to a further bin when there are no other bins between such one or more bins and the further bin.

[0117] As yet another example, the bins in the second quarter of cycle 1 and the third quarter of cycle 1 of voltage 112 are examples of the predetermined number of bins associated with positive intersection point 122.

[0118] As a further alternative explanation, the predetermined number of bins associated with the positive intersection 122 includes bin 1n (FIG. 1D-1) and a pre-defined number of additional bins adjacent to bin 1n. Bins 2n and Mm are adjacent to bin 1n (FIG. 1D-1). Also, bins 2n and 3n (FIG. 1D-1), and bins (M-1)m and Mm are adjacent to bin 1n (FIG. 1D-1).

[0119] Note that in one embodiment, the predetermined number of bins associated with the positive intersection 122 of a cycle is less than the number of bins for one half of a cycle. For example, the predetermined number of bins associated with the positive intersection 122 of cycle 1 is less than the number of bins in either the first half 112A or the second half 112B of cycle 1.

[0120] Another example of the pre-stored number of bins is a predetermined number of bins associated with the negative intersection point 124a. To explain, the predetermined number of bins associated with the negative intersection point 124a includes the bin Nn or bin lm (FIGS. 1B-1 and 1D-1) that includes the time tNn of the negative intersection point 124a.

[0121] Alternatively, the predetermined number of bins associated with the negative intersection point 124a may include bin Nn or bin 1m (FIG. 1B-1) and a pre-defined number of additional bins adjacent to bin Nn or bin 1m. As an example, bins (N-1)n and 1m are adjacent to bin Nn (FIG. 1B-1), and bins 2m and Nn are adjacent to bin 1m (FIG. 1B-1).

[0122] As another example, bins (N-1)n, (N-2)n (Figure 1B-1), and bins 1m and 2m are adjacent to bin Nn (Figure 1B-1), and bins (N-1)n and Nn, and bins 2m and 3m (Figure 1B-1) are adjacent to bin 1m.

[0123] As yet another example, the bins that are in the fourth quarter of cycle 0 and the first quarter of cycle 1 of the voltage 112 are examples of the predetermined number of bins associated with the negative intersection point 124a.

[0124] As a further alternative explanation, the predetermined number of bins associated with the negative intersection point 124a includes bin 1m (FIG. 1D-1) and a pre-defined number of additional bins adjacent to bin 1m. Bins 2m and Nn are adjacent to bin 1m (FIG. 1D-1). Also, bins 2m and 3m (FIG. 1D-1), and bins (N-1)n and Nn are adjacent to bin 1m (FIG. 1D-1).

[0125] Note that in one embodiment, the predetermined number of bins associated with a negative intersection point of a cycle, such as negative intersection point 124a or 124b, is less than the number of bins for one half of a cycle. For example, the predetermined number of bins associated with negative intersection point 124a of cycle 1 is less than the number of bins in the second half of cycle 0 or the first half of cycle 1 112A.

[0126] In one embodiment, after obtaining measurements of the delivered power for the pre-stored number of bins of cycle 1 of the voltage 112, the processor 214 determines whether a predetermined statistical power value of the delivered power for the pre-stored number of bins of cycle 1 is achieved. An example of the statistical power value of the delivered power for the pre-stored number of bins includes an average or median of multiple values ​​of the delivered power for the pre-stored number of bins. Upon determining that the predetermined statistical power value is not achieved, the processor 214 modifies one or more of the frequency levels for one or more of the pre-stored number of bins. The processor 214 continues to modify one or more of the frequency levels until the predetermined statistical power value of the delivered power for the pre-stored number of bins of cycle 1 is achieved.

[0127] For example, after obtaining measurements of the delivered power for bins 1m to Mm of cycle 1 of the voltage 112 from the power sensor 224, the processor 214 determines whether a predetermined statistical power value of the delivered power for bins 1m to Mm of cycle 1 is achieved by the frequency level for bins 1m to Mm. For example, the processor 214 obtains measurements of the delivered power for bins 1m to Mm and averages these measurements to determine an average delivered power level for bins 1m to Mm of cycle 1. The processor 214 further determines whether the average delivered power level for bins 1m to Mm of cycle 1 is greater than a predetermined average delivered power level stored in the memory device 216 for bins 1m to Mm. The predetermined average delivered power level for the first half 112A is received by the processor 214 from a user via a user interface including an input device. If the processor 214 determines that the average transmit power level for the bins 1m to Mm is greater than the predetermined average transmit power level for the bins 1m to Mm, the processor 214 does not modify one or more of the frequency levels for the bins 1m to Mm. On the other hand, if the processor 214 determines that the average transmit power level for the bins 1m to Mm is not greater than the predetermined average transmit power level for the bins 1m to Mm, the processor 214 changes one or more of the frequency levels for the bins 1m to Mm. The processor 214 continues to change one or more of the frequency levels for the bins 1m to Mm until the average transmit power level for the bins 1m to Mm is greater than the predetermined average transmit power level for the bins 1m to Mm. The frequency levels for the bins 1m to Mm are modified from frequency level HF1m to HFMm.

[0128] In one embodiment, instead of changing one or more of the frequency levels for bins 1m to Mm during bins 1m to Mm of cycle 1 of the voltage 112, the processor 214 changes one or more of the frequency levels for bins 1m to Mm during bins 1m to Mm of multiple consecutive cycles of the voltage 112 until the average delivered power level for bins 1m to Mm is greater than a predetermined average delivered power level for bins 1m to Mm.

[0129] As another example, after obtaining measurements of the delivered power for bins 1n to Nn of cycle 1 of the voltage 112 from the power sensor 224, the processor 214 determines whether a predetermined statistical power value of the delivered power for bins 1n to Nn of cycle 1 is achieved by the frequency level for bins 1n to Nn. For example, the processor 214 obtains measurements of the delivered power for bins 1n to Nn and averages these measurements to determine an average delivered power level for bins 1n to Nn of cycle 1. The processor 214 further determines whether the average delivered power level for bins 1n to Nn of cycle 1 is greater than a predetermined average delivered power level stored in the memory device 216 for bins 1n to Nn. The predetermined average delivered power level for the second half 112B is received by the processor 214 from a user via a user interface including an input device. If the processor 214 determines that the average transmit power level for bins 1n to Nn is greater than the predetermined average transmit power level for bins 1n to Nn, the processor 214 does not modify one or more of the frequency levels for bins 1n to Nn. On the other hand, if the processor 214 determines that the average transmit power level for bins 1n to Nn is not greater than the predetermined average transmit power level for bins 1n to Nn, the processor 214 changes one or more of the frequency levels for bins 1m to Mm. The processor 214 continues to change one or more of the frequency levels for bins 1n to Nn until the average transmit power level for bins 1n to Nn is greater than the predetermined average transmit power level for bins 1n to Nn. The frequency levels for bins 1n to Nn are modified to frequency levels HF1n to HFNn.

[0130] In one embodiment, instead of varying one or more of the frequency levels for bins 1n to Nn during bins 1n to Nn of cycle 1 of the voltage 112, the processor 214 varies one or more of the frequency levels for bins 1n to Nn during bins 1n to Nn of multiple consecutive cycles of the voltage 112 until the average delivered power level for bins 1n to Nn is greater than a predetermined average delivered power level for bins 1n to Nn.

[0131] In one embodiment, after obtaining measurements of the delivered power for the pre-stored number of bins of cycle 1 of voltage 112, processor 214 determines whether a predetermined statistical power value of the delivered power for the entire cycle 1 of voltage 112 is achieved. An example of the statistical power value of the delivered power for the cycle of the voltage includes an average or median value of multiple values ​​of the delivered power for all the bins of the cycle. If it is determined that the predetermined statistical power value is not achieved, processor 214 modifies one or more of the frequency levels for one or more of the pre-stored number of bins. Processor 214 continues to modify one or more of the frequency levels until the predetermined statistical power value of the delivered power for cycle 1 is achieved. The frequency levels for bins 1m to Nn are modified to frequency levels HF1m to HFNn.

[0132] As used herein, a predetermined statistical power value of the delivered power for a pre-stored number of bins corresponds to the uniformity level UNFM. For example, the uniformity level UNFM is achieved when the predetermined statistical power value is achieved for the pre-stored number of bins.

[0133] In one embodiment, instead of a predetermined statistical power value of the transmitted power, a predetermined ratio of the transmitted power is used, for example the ratio of the average transmitted power for bins 1n to Nn to the average transmitted power for bins 1m to Mm.

[0134] Another example of the ratio of the delivered power includes the ratio of the average delivered power for bins 1m to Mm and the average delivered power for bins 1n to Nn. For example, the processor 214 determines whether the predetermined delivered power ratio is achieved from the frequency levels of bins 1m to Nn during cycle 1. If it is determined that the predetermined delivered power ratio is not achieved, the processor 214 modifies one or more of the frequency levels of bins 1m to Nn. The processor 214 continues to modify one or more of the frequency levels of bins 1m to Nn until the predetermined delivered power ratio is achieved. The predetermined delivered power ratio corresponds to the uniformity level UNFM. For example, when the predetermined delivered power ratio is achieved for cycle 1, the uniformity level UNFM is achieved.

[0135] The processor 214 generates a table 240 including correspondences between each of the bins 1m to Mm and the corresponding ones of the frequency values ​​HF1m to HFMm, the corresponding ones of the power levels PR1m to PRMm, the predetermined statistical power values ​​of the delivered power for a pre-stored number of bins, and the uniformity level UNFM, and stores the table 240 in the memory device 216. Similarly, the processor 214 generates a table 242 including correspondences between each of the bins 1n to Nn and the corresponding ones of the frequency values ​​HF1n to HFNn, the corresponding ones of the power levels PR1n to PRNn, the predetermined statistical power values ​​of the delivered power for a pre-stored number of bins, and the uniformity level UNFM, and stores the table 242 in the memory device 216.

[0136] The processor 214 applies the RF levels in tables 240 and 242 during one or more subsequent cycles of the voltage 112. For example, when the RF level is determined during cycle 1 of the voltage 112, the processor 214 applies the RF level in tables 240 and 242 during cycle 2 of the voltage 112.

[0137] As another example, when the RF level is determined during cycle 1 of the voltage 112 , the processor 214 applies the RF levels in tables 240 and 242 during cycles 2 and 3 of the voltage 112 .

[0138] As yet another example, when the RF level is determined during cycles 1 and 2 of the voltage 112 , the processor 214 applies the RF levels of tables 240 and 242 during cycle 3 of the voltage 112 .

[0139] As another example, the processor 214 applies a determined high frequency level HF1n during bin 1n of cycle 1 of the voltage 112. The high frequency level HF1n is applied during bin 1n, such as from a start time of bin 1n to an end time of bin 1n, of cycle 2 of the voltage 112. An example of a start time of bin 1n includes time tMm (FIG. 1D-1) or time tQq (FIG. 1D-1). An example of an end time of bin 1n includes time t1n (FIG. 1D-1) or time t1r (FIG. 1D-1).

[0140] As yet another example, the processor 214 applies a determined high frequency level HFNn during bin Nn of cycle 1 of the voltage 112. The high frequency level HFNn is applied during bin Nn, such as from a start time of bin Nn to an end time of bin Nn, of cycle 2 of the voltage 112. An example of a start time of bin Nn includes time t(N-1)n (FIG. 1B-1) or time t(R-1)r (FIG. 1D-1). An example of an end time of bin Nn includes time tNn (FIG. 1B-1) or time tRr (FIG. 1D-1).

[0141] As another example, the processor 214 applies a determined high frequency level HF1m during bin 1m of cycle 1 of the voltage 112, where the high frequency level HF1m is applied during bin 1m of cycle 2 of the voltage 112.

[0142] As yet another example, the processor 214 applies a determined high frequency level HF1m during bin Mm of cycle 1 of the voltage 112, where the high frequency level HF1m is applied during bin Mm of cycle 2 of the voltage 112.

[0143] As another example, during bin 1n of cycle 2 of the voltage 112, the processor 214 transmits a data signal having a frequency value HF1n to the HF RF generator via the transmission cable 236B. Upon receiving the data signal having frequency value HF1n during bin 1n of cycle 2, the HF RF generator generates an RF signal 218B having a high frequency level HF1n.

[0144] Similarly, during bin Nn of cycle 2 of the voltage 112, the processor 214 transmits a data signal having a frequency value HFNn to the HF RF generator via the transmission cable 236B. Upon receiving the data signal having a frequency value HFNn during bin Nn of cycle 2, the HF RF generator generates an RF signal 218B having a high frequency level HFNn.

[0145] As yet another example, during bin 1m of cycle 2 of voltage 112, processor 214 transmits a data signal having a frequency value HF1m to the HF RF generator via transmission cable 236B. Upon receiving the data signal having frequency value HF1m during bin 1m of cycle 2, the HF RF generator generates RF signal 218B having a high frequency level HF1m.

[0146] Similarly, during bin Mm of cycle 2 of voltage 112, processor 214 transmits a data signal having a frequency value HFMm via transmission cable 236B to the HF RF generator. Upon receiving the data signal having frequency value HFMm during bin Mm of cycle 2, the HF RF generator generates RF signal 218B having high frequency level HFMm.

[0147] It should be noted that the processor 214 determines the change in the voltage 112 from one cycle to another based on the clock signal generated by the clock generator and based on the value of the voltage 112 received from the voltage sensor 204. For example, the processor 214 determines that the value of the voltage 112 repeats during a second period that is consecutive with a first period. When the processor 114 determines that the value of the voltage 112 begins to repeat, the processor 114 determines that a change in cycles has occurred, such as from cycle 1 to cycle 2. As another example, the processor 214 determines that a change from a previous cycle to a subsequent cycle has occurred by determining that a certain type of intersection, such as consecutive positive intersections or consecutive negative intersections, has occurred consecutively after the occurrence of the aforementioned type of intersection during the previous cycle of the voltage 112.

[0148] The first and second periods are part of a clock signal generated by a clock generator coupled to the processor 214. The clock generator provides a clock signal including the first and second periods to the processor 214. In one embodiment, the clock generator is part of the processor 214. In one embodiment, the processor 214 obtains the clock signal from a computer network, such as the Internet.

[0149] In one embodiment, processor 214 applies some, but not all, of the high frequency levels in tables 240 and 242 during one or more subsequent cycles of voltage 112. For example, processor 214 applies high frequency levels HF1n through HFNn, determined during the second half 112B of cycle 1 of voltage 112, to bins 1n through Nn of cycle 2 of voltage 112, but does not apply high frequency levels HF1m through HFMm, determined during the first half 112A of cycle 1 of voltage 112, to bins 1m through Mm of cycle 2 of voltage 112.

[0150] As another example, the processor 214 applies high frequency levels HF1m to HFMn determined during the first half 112A of cycle 1 of the voltage 112 to bins 1m to Mm of cycle 2 of the voltage 112, but does not apply high frequency levels HF1n to HFNn determined during the second half 112B of cycle 1 of the voltage 112 to bins 1n to Mn of cycle 1 of the voltage 112.

[0151] As yet another example, the processor 214 applies a high frequency level for a pre-stored number of bins during a pre-stored number of bins of cycle 2 of the voltage 112 .

[0152] As yet another example, the processor 214 applies high frequency levels HF1n to HF(N / 2)n determined during the third quarter of cycle 1 of the voltage 112 to bins 1n to (N / 2)n of cycle 2 of the voltage 112, but does not apply high frequency levels HF1m to HFMm determined during the first half 112A of cycle 1 of the voltage 112 to bins 1m to Mm of cycle 2, and does not apply high frequency levels HF((N / 2)+1)n to HFNn determined during the fourth quarter of cycle 1 of the voltage 112 to bins 1n to ((N / 2)+1)n of cycle 2 of the voltage 112.

[0153] In one embodiment, a frequency level, such as a radio frequency level, includes one or more frequency values. For example, a frequency level includes a single frequency value. As another example, a frequency level includes multiple frequency values, and the frequency value of one frequency level is different from, not the same as, or does not match the frequency value of another frequency level, to the exclusion of the frequency value of another frequency level.

[0154] In one embodiment, a voltage sensor (not shown) is used in place of the power sensor 224. If a voltage sensor is used in place of the power sensor 224, the processor 214 receives a voltage measurement from the voltage sensor and calculates the power based on the measurement.

[0155] 3A is a schematic diagram of one embodiment of a system 300 for illustrating the operation of an HF RF generator. The system 300 includes a host computer 212 and an HF RF generator. The HF RF generator includes a digital signal processor (DSP) and a power controller PWR. As an example, the controller includes a processor and a memory device such as a register. The processor is coupled to the register.

[0156] The HF RF generator further includes an automatic frequency tuner (AFT) for bins 1n through Nn. An example of an AFT as used herein includes a controller including a processor and a memory device. An example of a memory device for an AFT is a register. The HF RF generator includes an automatic frequency tuner AFTbin1m for bin 1m, an automatic frequency tuner AFTbin2m for bin 2m, etc., up to an automatic frequency tuner AFTbinMm for bin Mm. The HF RF generator includes an automatic frequency tuner AFTbin1n for bin 1n, an automatic frequency tuner AFTbin2n for bin 2n, etc., up to an automatic frequency tuner AFTbinNn for bin Nn.

[0157] The HF RF generator includes an HF power supply (PS) that is an RF oscillator, which is an electronic oscillator that generates a periodically oscillating electronic signal, such as a sine wave.

[0158] The DSP of the HF RF generator is coupled to the power controller PWR and to the automatic frequency tuners AFTbin1m to AFTbinNn of the HF RF generator. The power controller PWR and the automatic frequency tuners AFTbin1m to AFTbinNn are coupled to the HF RF generator's HF power supply. The HF power supply is coupled to the RF cable 234B. The DSP is coupled to the processor 214 via the transfer cable 236B.

[0159] The processor 214 accesses the high frequency levels HF1m to HFNn from tables 240 and 242 (FIG. 2) and transmits the high frequency levels HF1m to HFNn to the DSP via the transmission cable 236B. The processor 214 also generates a digital pulse signal that is pulsed according to bins 1m to Mm during each cycle of the voltage 112 and transmits the digital pulse signal to the DSP via the transmission cable 236B. An example of a digital pulse signal is the digital pulse signal 310 shown in FIG. 3B. FIG. 3B is one embodiment of a graph 312 that plots the logic levels of the digital pulse signal 310 versus time t.

[0160] The digital pulse signal 310 has a logic level for each of the bins 1m to Nn shown in FIG. 1B-1. For example, the digital pulse signal 310 has a logic level L(N-1)n for bin (N-1)n of FIG. 1B-1, another logic level LN for bin Nn of FIG. 1B-1, another logic level L1m for bin 1m of FIG. 1B-1, another logic level L2m for bin 2m of FIG. 1B-1, and so on up to a logic level LM for bin Mm of FIG. 1B-1. The logic level L(N-1)n occurs during the time period between time t(N-2)n and time t(N-1)n.

[0161] Similarly, logic level LNn occurs during the period between times t(N-1)n and tNn, logic level L1m occurs during the period between times tNn and t1m, logic level L2m occurs during the period between times t1m and t2m, logic level L3m occurs during the period between times t2m and t3m, and logic level LMm occurs during the period between times t(M-1)m and tMm. Logic levels L1m through LNn repeat during each cycle of voltage 112. Each logic level during a cycle of voltage 112 is a horizontal level and has a different value from another logic level during the cycle.

[0162] Another example of a digital pulse signal is the digital pulse signal 320 shown in Figure 3C, which is an embodiment of a graph 322 that plots the logic level of the digital pulse signal 320 versus time t.

[0163] The digital pulse signal 322 has a logic level for each of the bins 1m through Nn shown in Figure 1D-1. For example, the digital pulse signal 322 has a logic level L(N-1)n for bin (N-1)n of Figure 1D-1, a logic level LN for bin Nn of Figure 1D-1, a logic level L1m for bin 1m of Figure 1D-1, a logic level L2m for bin 2m of Figure 1D-1, and so on up to a logic level LM for bin Mm of Figure 1D-1. The logic level L(N-1)n occurs during the time period between time t(R-1)r and time tRr.

[0164] Similarly, logic level LNn occurs during the period between times tRr and t1q, logic level L1m occurs during the period between times t1q and t2q, logic level L2m occurs during the period between times t2q and t3q, logic level L3m occurs during the period between times t3q and t4q, and logic level LMm occurs during the period between times t(Q-1)q and tQq. Logic levels L1m through LNn repeat during each cycle of voltage 112.

[0165] 3A , the processor 214 also transmits information to the DSP via the transmission cable 236B identifying a cycle of the voltage 112. For example, the processor 214 transmits information identifying whether the cycle of the voltage 112 is cycle 0, or cycle 1, or cycle 2. Additionally, the processor 214 transmits instructions indicating the number of cycles of the voltage 112 to apply one or more of the frequency values ​​HF1m through HFNn for the pre-stored number of bins.

[0166] The DSP receives high frequency levels HF1m to HFNn and transmits each of the high frequency levels HF1m to HFNn to a corresponding one of the automatic frequency tuners AFTbin1m to AFTbinNn. The DSP receives information identifying cycles of the voltage 112, instructions indicating the number of cycles to apply one or more of the frequency values ​​HF1m to HFNn for a pre-stored number of bins, and a digital pulse signal from the processor 214.

[0167] The DSP transmits the frequency levels HF1m through HFNn to corresponding automatic frequency tuners AFT1m through AFTNn for storage. For example, the DSP transmits the frequency level HF1m to the automatic frequency tuner AFT1m for storage in the memory device of the automatic frequency tuner AFT1n, transmits the frequency level HFMm to the automatic frequency tuner AFTMm for storage in the memory device of the automatic frequency tuner AFTMm, and transmits the frequency level HFTNn to the automatic frequency tuner AFTNn for storage in the memory device of the automatic frequency tuner AFTNn.

[0168] Upon receiving the digital pulse signal and information regarding the cycle of the voltage 112, the DSP determines the logic level of the digital pulse signal and identifies the cycle of the voltage. For example, the DSP determines whether there is a match between the logic level LN and a pre-stored logic level in the memory device of the DSP, which is also LN. If there is a match, the DSP determines that the logic level of the digital pulse signal is LN. As another example, the DSP determines whether there is a match between the logic level LM and a pre-stored logic level in the memory device of the DSP, which is also LM. If there is a match, the DSP determines that the logic level of the digital pulse signal is LM.

[0169] Upon determining the logic level and identifying the cycle of the voltage 112, the DSP sends a control signal to the corresponding AFT of the HF RF generator during the logic level for the cycle number received in the instruction from the processor 214. For example, the DSP sends a control signal to an automatic frequency tuner AFT1m during bin 1m of cycle 2 and sends another control signal to an automatic frequency tuner AFTMm during bin Mm of cycle 2. Similarly, the DSP sends a control signal to an automatic frequency tuner AFT1n during bin 1n of cycle 2 and sends a control signal to an automatic frequency tuner AFTNn during bin Nn of cycle 2.

[0170] Each of the automatic frequency tuners AFT1m through AFTNn provides a corresponding one of the high frequency values ​​HF1m through HFNn to the HF power supply during a corresponding one of bins 1m through Nn. For example, in response to a control signal from the DSP, automatic frequency tuner AFT1m provides a high frequency level HF1m to the HF power supply during bin 1m of cycle 2, and automatic frequency tuner AFTMm provides a high frequency level HFMm to the HF power supply during bin Mm of cycle 2. Also, in response to a control signal from the DSP, automatic frequency tuner AFT1n provides a high frequency level HF1n to the HF power supply during bin 1n of cycle 2, and automatic frequency tuner AFTNn provides a high frequency level HFNn to the HF power supply during bin Nn of cycle 2.

[0171] The HF power source is HF From 1m HF For example, upon receiving a radio frequency level HF1m during bin 1m of cycle 2 of the voltage 112, the HF power supply generates a portion of the RF signal 218B during bin 1m of cycle 2 of the voltage 112, the portion of the RF signal 218B having the radio frequency level HF1m.

[0172] Similarly, upon receiving a high frequency level HFMm during bin Mm of cycle 2, the HF power supply generates a portion of an RF signal 218B during bin Mm of cycle 2 of the voltage 112, the portion of the RF signal 218B having a high frequency level HFMm.

[0173] Also, upon receiving high frequency level HF1n during bin 1n of cycle 2, the HF power supply generates a portion of RF signal 218B during bin 1n of cycle 2 of the voltage 112, the portion of RF signal 218B having high frequency level HF1n.

[0174] Similarly, upon receiving a high frequency level HFNn during bin Nn of cycle 2, the HF power supply generates a portion of an RF signal 218B during bin Nn of cycle 2 of the voltage 112, the portion of the RF signal 218B having the high frequency level HFNn.

[0175] The DSP also receives one or more power levels from the processor 214 via a transmission cable 236B and transmits the one or more power levels to the power controller PWR. The power controller PWR provides the one or more power levels to the HF power supply. Upon receiving the one or more power levels, the HF power supply generates an RF signal 218B having one or more power levels.

[0176] In one embodiment, one or more of the automatic frequency tuners AFT1m to AFTNn are combined into a single automatic frequency tuner. In one embodiment, one or more of the automatic frequency tuners AFT1m to AFTNn are part of a DSP.

[0177] 4 is a schematic diagram of an embodiment of a system 400 to illustrate the control of an auxiliary capacitor C3 of an impedance matching circuit (IMC) to modify the frequency in the high frequency range to control the power delivered by the HF RF generator. The system 400 includes an LF RF generator, an HF RF generator, a power sensor 224, a processor 214, an IMC, a motor 1, a motor 2, a motor 3, a drive system 1, a drive system 2, a drive system 3, and a voltage divider 402. The LF RF generator includes an LF power supply (PS) that is an RF oscillator. The LF power supply is coupled to an RF cable 234A (FIG. 2).

[0178] An example of each of the motors 1, 2, and 3 is an electric motor including a stator and a rotor. An example of each of the drive systems described herein is one or more transistors.

[0179] IMC is the main alignmentThe main matching circuit includes a branch circuit 406A and a branch circuit 406B. The branch circuit 406A includes one or more electrical components including a capacitor C1, and the branch circuit 406B includes one or more electrical components including a capacitor C2. Each of the capacitors C1 and C2 is a series capacitor. The branch circuit 406A is an example of a first branch circuit, and the branch circuit 406B is an example of a second branch circuit. Additionally, the auxiliary matching circuit includes one or more electrical components including a capacitor C3. Each of the capacitors C1 to C3 is a variable capacitor.

[0180] Each motor is connected to a corresponding capacitor of the IMC by a corresponding connection, such as one or more rods or a combination of multiple rods and one or more gears. For example, motor 1 is connected to the plate of capacitor C1 via connection 404A, motor 2 is connected to the plate of capacitor C2 via connection 404B, and motor 4 is connected to the plate of capacitor C3 via connection 404C.

[0181] The voltage divider 402 is an example of the voltage sensor 204 (FIG. 2). The voltage divider 402 includes a resistor R1 and a resistor R2, where the two resistors R1 and R2 are coupled in series with each other.

[0182] Prior to dividing the voltage 112 into bins, the processor 214 sets capacitance values ​​for the capacitors C1 and C2. For example, the processor 214 sends a control signal to the drive system 1 based on a predetermined capacitance of the capacitor C1. Upon receiving the control signal, the drive system 1 generates a current signal and sends the current signal to the motor 1. The motor 1 operates to change the capacitance of the capacitor C1 to the predetermined capacitance. The motor 1 operates to move a plate of the capacitor C1 relative to an opposing plate of the capacitor C1 to achieve the predetermined capacitance.

[0183] Similarly, as another example, the processor 214 sends a control signal to the drive system 2 based on a predetermined capacitance of the capacitor C2. Upon receiving the control signal, the drive system 2 generates a current signal and sends the current signal to the motor 2. The motor 2 operates to change the capacitance of the capacitor C2 to the predetermined capacitance. The motor 2 operates to move a plate of the capacitor C2 relative to an opposing plate of the capacitor C2 to achieve the predetermined capacitance.

[0184] Once the predetermined capacitances of capacitors C1 and C2 are set, processor 214 divides voltage 112 into bins and determines frequency values ​​for the bins to further control the delivered power at HF ​​RF generator output 230B.

[0185] The processor 214 also controls the capacitor C3 of the auxiliary matching circuit to control the delivered power at the output 230B of the HF RF generator. For example, the processor 214 receives a measurement of the delivered power at the output 230B from the power sensor 224 via the transfer cable 236D. The processor 214 determines a statistical power value of the delivered power for the pre-stored number of bins from the measurement in the same manner as described above, compares the statistical power value with a predetermined statistical power value, and determines that the predetermined statistical power value of the delivered power for the pre-stored number of bins is not achieved. If not achieved, the processor 214 sends a control signal to the drive system 3. Upon receiving the control signal, the drive system 3 generates a current signal and sends the current signal to the motor 3. The motor 3 operates to change the capacitance of the capacitor C1. The motor 3 operates to move a plate of the capacitor C3 relative to an opposing plate of the capacitor C3 to achieve the capacitance. Processor 214 continues to control capacitor C3 in this manner until a predetermined statistical power value of delivered power for a pre-stored number of bins is achieved.

[0186] It should be noted that the capacitance of capacitor C3 is controlled simultaneously with controlling the HF RF generator to operate at the high frequency values ​​in tables 240 and 242. Controlling capacitor C3 to achieve a predetermined statistical power value of the delivered power for a pre-stored number of bins facilitates the generation of a voltage at the output 206 of the IMC. The generation of a voltage at the output 206 facilitates applying one or more of the frequency levels HF1m through HFNn from the HF RF generator through the IMC to the plasma chamber 220 for the pre-stored number of bins to achieve the uniformity level UNFM.

[0187] In one embodiment, the capacitance of capacitor C3 is controlled prior to controlling the HF RF generator to operate at a high frequency value in tables 240 and 242. In one embodiment, the capacitance of capacitor C3 is controlled after controlling the HF RF generator to operate at a high frequency value in tables 240 and 242.

[0188] 5 is one embodiment of a graph 500 for illustrating the change in uniformity in etch rate when high frequency numerical values ​​for a pre-stored number of bins are applied. Graph 500 plots etch rate measured in angstroms (Å) per minute (min) along the Y-axis and radius R of substrate S along the X-axis. Graph 500 includes multiple plots 502, 504, 506, and 508 for different uniformities. Plot 508 shows a higher level of uniformity than that shown in plot 506. Similarly, plot 506 shows a higher level of uniformity than that shown in plot 504, which shows a higher level of uniformity than that shown in plot 502.

[0189] By controlling the frequency level of the HF RF generator during the pre-stored number of bins, the uniformity in terms of etch rate across the substrate S is changed from the uniformity shown in plot 502 to the uniformity shown in plot 508. For example, by controlling the frequency level of the HF RF generator to a range of values ​​HF1m to HFNn during cycle 2 and beyond of the voltage 112, the uniformity in terms of etch rate is increased from the uniformity shown in plot 502 to the uniformity shown in plot 508.

[0190] In one embodiment, the frequency level of the HF RF generator is controlled for a pre-stored number of bins to reduce the uniformity shown in plot 508 to the uniformity shown in any of plots 502, 504, and 506.

[0191] FIG. 6A is one embodiment of a graph 100.

[0192] FIG. 6B is an embodiment of a graph 600 to illustrate the increase in delivered power by applying the high frequency values ​​of tables 240 and 242. Graph 600 plots voltage on the Y-axis and time t on the X-axis. The voltage envelope of the forward power measured by the directional coupler coupled at the HF RF generator output 230B (FIG. 2) is shown by plots 602A and 602B, and the voltage envelope of the reflected power measured by the directional coupler coupled at the output 230B is shown by plots 604A and 604B. Plots 602A and 602B are of the voltage envelope showing the delivered power at the output of the HF RF generator, and plots 604A and 604B are of the voltage envelope showing the reflected power at the output of the HF RF generator. As shown in FIGS. 6A and 6B, an increase in the reflected power is seen after time t2 and after time t4. The reflected power increases as a result of the LF RF generator voltage 112 decreasing during each cycle of voltage 112. By controlling the HF RF generator to achieve a high frequency value for a pre-stored number of bins, the reflected power at output 230B is decreased and the transmitted power at output 230B is increased.

[0193] The embodiments described herein may be practiced with a variety of computer system configurations including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0194] In some embodiments, the controller is part of the system and may be part of the above examples. Such systems include semiconductor processing equipment including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestal, gas flow system, etc.). These systems are integrated with electronics for controlling the operation of the system before, during, and after processing of a semiconductor wafer or substrate. The electronics are referred to as "controllers" and the controller may control various components or sub-components of one or more systems. The controller is programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and motion settings, wafer loading and unloading from tools and other transport tools and / or load locks coupled or interfacing with the system, depending on the processing requirements and / or type of system.

[0195] Broadly, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include chips that store program instructions in the form of firmware, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions that are communicated to the controller in the form of various individual settings (or program files) and define parameters, coefficients, variables, etc. for performing a particular process on or for a semiconductor wafer or for a system. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0196] The controller, in some embodiments, is part of or coupled to a computer that is integrated with, coupled to, or otherwise networked with the system, or a combination thereof. For example, the controller may reside in the "cloud" or be all or part of a fab host computer system, thereby enabling remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a fabrication operation, examine the history of past fabrication operations, or examine trends or performance metrics from multiple fabrication operations to modify parameters of a current process, set up processing steps following the current process, or initiate a new process.

[0197] In some embodiments, a remote computer (e.g., a server) provides the process recipe to the system over a network, the network including a local network or the Internet. The remote computer includes a user interface that allows for input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data, the instructions specifying parameters, coefficients, and / or variables for each processing step to be performed during one or more operations. It should be understood that the parameters, coefficients, and / or variables are specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as noted above, the controller may be distributed, such as by including one or more separate controllers that are networked together and cooperate toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes includes one or more integrated circuits in a chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and that cooperatively control the processes in the chamber.

[0198] Without being limited thereto, in various embodiments, example systems to which the present methods may be applied include plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, clean chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems associated with or used in the creation and / or manufacturing of semiconductor wafers.

[0199] It is further noted that in some embodiments, the above operations apply to several types of plasma chambers, such as plasma chambers including inductively coupled plasma (ICP) reactors, transformer coupled plasma chambers, conductor tools, dielectric tools, plasma chambers including electron cyclotron resonance (ECR) reactors, etc. For example, one or more RF generators are coupled to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome coil, a flat coil, etc.

[0200] As described above, depending on the process step or steps being performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools installed throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0201] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are operations that physically manipulate physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations.

[0202] Some of the embodiments also relate to hardware units or apparatus for performing these operations, the apparatus being specially constructed for a special purpose computer. When defined as a special purpose computer, the computer is operable for its special purpose while also performing other processes, program execution or routines that are not part of its special purpose.

[0203] In some embodiments, operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or obtained over a computer network. If data is obtained over a computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0204] One or more embodiments may also be fabricated as computer readable code on a non-transitory computer readable medium. The non-transitory computer readable medium is any data storage hardware unit, such as a memory device, that stores data, which is then read by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disk ROM (CD-ROM), CD recordable (CD-R), CD rewriteable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer readable medium includes computer readable tangible media distributed over network-coupled computer systems such that the computer readable code is stored and executed in a distributed manner.

[0205] Although the method operations above have been described in a particular order, it should be understood that in various embodiments, other housekeeping operations may be performed between each operation, each method operation may be coordinated to occur at slightly different times, each method operation may be distributed across a system that allows each method operation to occur at various intervals, or may be performed in an order different than that set forth above.

[0206] It is further noted that in one embodiment, one or more features from any of the above embodiments may be combined with one or more features from any other of the above embodiments without departing from the scope described in the various embodiments described in this disclosure.

[0207] It should also be noted that in one embodiment, one or more features from any of the above-described examples may be combined with one or more features from any other of the above-described examples without departing from the scope described in the various embodiments described in this disclosure.

[0208] It should also be noted that in one embodiment, one or more features from any of the above-described examples may be combined with one or more features from any of the above-described embodiments without departing from the scope described in the various embodiments described in this disclosure.

[0209] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. The present embodiments are therefore to be regarded as illustrative and not restrictive, and it is not intended that the embodiments be limited to the details set forth herein. The present disclosure includes the following application examples: [Application example 1] 1. A method for achieving uniformity in etch rate, comprising: receiving a voltage signal from an output of the matching section; determining positive and negative crossing points of the voltage signal for each cycle of the voltage signal, the negative crossing point of each cycle being consecutive with the positive crossing point of the cycle; dividing a time interval of each cycle of the voltage signal into a number of bins; adjusting a frequency of a radio frequency generator to achieve the uniformity in the etch rate for one or more of the plurality of bins associated with the positive intersection point and for one or more of the plurality of bins associated with the negative intersection point. The method includes: [Application example 2] In the method according to application example 1, determining the regular intersections includes: determining a point at which the voltage signal is at a predetermined value; and determining that the value of the voltage signal increases after the voltage signal has reached the predetermined value as compared to a time before the voltage signal has reached the predetermined value; The method includes: [Application example 3] In the method according to application example 1, determining the negative intersection point comprises: determining a point at which the voltage signal is at a predetermined value; and determining that the value of the voltage signal decreases after the voltage signal has reached the predetermined value as compared to a time before the voltage signal has reached the predetermined value; The method includes: [Application example 4] A method as described in Application Example 1, wherein one or more of the plurality of bins associated with the positive intersection point includes a predetermined number of bins, and one of the predetermined number of bins includes the positive intersection point. [Application example 5] A method as described in Application Example 1, wherein one or more of the plurality of bins associated with the negative intersection point includes a predetermined number of bins, and one of the predetermined number of bins includes the negative intersection point. [Application Example 6] 1. A method for achieving uniformity in etch rate, comprising: receiving a voltage signal from an output of the matching section; determining positive and negative crossing points of the voltage signal for each cycle of the voltage signal, the negative crossing point of each cycle being consecutive with the positive crossing point of the cycle; dividing a time interval of each cycle of the voltage signal, the time interval beginning at a time proximate the positive crossing point and ending at a time proximate the negative crossing point, into a number of bins; adjusting a frequency of a first radio frequency generator to achieve the uniformity in the etch rate for one or more of the plurality of bins. The method includes: [Application Example 7] In the method according to application example 6, determining the regular intersections includes: determining a point at which the voltage signal is at a predetermined value; and determining that the value of the voltage signal increases after the voltage signal has reached the predetermined value as compared to a time before the voltage signal has reached the predetermined value; The method includes: [Application Example 8] In the method according to application example 6, determining the negative intersection point comprises: determining a point at which the voltage signal is at a predetermined value; and determining that the value of the voltage signal decreases after the voltage signal has reached the predetermined value as compared to a time before the voltage signal has reached the predetermined value; The method includes: [Application Example 9] The method according to Application Example 6, wherein the time close to the positive intersection is the time at which the positive intersection occurs, and the time close to the negative intersection is the time at which the negative intersection occurs. [Example 10] A method as described in Application Example 6, wherein the time close to the positive intersection is a time within a first predetermined range before the time when the positive intersection occurs, and the time close to the negative intersection is a time within a second predetermined range after the time when the negative intersection occurs. [Application Example 11] The method of claim 6, wherein each of the plurality of bins is of equal duration. [Application Example 12] The method described in Application Example 6, wherein the voltage signal is received from a voltage sensor coupled to the output of the matching unit, and the output of the matching unit is coupled to an input of a plasma chamber via a radio frequency transmission path. [Application Example 13] The method described in Application Example 6, wherein each cycle includes an early portion and a latter portion, the early portion coinciding with a period during which the voltage of the plasma sheath reaches its highest point, and the latter portion coinciding with a period during which the voltage of the plasma sheath reaches its lowest point. [Example 14] 7. The method according to claim 6, wherein the plurality of bins includes a first bin and a second bin, the first radio frequency generator has a higher operating frequency compared to a second radio frequency generator, the cycle corresponds to an operation of the second radio frequency generator, and adjusting the frequency includes: varying the first value of the frequency during the first bin to achieve a second value; and Varying the second value of the frequency during the second bin to achieve a third value. A method comprising: [Example 15] The method of application example 14, wherein the cycle of the voltage signal includes a first cycle and a second cycle, the first value is changed to achieve the second value during the first bin of the second cycle, and the second value is changed to achieve the third value during the second bin of the second cycle. [Example 16] The method according to Application Example 14, receiving a first measurement of a transmitted power, the first measurement associated with the first bin, the first measurement received from a sensor coupled to an output of the first radio frequency generator; receiving a second measurement of the delivered power, the second measurement associated with the second bin; Varying the first value of the frequency includes increasing or decreasing the first value of the frequency to decrease the first measurement value; The method, wherein varying the second value of the frequency includes increasing or decreasing the second value of the frequency so as to decrease the second measurement value. [Application Example 17] 17. The method of claim 16, wherein the reduction in the first and second measurements facilitates achieving the uniformity in the etch rate. [Example 18] 1. A controller for achieving uniformity in etch rate, comprising: 1. A processor comprising: receiving a voltage signal from the output of the matching section; determining positive and negative crossings of the voltage signal for each cycle of the voltage signal, the negative crossings of each cycle being contiguous with the positive crossings of the cycle; Dividing a time interval of each cycle of the voltage signal, the time interval beginning at a time proximate to the positive crossing point and ending at a time proximate to the negative crossing point, into a number of bins; adjusting a frequency of a radio frequency generator to achieve the uniformity in the etch rate for one or more of the plurality of bins. A processor comprising: a memory device coupled to the processor; Including, the controller. [Example 19] In the controller of Example 18, in order to determine the negative intersection, the processor determining a point at which the voltage signal is at a predetermined value; The controller is configured to determine an increase in value of the voltage signal a time after the voltage signal is at the predetermined value compared to a time before the voltage signal is at the predetermined value. [Example 20] In the controller of Example 18, in order to determine the negative intersection, the processor determining a point at which the voltage signal is at a predetermined value; The controller is configured to determine a decrease in value of the voltage signal a time after the voltage signal is at the predetermined value compared to a time before the voltage signal is at the predetermined value. [Example 21] A controller according to an eighteenth aspect, wherein the time approaching the positive intersecting point is a time when the positive intersecting point occurs, and the time approaching the negative intersecting point is a time when the negative intersecting point occurs. [Example 22] A controller according to an eighteenth aspect, wherein the time approaching the positive intersecting point is a time within a first predetermined range before the time when the positive intersecting point occurs, and the time approaching the negative intersecting point is a time within a second predetermined range after the time when the negative intersecting point occurs.

Claims

1. 1. A method for achieving uniformity in etch rate, comprising: receiving a voltage signal from an output of the matching section; determining positive and negative crossing points of the voltage signal for each cycle of the voltage signal, the negative crossing point of each cycle being consecutive with the positive crossing point of the cycle; Dividing a time interval of each cycle of the voltage signal into a number of bins; and adjusting a frequency of a radio frequency generator to achieve the uniformity in the etch rate for one or more of the plurality of bins associated with the positive intersection point and for one or more of the plurality of bins associated with the negative intersection point. Including, adjusting the frequency includes increasing or decreasing the frequency based on the measured power until a predetermined level of delivered power is achieved, the predetermined level of delivered power corresponding to the level of uniformity. method.

2. 2. The method of claim 1, wherein determining the positive intersections comprises: determining a point at which the voltage signal is at a predetermined value; and determining that the value of the voltage signal increases after the voltage signal has reached the predetermined value as compared to a time before the voltage signal has reached the predetermined value; The method includes:

3. 2. The method of claim 1, wherein determining the negative intersection point comprises: determining a point at which the voltage signal is at a predetermined value; and determining that the value of the voltage signal decreases after the voltage signal has reached the predetermined value as compared to a time before the voltage signal has reached the predetermined value; The method includes:

4. 2. The method of claim 1, wherein one or more of the plurality of bins associated with the positive intersection point comprises a predetermined number of bins, one of the predetermined number of bins including the positive intersection point.

5. 2. The method of claim 1, wherein one or more of the plurality of bins associated with the negative intersection point comprises a predetermined number of bins, and one of the predetermined number of bins includes the negative intersection point.

6. 1. A method for achieving uniformity in etch rate, comprising: receiving a voltage signal from an output of the matching section; determining positive and negative crossing points of the voltage signal for each cycle of the voltage signal, the negative crossing point of each cycle being consecutive with the positive crossing point of the cycle; Dividing a time interval of each cycle of the voltage signal, the time interval beginning at a time proximate the positive crossing point and ending at a time proximate the negative crossing point, into a number of bins; and adjusting a frequency of a first radio frequency generator to achieve said uniformity in said etch rate for one or more of said plurality of bins. Including, adjusting the frequency includes increasing or decreasing the frequency based on the measured power until a predetermined level of delivered power is achieved, the predetermined level of delivered power corresponding to the level of uniformity. method.

7. 7. The method of claim 6, wherein determining the positive intersections comprises: determining a point at which the voltage signal is at a predetermined value; and determining that the value of the voltage signal increases after the voltage signal has reached the predetermined value as compared to a time before the voltage signal has reached the predetermined value; The method includes:

8. 7. The method of claim 6, wherein determining the negative intersection point comprises: determining a point at which the voltage signal is at a predetermined value; and determining that the value of the voltage signal decreases after the voltage signal has reached the predetermined value as compared to a time before the voltage signal has reached the predetermined value; The method includes:

9. 7. The method of claim 6, wherein the time proximate to a positive intersection is the time at which the positive intersection occurs and the time proximate to a negative intersection is the time at which the negative intersection occurs.

10. 7. The method of claim 6, wherein the time proximate to the positive intersecting point is a time that is within a first predetermined range before the time the positive intersecting point occurs, and the time proximate to the negative intersecting point is a time that is within a second predetermined range after the time the negative intersecting point occurs.

11. The method of claim 6 , wherein each of the plurality of bins is of equal duration.

12. 7. The method of claim 6, wherein the voltage signal is received from a voltage sensor coupled to the output of the matching section, the output of the matching section being coupled to an input of a plasma chamber via a radio frequency transmission line.

13. 7. The method of claim 6, wherein each cycle includes an early portion and a late portion, the early portion coinciding with a period during which a voltage of a plasma sheath reaches its highest point and the late portion coinciding with a period during which the voltage of the plasma sheath reaches its lowest point.

14. 7. The method of claim 6, wherein the plurality of bins includes a first bin and a second bin, the first radio frequency generator has a higher operating frequency compared to a second radio frequency generator, the cycle corresponds to an operation of the second radio frequency generator, and adjusting the frequency comprises: varying the first value of the frequency during the first bin to achieve a second value; and Varying the second value of the frequency during the second bin to achieve a third value. A method comprising:

15. 15. The method of claim 14, wherein the cycle of the voltage signal includes a first cycle and a second cycle, the first value is changed to achieve the second value during the first bin of the second cycle, and the second value is changed to achieve the third value during the second bin of the second cycle.

16. 15. The method of claim 14, receiving a first measurement of the delivered power, the first measurement associated with the first bin, the first measurement received from a sensor coupled to an output of the first radio frequency generator; receiving a second measurement of the delivered power, the second measurement being associated with the second bin; Varying the first value of the frequency includes increasing or decreasing the first value of the frequency to decrease the first measurement value; The method, wherein varying the second value of the frequency includes increasing or decreasing the second value of the frequency so as to decrease the second measurement value.

17. 17. The method of claim 16, wherein the decrease in the first and second measurements facilitates achieving the uniformity in the etch rate.

18. 1. A controller for achieving uniformity in etch rate, comprising:

1. A processor comprising: receiving a voltage signal from the output of the matching section; determining positive and negative crossings of the voltage signal for each cycle of the voltage signal, the negative crossings of each cycle being contiguous with the positive crossings of the cycle; Dividing a time interval of each cycle of the voltage signal, the time interval beginning at a time proximate to the positive crossing point and ending at a time proximate to the negative crossing point, into a number of bins; adjusting a frequency of a radio frequency generator to achieve said uniformity in the etch rate for one or more of said plurality of bins. A processor comprising: a memory device coupled to the processor; Including, and to adjust the frequency, the processor is configured to increase or decrease the frequency based on the measured power until a predetermined level of transmitted power is achieved; the predetermined level of delivered power corresponds to the level of uniformity. controller.

19. 20. The controller of claim 18, wherein to determine the negative intersection point, the processor comprises: determining a point at which the voltage signal is at a predetermined value; The controller is configured to determine an increase in value of the voltage signal a time after the voltage signal is at the predetermined value compared to a time before the voltage signal is at the predetermined value.

20. 20. The controller of claim 18, wherein to determine the negative intersection point, the processor comprises: determining a point at which the voltage signal is at a predetermined value; The controller is configured to determine that the voltage signal decreases in value a time after the voltage signal is at the predetermined value compared to a time before the voltage signal is at the predetermined value.

21. 20. The controller of claim 18, wherein the time approaching a positive crossing is a time at which the positive crossing occurs and the time approaching a negative crossing is a time at which the negative crossing occurs.

22. 20. The controller of claim 18, wherein the time approaching the positive intersecting point is a time that is within a first predetermined range before the time the positive intersecting point occurs, and the time approaching the negative intersecting point is a time that is within a second predetermined range after the time the negative intersecting point occurs.

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