Display device

Abstract

To improve an aperture ratio of a semiconductor device.SOLUTION: A semiconductor device is provided in which a pixel portion including a first thin film transistor and a driver circuit including a second thin film transistor are provided over one substrate. The thin film transistor of the pixel portion includes: a gate electrode layer; a gate insulation layer; an oxide semiconductor layer having a thin film thickness in a peripheral edge; an oxide insulation layer that is in contact with one part of the oxide semiconductor layer; a source electrode layer and a drain electrode layer; and a pixel electrode layer. Each of the gate electrode layer, the gate insulation layer, the oxide semiconductor layer, the source electrode layer, the drain electrode layer, the oxide insulation layer, and a pixel electrode layer, of the first thin film transistor has a light transmissivity. The source electrode layer and the drain electrode layer of the thin film transistor of the driver circuit are covered with a protection insulation layer and made of a conductive material of which a resistance is lower than that of the source electrode layer and the drain electrode layer of the pixel portion.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to electro-optical devices such as display devices, semiconductor circuits, and electronic devices. be. [Background technology]

[0003] Metal oxides having light transmitting properties are used in semiconductor devices. For example, indium oxide Conductive metal oxides such as indium tin oxide (ITO) (hereafter referred to as oxide conductors) are used in liquid crystal displays. It is used as a transparent electrode material required for display devices such as displays.

[0004] In addition, metal oxides that have light-transmitting properties are attracting attention as materials that exhibit semiconductor properties. For example, In-Ga-Zn-O oxides are required for display devices such as liquid crystal displays. It is expected that this technology will be applied to semiconductor materials that are used in thin film transistors (TFTs). It is expected that this technology will be applied to the channel layer of a FT (fiber-transistor-type thin-film transistor).

[0005] TFTs that use metal oxides with semiconducting properties (hereinafter referred to as oxide semiconductors) can be used at low temperatures. Therefore, it is possible to manufacture alumina, which is used in display devices, etc. There is growing expectation that this material will replace or surpass rufus silicon.

[0006] In addition, a TFT is formed using a light-transmitting oxide conductor and an oxide semiconductor. This makes it possible to fabricate a light-transmitting TFT (see, for example, Non-Patent Document 1).

[0007] In addition, TFTs that use oxide semiconductors for the channel layer have high field effect mobility. The TFT can also be used to configure a driving circuit for a display device or the like (for example, See patent document 2. ). [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] Tetsuo Nozawa, "Transparent Circuits," Nikkei Electronics, August 27, 2007 (no. 959), pp. 39-52 [Non-Patent Document 2] T.Osada, and 8 others, SID 09 DIGEST, pp.184-187(2009) Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to reduce manufacturing costs of a semiconductor device.

[0010] An object of one embodiment of the present invention is to improve the aperture ratio of a semiconductor device.

[0011] An object of one embodiment of the present invention is to improve the resolution of an image displayed on a display portion of a semiconductor device. do.

[0012] An object of one embodiment of the present invention is to provide a semiconductor device capable of high-speed operation. [Means for solving the problem]

[0013] One embodiment of the present invention is a display device having a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit portion includes a source electrode (also called a source electrode layer) and a drain electrode (a drain electrode The driving layer (also referred to as the driving layer) is made of a metal and the semiconductor layer is made of an oxide semiconductor. A thin film transistor for a driving circuit and wiring for a driving circuit made of metal are provided. The display unit includes a source electrode layer and a drain electrode layer made of an oxide conductor and a semiconductor layer A pixel thin film transistor is made of an oxide semiconductor, and a pixel thin film transistor is made of an oxide conductor. The semiconductor device has wiring for a display portion formed thereon.

[0014] As a thin-film transistor for pixels and a thin-film transistor for driving circuits, Staggered thin-film transistors are used. The thin-film transistors for pixels form a channel in the semiconductor layer. A channel-protected (channel-stop) thin-film transistor with a channel protection layer on the region On the other hand, the driver circuit thin film transistor has a source electrode layer and a drain electrode layer. A channel-etched thin-film transistor having an oxide insulating film in contact with a semiconductor layer in a region between the It is.

[0015] In addition, Non-Patent Document 1 does not disclose a specific process for manufacturing a TFT and other elements constituting a semiconductor device. The structure of the capacitors (for example, the capacitor elements) is not disclosed. There is also no description of fabricating a TFT having light-transmitting properties.

[0016] The semiconductor device according to one embodiment of the present invention includes a driver circuit having a TFT for a driver circuit on the same substrate. A display section having a path section and a pixel TFT is manufactured. Costs can be reduced.

[0017] In addition, in the semiconductor device of one embodiment of the present invention, a source electrode and a drain electrode are formed of an oxide A pixel TFT made of a conductor and having a semiconductor layer made of an oxide semiconductor. and a display wiring made of an oxide conductor. The region in which the pixel TFT and the display wiring are formed is used as the display region of the pixel section. Therefore, the aperture ratio of the semiconductor device can be improved.

[0018] In addition, in the semiconductor device of one embodiment of the present invention, a source electrode and a drain electrode are formed of an oxide A pixel TFT made of a conductor and having a semiconductor layer made of an oxide semiconductor. and a display wiring made of an oxide conductor. Therefore, the pixel size can be designed without being limited by the size of the pixel TFT. Therefore, an image displayed on a display portion of the semiconductor device can be made higher in definition.

[0019] In the semiconductor device of one embodiment of the present invention, a source electrode and a drain electrode are formed of gold in a driver circuit portion. A TFT for a driving circuit, the TFT being made of a metal and the channel layer being made of an oxide semiconductor. and a driver circuit wiring made of metal. The driving circuit is composed of a TFT that exhibits high field effect mobility and low resistance wiring. Therefore, the semiconductor device can be a semiconductor device capable of high speed operation.

[0020] The oxide semiconductor used in this specification is InMO 3 (ZnO) m (m>0) A thin film is formed on the oxide semiconductor layer, and a thin film transistor is fabricated using the thin film as an oxide semiconductor layer. In addition, M is one or more metal elements selected from Ga, Fe, Ni, Mn, and Co. Indicates a metal element. For example, M can be Ga, Ga and Ni, or Ga and Ni. In some cases, the oxide semiconductor may contain the above-mentioned metal elements other than Ga, such as Fe. In addition to the metal elements contained as M, Fe, Ni and other transition metals are included as impurity elements. In the present specification, the term "In" refers to a transition metal oxide. MO 3 (ZnO) m In the oxide semiconductor layer with a structure represented by (m>0), M is Ga The oxide semiconductor with the structure containing In-Ga-Zn-O is called the In-Ga-Zn-O oxide semiconductor, and the thin film of the In-Ga-Zn-O oxide semiconductor is called the In-Ga-Zn-O oxide semiconductor. It is also called n-Ga-Zn-O type non-single crystal film.

[0021] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-Zn-O In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- Metal oxides of O, Sn-O, and Zn-O can be used. The oxide semiconductor layer may contain silicon oxide. By including silicon oxide (SiOx(X>0)), which is a type of oxide, during the manufacturing process When a heat treatment is performed after the formation of the semiconductor layer, crystallization can be suppressed. Note that the oxide semiconductor layer is preferably in an amorphous state and may be partially crystallized. .

[0022] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), Hydrogenation or dehydrogenation is effective.

[0023] Under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), or under reduced pressure By performing heat treatment on the oxide semiconductor layer, the oxide semiconductor layer becomes oxygen-deficient and has low resistance. That is, N-type (N - Then, an oxide insulating film is formed so as to contact the oxide semiconductor layer. By forming the oxide semiconductor layer in an oxygen-excess state, the oxide semiconductor layer becomes highly resistive, i.e., an I-type This makes it possible to obtain a thin film transistor having good electrical characteristics and high reliability. It is possible to manufacture and provide a semiconductor device having the above structure.

[0024] The heat treatment for dehydration or dehydrogenation may be carried out, for example, in the presence of nitrogen or a rare gas (arsenic). Preferably, the reaction is carried out at 350°C or higher under an inert gas atmosphere (e.g., argon, helium, etc.) or under reduced pressure. The heat treatment is performed at a temperature of 400°C or higher but below the distortion point of the substrate. The oxide semiconductor layer is dehydrated or dehydrogenated to reduce impurities including hydrogen such as moisture contained in the oxide semiconductor layer. Reduce.

[0025] The heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor after dehydration or dehydrogenation. Thermal Desorption Spectroscopy was used to measure the Even when the temperature was measured up to 450°C using TDS, two peaks of water were observed. It is preferable to set the heat treatment conditions so that one peak appearing around 300°C is not detected. The oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation under these conditions is used. Even when TDS measurements were performed up to 450°C on the thin-film transistors, The water peak around °C is not detected.

[0026] Cooling after heating should be done using the same furnace as used for dehydration or dehydrogenation, without exposing the material to air. The oxide semiconductor layer is cooled to prevent contact with water or hydrogen. The oxide semiconductor layer is then heat-treated to reduce its resistance, i.e., to become an N-type (N - (e.g., Then, a thin film transistor is manufactured using the oxide semiconductor layer that is made to have a high resistance and is made into an i-type oxide semiconductor layer. The threshold voltage value of the thin film transistor can be made positive, so that the so-called normally-off transistor can be realized. The gate voltage of the thin film transistor is set as close to 0V as possible. It is desirable for a display device to have a channel formed at a threshold voltage of 1000V. If the threshold voltage of a transistor is negative, the source and drain electrodes are In this case, the current flows between the active electrodes, which is called normally-on. In such display devices, the electrical characteristics of the thin film transistors that make up the circuits are important. The performance of a display device is determined by its electrical characteristics. In particular, the electrical characteristics of thin film transistors Even if the field effect mobility is high, the threshold voltage is high, or If the threshold voltage is negative, it is difficult to control the circuit. In the case of a thin film transistor having a high threshold voltage and a large absolute value of the threshold voltage, the driving voltage When the switching function of the TFT is low, it cannot be performed and there is a risk of it becoming a load. In the case of an n-channel thin film transistor, a positive voltage is applied to the gate voltage. It is desirable to have a transistor in which a channel is formed first and a drain current starts to flow. There are transistors in which the channel does not form unless the voltage is high, and transistors in which the channel forms even under negative voltage conditions. A transistor that is constructed so that a drain current flows is a thin-film transistor used in a circuit. It is not suitable.

[0027] In addition, cooling after heating may be performed after changing the heated gas atmosphere to a different gas. For example, do not expose the material to air in the same furnace where it was heated for dehydration or dehydrogenation. The furnace is filled with high-purity oxygen gas or N 2 O2 gas, ultra-dry air (dew point below -40℃, The container may be filled with water (preferably -60°C or less) to perform cooling.

[0028] The heat treatment for dehydration or dehydrogenation removes impurities, including hydrogen, such as moisture contained in the film. After reducing the temperature, place in a moisture-free atmosphere (dew point is -40°C or less, preferably -60°C or less). The electrical characteristics of a thin film transistor are evaluated using an oxide semiconductor film that is gradually cooled (or cooled) under The aim is to realize a thin-film transistor that is both highly efficient and suitable for mass production.

[0029] In this specification, under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), Alternatively, the heat treatment under reduced pressure is called a heat treatment for dehydration or dehydrogenation. This heat treatment causes H 2 Not only does it eliminate H, OH, etc. For convenience, this process is referred to as dehydration or dehydrogenation.

[0030] Under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), or under reduced pressure When the heat treatment is performed, the oxide semiconductor layer becomes oxygen-deficient and has low resistance. , that is, N-type (N - As a result, oxygen-deficient ZnO is formed in the area overlapping with the drain electrode layer. In this way, a high-resistance drain region (also called an HRD region) is formed.

[0031] Specifically, the carrier concentration in the high-resistance drain region is 1×10 17 / cm 3 Within the above range and the carrier concentration in the channel formation region is at least (1×10 17 / cm 3 Less than The carrier concentration in this specification is calculated from Hall effect measurements at room temperature. This refers to the carrier concentration value measured.

[0032] In addition, a low-resistance drain region (L Specifically, the carrier concentration of the low-resistance drain region may be is larger than the high resistance drain region (HRD region), for example, 1×10 20 / cm 3 End 1×10 21 / cm 3 It is within the following range.

[0033] Then, at least a part of the oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation is By making the material oxygen-rich, the resistance is increased, that is, the material is made I-type, and a channel formation region is formed. Note that the oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation is heated in an oxygen-excess state. As a treatment for the above-mentioned state, a heat treatment for dehydration or dehydrogenation is performed on an oxide semiconductor layer. A contact oxide insulating film is formed by sputtering, or heating is performed for dehydration or dehydrogenation. An oxide insulating film is formed so as to be in contact with the treated oxide semiconductor layer, and heat treatment is further performed. Alternatively, the oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation is treated to include oxygen. Oxides that have been heat-treated in an atmosphere containing fluorine or for the purpose of dehydration or dehydrogenation The semiconductor layer is heated in an inert gas atmosphere and then cooled in an oxygen atmosphere; The oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation is subjected to a thermal treatment under an inert gas atmosphere. Heat and then cool with ultra-dry air (dew point below -40°C, preferably below -60°C). Examples include performing processing such as:

[0034] In addition, at least a part of the oxide semiconductor layer ( In order to form a channel formation region in the region overlapping with the gate electrode (also called the gate electrode layer), By selectively creating an oxygen-excess state, it is possible to make the material highly resistive, i.e., I-type. Alternatively, a metal electrode such as Ti is formed on the oxide semiconductor layer that has been heat-treated for dehydrogenation. A source electrode layer and a drain electrode layer are formed so as not to overlap the source electrode layer and the drain electrode layer. The region where no oxygen is present can be selectively made into an oxygen-excessive state to form a channel formation region. In the case of selectively providing an oxygen excess state, a first high-resistance drain region overlapping the source electrode layer; A second high-resistance drain region is formed overlapping the drain electrode layer, and the first high-resistance drain The region between the first high-resistance drain region and the second high-resistance drain region is the channel formation region. A hole formation region is formed in a self-aligned manner between the source electrode layer and the drain electrode layer.

[0035] This allows the fabrication of a semiconductor device having thin film transistors with good electrical characteristics and high reliability. It will be possible to provide such information.

[0036] Note that a high-resistance drain electrode layer (and a source electrode layer) is formed in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer). By forming the drain region, it is possible to improve the reliability when forming the drive circuit. Specifically, by forming a high-resistance drain region, the high-resistance drain can be The structure is such that the conductivity can be changed stepwise from the drain region to the channel formation region. Therefore, the drain electrode layer is connected to a wiring that supplies a high power supply potential VDD. When the gate electrode layer and the drain electrode layer are operated in the same manner, a high resistance is not obtained even if a high electric field is applied between the gate electrode layer and the drain electrode layer. The drain region acts as a buffer to prevent localized high electric fields from being applied, improving the breakdown voltage of the transistor. It is possible to adopt a configuration in which

[0037] In addition, between the drain electrode layer (and source electrode layer) made of a metal material and the oxide semiconductor layer A low-resistance drain region (also called an LRN region) may be formed. By forming a junction region (also called an RN region), the breakdown voltage of the transistor is improved. It can be said that:

[0038] In addition, a high resistance drain electrode layer (and a source electrode layer) is formed in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer). By forming a drain region, leakage in the channel formation region when forming a driver circuit is prevented. Specifically, the drain current can be reduced by forming a high-resistance drain region. The drain electrode layer and the source electrode layer are connected to each other as a leakage current path of the transistor. Drain electrode layer, high-resistance drain region on the drain electrode layer side, channel formation region, source electrode The high-resistance drain region on the side of the gate electrode is followed by the source electrode layer. The leakage current flowing from the high-resistance drain region on the drain electrode layer side to the channel formation region is called the transistor. The transistor is concentrated near the interface between the gate insulating layer and the channel formation region, which has high resistance when the transistor is off. The back channel portion (the surface of the channel forming region separated from the gate electrode layer) can be formed. It is possible to reduce leakage current in the semiconductor device (part of the surface).

[0039] A first high-resistance drain region overlapping the source electrode layer and a second high-resistance drain region overlapping the drain electrode layer. The high resistance drain region is formed so as to overlap a part of the gate electrode layer via the gate insulating layer. By doing so, it is possible to more effectively reduce the electric field strength in the vicinity of the end portion of the drain electrode layer. .

[0040] Further, a low-resistance drain region is provided between the source electrode layer and the drain electrode layer and the oxide semiconductor layer. The structure having such a low temperature junction provides a more thermally stable operation than a Schottky junction. The resistive drain region has a lower resistance than the oxide semiconductor layer and is Since an oxide conductive layer having a higher resistance than an electrode layer is used, The contact resistance with the drain electrode layer can be reduced.

[0041] One embodiment of the configuration of the present invention disclosed in this specification is a semiconductor device having a first thin film transistor on the same substrate. The first thin film transistor is a pixel portion having a first insulating film and a driver circuit having a second thin film transistor. A gate electrode layer is formed on the substrate, a gate insulating layer is formed on the gate electrode layer, and a gate insulating layer having a thickness of 100 nm is formed on the gate insulating layer. An oxide semiconductor layer having a thin region on its periphery, and an oxide insulating layer in contact with a part of the oxide semiconductor layer A source electrode layer and a drain electrode layer are formed on the oxide insulating layer and the oxide semiconductor layer. a pixel electrode layer electrically connected to the first thin film transistor; The gate electrode layer of the transistor, the gate insulating layer, the oxide semiconductor layer, the source electrode layer, the drain electrode layer, The oxide insulating layer and the pixel electrode layer have a light-transmitting property, and the source electrode layer of the second thin film transistor and The source electrode layer and the drain electrode layer of the first thin film transistor are covered with a protective insulating layer. The material of the source electrode layer and the drain electrode layer of the first thin film transistor is different from that of the drain electrode layer. The semiconductor device is made of a conductive material having a lower resistance than the pole layer.

[0042] In the above semiconductor device, the oxide semiconductor layer of the second thin film transistor and the source Between the source electrode layer and the drain electrode layer of the first thin film transistor, It may also have a low resistance drain region made of the same material as the gate electrode layer.

[0043] In the above semiconductor device, the oxide semiconductor layer of the second thin film transistor and the source A low-resistance drain region is provided between the electrode layer and the drain electrode layer. The portion protrudes from the end face of the low resistance drain region and serves as a channel forming portion of the second thin film transistor. It may be the same thickness as the film thickness of the region.

[0044] In the above semiconductor device, the oxide semiconductor layer of the first or second thin film transistor is At least one of the source and drain electrode layers is provided at a position overlapping with the source electrode layer or the drain electrode layer. It may also have a high resistance drain region that has a lower resistance than the drain region.

[0045] In the above semiconductor device, the source electrode layer and the drain electrode layer of the second thin film transistor The electrode layer is a film whose main component is an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. or a laminated film in which these are combined.

[0046] In the above semiconductor device, the source electrode layer and the drain electrode of the first thin film transistor are The electrode layer and the pixel electrode layer are made of indium oxide, an indium oxide tin oxide alloy, or indium oxide. It is preferred that the insulating layer 10 be made of zinc oxide alloy or zinc oxide.

[0047] In addition, the semiconductor device further includes a capacitance section on the same substrate, the capacitance section being a capacitance array. a line and a capacitance electrode overlapping the capacitance line, and the capacitance line and the capacitance electrode are transparent good.

[0048] In the semiconductor device, the oxide semiconductor layer of the second thin film transistor is A channel forming region having a thickness smaller than that of a region overlapping with the electrode layer or the drain electrode layer, A conductive layer may be provided on the channel forming region via a protective insulating layer.

[0049] In one embodiment of the present invention, a first gate electrode layer and a second gate electrode layer are formed over the same substrate. A gate electrode layer is formed, and a gate insulating layer is formed on the first gate electrode layer and the second gate electrode layer. an oxide semiconductor film is formed over the gate insulating layer; and the oxide semiconductor film is dehydrated or After the heat treatment for oxidation, the oxide semiconductor film is prevented from coming into contact with water or hydrogen. The first oxide semiconductor layer, the second oxide semiconductor layer, and the second oxide semiconductor layer are formed without being exposed to air. forming first and second low resistance drain regions on the conductor layer; A second source electrode layer and a second drain electrode layer are formed on the gate region, respectively, and a second oxide a second source electrode layer and a second drain electrode layer; a second oxide insulating layer in contact with the front and side surfaces of the first oxide semiconductor layer; and a first gate electrode layer. a first oxide insulating layer is formed in a region overlapping the first oxide semiconductor layer and the first oxide insulating layer; forming a first source electrode layer and a first drain electrode layer on the edge layer; a first oxide insulating layer; A protective insulating layer is formed on the first source electrode layer, the first drain electrode layer, and the second oxide insulating layer. A first drain electrode layer or a first source electrode layer is formed on the protective insulating layer. and a conductive layer overlapping with the second oxide semiconductor layer. This is the method.

[0050] In the above structure, the oxide semiconductor layer of the second thin film transistor is a source electrode layer or a drain electrode layer. The second thin film transistor may have a region having a thickness smaller than that of the region overlapping the second thin film transistor. The oxide semiconductor layer of the transistor is thicker than the region overlapping with the source electrode layer or the drain electrode layer. A thin channel forming region is provided on the channel forming region via a second oxide insulating layer. A structure having a conductive layer may also be used.

[0051] The first oxide insulating layer and the second oxide insulating layer can be formed in the same process, and therefore have the same light transmitting property. An insulating material having such a property can be used.

[0052] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. In addition, the specific names used in this specification are not intended to identify the invention. This does not indicate the

[0053] In addition to liquid crystal display devices, display devices having a driving circuit include light-emitting devices using light-emitting elements. display devices, and display devices also called electronic paper using electrophoretic display elements. .

[0054] In a light-emitting display device using a light-emitting element, a pixel portion has a plurality of thin film transistors. In the elemental area, the gate electrode of a thin-film transistor and the source wiring (so The point where the source wiring layer or drain wiring (also called drain wiring layer) is connected In addition, in a driving circuit of a light-emitting display device using a light-emitting element, a thin-film transistor The gate electrode of the thin film transistor is connected to the source wiring or drain wiring of the thin film transistor. It has some parts that allow you to do so. Effect of the Invention

[0055] According to one embodiment of the present invention, a thin film transistor having stable electrical characteristics is manufactured and provided. Therefore, a semiconductor having a thin film transistor with good electrical characteristics and high reliability can be obtained. An apparatus can be provided. [Brief description of the drawings]

[0056] [Figure 1] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 2] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 3] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 5] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 8] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 9] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 10] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 11] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 12]1A and 1B are diagrams illustrating a pixel equivalent circuit of a semiconductor device. [Figure 13] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 14] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 15] 1A and 1B are circuit diagrams and a timing chart of a signal line driver circuit. [Figure 16] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 17] 4A and 4B are a timing chart and a circuit diagram illustrating the operation of a shift register. [Figure 18] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 19] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 20] FIG. 1 is an external view showing an example of an electronic book. [Figure 21] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 22] FIG. 1 is an external view showing an example of a gaming machine. [Figure 23] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 24] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 25] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 26] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 27] 1A to 1C are circuit diagrams of a semiconductor device. [Figure 28] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 29] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 30] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 31] 1A to 1C are circuit diagrams of a semiconductor device. [Diagram 32] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 33] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 34] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 35] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 36] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 37] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 38] 1A to 1C are diagrams illustrating a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0057] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0058] (Embodiment 1) A semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. (C) shows a cross-sectional structure of two thin-film transistors with different structures fabricated on the same substrate. An example of the thin film transistor 460 shown in FIG. The thin film transistor 470 is a channel-protection type (channel-stop type). The thin film transistor 460 and the thin film The transistor 470 is also called an inverted staggered thin film transistor.

[0059] FIG. 1(A1) is a plan view of a thin film transistor 460 disposed in a driving circuit. 2) is a plan view of a thin film transistor 470 disposed in a pixel portion. 1(A1) and FIG. 1(A2) along line H1-H2. FIG. 1C shows the relationship between the line G3-G4 in FIG. 1A1 and the line H3-H4 in FIG. 1A2. FIG.

[0060] The thin film transistor 460 arranged in the driving circuit is a channel-etch type thin film transistor. A gate electrode layer 461 and a first gate insulating layer 45 are formed on a substrate 450 having an insulating surface. 2a, the second gate insulating layer 452b, at least the channel forming region 463, the first high resistance an oxide semiconductor layer including a drain region 464a and a second high-resistance drain region 464b; 462, the first low resistance drain region 408a, the second low resistance drain region 408b, The thin film transistor 460 also includes a source electrode layer 465a and a drain electrode layer 465b. An oxide insulating layer 466 is provided to cover the channel formation region 463 and in contact with the channel formation region 463.

[0061] A first high-resistance drain region 464a is in contact with the lower surface of the first low-resistance drain region 408a. The second low-resistance drain region 408b is formed in a self-aligned manner. The second high-resistance drain region 464b is formed in a self-aligned manner. The region 463 is in contact with an oxide insulating layer 466 and includes a first high-resistance drain region 464a and The thickness of the first high-resistance drain region 464b is smaller than that of the second high-resistance drain region 464b. A region (I-type region) having a higher resistance than the region 464a and the second high-resistance drain region 464b Let us assume that.

[0062] In addition, the thin film transistor 460 includes a source electrode layer 465a and The drain electrode layer 465b is preferably made of a metal material.

[0063] In addition, in a liquid crystal display device, when a pixel portion and a driver circuit are formed on the same substrate, In this paper, logic gates such as inverter circuits, NAND circuits, NOR circuits, and latch circuits are used. The thin-film transistors that make up the Thin-film transistors, which make up analog circuits such as MOS transistors, have a gate between the source and drain electrodes. Only positive polarity or only negative polarity is applied to the second high resistance transistor, which is required to withstand voltage. The width of the anti-drain region 464b is designed to be wider than the width of the first high-resistance drain region 464a. In addition, the first high-resistance drain region 464a and the second high-resistance drain region 4 The width of the portion 64b overlapping the gate electrode layer may be increased.

[0064] In addition, the thin film transistor 460 disposed in the driving circuit is a thin film transistor with a single gate structure. Although the above description is based on a transistor, a multi-gate transistor having multiple channel formation regions may be used as necessary. A thin film transistor having the above structure can also be formed.

[0065] In addition, a conductive layer 467 is provided so as to overlap the channel forming region 463. By electrically connecting the gate electrode layer 461 and the conductive layer 462 to each other and setting them at the same potential, the gate electrode layer 461 and the conductive layer 462 are electrically connected to each other and set at the same potential. A gate voltage can be applied from above and below to the oxide semiconductor layer 462 disposed between the gate electrodes 67. In addition, the gate electrode layer 461 and the conductive layer 467 are set to different potentials, for example, a fixed potential, GND, When the voltage is set to 0 V, the electrical characteristics of the TFT, such as the threshold voltage, can be controlled. That is, the gate electrode layer 461 functions as a first gate electrode layer, and the conductive layer 467 As a result, the thin film transistor 460 is a four-terminal thin film transistor. It can be used as a transistor.

[0066] In addition, a protective insulating layer 453 and a planarizing insulating layer 454 are provided between the conductive layer 467 and the oxide insulating layer 466. 54 and are laminated together.

[0067] The protective insulating layer 453 is formed by insulating a first gate insulating layer 452 provided under the protective insulating layer 453. It is preferable that the insulating film be in contact with the substrate. , hydrogen ions, OH - In particular, the protective insulating layer The first gate insulating layer 452a in contact with 453 or the insulating film serving as the base is made of silicon nitride. is valid.

[0068] In addition, the thin film transistor 470 disposed in the pixel is a channel stop type thin film transistor. A gate electrode layer 471, a first gate insulating layer 472, and a second gate insulating layer 473 are formed on a substrate 450 having an insulating surface. 452a, a second gate insulating layer 452b, and an oxide semiconductor layer 472 including a channel formation region. , a source electrode layer 475a, and a drain electrode layer 475b. 470, a channel protection layer 476, a source electrode layer 475a, and a drain electrode layer 47 A protective insulating layer 453 and a planarization insulating layer 454 are stacked in contact with the insulating film 5b. A pixel electrode layer 477 in contact with the drain electrode layer 475b is provided on the flat insulating layer 454. The thin film transistor 470 is electrically connected to the driving circuit. The first low-resistance drain region 408a and the second low-resistance drain region 408b of the transistor 460 The material of the thin film transistor for the pixel is a source electrode layer 475a and a drain electrode layer 47 The material of 5b is preferably the same.

[0069] However, liquid crystal display devices are driven by alternating current to prevent deterioration of the liquid crystal. By this operation, the polarity of the signal potential applied to the pixel electrode layer is changed to positive or negative at regular intervals. The TFT connected to the pixel electrode layer has a pair of electrodes that alternate between the source electrode layer and the drain electrode layer. In this specification, for convenience, one electrode of the thin film transistor of the pixel is The first electrode is called the source electrode layer and the other electrode is called the drain electrode layer. In this case, one electrode alternately functions as a source electrode layer and a drain electrode layer. In order to reduce the current, the width of the gate electrode layer 471 of the thin film transistor 470 arranged in the pixel is may be narrower than the width of the gate electrode layer 461 of the thin film transistor 460 in the driver circuit. In order to reduce leakage current, the gate voltage of the thin film transistor 470 disposed in the pixel is The electrode layer 471 is set so as not to overlap with the source electrode layer 475a or the drain electrode layer 475b. It may be calculated.

[0070] In addition, the thin film transistor 470 disposed in the pixel is a thin film transistor having a single gate structure. However, if necessary, a multi-gate structure having a plurality of channel forming regions may be used. A thin film transistor having the above structure can also be formed.

[0071] In addition, after the formation of the oxide semiconductor film, a heat treatment (dehydration) for reducing moisture or the like which is an impurity may be performed. Heat treatment for dehydration or dehydrogenation) is carried out. After the oxide semiconductor layer is heated and slowly cooled, an oxide insulating film is formed in contact with the oxide semiconductor layer. Reducing the carrier concentration of the conductor layer improves the electrical characteristics of the thin film transistor 470 and This leads to improved reliability.

[0072] Note that the oxide semiconductor layer 472 is a gate insulating film between the source electrode layer 475a and the drain electrode layer 475b. The oxide semiconductor layer 472 is formed below and partially overlaps with the gate electrode layer 471. and overlap with the first gate insulating layer 452a and the second gate insulating layer 452b interposed therebetween. The channel formation region of the thin film transistor 470 arranged in the pixel is the oxide semiconductor layer 472. Among them, the side surface of the source electrode layer 475a and the drain electrode layer 475b facing the side surface The region sandwiched between the side surface and the second gate insulating layer 452b, i.e., the region in contact with the second gate insulating layer 452b and the gate electrode layer 4 This is the area that overlaps with 71.

[0073] In addition, the thin film transistor 470 is a light-transmitting thin film transistor having a high aperture ratio. In order to realize a display device that can display a transparent display, the source electrode layer 475a and the drain electrode layer 475b are A conductive film having optical properties is used.

[0074] A gate electrode layer 471 of the thin film transistor 470 is also formed using a light-transmitting conductive film.

[0075] In addition, in the pixel where the thin film transistor 470 is arranged, a pixel electrode layer 477 or other The electrode layer (capacitor electrode, etc.) and other wiring layers (capacitor wiring layer, etc.) are transparent to visible light. By using a conductive film having a high insulating property, a display device having a high aperture ratio can be realized. The edge layer 452a, the second gate insulating layer 452b, and the channel protection layer 476 are also transparent to visible light. It is preferable to use a film having optical properties.

[0076] In this specification, a light-transmitting film refers to a film having a visible light transmittance of 75 to 100%. When the film has conductivity, it is called a transparent conductive film. Applied to electrode layer, drain electrode layer, pixel electrode layer, other electrode layers, and other wiring layers A conductive film that is semi-transparent to visible light may be used as the metal oxide that is transparent to visible light. Translucency refers to a visible light transmittance of 50-75%.

[0077] In the following, using Figs. 2(A) to (E) and Figs. 3(A) to (E), A manufacturing process of the thin film transistor 460 and the thin film transistor 470 will be described.

[0078] First, a light-transmitting conductive film is formed on a substrate 450 having an insulating surface, and then a first photo Gate electrode layers 461 and 471 are formed by a lithography process. The capacitor array is formed of the same material as the gate electrode layers 461 and 471 by the same first photolithography process. In addition, if capacitance is required not only for the pixel section but also for the driver circuit, A capacitance wiring (also called a capacitance wiring layer) is formed. Note that a resist mask is formed by an inkjet method. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0079] There is no significant limitation on the substrate that can be used for the substrate 450 having an insulating surface, but at least In any case, it is necessary for the insulating surface to have sufficient heat resistance to withstand subsequent heat treatment. The substrate 450 is made of glass such as barium borosilicate glass or aluminoborosilicate glass. A substrate can be used.

[0080] In addition, when a glass substrate is used as the substrate 450, if the temperature of the subsequent heat treatment is high, It is preferable to use a substrate having a distortion point of 730° C. or higher. In addition, a glass substrate is used as the substrate 450. In cases where glass is used, for example, aluminosilicate glass, aluminoborosilicate glass, barium oxide glass, Glass materials such as borosilicate glass are used. By adding more BaO, a more practical heat-resistant glass can be obtained. , B 2 O 3 It is preferable to use a glass substrate containing more BaO.

[0081] Instead of the above glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may be used as the substrate 450. Alternatively, crystallized glass or the like may be used. This can be done.

[0082] In addition, an insulating film serving as a base film may be provided between the substrate 450 and the gate electrode layers 461 and 471. The undercoat film has a function of preventing the diffusion of impurity elements from the substrate 450. A stack of one or more films selected from a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. It can be formed in a layer structure.

[0083] The gate electrode layers 461 and 471 are formed of a conductive material that transmits visible light, for example. In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-G a-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al -Zn-O, In-O, Sn-O, and Zn-O metal oxides can be used. The thickness of the gate electrode layer 461 is appropriately selected within the range of 50 nm to 300 nm. The metal oxide film deposition method used for 71 is the sputtering method or the vacuum deposition method (electron beam deposition method, etc.). ) or arc discharge ion plating or spraying. Also, sputtering is used. When used, SiO 2 The film is formed using a target containing 2% by weight or more and 10% by weight or less. In the subsequent process, the conductive film having a light-transmitting property is made to contain SiOx (X>0) which inhibits crystallization. It is preferable to suppress crystallization during the heat treatment for dehydration or dehydrogenation. I wish.

[0084] Next, a gate insulating layer is formed on the gate electrode layers 461 and 471 .

[0085] The gate insulating layer is a silicon oxide layer, a nitride layer, etc., formed by plasma CVD or sputtering. The silicon layer, the silicon oxynitride layer, or the silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, the deposition gas is SiH 4 The oxygen and nitrogen were used to produce the acid by plasma CVD. A silicon nitride layer may be formed.

[0086] In this embodiment, a first gate insulating layer 452a having a thickness of 50 nm or more and 200 nm or less, A second gate insulating layer 452b having a thickness of 50 nm to 300 nm is a stacked gate insulating layer. The first gate insulating layer 452a is a silicon nitride film or a nitride oxide film having a thickness of 100 nm. The second gate insulating layer 452b is a silicon oxide film having a thickness of 100 nm. A bare membrane is used.

[0087] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is deposited on the second gate insulating layer 452b. After the oxide semiconductor film is formed, the oxide semiconductor film is dehydrated or dehydrogenated. In order to make the oxide semiconductor layer amorphous even after the heat treatment for the purpose of the present invention, the thickness of the oxide semiconductor layer is set to 50 nm. It is preferable to make the oxide semiconductor layer as thin as or less. When a heat treatment is performed after the formation of the film, crystallization can be suppressed.

[0088] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced to the plasma The reverse sputtering is performed to generate a gallium oxide, and the gallium oxide adhering to the surface of the second gate insulating layer 452b is removed. It is preferable to remove aluminum by reverse sputtering without applying voltage to the target side. In a nitrogen atmosphere, a voltage is applied to the substrate side using an RF power source to form plasma near the substrate. This is a method for modifying the surface. Note that nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. It may be used.

[0089] The oxide semiconductor film is an In-Ga-Zn-O non-single crystal film, an In-Sn-Zn-O film, or an In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, S In this embodiment, an In-Ga-Zn The film is formed by sputtering using a -O-based oxide semiconductor target. The film is heated under a rare gas (typically argon) atmosphere, under oxygen atmosphere, or under a rare gas (typically The film can be formed by sputtering under an atmosphere of argon and oxygen. When using the sputtering method, SiO 2 Using a target containing 2% by weight or more and 10% by weight or less The oxide semiconductor film is then formed to contain SiOx (X>0), which inhibits crystallization, and the oxide semiconductor film is then processed in the following steps. In order to prevent crystallization during the heat treatment for dehydration or dehydrogenation, is preferred.

[0090] Next, the oxide semiconductor film 480 is dehydrated or dehydrogenated. The temperature of the first heat treatment is 350° C. or higher and lower than the distortion point of the substrate, preferably 400° C. or higher. The substrate is placed in an electric furnace, which is a type of heat treatment device, and heated to a temperature below the distortion point of the substrate. After the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere, In order to prevent water or hydrogen from re-mixing into the oxide semiconductor layer, the oxide semiconductor layer is cooled slowly without being exposed to the air. In this embodiment, the oxide semiconductor layer is dehydrated. Or, heat the same furnace from the heating temperature T at which dehydrogenation takes place to a temperature high enough to prevent water from entering again. Specifically, the temperature is gradually cooled in a nitrogen atmosphere until it is 100°C lower than the heating temperature T. In addition, the atmosphere is not limited to nitrogen, and may be a rare gas atmosphere such as helium, neon, argon, or the like, or a reduced pressure atmosphere. A heat treatment is carried out under pressure for dehydration or dehydrogenation.

[0091] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0092] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor film, the oxide semiconductor film may be crystallized and microcrystallized. In some cases, the film may be a crystalline or polycrystalline film.

[0093] Note that the first heat treatment of the oxide semiconductor film 480 is performed after the oxide semiconductor layer is processed into an island shape. It can also be done.

[0094] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, Heat treatment (400℃ or higher) in an oxygen atmosphere or reduced pressure (argon, etc.) 100 ℃) to remove impurities such as hydrogen and water contained in the gate insulating layer.

[0095] Next, an oxide conductive film for use as a low-resistance drain region is formed on the oxide semiconductor layer 481. A layer and a conductive layer are formed.

[0096] The oxide conductive layer is formed by sputtering, vacuum deposition (electron beam deposition, etc.), or arc deposition. The low-resistance drain region is made of a material such as a silicon dioxide gas. For the above, an oxide conductive material can be used, for example, In-Sn-Zn-O system, In-Al -Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn- O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O In addition, a low-resistance drain region can be formed by using a metal oxide of the Zn-O system. The oxide conductive material used has a lower resistance than the oxide semiconductor layer 483 and a lower resistance than the conductive layer 484. A material with high resistance can be appropriately selected and used. In addition, when using the sputtering method, S iO 2 A film is formed using a target containing 2% by weight or more and 10% by weight or less of The conductive film contains SiOx (X>0), which inhibits crystallization, and is dehydrated or It is preferable to suppress crystallization during the heat treatment for dehydrogenation.

[0097] The conductive layer is made of an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. The alloys are made up of the above elements, or a combination of the above elements. .

[0098] The conductive layer is a layer of aluminum on a layer of titanium, and a layer of titanium on the aluminum layer. or a molybdenum layer on an aluminum layer and a It is preferable to use a three-layer laminate structure in which a molybdenum layer is laminated on the conductive layer. It may be a layered structure, a two-layered structure, or a laminated structure of four or more layers.

[0099] After forming the oxide conductive layer and the conductive layer, a resist used in a second photolithography process is Masks 482a and 482b are formed. Note that the resist mask 482a and the resist The mask 482b may be formed by an ink-jet method. When the method is used for formation, no photomask is used, and therefore the manufacturing cost can be reduced.

[0100] The resist mask 482a in this embodiment is a resist mask having a concave or convex portion. In other words, the resist is made up of multiple regions (two regions in this case) with different thicknesses. In the resist mask 482a, the thick region is made of a resist mask. The thin regions are called convex portions of the resist mask 482a, and the thin regions are called concave portions of the resist mask 482a. .

[0101] In the resist mask 482a, a portion where a source electrode layer and a drain electrode layer will be formed later is A protrusion is formed on the portion, and the protrusion is sandwiched between the source electrode layer and the drain electrode layer. A recess is formed in the portion that will become the region.

[0102] The resist mask 482a can be formed using a multi-tone mask. A mask is a mask that can perform exposure with multiple levels of light intensity. This refers to a mask that exposes the area with three levels of light intensity: the exposed area, the half-exposed area, and the unexposed area. By using this method, multiple thicknesses (typically two types) can be produced by a single exposure and development process. Therefore, by using a multi-tone mask, The number of photomasks can be reduced.

[0103] By exposing and developing using a multi-tone mask, a resist mask with regions of different thicknesses is created. However, the present invention is not limited to this, and a multi-tone mask may be used. Alternatively, the resist mask 482a may be formed without performing the etching.

[0104] Next, a conductive layer and a low resistance The drain region and the oxide semiconductor layer 481 are selectively and simultaneously etched to form an island-like The oxide semiconductor layers 483 and 485 and the low-resistance drain regions 406 and 4 07, and conductive layers 484 and 486 are formed (FIG. 2(C)). When a laminated conductive film of an aluminum film and a titanium film is used, dry etching using chlorine gas is performed. The etching can be performed by a etching method.

[0105] Next, the resist masks 482a and 482b are recessed (reduced). The resist mask is then recessed (reduced). To do this, ashing using oxygen plasma may be performed. By this, the conductive portion between the resist mask 487a and the resist mask 487b is The conductive layer 484 is exposed.

[0106] Next, the conductive layer 48 between the resist mask 487a and the resist mask 487b is 4 and the low-resistance drain region 406 in contact with the region are covered with a resist mask 487a and a resist The source electrode layer 465a is selectively etched using the mask 487b. and the drain electrode layer 465b, the first low-resistance drain region 408a and the second low-resistance drain In this case, the oxide semiconductor layer is only partially The oxide semiconductor layer 488 is etched to have a groove (depression).

[0107] As shown in FIG. 2(D), the resist masks 482a and 482b are recessed (reduced). The resist mask 487a and the resist mask 487b are used for etching to form an oxidized A thin region is formed on the periphery of the oxide semiconductor layers 483 and 485. The ends of the body layer 488 are closer to the ends of the first and second low-resistance drain regions 408a, 408b. The end of the oxide semiconductor layer 489 also protrudes further than the end of the low-resistance drain region 409. Note that the periphery of the oxide semiconductor layer 483 and the oxide semiconductor layer 484 which will be a channel formation region later are The groove (recess) of the semiconductor layer 488 has the same thickness.

[0108] Next, the resist masks 487a, 487b, and 487c are removed, and a third photolithography process is performed. A resist mask 491 is formed by a photolithography process, and selective etching is performed to remove the acid from the pixel area. The low-resistance drain region 409 and the conductive layer 490 formed on the nitride semiconductor layer 489 are then removed. (Figure 2(E)).

[0109] Note that the low-resistance drain region overlapping with the oxide semiconductor layer 489 is formed in the third photolithography process. In order to selectively remove the region 409 and the conductive layer 490, the oxide semiconductor layer The materials and etching conditions are adjusted appropriately so that the 489 is not removed. The resist mask 491 may be formed by an ink-jet method. When the film is formed by the jet method, a photomask is not used, and therefore the manufacturing cost can be reduced.

[0110] Next, the resist mask 491 is removed, and a metal film is formed in contact with the groove (depression) of the oxide semiconductor layer 488. The oxide insulating film 492 which serves as a protective insulating film in contact with the top surface and side surfaces of the oxide semiconductor layer 489 is formed. Complete.

[0111] The oxide insulating film 492 has a thickness of at least 1 nm and is formed by an oxide deposition method such as a sputtering method. The insulating film 492 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed in. In this embodiment, a silicon oxide film having a thickness of 300 nm is used as the oxide insulating film 492. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. Gas (typically argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) atmosphere The target can be a silicon oxide target. A get or silicon target can be used. For example, a silicon target can be used to A silicon oxide film can be formed by sputtering in an oxygen and nitrogen atmosphere. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is resistant to moisture and hydrogen ions. Nya, OH - It does not contain impurities such as chlorine and is an inorganic material that blocks the intrusion of these substances from the outside. An insulating film is used, typically a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an oxide film. An aluminum nitride film or the like is used.

[0112] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. The temperature is between 00°C and 400°C, for example between 250°C and 350°C (Figure 3(A)). For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The grooves of the oxide semiconductor layer 488 and the top and side surfaces of the oxide semiconductor layer 489 are covered with an oxide insulating film. It is heated in contact with 492.

[0113] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor film is selectively As a result, the channel formation region 463 overlapping with the gate electrode layer 461 has an I-type structure. The first high-resistance drain region 464a overlaps the source electrode layer 465a, and the drain electrode A second high-resistance drain region 464b overlapping the pole layer 465b is formed in a self-aligned manner. In addition, the oxide semiconductor layer 472 overlapping with the gate electrode layer 471 has an i-type structure as a whole.

[0114] Note that the oxide semiconductor layer overlapping with the drain electrode layer 465b (and the source electrode layer 465a) In the second high-resistance drain region 464b (or the first high-resistance drain region 464a By forming the insulating layer 3, the reliability of the formed driver circuit can be improved. Specifically, by forming the second high-resistance drain region 464b, the first high-resistance drain region 464b is formed. The conductivity is gradually changed from the high resistance drain region 464b to the channel formation region. Therefore, a high power supply potential can be applied to the drain electrode layer 465b. When the device is connected to a wiring that supplies VDD, the gate electrode layer 461 and the drain electrode layer Even if a high electric field is applied between 465b and the drain region, the high resistance drain region acts as a buffer and prevents local high A structure in which no electric field is applied and the withstand voltage of the transistor can be improved can be obtained.

[0115] In addition, the oxide semiconductor layer overlapping with the drain electrode layer 465b (and the source electrode layer 465a) In the second high-resistance drain region 464b (or the first high-resistance drain region 464a ) is formed, the leakage current in the channel formation region 463 when the driver circuit is formed is reduced. It is possible to reduce the flow.

[0116] In addition, between the drain electrode layer 465b (and the source electrode layer 465a) and the oxide semiconductor layer The second low-resistance drain region 408b (and the first low-resistance drain region 408a) This structure allows the device to have a more thermally stable operation than a Schottky junction. The resistive drain region 408a and the second low-resistive drain region 408b are formed of an oxide semiconductor layer. and has a lower resistance than the drain electrode layer 465b (and the source electrode layer 465a). Since the contact resistance between the oxide semiconductor layer and the drain or source electrode layer is high, the contact resistance between the oxide semiconductor layer and the drain or source electrode layer is reduced. It is possible.

[0117] Next, resist masks 493a and 493b are formed by a fourth photolithography process. The oxide insulating film 492 is selectively etched to remove the oxide semiconductor layer 472 in the pixel portion. An oxide insulating layer (channel protection layer) 476 is formed on the channel formation region (FIG. 3(B)). By providing the channel protective layer 476, a channel formation region of the oxide semiconductor layer 472 is Damage during the process (film loss due to plasma or etching agent during etching, etc.) Therefore, the reliability of the thin film transistor can be improved. Note that in the case where an oxide insulating layer is used as the gate insulating layer 452b as in this embodiment, Part of the gate insulating layer 452b is also etched by the etching process of the oxide insulating layer 492. The oxide insulating layer 452b may be formed by the gate insulating layer 452a. When a nitride insulating film having a smaller etching rate than the insulating film 492 is used, the gate insulating layer 45 This can prevent 2b from being partially etched.

[0118] In addition, after dehydration or dehydrogenation, the channel protection layer 476 is continuously formed without exposure to air. By continuously treating the surface without exposing it to air, the interface can be formed as follows: Contamination by atmospheric components or impurities suspended in the air, such as water or hydrocarbons Since each lamination interface can be formed without any trouble, the variation in thin film transistor characteristics can be reduced. It is possible.

[0119] The resist masks 493a and 493b may be formed by an ink-jet method. When the photomask is formed by the inkjet method, no photomask is used, so the manufacturing cost is reduced. It can be reduced.

[0120] Next, the second gate insulating layer 452b, the oxide semiconductor layer 472, and the channel protection layer 474 in the pixel portion are After forming a light-transmitting conductive film on the protective layer 476, a fifth photolithography process is performed. Thus, a source electrode layer 475a and a drain electrode layer 475b are formed (FIG. 3C). The methods for forming conductive films with optical properties include sputtering, vacuum deposition (electron beam deposition, etc.), and The arc discharge ion plating method and the spray method are used. The conductive film is made of the following materials: Conductive materials that are transparent to visible light, such as In-Sn-Zn-O, In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system Zn-O-based metal oxides can be used, and the film thickness is 50 nm to 300 nm. In addition, when using a sputtering method, SiO 2 2% by weight or more 10 times The film is formed using a target containing 0.01% or less of the compound, and the film is then formed into a light-transmitting conductive film having a crystallization inhibiting property. It is preferable that SiOx (x>0) is contained.

[0121] Note that a resist pattern for forming the source electrode layer 475a and the drain electrode layer 475b was used. The resist mask may be formed by an ink-jet method. This eliminates the need for a photomask, reducing manufacturing costs.

[0122] Next, the oxide insulating layer 466, the channel protection layer 476, the source electrode layer 475a, and the drain A protective insulating layer 453 is formed on the inner electrode layer 475b (FIG. 3(D)). The silicon nitride film is formed by RF sputtering. RF sputtering is suitable for mass production. This is a preferable method for forming the protective insulating layer 453. The protective insulating layer 453 is formed by absorbing moisture, hydrogen ions, and the like. Nya, OH - It does not contain impurities such as chlorine and is an inorganic material that blocks the intrusion of these substances from the outside. The insulating film is a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, Of course, the protective insulating layer 453 is a light-transmitting insulating film.

[0123] The protective insulating layer 453 is formed by insulating a first gate insulating layer 452 provided under the protective insulating layer 453. a or a structure in which it is in contact with the insulating film serving as the base, and water from the vicinity of the side surface of the substrate is prevented. Molecular weight, hydrogen ions, and OH - In particular, it blocks the intrusion of impurities such as The first gate insulating layer 452a in contact with the edge layer 453 or the insulating film serving as the base is made of a silicon nitride film. That is, it is effective to form a silicon nitride film so as to surround the lower surface, the upper surface, and the side surfaces of the oxide semiconductor layer. The provision of the film improves the reliability of the display device.

[0124] Next, a planarization insulating layer 454 is formed over the protective insulating layer 453. Examples of resins include acrylic resins, polyimides, benzocyclobutene resins, polyamides, and epoxy resins. In addition to the above organic materials, organic materials having low dielectric constant can be used. low-k materials, siloxane resins, PSG (phosphorus glass), BPSG (phosphorus In addition, the insulating film formed of these materials can be used in multiple layers. A planarization insulating layer 454 may be formed by stacking.

[0125] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0126] The method for forming the planarization insulating layer 454 is not particularly limited. Depending on the material, it may be a sputtering method, a SO G method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen Printing methods such as inkjet printing, offset printing, doctor knife, roll coater, curtain Tools such as a spool coater or a knife coater can be used.

[0127] Next, a sixth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 54 and the protective insulating layer 453 are etched to form a contact that reaches the drain electrode layer 475b. Also, the etching in this step forms a hole 494. A contact hole reaching the drain electrode layer 475b is also formed. A resist mask for forming a resist hole may be formed by an ink-jet method. If the mask is formed by the inkjet method, no photomask is used, so the manufacturing cost is reduced. can be reduced.

[0128] Next, after removing the resist mask, a light-transmitting conductive film is formed. The conductive film material is indium oxide (In 2 O 3 ) and indium oxide tin oxide alloy (In 2 O 3 - SnO 2 ITO is abbreviated as ITO, and is made by sputtering or vacuum deposition. As another material for the conductive film having light-transmitting properties, an Al-Zn-O-based Non-single crystal films, i.e. Al-Zn-ON non-single crystal films and Zn-O non-single crystal films containing nitrogen Crystalline films, i.e. Zn-ON type non-single crystal films and nitrogen-containing Sn-Zn-O type non-single crystal films, That is, a Sn-Zn-ON non-single crystal film may be used. The composition ratio (atomic %) of zinc in the crystalline film is 47 atomic % or less, and the aluminum in the non-single crystal film is The composition ratio (atomic %) of aluminum in the non-single crystal film is larger than that of The composition ratio (atomic percentage) of nitrogen in the single crystal film is larger than that in the single crystal film. It is done with an acid solution. However, etching of ITO is particularly prone to leaving residues, so Indium oxide zinc oxide alloy (InO2) was used to improve etching workability. 2 O 3 -ZnO) You may use it.

[0129] The composition ratio of the light-transmitting conductive film is expressed in atomic percent. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be used for the evaluation.

[0130] Next, a seventh photolithography step is performed to form a resist mask and to form a Then, unnecessary portions are removed to form a pixel electrode layer 477 and a conductive layer 467 (see FIG. 3E). .).

[0131] Through the above steps, the thin film transistor 460 and the thin film transistor 470 are formed on the same substrate using seven masks. The film transistor 470 can be fabricated separately for the driver circuit or pixel portion. The thin film transistor 460 for the driving circuit has a first high resistance drain region 464a, a second The oxide semiconductor layer includes the high-resistance drain region 464b and the channel formation region 463. The pixel thin film transistor 470 is a channel-etched thin film transistor. A channel protection thin film transistor including an oxide semiconductor layer 472 having an i-type structure It is a channel-stop type thin-film transistor.

[0132] In addition, the first gate insulating layer 452a and the second gate insulating layer 452b are used as dielectrics to form a capacitance wiring The storage capacitor formed by the thin film transistor and the capacitance electrode can also be formed on the same substrate. The pixel section is configured by arranging the stator 470 and the storage capacitor in a matrix corresponding to each pixel, By disposing a driving circuit having a thin film transistor 460 around the pixel portion, active The present invention can be used as one of the substrates for manufacturing a sub-matrix type display device. For convenience, such a substrate is called an active matrix substrate.

[0133] The pixel electrode layer 477 is formed on the planarization insulating layer 454 and the protective insulating layer 453. The capacitor electrode is electrically connected to the source electrode 47 through a contact hole. It can be formed of the same material and in the same process as the drain electrode layer 5a and the drain electrode layer 475b.

[0134] The conductive layer 467 is provided so as to overlap with the channel formation region 463 of the oxide semiconductor layer. The bias-thermal stress test (BT) is used to check the reliability of thin-film transistors. In the test, the threshold voltage of the thin film transistor 460 before and after the BT test was In addition, the conductive layer 467 has a potential equal to that of the gate electrode layer 461. It may be the same or different and may also function as the second gate electrode layer. The potential of the conductive layer 467 may be GND, 0V, or may be in a floating state. .

[0135] In addition, a resist mask for forming the pixel electrode layer 477 is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not required. This reduces manufacturing costs.

[0136] This embodiment mode can be freely combined with other embodiment modes.

[0137] (Embodiment 2) In this embodiment mode, a semiconductor device and a manufacturing method of the semiconductor device, which are different from those in Embodiment Mode 1, will be described with reference to FIGS. Specifically, in the semiconductor device shown in FIG. Both the thin film transistor and the thin film transistor arranged in the pixel portion have at least a channel. a first high-resistance drain region and a second high-resistance drain region; A semiconductor device having a structure in which a conductor layer is an active layer will be described. The thin film transistor arranged in the driver circuit is the thin film transistor shown in the first embodiment. It has the same structure as 460 and can be manufactured by the same process. In this embodiment, the same parts as those in the first embodiment or parts and steps having similar functions are the same as those in the first embodiment. This can be performed in the same manner as in embodiment 1, and a repeated explanation will be omitted.

[0138] On a substrate 450 having an insulating surface, gate electrode layers 461 and 471 and a first gate insulating layer 4 52a, a second gate insulating layer 452b is formed, and in the driver circuit area, a channel forming region The drain region 463 includes a first high-resistance drain region 464a and a second high-resistance drain region 464b. The oxide semiconductor layer, the first low-resistance drain region 408a, the second low-resistance drain region 40 8b, a source electrode layer 465a, a drain electrode layer 465b, and an oxide insulating layer 466 are formed. In the pixel portion, an oxide semiconductor layer 472 and a channel protection layer 476 are formed (see FIG. 4(A)). The oxide semiconductor layer 472 is an i-type oxide semiconductor layer with high resistance.

[0139] Note that the oxide semiconductor layer of the thin film transistor 460 provided in the driver circuit portion and the oxide semiconductor A thin region is formed on the periphery of the conductor layer 472. The end of the oxide semiconductor layer 400 is a first low-resistance drain region 408a, a second low-resistance drain region 408b, and a third low-resistance drain region 408c. The oxide semiconductor of the thin film transistor 460 is The peripheral portion of the oxide semiconductor layer and the groove (recess) of the oxide semiconductor layer which will later become the channel formation region are aligned in the same direction. The thickness of the film is the same.

[0140] In this embodiment, the oxide semiconductor layer 472 is exposed to nitrogen. Heat treatment is performed under an inert gas atmosphere such as fluorine or under reduced pressure. Further, the oxide semiconductor layer 472 is heated under an inert gas atmosphere such as nitrogen while being partly exposed. When heat treatment is performed under reduced pressure, the exposed high-resistance oxide semiconductor layer 472 is The resistivity of the region that has been made I-type can be reduced to form a high-resistance drain region.

[0141] In the oxide semiconductor layer 472, a high-resistance (i-type) region is changed to a low-resistance region. The heat treatment is preferably carried out at a temperature of 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. For example, a heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0142] In this embodiment, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer 4 After heat treatment under a nitrogen atmosphere, the heating temperature was reduced without exposure to air. The specimen is gradually cooled in a nitrogen atmosphere from the heating temperature T to a temperature 100°C or more lower than the heating temperature T. The decomposition atmosphere is not limited to nitrogen, but may be helium, neon, argon, or the like, or may be reduced pressure. The hydrogen is hydrated or dehydrogenated. In the heat treatment, nitrogen, helium, or neon is used. It is preferable that the rare gas such as argon does not contain water, hydrogen, etc. The purity of the nitrogen or rare gases such as helium, neon, and argon introduced into the device is 6N (9 9.9999%) or more, preferably 7N (99.99999%) or more (i.e. impurity concentration It is preferable to set the content of the EDTA to 1 ppm or less, and preferably 0.1 ppm or less.

[0143] The oxide semiconductor layer 472 is subjected to heat treatment in an inert gas atmosphere such as nitrogen or under reduced pressure. As a result, the exposed region of the oxide semiconductor layer 472 has a low resistance, and the first high-resistance drain region 4 The oxide semiconductor layer 472 is formed on the first high-resistance drain region 474a and the second high-resistance drain region 474b. In this case, the region covered by the channel protection layer 476 remains a high resistance region. Therefore, the first high-resistance drain region 474 is an I-type channel formation region 473. a, the second high-resistance drain region 474b, and the oxide semiconductor including the channel formation region 473. A layer 495 is formed (see FIG. 4(B)).

[0144] Next, a light-transmitting conductive film was formed over the oxide semiconductor layer 495 and the channel protective layer 476. After the formation, the source electrode layer 475a and the drain electrode layer 475b are formed by a fifth photolithography process. An electrode layer 475b is formed (FIG. 4(C)).

[0145] Then, the oxide insulating layer 466, the source electrode layer 475a, the drain electrode layer 475b, and the channel electrode layer 475c are A protective insulating layer 453 and a planarizing insulating layer 454 are stacked over the panel protective layer 476 .

[0146] Next, a sixth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 54, and the protective insulating layer 453 is etched to form a contact that reaches the drain electrode layer 475b. A cut hole 494 is formed (FIG. 4(D)).

[0147] Next, after removing the resist mask, a light-transmitting conductive film is formed.

[0148] Next, a seventh photolithography step is performed to form a resist mask and to form a Then, unnecessary portions are removed to form a pixel electrode layer 477 and a conductive layer 467 (FIG. 4(E)).

[0149] Through the above steps, the thin film transistor 460 and the thin film transistor 470 are formed on the same substrate using seven masks. The film transistor 498 can be fabricated separately for the driver circuit or pixel portion. The thin film transistor 460 disposed in the driving circuit has a first high resistance drain region 464 a, the second high-resistance drain region 464b, and the oxide semiconductor including the channel formation region 463. The thin-film transistor is a channel-etch type thin-film transistor including a dielectric layer. The stum 498 also has a first high-resistance drain region 474a, a second high-resistance drain region 474b, and The channel-protective thin film transistor 471 includes an oxide semiconductor layer 495 having a channel formation region 473. Therefore, the thin film transistors 460 and 498 are The high-resistance drain region acts as a buffer to prevent localized high electric fields from being applied, and the breakdown voltage of the transistor is This configuration improves the following:

[0150] In the thin film transistor 460, the drain electrode layer 465b (and the source electrode layer 46 5a) and the oxide semiconductor layer, a second low-resistance drain region 408b (and a first low-resistance By using a structure having a drain region 408a), the thermal The first low-resistance drain region 408a and the second low-resistance drain region 408b have a stable operation. The region 408b has a lower resistance than the oxide semiconductor layer and is Since the resistance of the oxide semiconductor layer and the drain or source electrode layer 465a is higher than that of the The contact resistance with the layer can be reduced.

[0151] In addition, the first gate insulating layer 452a and the second gate insulating layer 452b are used as dielectrics to form a capacitance wiring The storage capacitor formed by the thin film transistor and the capacitor electrode can also be formed on the same substrate. The pixel section is composed of a matrix of resistors 498 and storage capacitors corresponding to each pixel. By disposing a driving circuit having a thin film transistor 460 around the pixel portion, The liquid crystal display device may be one of the substrates for manufacturing a display device of a positive matrix type.

[0152] The conductive layer 467 is provided so as to overlap with the channel formation region 463 of the oxide semiconductor layer. The bias-thermal stress test (BT) is used to check the reliability of thin-film transistors. In the test, the threshold voltage of the thin film transistor 460 before and after the BT test was In addition, the conductive layer 467 has a potential equal to that of the gate electrode layer 461. It may be the same or different and may also function as the second gate electrode layer. The potential of the conductive layer 467 may be GND, 0V, or may be in a floating state. .

[0153] Note that this embodiment mode can be freely combined with other embodiment modes.

[0154] (Embodiment 3) In this embodiment mode, a semiconductor device and a manufacturing method of the semiconductor device different from those in Embodiment Modes 1 and 2 are described. Specifically, in the semiconductor device shown in FIG. Both the thin film transistor disposed in the pixel portion and the thin film transistor disposed in the pixel portion have a gate electrode layer. The entire channel formation region overlapping with the oxide semiconductor layer is an I-type oxide semiconductor layer as an active layer. A semiconductor device will be described. In this embodiment, the same parts as those in the first embodiment and The parts and steps having the same functions as those in the first embodiment can be carried out repeatedly. The explanation of this will be omitted.

[0155] 5A to 5C are cross-sectional views showing a manufacturing process of a thin film transistor 498. According to the first embodiment, a conductive film having a light-transmitting property is formed on a substrate 450 having an insulating surface. Gate electrode layers 461 and 471 are formed by a first photolithography process.

[0156] Next, a first gate insulating layer 452a and a second gate insulating layer 452b are formed on the gate electrode layers 461 and 471. Next, a 2 nm thick edge layer 452b is formed on the second gate insulating layer 452b. An oxide semiconductor film 480 having a thickness of 200 nm or less is formed (FIG. 5A). The process is the same as that in the first embodiment, and FIG. 5(A) corresponds to FIG. 2(A).

[0157] Next, the oxide semiconductor film 480 is dehydrated or oxidized under an inert gas atmosphere or reduced pressure. The temperature of the first heat treatment for dehydration or dehydrogenation is 350° C. or higher. The temperature is set to be lower than the distortion point of the substrate, preferably 400° C. or higher. The substrate is placed in an electric furnace, and the oxide semiconductor film is subjected to heat treatment in a nitrogen atmosphere. After that, the oxide semiconductor film is not exposed to the air, and water and hydrogen are prevented from re-mixing into the oxide semiconductor film. The membrane is made oxygen-deficient to reduce resistance, i.e., N-type (N - After that, in the same furnace, High purity oxygen gas or high purity N 2 O2 gas or ultra-dry air (dew point below -40℃) Cooling is performed by introducing oxygen gas or N 2 O gas, water, It is preferable that hydrogen and the like are not included. Alternatively, oxygen gas or N 2 The purity of O gas is 6N (99.9999%) or more, preferably 7N (99.9999%). 9%) or more (i.e. oxygen gas or N 2 The impurity concentration in the O gas is preferably 1 ppm or less. It is preferable that the concentration of the ion exchange resin is 0.1 ppm or less.

[0158] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. or in an oxygen gas atmosphere at a temperature between 200°C and 300°C, or in an N 2 Under O gas atmosphere Or heating in an ultra-dry air atmosphere (dew point below -40°C, preferably below -60°C) Processing may be carried out.

[0159] Through the above steps, the entire oxide semiconductor film 496 is made to have an oxygen excess state. , the resistance is increased, that is, the I-type is formed (Figure 5(B)).

[0160] As a result, the reliability of the thin film transistor to be formed later can be improved.

[0161] Next, the oxide semiconductor film is subjected to a photolithography process to form an island-shaped oxide semiconductor layer. The resulting semiconductor layers are then processed into nitride semiconductor layers 497 and 472 .

[0162] Note that the oxide semiconductor film is dehydrated or dehydrogenated under an inert gas atmosphere or reduced pressure. After cooling under an inert gas atmosphere, island-shaped oxide layers are formed by a photolithography process. Then, the oxide semiconductor layers 497 and 472 are processed into a semiconductor layer. ℃ or less, preferably 200 ℃ to 300 ℃ in an oxygen gas atmosphere or N 2 Oga Under a dry atmosphere or under an ultra-dry air atmosphere (dew point below -40°C, preferably below -60°C) Heat treatment at 40° C. may also be performed.

[0163] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, Heat treatment (400℃ or higher) in an oxygen atmosphere or reduced pressure (argon, etc.) The gate insulating layer is then formed by removing impurities such as hydrogen and water contained in the layer. Good too.

[0164] However, the high-resistance (i-type) oxide semiconductor layers 497 and 472 are exposed. When heat treatment was performed under nitrogen or inert gas atmosphere or reduced pressure in this state, the resistance increased ( The resistance of the oxide semiconductor layers 497 and 472 (which have been made i-type) is reduced to form high-resistance drain regions. Therefore, the heat treatment performed in the state where the oxide semiconductor layers 497 and 472 are exposed is performed with oxygen. Gas, N 2 Under an O2 gas atmosphere or ultra-dry air (dew point below -40°C, preferably -60°C This is done as follows:

[0165] Note that in this embodiment, an example in which dehydration or dehydrogenation is performed after the oxide semiconductor film is formed will be described. However, the first heat treatment of the oxide semiconductor layer is not particularly limited, and the oxide semiconductor layer is formed into an island-shaped oxide semiconductor layer. Alternatively, the oxide semiconductor film may be processed into a desired shape.

[0166] Next, similarly to FIGS. 2(C) to (E) and 3(A) to (E) in the first embodiment, In the peripheral driver circuit area, only a part of the oxide semiconductor layer 497 is etched to form a groove. The oxide semiconductor layer 497 having a recess is formed. The second low-resistance drain region 408b, the source electrode layer 465a which is a conductive layer, the drain electrode The oxide insulating layer 466 is formed in contact with the oxide semiconductor layer 497. On the other hand, in the pixel portion, a thin film transistor 499 having an oxide semiconductor layer 472 is manufactured. A channel protection layer 476 is formed on the channel formation region of the semiconductor substrate 470, and a conductive layer having a light-transmitting property is formed on the channel formation region of the semiconductor substrate 470. A source electrode layer 475a and a drain electrode layer 475b are formed, and a thin film transistor 47 Create 0.

[0167] Note that thin regions are formed around the peripheries of the oxide semiconductor layers 497 and 472. The end portions of the oxide semiconductor layer 483 are connected to the first low-resistance drain region 408a and the second low-resistance drain region 408b. The oxide semiconductor layer 483 and the drain region 408b are formed on the oxide semiconductor layer 483. The thickness of the oxide semiconductor layer 483 is the same as that of the groove (depression) of the oxide semiconductor layer 483 which is to become a channel formation region later. is doing.

[0168] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. For example, the heating is performed in a nitrogen atmosphere. A second heat treatment is carried out at 250° C. for 1 hour under atmospheric pressure.

[0169] Next, the thin film transistors 499 and 470 are covered with an oxide insulating layer 466 and a channel protection layer 476, and a protective insulating layer 453 in contact with the source electrode layer 475a and the drain electrode layer 475b. A protective insulating layer 453 and a planarization insulating layer 454 are stacked. A contact hole reaching the drain electrode layer 475b is formed in the contact hole 4. A light-transmitting conductive film is deposited over the planarization insulating layer 454. a pixel electrode layer 477 which is selectively etched to electrically connect to the thin film transistor 470; A conductive layer 467 is formed (FIG. 5(C)).

[0170] Through the above process, seven masks are used to form a thin film transistor 499 and a thin The film transistor 470 can be fabricated separately for the driver circuit or pixel portion. The thin film transistor 499 for the driver circuit has an oxide semiconductor layer 497 which is entirely i-type. The thin film transistor 470 for the pixel is also a channel-etch type thin film transistor including The channel-protective thin film transistor includes an oxide semiconductor layer 472 whose body is i-type.

[0171] In the thin film transistor 499, the drain electrode layer 465b (and the source electrode layer 46 5a) and the oxide semiconductor layer, a second low-resistance drain region 408b (and a first low-resistance By using a structure having a drain region 408a), the thermal The first low-resistance drain region 408a and the second low-resistance drain region 408b have a stable operation. The region 408b has a lower resistance than the oxide semiconductor layer and is Since the resistance of the oxide semiconductor layer and the drain or source electrode layer 465a is higher than that of the The contact resistance with the layer can be reduced.

[0172] In addition, the first gate insulating layer 452a and the second gate insulating layer 452b are used as dielectrics to form a capacitance wiring The storage capacitor formed by the thin film transistor and the capacitor electrode can also be formed on the same substrate. The pixel section is composed of a matrix of resistors 470 and storage capacitors corresponding to each pixel. By disposing a driver circuit having a thin film transistor 499 around the pixel portion, The liquid crystal display device may be one of the substrates for manufacturing a display device of a positive matrix type.

[0173] The conductive layer 467 is provided so as to overlap with a channel formation region of the oxide semiconductor layer 497. The bias-thermal stress test (BT) is used to check the reliability of thin-film transistors. In the test, the threshold voltage of the thin film transistor 499 before and after the BT test was In addition, the conductive layer 467 has a potential equal to that of the gate electrode layer 461. It may be the same or different and may also function as the second gate electrode layer. The potential of the conductive layer 467 may be GND, 0V, or may be in a floating state. .

[0174] Note that this embodiment mode can be freely combined with other embodiment modes.

[0175] (Embodiment 4) In this embodiment mode, a semiconductor device and a manufacturing method of the semiconductor device which are different from those in Embodiment Modes 1 to 3 will be described. This will be described with reference to FIG. 6. Specifically, in the semiconductor device shown in FIG. In the thin film transistor to be fabricated, the entire channel formation region overlapping with the gate electrode layer is I-type. The thin film transistor, which has an oxide semiconductor layer as an active layer and is arranged in the pixel portion, is a first highly resistive drain region and a second highly resistive drain region; A semiconductor device having a structure in which a semiconductor layer is an active layer will be described. In the embodiment, the same parts as those in the first embodiment or parts and steps having similar functions are the same as those in the first embodiment. This can be performed in the same manner as in mode 1, and a repeated explanation will be omitted.

[0176] 6A to 6D are cross-sectional views showing manufacturing steps of thin film transistors 499 and 498. FIG.

[0177] First, the steps up to the step of FIG. 5(B) in the third embodiment are carried out according to the third embodiment. A) is the same as the process in FIG. 5(B).

[0178] On a substrate 450 having an insulating surface, gate electrode layers 461 and 471 and a first gate insulating layer 4 52a, a second gate insulating layer 452b is formed, and an oxide layer is formed on the second gate insulating layer 452b. An oxide semiconductor film 496 is formed on the oxide semiconductor film 496 (FIG. 6(A)). It is type I.

[0179] Next, the oxide semiconductor film 496 is formed into an island-shaped oxide semiconductor layer by a photolithography process. The oxide semiconductor layers 497 and 472 are processed.

[0180] Next, similarly to FIGS. 2(C) to (E) and 3(A) to (E) in the first embodiment, In the peripheral driver circuit area, only a part of the oxide semiconductor layer 497 is etched to form a groove. The oxide semiconductor layer 497 having a recess is formed. The second low-resistance drain region 408b, the source electrode layer 465a which is a conductive layer, the drain electrode The oxide insulating layer 466 is formed in contact with the oxide semiconductor layer 497. On the other hand, in the pixel portion, a thin film transistor 499 having an oxide semiconductor layer 472 is manufactured. A channel protection layer 476 is formed on the channel formation region (FIG. 6(B)).

[0181] Note that thin regions are formed around the peripheries of the oxide semiconductor layers 497 and 472. The end portions of the oxide semiconductor layer 483 are connected to the first low-resistance drain region 408a and the second low-resistance drain region 408b. The oxide semiconductor layer 483 and the drain region 408b are formed on the oxide semiconductor layer 483. The thickness of the oxide semiconductor layer 483 is the same as that of the groove (depression) of the oxide semiconductor layer 483 which is to become a channel formation region later. is doing.

[0182] In this embodiment, as in the second embodiment, at least a part of the oxide semiconductor layer 472 is exposed. In this state, heat treatment is performed in an inert gas atmosphere such as nitrogen or under reduced pressure. In the state where the oxide semiconductor layer 472 is exposed, an inactive ion such as nitrogen is introduced. When heat treatment is performed under a reactive gas atmosphere or under reduced pressure, the exposed oxide semiconductor layer 472 The high-resistance (I-type) region is then made low-resistance to become a high-resistance drain region. This can be done.

[0183] In the oxide semiconductor layer 472, a high-resistance (i-type) region is changed to a low-resistance region. The heat treatment is preferably carried out at a temperature of 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. For example, a heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0184] In this embodiment, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer 4 After heat treatment under a nitrogen atmosphere, the heating temperature was reduced without exposure to air. The specimen is gradually cooled in a nitrogen atmosphere from the heating temperature T to a temperature 100°C or more lower than the heating temperature T. Dehydration is performed under an atmosphere (not limited to nitrogen, but may be performed under helium, neon, argon, etc.) or reduced pressure. In the heat treatment, nitrogen, helium, neon, or arsenic is used. It is preferable that the rare gas such as argon does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the 9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1 ppm or less, preferably 0.1 ppm or less).

[0185] The oxide semiconductor layer 472 is subjected to heat treatment in an inert gas atmosphere such as nitrogen or under reduced pressure. By the heat treatment, the resistance of an exposed region of the oxide semiconductor layer 472 is reduced, and the first high-resistance drain A first high-resistance drain region 474a and a second high-resistance drain region 474b are formed. The region of the layer 472 covered by the channel protection layer 476 is a high resistance region. The first high-resistance drain region 473 remains as it is and becomes an I-type channel formation region 473. The oxide layer 474 includes a first high-resistance drain region 474a, a second high-resistance drain region 474b, and a channel forming region 473. A compound semiconductor layer 495 is formed (FIG. 6(C)).

[0186] Next, a light-transmitting conductive film was formed over the oxide semiconductor layer 495 and the channel protective layer 476. After the formation, the source electrode layer 475a and the drain electrode layer 475b are formed by a fifth photolithography process. An electrode layer 475b is formed.

[0187] Then, the oxide insulating layer 466, the source electrode layer 475a, the drain electrode layer 475b, and the channel electrode layer 475c are A protective insulating layer 453 and a planarizing insulating layer 454 are stacked over the panel protective layer 476 .

[0188] Next, a sixth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 54, and the protective insulating layer 453 is etched to form a contact that reaches the drain electrode layer 475b. Forms a cut hole 494.

[0189] Next, after removing the resist mask, a light-transmitting conductive film is formed.

[0190] Next, a seventh photolithography step is performed to form a resist mask and to form a Then, unnecessary portions are removed to form a pixel electrode layer 477 and a conductive layer 467 (FIG. 6(D)).

[0191] Through the above process, seven masks are used to form a thin film transistor 499 and a thin The film transistor 498 can be fabricated separately for the driver circuit or pixel portion. The thin film transistor 499 for the driver circuit has an oxide semiconductor layer 497 which is entirely i-type. The pixel thin film transistor 498 is a channel-etched thin film transistor including the first A first high-resistance drain region 474a, a second high-resistance drain region 474b, and a channel type The channel-protective thin film transistor includes an oxide semiconductor layer 472 having a semiconductor region 473. The thin film transistor 498 has a high resistance drain region that acts as a buffer even when a high electric field is applied. This prevents a high electric field from being applied locally, improving the breakdown voltage of the transistor.

[0192] In the thin film transistor 499, the drain electrode layer 465b (and the source electrode layer 46 5a) and the oxide semiconductor layer, a second low-resistance drain region 408b (and a first low-resistance By using a structure having a drain region 408a), the thermal The first low-resistance drain region 408a and the second low-resistance drain region 408b have a stable operation. The region 408b has a lower resistance than the oxide semiconductor layer and is Since the resistance of the oxide semiconductor layer and the drain or source electrode layer 465a is higher than that of the The contact resistance with the layer can be reduced.

[0193] In addition, the first gate insulating layer 452a and the second gate insulating layer 452b are used as dielectrics to form a capacitance wiring The storage capacitor formed by the thin film transistor and the capacitor electrode can also be formed on the same substrate. The pixel section is composed of a matrix of resistors 498 and storage capacitors corresponding to each pixel. By disposing a driver circuit having a thin film transistor 499 around the pixel portion, The liquid crystal display device may be one of the substrates for manufacturing a display device of a positive matrix type.

[0194] The conductive layer 467 is provided so as to overlap with a channel formation region of the oxide semiconductor layer 497. The bias-thermal stress test (BT) is used to check the reliability of thin-film transistors. In the test, the threshold voltage of the thin film transistor 499 before and after the BT test was In addition, the conductive layer 467 has a potential equal to that of the gate electrode layer 461. It may be the same or different and may also function as the second gate electrode layer. The potential of the conductive layer 467 may be GND, 0V, or may be in a floating state. .

[0195] Note that this embodiment mode can be freely combined with other embodiment modes.

[0196] (Embodiment 5) In this embodiment mode, the active matrix substrate shown in Embodiment 1 is used to This embodiment shows an example of manufacturing a liquid crystal display device of a matrix type. The present invention can also be applied to the active matrix substrates shown in 2 to 4.

[0197] FIG. 7A shows an example of a cross-sectional structure of an active matrix substrate.

[0198] In the first embodiment, the thin film transistors of the driver circuit and the thin film transistors of the pixel section are formed on the same substrate. In the present embodiment, in addition to the thin film transistors, a storage capacitor, a gate The terminals of the gate and source lines are also shown in the figures. The manufacturing process can be the same as that shown in the first embodiment, and the number of photomasks can be reduced. In addition, the display area of ​​the pixel portion can be manufactured without increasing the number of steps. In the portion where the gate wiring, the source wiring, and the capacitance wiring layer are all made of a conductive material having light transmission properties. The film is used to achieve a high aperture ratio. The line layer can be made of metal wiring in order to reduce the wiring resistance.

[0199] In FIG. 7A, a thin film transistor 210 is a channel etched thin film transistor provided in a driving circuit. The thin film transistor 227 is electrically connected to the pixel electrode layer 227. Reference numeral 20 denotes a channel protection type thin film transistor provided in a pixel portion.

[0200] In this embodiment, the thin film transistor 220 formed above the substrate 200 is The same structure as the thin film transistor 470 of the first embodiment is used.

[0201] A layer formed of the same material and process as the gate electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is made of a first gate insulating layer 202a and a second gate insulating layer 202b, which are dielectrics. The insulating layer 202b overlaps with the capacitance electrode 231 to form a storage capacitor. The thin film transistor 220 has a source electrode layer or a drain electrode layer having the same light-transmitting property as the thin film transistor 220. Therefore, the thin film transistor 220 has a light-transmitting property. In addition, each storage capacitor is transparent, which improves the aperture ratio. can be done.

[0202] It is important for the storage capacitor to have light transmittance in order to improve the aperture ratio. In the following small LCD panels, the number of gate wirings is increased to improve the resolution of the displayed image. Even if the pixel size is reduced to achieve high resolution, a high aperture ratio can be achieved. By using a film having light transmitting properties as the constituent members of the thin film transistor 220 and the storage capacitor, To achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple sub-pixels. That is, even if a high density group of thin film transistors is arranged, a large aperture ratio can be obtained. For example, two to four pixels can be arranged in one pixel, and a sufficient area can be secured for the display area. When the device has four sub-pixels and a storage capacitor, the thin film transistor is transparent. In addition, each storage capacitor is transparent, so that the aperture ratio can be improved. do.

[0203] The storage capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is disposed below the pixel electrode layer 227. 27.

[0204] In this embodiment, a storage capacitor is formed using a capacitor electrode 231 and a capacitor wiring layer 230. However, the structure for forming the storage capacitor is not particularly limited. For example, The pixel electrode layer is not provided with a gate wiring of an adjacent pixel, a planarizing insulating layer, a protective insulating layer, and A storage capacitor may be formed by overlapping the first gate insulating layer and the second gate insulating layer therebetween.

[0205] In addition, the gate wiring, source wiring, and capacitance wiring layer are provided in multiple lines according to the pixel density. In the terminal section, a first terminal electrode having the same potential as the gate line, a source line a second terminal electrode having the same potential as the capacitance wiring layer, a third terminal electrode having the same potential as the capacitance wiring layer, etc. are arranged in a row. The number of each terminal electrode may be any number. The implementer should make the appropriate decision.

[0206] In the terminal portion, the first terminal electrode having the same potential as the gate line is formed of the same light-transmitting material as the pixel electrode layer 227. The first terminal electrode can be formed of a material having a good thermal conductivity. The contact hole is electrically connected to the gate wiring. The pin electrically connects the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The same photomask as that used for the contact holes for connecting the semiconductor substrate to the semiconductor substrate is used to form the planarizing insulating layer 204 and the protective insulating layer 205. The border layer 203, the oxide insulating layer 216, the second gate insulating layer 202b, and the first gate insulating layer 202c. Layer 202a is formed by selectively etching.

[0207] In addition, the gate electrode layer of the thin film transistor 210 of the driving circuit is provided above the oxide semiconductor layer. In this case, the thin film transistor 217 may be electrically connected to the conductive layer 217. A contact for electrically connecting the drain electrode layer of the transistor 220 and the pixel electrode layer 227. Using the same photomask as the tact hole, the planarization insulating layer 204, the protective insulating layer 203, and the oxide The gate insulating layer 216, the second gate insulating layer 202b, and the first gate insulating layer 202a are selected. A contact hole is formed by selectively etching the conductive layer through the contact hole. 217 is electrically connected to the gate electrode layer of the thin film transistor 210 of the driving circuit.

[0208] In addition, the second terminal electrode 235, which has the same potential as the source wiring 234c of the driving circuit, is connected to the pixel electrode layer 2 The source wiring 234c can be formed of the same light-transmitting material as the thin film transistor 27. The source and drain electrodes of the transistor 210 can be fabricated in the same process. Between the drain wiring 234c and the substrate, an oxide semiconductor layer 234a and a low-resistance drain region 234 The second terminal electrode 235 is a contact that reaches the source wiring 234c. The source wiring is electrically connected to the source electrode through a contact hole. The source wiring is a metal wiring. It is formed of the same material and in the same process as the source electrode layer of the thin film transistor 210, and has the same potential. .

[0209] The third terminal electrode having the same potential as the capacitance wiring layer 230 has the same light-transmitting property as the pixel electrode layer 227. In addition, the contact hole reaching the capacitance wiring layer 230 can be formed of a material having the above-mentioned properties. The contact hole 231 is electrically connected to the pixel electrode layer 227. The same photomask and process can be used to form the insulating film.

[0210] In addition, when an active matrix type liquid crystal display device is manufactured, A liquid crystal layer is provided between a substrate and a counter substrate on which a counter electrode (also called a counter electrode layer) is provided. The active matrix substrate and the opposing substrate are fixed together. A common electrode electrically connected to the electrode is provided on the active matrix substrate. A fourth terminal electrode is provided on the terminal portion for connecting the common electrode to the The fourth terminal electrode is a terminal for setting the potential, for example, GND, 0V, etc. It can be made of the same light-transmitting material as the pole layer 227 .

[0211] In addition, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 The configuration for electrically connecting the source of the thin film transistor 220 is not particularly limited. A connection electrode that connects the electrode layer and the source electrode layer of the thin film transistor 210 is formed on the pixel electrode layer 227. In addition, in the portion other than the display region, the thin film transistor 2 may be formed in the same process. The source electrode layer of the thin film transistor 20 and the source electrode layer of the thin film transistor 210 are overlapped in contact with each other. This is also fine.

[0212] The cross-sectional structure of the gate wiring layer 232 of the driving circuit is shown in FIG. Since this embodiment is an example of a small liquid crystal display panel of 10 inches or less, the gate wiring layer of the driving circuit is The gate electrode layer 232 is made of the same light-transmitting material as the gate electrode layer of the thin film transistor 220. do.

[0213] Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes If the same material is used for the layers and other wiring layers, common sputter targets and common manufacturing equipment can be used. The cost of the material and the etchant (or This reduces the cost of etching gas, resulting in reduced manufacturing costs. It is possible.

[0214] In the structure of FIG. 7A, a photosensitive resin material is used as the planarizing insulating layer 204. In this case, the step of forming a resist mask can be omitted.

[0215] FIG. 7B shows a cross-sectional structure that is partially different from that shown in FIG. Since the same as A) except that the planarization insulating layer 204 is not present, the same parts are designated by the same reference numerals. In FIG. 7B, a protective insulating layer 203 is in contact with the protective insulating layer 203. The pixel electrode layer 227, the conductive layer 217, and the second terminal electrode 235 are formed.

[0216] When the structure of FIG. 7B is used, the step of forming the planarization insulating layer 204 can be omitted.

[0217] This embodiment mode can be freely combined with other embodiment modes.

[0218] (Embodiment 6) In this embodiment, the size of the liquid crystal display panel exceeds 10 inches, and is 60 inches or even When using a 120-inch display, the wiring resistance of the light-transmitting wiring may become a problem. An example in which a part of the gate wiring is made into a metal wiring to reduce the wiring resistance will be shown.

[0219] In FIG. 8(A), the same reference numerals are used for the same parts as in FIG. 7(A), and detailed explanations of the same parts will be omitted. Omitted.

[0220] FIG. 8A shows a gate wiring of a driving circuit that is partly made of metal wiring, and a thin film transistor 210 In this example, the gate electrode layer is formed in contact with a wiring having the same light-transmitting property as the gate electrode layer. Therefore, the number of photomasks increases compared to the first embodiment.

[0221] First, a layer capable of withstanding a first heat treatment for dehydration or dehydrogenation is formed on the substrate 200. A heat-resistant conductive material film (thickness: 100 nm or more and 500 nm or less) is formed.

[0222] In this embodiment, a tungsten film with a thickness of 370 nm and a tantalum nitride film with a thickness of 50 nm are used. Here, the conductive film is a laminate of a tantalum nitride film and a tungsten film. It is not limited, and an element selected from Ta, W, Ti, Mo, Al, Cu, or the above-mentioned elements Alloys containing the above elements or alloys containing the above elements The heat-resistant conductive material film is not limited to a single layer containing the above-mentioned elements, but may be a double layer. The above stacked layers can be used.

[0223] A metal wiring is formed by a first photolithography process, and a first metal wiring layer 236 and a second The metal wiring layer 237 is formed. The tungsten film and the tantalum nitride film are etched using I CP (Inductively Coupled Plasma) It is recommended to use the etching method. The ICP etching method is used, and the etching conditions (coil type The amount of power applied to the electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc. By appropriately adjusting the thickness, the film can be etched into a desired tapered shape. The metal wiring layer 236 and the second metal wiring layer 237 are tapered to be in contact with each other. This can reduce defects in the formation of a light-transmitting conductive film.

[0224] Next, a light-transmitting conductive film is formed, and then a gate is formed by a second photolithography process. a gate wiring layer 238, a gate electrode layer of the thin film transistor 210, a gate The light-transmitting conductive film is transparent to visible light as described in Embodiment 1. A light-transmitting conductive material is used.

[0225] Depending on the material of the conductive film having light transmitting properties, for example, the gate wiring layer 238 may be a first gold At the interface with the metal wiring layer 236 or the second metal wiring layer 237, the Since an oxide film may be formed and the contact resistance may increase, the second metal wiring layer 237 is It is preferable to use a metal nitride film that prevents the metal wiring layer 236 from being oxidized.

[0226] Next, a gate insulating layer, an oxide semiconductor layer, and the like are formed in the same steps as those in the first embodiment. In this process, an active matrix substrate is manufactured according to the first embodiment.

[0227] In this embodiment, after the planarization insulating layer 204 is formed, the terminal This shows an example of selectively removing the planarizing insulating layer in the terminal area. It is preferable not to do this in order to ensure a good connection with the FPC.

[0228] In FIG. 8A, the second terminal electrode 235 is formed on the protective insulating layer 203. 8(A) shows the gate wiring layer 238 overlapping a part of the second metal wiring layer 237. As a gate wiring layer covering the entire first metal wiring layer 236 and the second metal wiring layer 237, That is, the first metal wiring layer 236 and the second metal wiring layer 237 are the gate wiring layer 23. 8 can be called an auxiliary wiring for reducing the resistance.

[0229] In the terminal section, a first terminal electrode having the same potential as the gate wiring is provided on the protective insulating layer 203. The wiring from the terminal portion is also made of metal. Formed by wiring.

[0230] In addition, the gate wiring layer and the capacitance wiring layer in the non-display area are made to have low wiring resistance. Metal wiring, that is, the first metal wiring layer 236 and the second metal wiring layer 237 are used as auxiliary wiring. It can also be used.

[0231] FIG. 8B shows a cross-sectional structure that is partially different from that shown in FIG. A) is the same as A, except that the material of the gate electrode layer of the thin film transistor in the driver circuit is different. Therefore, the same reference numerals are used for the same parts, and detailed explanations of the same parts are omitted.

[0232] FIG. 8B shows an example in which the gate electrode layer of the thin film transistor of the driver circuit is formed of a metal wiring. In the driver circuit, the material for the gate electrode layer is not limited to a light-transmitting material.

[0233] In FIG. 8B, a thin film transistor 240 of the driving circuit is formed on a first metal wiring layer 242. The second metal wiring layer 241 is stacked on the gate electrode layer. The second metal wiring layer 236 can be formed using the same material and process as the first metal wiring layer 236. The second metal wiring layer 241 is formed of the same material and in the same process as the second metal wiring layer 237. can be done.

[0234] In addition, when the first metal wiring layer 242 is electrically connected to the conductive layer 217, the first metal wiring The second metal wiring layer 241 is preferably a metal nitride film to prevent oxidation of the layer 242. .

[0235] In this embodiment, the wiring resistance is reduced by partially using metal wiring, and the size of the liquid crystal display panel is Even if the display size exceeds 10 inches and is increased to 60 inches or even 120 inches, It is possible to achieve high definition and a high aperture ratio.

[0236] This embodiment mode can be freely combined with other embodiment modes.

[0237] (Embodiment 7) In this embodiment, a configuration of a storage capacitor different from that of the fifth embodiment is shown in FIG. FIG. 9(B) shows the same as FIG. 7(A) except for the configuration of the storage capacitor. Therefore, the same parts are designated by the same reference numerals, and detailed explanations of the same parts are omitted. 1A shows the cross-sectional structure of a thin film transistor 220 and a storage capacitor disposed in a pixel.

[0238] FIG. 9(A) shows a dielectric layer including an oxide insulating layer 216, a protective insulating layer 203, and a planarizing insulating layer 20. 4, the pixel electrode layer 227 and the capacitance wiring layer 250 overlapping the pixel electrode layer 227 form a storage capacitor. The capacitance wiring layer 250 is connected to the thin film transistor 220 disposed in the pixel. Since the source electrode layer is formed of the same material and in the same process as the source electrode layer, It is laid out so as not to overlap with the source wiring layer of the resistor 220.

[0239] In the storage capacitor shown in FIG. 9A, a pair of electrodes and a dielectric material are transparent, and the entire storage capacitor The body is translucent.

[0240] FIG. 9B shows an example of a storage capacitor configuration different from that shown in FIG. 9A. Since this is the same as 7(A) except for the difference in the configuration of the storage capacitor, the same symbols are used for the same parts. Detailed explanations of the same parts will be omitted.

[0241] FIG. 9B shows a structure in which the dielectric is a first gate insulating layer 202a and a second gate insulating layer 202b. The capacitance wiring layer 230 and the oxide semiconductor layer 251 and the capacitance In this example, a storage capacitor is formed by laminating the capacitor electrode 231. The capacitor electrode 231 is an oxide semiconductor. It is laminated on the layer 251 in contact with the layer 251 and functions as one electrode of the storage capacitor. The electrode 231 has the same light-transmitting property as the source electrode layer or the drain electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is formed in the same process as the thin film transistor 2. Since the gate electrode layer 20 is formed of the same material and in the same process, the thin film transistor The layout is such that it does not overlap with the gate wiring layer of the resistor 220.

[0242] In addition, the capacitance electrode 231 is electrically connected to the pixel electrode layer 227 .

[0243] The storage capacitor shown in FIG. 9B also has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The body is translucent.

[0244] The storage capacitor shown in FIG. 9(A) and FIG. 9(B) has a light-transmitting property, and the number of gate wirings is In order to increase the resolution of displayed images, it is necessary to increase the capacity of the display even if the pixel size is reduced. It is possible to obtain a high aperture ratio.

[0245] This embodiment mode can be freely combined with other embodiment modes.

[0246] (Embodiment 8) In this embodiment, at least a part of the driver circuit and a thin film transistor to be disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0247] The thin film transistor disposed in the pixel portion is formed according to any one of the first to fourth embodiments. Since the thin film transistors shown in the first to fourth embodiments are n-channel TFTs, the driver circuit Of these, a part of the driver circuit that can be configured with n-channel TFTs is a thin-film transistor in the pixel area. It is formed on the same substrate as the resistor.

[0248] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 includes a signal line driver circuit 5303 and a signal line driver circuit 5304. is arranged extending from a signal line driver circuit 5304, and a plurality of scanning lines are arranged in a first scanning line driver circuit The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. At the intersections of the signal lines and the display elements, pixels each having a display element are arranged in a matrix. In addition, the substrate 5300 of the display device is a flexible printed circuit (FPC). A timing control circuit 5305 (controller, control I / F) is connected to the timing control circuit 5305 via a connection part such as a It is connected to the

[0249] In FIG. 14A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of external components such as drive circuits, and therefore reduces costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, and the reliability and yield can be improved.

[0250] The timing control circuit 5305 is, for example, The first scanning line driving circuit start signal (GSP1) (the start signal is a start pulse Also, the timing The control circuit 5305 controls the second scanning line driver circuit 5303 to control the second scanning line Provides the start signal (GSP2) for the driver circuit and the clock signal (GCK2) for the scanning line driver circuit. A start signal (SSP) for the signal line driver circuit is supplied to the signal line driver circuit 5304. Clock signal for the driver circuit (SCK), data for the video signal (DATA) (simply video signal Each clock signal has a period of It may be multiple clock signals with different timings, or it may be an inverted clock signal (CKB) and The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 may be supplied to the same circuit. It is possible to omit one of the line driver circuits 5302 and 5303 .

[0251] In FIG. 14B, a first scanning line driver circuit 5302 and a second scanning line driver circuit 5303 are shown. A signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. shows a structure in which the semiconductor device is formed on a separate substrate.

[0252] The thin film transistors described in Embodiments 1 to 4 are n-channel TFTs. 5(A) and 15(B) show the configuration and operation of a signal line driver circuit configured with n-channel TFTs. An example will be given below.

[0253] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 includes switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a A plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) are provided. The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example will be explained.

[0254] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are respectively connected to the wiring 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0255] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , or high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in sequence.

[0256] The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have a function of controlling whether or not potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k The thin film transistor 56 has a function of supplying the potential to the signal lines S1 to Sk. Each of 03_1 to 5603_k has a function as a switch.

[0257] In addition, the wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal that

[0258] Next, the operation of the signal line driver circuit of FIG. 15(A) will be described with reference to the timing chart of FIG. 15(B). FIG. 15B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. These are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is a period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0259] In the drawings of the present embodiment, the signal waveforms of the components are not rounded for clarity. Therefore, the scale may not necessarily be limited to the actual scale. It should be noted that

[0260] During the period T1 to the period TN, the shift register 5601 outputs an H-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. Since 5603_1 to 5603_k are turned on, wiring 5604_1 to 5604_k and signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to a selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, Then, the video signal data (DATA) is sent to the pixels in the selected row in order of k columns. It will be written.

[0261] As described above, video signal data (DATA) is written to the pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written more quickly. This can prevent under-crowding.

[0262] The shift register 5601 and the switching circuit 5602 may be the same as those in the first embodiment. It is possible to use circuits constituted by thin film transistors such as those shown in FIG.

[0263] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be described with reference to FIG. 16 and FIG. 17.

[0264] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal is input to the shift register. The selection signal is generated by inputting the clock (CLK) and start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scan line. The gate electrodes of the transistors of the pixels for one line are connected to the scanning line. Since the transistors of the pixels in one line must be turned on simultaneously, The capacitor used is capable of carrying a large current.

[0265] The shift register includes a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 16(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is output from a third wiring 13, and a fourth clock signal CK4 is output from a fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the previous stage (called the previous stage signal OUT(n-1)) is input. Also, the first pulse output A signal is input to the circuit 10_1 from a third pulse output circuit 10_3 which is two stages later. Similarly, in the n-th pulse output circuit 10_n in the second or subsequent stage, the (n+2)-th pulse A signal from the output circuit 10_(n+2) (called the next stage signal OUT(n+2)) is input. Therefore, the pulse output circuit of each stage outputs a pulse to the pulse output circuit of the following stage and / or the preceding stage. A first output signal (OUT(1)(SR) to OUT(N)(SR)) for inputting another The second output signals (OUT(1) to OUT(N)) are outputted to be inputted to a circuit or the like. As shown in FIG. 16A, the last two stages of the shift register are connected to the rear stage signal OUT Since (n+2) is not input, for example, the second start pulse SP2 and the third The start pulse SP3 may be input to each of the first and second inputs.

[0266] The clock signal (CK) goes between H and L levels (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are The fourth clock signal (CK4) is delayed by 1 / 4 cycle in sequence. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is GCK depending on the input drive circuit. It is sometimes called SCK, but here we will use the term CK for explanation.

[0267] FIG. 16B shows one of the pulse output circuits 10_N shown in FIG. 16A. The terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to the fourth wiring 14. For example, in FIG. 16(A), the first pulse The first input terminal 21 of the output circuit 10_1 is electrically connected to the first wiring 11, and the second The input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. The second pulse output circuit 10_2 is electrically connected to a first input terminal The second input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The third input terminal 23 is electrically connected to the fourth wiring 14 .

[0268] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 16(B)). In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 22, a second clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the second input terminal 24. A third clock signal CK3 is input to the input terminal 23 of the second clock CLK1, and a start signal CK4 is input to the fourth input terminal 24 of the third clock CLK2. A pulse is input, the next stage signal OUT(3) is input to the fifth input terminal 25, and the first output A first output signal OUT(1)(SR) is output from a terminal 26, and a second output signal OUT(1)(SR) is output from a second output terminal 27. The second output signal OUT(1) is output.

[0269] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are each a three-terminal thin-film transistor. In addition to TFTs (also called Thin Film Transistors), The four-terminal thin film transistor described in the above embodiment can be used. In the document, when a thin film transistor has two gate electrodes via a semiconductor layer, The gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is called the upper gate electrode. It is also called the gate electrode.

[0270] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor in which an oxide semiconductor is used for a semiconductor layer including a channel formation region, A configuration capable of controlling the threshold voltage is preferable. The threshold voltage is determined by gate insulating films provided above and below the channel formation region of a thin-film transistor. By providing a gate electrode and controlling the potential of the upper and / or lower gate electrodes, a desired The value can be controlled.

[0271] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. This is explained in (C).

[0272] The pulse output circuit shown in FIG. 16C includes a first transistor 31 to a thirteenth transistor 16(D)). In addition, the first input terminal 21 to the fifth input terminal In addition to the input terminal 25, the first output terminal 26, and the second output terminal 27, a first high power supply potential V A power supply line 51 to which a second high power supply potential VCC is supplied, a power supply line 52 to which a low power supply potential DD is supplied, The first transistor 31 to the thirteenth transistor are connected to a power supply line 53 to which a potential VSS is supplied. A signal or a power supply potential is supplied to the power supply 43. The magnitude relationship of the power supply potentials is such that the first power supply potential VDD is equal to or higher than the second power supply potential VCC, and the third power supply potential VDD is equal to or higher than the second power supply potential VCC. The second power supply potential VCC is set to a potential higher than the third power supply potential VSS. The fourth clock signal (CK1) through the fourth clock signal (CK4) go between H and L levels at regular intervals. It is a signal that repeats this cycle, with VDD when it is at H level and VSS when it is at L level. By setting the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, The potential applied to the gate electrode of the transistor can be kept low without affecting the This makes it possible to reduce the shift in the threshold voltage of the transistor and suppress degradation. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 31 The sixth transistor 36 to the ninth transistor 39 are four-terminal thin film transistors. It is preferable to use the first transistor 31, the sixth transistor 36 to the ninth transistor The operation of the transistor 39 is controlled by a node to which one of the electrodes serving as the source or drain is connected. The potential of the transistor is required to be switched by a control signal of the gate electrode. This allows for a fast response to the control signal input to the gate electrode (the on-current rises sharply). ) This makes it possible to reduce malfunctions in the pulse output circuit. Therefore, the threshold voltage can be controlled by using a four-terminal thin-film transistor. This makes it possible to provide a pulse output circuit that can further reduce malfunctions.

[0273] In FIG. 16C, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; (the lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal a gate electrode electrically connected to the first terminal of the ninth transistor 39 and a gate electrode electrically connected to the first terminal of the fourth transistor The third transistor 33 is electrically connected to the gate electrode of the first terminal The first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53, The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate of the second transistor 32. The electrode of the fourth transistor 34 is electrically connected to the gate electrode of the fourth transistor 34. The sixth transistor 36 has a first terminal electrically connected to the power supply line 52, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 33. The gate electrode of the transistor 34 is electrically connected to the gate electrode of the transistor 34. The seventh transistor (the gate electrode of the seventh transistor) is electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode (a lower gate electrode and an upper gate electrode) electrically connected to the second terminal of the is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrodes (the lower gate electrode and the upper gate electrode) are connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the second transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to The gate electrodes (the lower gate electrode and the upper gate electrode) are electrically connected to the power supply line 51. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 2. 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. 41 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27. The gate electrodes of the second transistor 32 and the fourth transistor The twelfth transistor 42 is electrically connected to the gate electrode of the first terminal of the transistor 34. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 5 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode The seventh transistor 37 has a gate electrode (lower gate electrode and upper gate electrode) are electrically connected.

[0274] In FIG. 16C, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 4 The connection point of the gate electrode of transistor 0 and the second terminal of transistor 939 is referred to as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is node B. Let us assume that.

[0275] FIG. 17A shows the pulse output circuit described in FIG. 16C as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and a signal input to or output from a second output terminal 27.

[0276] Specifically, a first clock signal CK1 is input to the first input terminal 21, and A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse (SP1) is input to the fourth input terminal 24, and a fifth The next stage signal OUT(3) is input to the first input terminal 25, and the first output terminal 26 outputs the first output The signal OUT(1) (SR) is output, and the second output signal OUT( 1) is output.

[0277] A thin film transistor is defined as a transistor having at least three elements including a gate, a drain, and a source. A semiconductor device has a terminal and a channel region formed in a region overlapping with the gate. By controlling the gate potential, the drain and source are connected via the channel region. The current flowing between the source and drain can be controlled by the thin film transistor. Which is the source and which is the drain depends on the transistor structure and operating conditions, etc. Therefore, the regions that function as the source and drain are In some cases, the term "source" or "drain" is not used. In such cases, for example, They may be written as terminal or second terminal.

[0278] In FIG. 16(C) and FIG. 17(A), the node A is put into a floating state, and the boot A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0279] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 17(B) corresponds to a vertical blanking period, and the period 62 corresponds to a gate selection period. do.

[0280] As shown in FIG. 17A, the ninth transistor in which the second power supply potential VCC is applied to the gate electrode By providing the transistor 39, the following can be achieved before and after the bootstrap operation: The advantages are as follows:

[0281] In the absence of the ninth transistor 39, the gate electrode of which is applied with the second power supply potential VCC, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes higher than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, between the gate and the source, between the gate and the drain In both cases, a large bias voltage is applied, which places a large stress on the transistor. Therefore, the ninth power supply potential VCC is applied to the gate electrode. By providing the transistor 39, the voltage of the node A is increased by the bootstrap operation. The potential of the second terminal of the first transistor 31 is increased, but the potential of the second terminal of the first transistor 31 is not increased. That is, by providing the ninth transistor 39, It is possible to reduce the value of the negative bias voltage applied between the gate and source of the transistor 31. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the stress-induced Deterioration of the first transistor 31 can be suppressed.

[0282] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0283] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and Because it is possible to increase the field effect mobility and reduce the degree of degradation. In addition, a transistor including an oxide semiconductor can be Compared to transistors using amorphous silicon, a high potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line. Since the number of power lines to be routed can be reduced, the circuit can be made more compact.

[0284] The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 a clock signal CK3 provided by the third input terminal 23 to the eighth transistor 38 The gate electrodes (lower gate electrode and upper gate electrode) of The supplied clock signal CK2 is applied to the gate electrode of the seventh transistor 37 (the lower gate A clock signal CK is supplied to the first input terminal 22 (the upper gate electrode and the lower gate electrode). 2. The gate electrodes (lower gate electrode and upper gate electrode) of the eighth transistor 38 The wiring is input so that the clock signal CK3 is supplied from the third input terminal 23. In this case, in the shift register shown in FIG. The seventh transistor 37 and the eighth transistor 38 are both in an on state. The seventh transistor 37 is turned off, the eighth transistor 38 is turned on, and then the seventh transistor By turning off the eighth transistor 37 and the eighth transistor 38, the second input terminal The potential at the node B decreases due to the potential at the third input terminal 22 and the potential at the third input terminal 23 decreasing. The potential of the gate electrode of the seventh transistor 37 is lowered, and the potential of the gate electrode of the eighth transistor 38 is lowered. This occurs twice due to a drop in the potential of the electrode. 17B, ​​the seventh transistor 37 and the eighth transistor The seventh transistor 37 is turned on and the eighth transistor 38 is turned on. In the off state, the seventh transistor 37 is off and the eighth transistor 38 is off. By setting the state, the potentials of the second input terminal 22 and the third input terminal 23 are decreased. The drop in the potential of the node B caused by the above is reflected by the drop in the potential of the gate electrode of the eighth transistor 38. Therefore, the gate electrode of the seventh transistor 37 A clock signal CK is input from the third input terminal 23 to the lower gate electrode and the upper gate electrode. 3 is supplied to the gate electrode of the eighth transistor 38 (the lower gate electrode and the upper gate The clock signal CK2 is supplied from the second input terminal 22 to the second electrode. is preferable because it reduces the number of fluctuations in the potential of node B and reduces noise. Because it is possible.

[0285] In this manner, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during the period, the pulse output This makes it possible to suppress malfunction of the power circuit.

[0286] (Embodiment 9) A thin film transistor is manufactured according to one embodiment of the present invention, and the thin film transistor is disposed in a pixel portion. In order to manufacture a semiconductor device (also called a display device) having a display function by using the semiconductor device in a driver circuit, In addition, a part or the whole of a driver circuit using thin film transistors can be formed on the same substrate as the pixel portion. It is possible to form the display panel on a substrate.

[0287] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. These include organic EL elements, electronic inks, etc. A display medium whose contrast changes due to an electrical effect, such as a liquid crystal display, can also be used.

[0288] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process, the element substrate, which corresponds to a form before the display element is completed, is used to transmit the current to the display element. The element substrate is provided with a means for supplying a voltage to each of the pixels of the display element. The electrode (also called pixel electrode layer) may be formed alone, or the conductive layer that becomes the pixel electrode may be formed. This may be after the conductive film is formed and before the pixel electrode is formed by etching. And all forms apply.

[0289] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0290] The appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device, will be described with reference to FIG. 10(A1) and 10(A2) show thin film transistors 4010 and 4011 and a liquid crystal display. The element 4013 is disposed between the first substrate 4001 and the second substrate 4006 by a sealant 4005. FIG. 10(B) is a plan view of the panel sealed by the above method. Equivalent to the cross-sectional view at -N.

[0291] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0292] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 10A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0293] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 10B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 An insulating layer 4041 and a protective insulating layer 4042 are provided on the thin film transistors 4010 and 4011. An edge layer 4020 and an insulating layer 4021 are provided. It has a channel protection layer 4042 .

[0294] The thin film transistors 4010 and 4011 each include the oxide semiconductor layer described in any of Embodiments 1 to 4. Thin film transistors with high reliability, including thin film transistors for driving circuits, can be used. The transistor 4011 may be the thin film transistors 460 and 499 shown in any of the embodiments 1 to 4. The thin film transistor 4010 for a pixel is a combination of thin film transistors 470 and 498. In this embodiment, thin film transistors 4010 and 401 1 is an n-channel thin film transistor.

[0295] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the gate insulating film at a position overlapping the channel formation region of the nitride semiconductor layer, In addition, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0296] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0297] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Room can be used.

[0298] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating film. and the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrodes via conductive particles disposed between the pair of substrates. The electrode layer 4031 can be electrically connected to a common potential line. It is incorporated into material 4005.

[0299] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears in a relatively narrow temperature range, so it is necessary to improve the temperature range. In order to improve the liquid crystal layer 4008, a liquid crystal composition containing 5% by weight or more of chiral agent is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. c or less, it is optically isotropic so no alignment treatment is required, and it has low viewing angle dependency.

[0300] In addition to the transmission type liquid crystal display device, the present invention can also be applied to a semi-transmission type liquid crystal display device.

[0301] In addition, in liquid crystal display devices, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and a colored layer (color In this example, the polarizing plate is placed on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to the embodiment, and the polarizing plate may be provided in the same manner. The color layer may be appropriately set depending on the material and manufacturing process conditions of the color layer. A light-shielding film that functions as a light-shielding matrix may be provided.

[0302] In addition, a protective insulating layer 4020 is formed on the thin film transistors 4010 and 4011. Here, as the protective insulating layer 4020, a silicon nitride film is formed by an RF sputtering method. Note that the protective insulating layer 4020 is formed using a material similar to that of the protective insulating layer 453 described in Embodiment 1. It may be formed by the method.

[0303] In addition, an insulating layer 4021 is formed as a planarization insulating film. The planarization insulating layer 454 may be formed of the same material and by the same method as in the first embodiment. Heat resistance of resins such as grease, polyimide, benzocyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, low dielectric constant materials (low -k materials), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass) In addition, it is possible to laminate a plurality of insulating films made of these materials. Then, the insulating layer 4021 may be formed.

[0304] In this embodiment, a plurality of thin film transistors in a pixel portion are surrounded by a nitride insulating film. A nitride insulating film may be used for the protective insulating layer 4020 and the gate insulating layer, as shown in FIG. As shown in the figure, a protective insulating layer is formed so as to surround at least the periphery of the pixel portion of the active matrix substrate. In this manufacturing process, a region where the gate insulating layer 4020 is in contact with the gate insulating layer is provided. In addition, when a semiconductor device, for example a display device, is used, the insulating layer 14 can prevent moisture from entering the semiconductor device. This prevents moisture from entering the device from the outside for a long period of time even after the device is completed. The long-term reliability of the device can be improved.

[0305] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0306] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen Printing, offset printing, etc.), doctor knife, roll coater, curtain coater, etc. The insulating layer 4021 can be baked and semi-sintered. By combining this with annealing of the conductor layer, it becomes possible to efficiently manufacture a semiconductor device.

[0307] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0308] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0309] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0310] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0311] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layer and the drain electrode layer of the thin film transistor 4011. The gate electrode layer is formed of the same conductive film.

[0312] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0313] In FIG. 10, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. The embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0314] FIG. 19 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed in this specification. 1 shows an example in which a liquid crystal display module is configured as a semiconductor device.

[0315] FIG. 19 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is necessary for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. A wiring board 2609 is connected to the wiring circuit section 2608 of the TFT board 2600, and the controller The LCD has external circuits such as a filter circuit and a power supply circuit. The layers may be laminated with a retardation plate interposed therebetween.

[0316] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid uid Crystal) mode, AFLC(AntiFerroelectric L iquid Crystal mode etc. can be used.

[0317] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0318] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0319] (Embodiment 10) An example of electronic paper will be shown as one mode of a semiconductor device.

[0320] Electronic paper that uses switching elements and elements electrically connected to drive electronic ink Electronic paper is also called an electrophoretic display. It is known to be as easy to read as paper, consumes less power than other display devices, and is thin and light. This has the advantage that it is possible to

[0321] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0322] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. No polarizers are required in the display.

[0323] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0324] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. An active matrix substrate obtained by using transistors can be used.

[0325] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0326] FIG. 18 shows an active matrix type electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in the embodiment mode 1. The thin film transistor can be fabricated in the same manner as the conventional thin film transistor, and is highly reliable, including an oxide semiconductor layer. The thin film transistors shown in any of the embodiments 2 to 4 may be used as the thin film transistor 581 in this embodiment. It can also be applied.

[0327] The electronic paper in FIG. 18 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0328] The thin film transistor 581 formed on the substrate 580 is a bottom-gate thin film transistor. The thin film transistor 581 is covered with an insulating film 583 that is in contact with the semiconductor layer. The source electrode layer or drain electrode layer is a first electrode layer 587, an insulating film 583, and an insulating layer 585. The first electrode layer 587 and the substrate 596 are in contact with each other through an opening formed in the substrate 596 and are electrically connected to each other. Between the second electrode layer 588 formed on top are black areas 590a and white areas 590b. and a spherical particle 589 having a cavity 594 therearound that is filled with liquid. The spherical particles 589 are filled with a filler 595 such as a resin. The second electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. 88 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. The common connection portion is used to connect the second electrode layer to the conductive particles disposed between the pair of substrates. 588 can be electrically connected to a common potential line.

[0329] Also, instead of the element using the twist ball, an electrophoretic element can be used. A transparent liquid is enclosed in a 1 mm diameter tube that contains positively charged white particles and negatively charged black particles. Microcapsules with a size of about 0 μm to 200 μm are used. The microcapsules placed between the first and second electrode layers are subjected to an electric field. When the light is turned on, the white particles and black particles move in opposite directions, resulting in a white or black display. A display element that applies this principle is an electrophoretic display element. The device is generally called electronic paper. Electrophoretic display elements are liquid crystal display elements. Because it has a higher reflectivity than the children, auxiliary lights are not required, and it consumes less power and is dim. The display can be recognized even in a place where the power is not supplied to the display. Even if the image is displayed, it is possible to retain the image once it has been displayed, so the device with the display function can be easily moved away from the radio wave source. The semiconductor device (also referred to simply as a display device or a semiconductor device equipped with a display device) was kept away from the Even if the image is not displayed correctly, it is possible to store the displayed image.

[0330] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0331] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0332] (Embodiment 11) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that uses electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0333] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0334] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0335] FIG. 12 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0336] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The figure shows an n-channel transistor that uses an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0337] The pixel 6400 includes a switching transistor 6401 and a light-emitting element driving transistor 6 The transistor 402 has a light emitting element 6404 and a capacitor element 6403. The gate of the gate electrode of the gate electrode 6401 is connected to the scanning line 6406, and the first electrode (the source electrode and the drain electrode) One of the electrodes) is connected to a signal line 6405, and the second electrode (the source electrode and the drain electrode) is connected to a signal line 6405. The other end of the transistor 6402 is connected to the gate of the light-emitting element driving transistor 6402. The transistor 6402 has a gate connected to a power supply line 6407 via a capacitor element 6403. The first electrode is connected to a power line 6407, and the second electrode is the first electrode (pixel The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0338] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0339] The capacitor 6403 is substituted for the gate capacitance of the light-emitting element driving transistor 6402. It is possible to omit it. Regarding the gate capacitance of the light-emitting element driving transistor 6402 A capacitance may be formed between the channel region and the gate electrode.

[0340] In the case of a voltage input voltage driving method, the gate of the light emitting element driving transistor 6402 In the test, the light emitting element driving transistor 6402 is either fully turned on or fully turned off. In other words, the light emitting element driving transistor 6402 is inputted with a video signal that is in the state of The light emitting element driving transistor 6402 is operated in the linear region. Therefore, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the light emitting element driving transistor 6402. The signal line 6405 is connected to the power supply line voltage + transistor for driving the light emitting element. Apply a voltage equal to or higher than the Vth of 6402.

[0341] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 12 can be used.

[0342] When analog gradation driving is performed, a light emitting element is connected to the gate of the light emitting element driving transistor 6402. Apply the forward voltage of 6404 + a voltage equal to or higher than the Vth of the light emitting element driving transistor 6402 The forward voltage of the light emitting element 6404 refers to a voltage for achieving a desired luminance. At least it is larger than the forward threshold voltage. By inputting a video signal that operates in the saturation region, a current flows through the light emitting element 6404. In order to operate the light emitting element driving transistor 6402 in a saturation region, The potential of the power source line 6407 is set higher than the gate potential of the light emitting element driving transistor 6402. By converting the video signal into an analog signal, a current corresponding to the video signal is supplied to the light emitting element 6404. It is possible to perform analog gray scale driving.

[0343] Note that the pixel configuration shown in FIG. 12 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0344] Next, the configuration of the light emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be described using an example in which FT is n-type. (C) TFTs 7001 and 7011 which are TFTs for driving light emitting elements used in the semiconductor device The thin film transistor 7021 can be manufactured in the same manner as the thin film transistor arranged in the pixel shown in the embodiment mode 1. In addition, the thin film transistor according to the embodiment 2 to 5 has high reliability and includes an oxide semiconductor layer. The thin film transistors arranged in the pixel indicated by 4 are designated as TFT7001, 7011, and 7021. It can also be applied.

[0345] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and side emission. There are light-emitting elements with a double-sided emission structure that emits light from the side of the pixel. The present invention can also be applied to optical elements.

[0346] A light emitting element having a top emission structure will be described with reference to FIG.

[0347] In FIG. 13A, a TFT 7001 for driving a light-emitting element is an n-type TFT, and a light-emitting element 700 is FIG. 13 shows a cross-sectional view of a pixel when light emitted from the cathode 7002 exits to the anode 7005 side. ) is a cathode 7003 of a light-emitting element 7002 and a TFT 7001 which is a TFT for driving the light-emitting element. are electrically connected, and a light-emitting layer 7004 and an anode 7005 are laminated in this order on a cathode 7003. The cathode 7003 may be made of any conductive film having a small work function and capable of reflecting light. Various materials can be used. For example, Ca, Al, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be composed of a single layer or may be composed of multiple layers stacked together. When it is made up of multiple layers, the cathode 7003 is provided with a layer The electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are laminated in this order. It is not necessary to provide all of these layers. The anode 7005 is made of a conductive material having a light transmitting property. For example, indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide Alternatively, a light-transmitting conductive film such as indium tin oxide to which silicon oxide is added may be used. .

[0348] In addition, a partition wall is formed between the cathode 7003 and the cathode 7008 of the adjacent pixel, covering the ends of each. The partition wall 7009 is made of polyimide, acrylic resin, polyamide, or epoxy. The partition wall 70 is formed using an organic resin film such as a resin film, an inorganic insulating film, or an organic polysiloxane. 09 is made of a photosensitive resin material, and the side of the partition wall 7009 is formed with a continuous curvature. It is preferable to form the partition wall 7009 so as to have an inclined surface. When the material is used, the step of forming a resist mask can be omitted.

[0349] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 13A, the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0350] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. The TFT 7011 is an n-type, and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013. FIG. 13B shows a cross-sectional view of a pixel in the case where a light-emitting element driving TFT 7011 and a A cathode 7013 of the light-emitting element 7012 is formed on the conductive film 7017 having a light-transmitting property and is electrically connected to the light-emitting element 7012. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. In addition, when the anode 7015 has a light-transmitting property, a light reflecting or blocking layer is provided so as to cover the anode. A shielding film 7016 for shielding the cathode 7013 may be formed. As in the case of the first embodiment, various conductive materials having a small work function can be used. However, the thickness of the film is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm can be used as the cathode 7013. The light-emitting layer 7014 may be composed of a single layer as in FIG. 13(A) or may be composed of multiple layers. The anode 7015 is a light-transmitting layer. Although not necessary, the insulating film 11 may be formed using a light-transmitting conductive material as in FIG. 13(A). The shielding film 7016 can be made of, for example, a metal that reflects light. The material is not limited to a metal film, and for example, a resin to which a black pigment is added may be used.

[0351] In addition, between the conductive film 7017 and the conductive film 7018 of the adjacent pixel, A partition 7019 is provided. The partition 7019 is made of polyimide, acrylic resin, polyamide, epoxy, etc. The partition wall is formed by using an organic resin film such as an alkoxy resin, an inorganic insulating film, or an organic polysiloxane. The partition wall 7019 is made of a photosensitive resin material, and the side of the partition wall 7019 has a continuous curvature. It is preferable to form the partition wall 7019 so that the partition wall 7019 has an inclined surface. When a resin material is used, the step of forming a resist mask can be omitted.

[0352] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 13B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0353] Next, a light emitting element having a dual emission structure will be described with reference to FIG. In the example, a light-transmitting conductive film 702 electrically connected to a light-emitting element driving TFT 7021 is A cathode 7023 of a light-emitting element 7022 is formed on the substrate 701, and a light-emitting layer 7023 is formed on the cathode 7023. 13(A) and an anode 7025 are laminated in this order. Similarly, various conductive materials with small work functions can be used. The thickness of the cathode 702 is set to a level that allows light to pass through. For example, an Al film having a thickness of 20 nm is used as the cathode 702. 3. The light-emitting layer 7024 can be formed of a single It may be configured as a layer or as a laminate of a plurality of layers. The anode 7025 is made of a light-transmitting conductive material, similar to that of FIG. It can be formed by:

[0354] In addition, between the conductive film 7027 and the conductive film 7028 of the adjacent pixel, A partition 7029 is provided. The partition 7029 is made of polyimide, acrylic resin, polyamide, or epoxy. The partition wall is formed by using an organic resin film such as an alkoxy resin, an inorganic insulating film, or an organic polysiloxane. 7029 is made of a photosensitive resin material, and the side of the partition 7029 has a continuous curvature. It is preferable to form the partition wall 7029 so that the partition wall 7029 has an inclined surface. When a resin material is used, the step of forming a resist mask can be omitted.

[0355] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 13C, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0356] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0357] In addition, a thin film transistor (a TFT for driving a light-emitting element) that controls the driving of the light-emitting element and a light-emitting element In the above example, the light-emitting element driving TFT and the light-emitting element are electrically connected. A control TFT may be connected.

[0358] The semiconductor device is not limited to the configuration shown in FIG. 13, and may be any of the configurations disclosed in this specification. Various modifications based on the technical concept are possible.

[0359] Next, the appearance and structure of a light-emitting display panel (also called a light-emitting panel) which corresponds to one embodiment of a semiconductor device will be described. The cross section will be described with reference to FIG. 11. FIG. 11(A) shows a thin film formed on a first substrate. A panel in which the film transistor and the light emitting element are sealed between the second substrate and the film transistor and the light emitting element by a sealant. 11(B) is a plan view of the above-mentioned embodiment, and FIG. 11(B) is a cross-sectional view taken along line HI of FIG. 11(A).

[0360] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0361] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 11B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0362] The thin film transistors 4509 and 4510 each include the oxide semiconductor layer described in any of Embodiments 1 to 4. A highly reliable thin film transistor including a thin film transistor arranged in a driving circuit can be applied. The transistor 4509 can be the thin film transistor 460 described in any of Embodiments 1 to 4. 499, as a thin film transistor 4510 arranged in a pixel, a thin film transistor 470 , 498 can be used in combination. 4509 and 4510 are n-channel thin film transistors.

[0363] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping with the channel forming region. By providing the MOSFET in a position overlapping the channel formation region of the semiconductor layer, It is possible to reduce the amount of change in the threshold voltage of the thin film transistor 4509. The potential of the gate electrode layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or may be different. The conductive layer 4 may be formed of a conductive material and may function as a second gate electrode layer. The potential of 540 may be GND, 0V, or may be in a floating state.

[0364] In addition, an insulating layer 4543 is formed over the thin film transistors 4509 and 4510 . Here, a silicon nitride film is formed as the insulating layer 4543 by an RF sputtering method. The insulating layer 4543 is formed using a material and a method similar to those of the protective insulating layer 453 described in Embodiment 1. This is also fine.

[0365] In addition, an insulating layer 4544 is formed as a planarization insulating film. The planarization insulating layer 454 may be formed using a material and a method similar to those of the planarization insulating layer 454 described in Mode 1. Acrylic is used as the insulating layer 4544 .

[0366] In this embodiment, a plurality of thin film transistors in a pixel portion are surrounded by a nitride insulating film. The insulating layer 4543 and the gate insulating layer may be formed using a nitride insulating film as shown in FIG. In order to achieve this, an insulating layer 4543 is provided so as to surround at least the periphery of the pixel portion of the active matrix substrate. In this manufacturing process, the external In addition, when the semiconductor device is used as a display device, for example, Even after the design is completed, it can prevent moisture from entering from the outside for a long period of time, ensuring long-term reliability of the device. This can improve reliability.

[0367] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured as a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown in the figure. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0368] The partition 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0369] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0370] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon oxynitride film, DLC film, etc. can be formed.

[0371] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0372] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed of a source electrode layer and The drain electrode layer is formed from the same conductive film as the drain electrode layer.

[0373] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0374] The second substrate is not transparent to light, and is located in the direction of light extraction from the light emitting element 4511. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0375] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of resin or thermosetting resin, and is suitable for PVC (polyvinyl chloride), acrylic resin, etc. Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (copolymer of ethylene and vinyl acetate) can be used. Nitrogen may be used as the material.

[0376] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0377] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0378] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0379] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0380] (Embodiment 12) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, train rides, etc. It can be used for in-car advertising, display on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 20.

[0381] FIG. 20 shows an electronic book 2700. For example, the electronic book 2700 includes a housing 2701. The housing 2701 and the housing 2703 are The opening and closing operations are performed by using the shaft portion 2711 as an axis. With this configuration, it becomes possible to operate like a paper book.

[0382] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 20) and An image can be displayed on the display unit 2707 in FIG.

[0383] FIG. 20 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a touch panel, a touch screen, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. This is also fine.

[0384] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0385] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0386] (Embodiment 13) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), (c) Portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Some examples include:

[0387] FIG. 21A shows a television device 9600. The television device 9600 includes A display portion 9603 is incorporated in the housing 9601. In addition, in this example, the housing 9601 is supported by a stand 9605. This shows the configuration.

[0388] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0389] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0390] FIG. 21B shows a digital photo frame 9700. The display frame 9700 includes a display unit 9703 built into a housing 9701. 03 is capable of displaying various images, such as images taken with a digital camera. By displaying image data, it can function like a normal photo frame.

[0391] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have one as it improves the design. For example, the Digital Photo Frame 9700 Insert a memory that stores image data taken with a digital camera into the recording medium insertion section of the Image data can be captured and the captured image data can be displayed on the display unit 9703. do.

[0392] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0393] FIG. 22(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 22(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and may be at least as described in the present specification. The present invention is not limited to the above, and may be applied to any configuration having the semiconductor device disclosed in the above and other auxiliary equipment. The portable game machine shown in FIG. 22(A) can be used to play a game recorded on a recording medium. The function of reading out the program or data and displaying it on the display unit, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 22(A) has the following functions: The functions are not limited to these, and various functions can be provided.

[0394] FIG. 22(B) shows a slot machine 9900, which is a large-scale gaming machine. The slot machine 9900 includes a display unit 9903 built into a housing 9901. The 9900 also has other controls such as a start lever and stop switch, and a coin slot. , speakers, etc. Of course, the configuration of the slot machine 9900 is the same as that described above. There is no limitation, and any configuration including at least the semiconductor device disclosed in this specification may be used. Other auxiliary equipment may be provided as appropriate.

[0395] FIG. 23A is a perspective view showing an example of a portable computer.

[0396] The portable computer of FIG. 23(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display unit 9303 and a keyboard. The lower housing 9302 having the base 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to type on the keyboard, the hinge unit needs to be opened. The user can perform input operations by looking at the display portion 9303.

[0397] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the touch panel. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the USB communication standard is inserted. There are.

[0398] The upper housing 9301 further includes a display unit 93 that can be slid and stored inside the upper housing 9301. 07, it is possible to realize a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display unit.

[0399] The display unit 9303 or the foldable display unit 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses an image display device such as a light-emitting display panel using inorganic light-emitting elements.

[0400] The portable computer shown in FIG. 23A is configured with a receiver and the like, and is also a television. It is possible to receive broadcasts and display images on the display unit or the display unit. The hinge unit connecting the display unit 9301 and the lower housing 9302 is closed. 7. Slide the screen to expose the entire screen, and adjust the screen angle to watch TV broadcasts. In this case, the hinge unit can be opened to display the display unit 9303. Furthermore, it only activates the circuits that display TV broadcasts, so it consumes minimal power. This is useful for portable computers with limited battery capacity. do.

[0401] FIG. 23(B) shows a portable electronic device that can be worn on the user's arm like a wristwatch. FIG. 13 is a perspective view showing an example of a story.

[0402] This mobile phone is a main body having at least a communication device having a telephone function and a battery. A band part 9204 for attaching the body to the arm, and a fastening state of the band part 9204 to the arm are adjusted. The device is made up of an adjustment unit 9205 for adjusting the temperature, a display unit 9201, a speaker 9207, and a microphone 9208. It has been made.

[0403] The main body also has an operation switch 9203, which serves as a power input switch and a display switching switch. In addition to the camera switch and the camera start switch, there are also other buttons, such as a button that starts an Internet program. Each function can be associated with a specific function, such as being started.

[0404] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the mobile phone. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 23(B) shows a display button 9202 displayed on a display unit 9201. Input can be made by touching the screen with a finger or other object.

[0405] The main body also includes an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. The camera unit 9206 has a step. Note that the camera unit does not necessarily have to be provided.

[0406] The mobile phone shown in FIG. 23(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in memory, etc. It is possible to record television broadcasts in memory by using a storage device. The mobile phone shown in B) may have a function capable of collecting location information such as GPS.

[0407] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in FIG. 23(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force actuable panel.

[0408] Although FIG. 23B illustrates an electronic device that is worn on the arm, the electronic device is not limited to this. It is sufficient that the device has a shape that can be carried around.

[0409] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0410] (Embodiment 14) In this embodiment mode, the thin film transistor shown in any one of Embodiments 1 to 4 is used as one mode of a semiconductor device. An example of a display device having a star will be described with reference to FIGS. An example of a liquid crystal display device using a liquid crystal element as an element will be described with reference to FIGS. The TFTs 628 and 629 used in the liquid crystal display devices of FIGS. The thin film transistor shown in FIG. 4 can be applied to the thin film transistor shown in FIG. The TFT628 is a thin-film transistor with excellent electrical characteristics and high reliability that can be fabricated easily. The TFT 629 has a channel protection layer 611, and the TFT 629 has an oxide semiconductor The layer is an inverted staggered thin-film transistor having a channel formation region.

[0411] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. VA type is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. In a liquid crystal display device, when no voltage is applied, the liquid crystal molecules are oriented vertically to the panel surface. In this embodiment, a pixel is divided into several regions (sub-pixels). The liquid crystal molecules are tilted in a different direction in each cell. In the following explanation, multi-domain design is considered. A liquid crystal display device in which this has been considered will now be described.

[0412] 25 and 26 show a pixel electrode and a counter electrode, respectively. FIG. 2 is a plan view of the substrate side on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. FIG. 24 shows the structure. FIG. 26 shows a plan view of the substrate on which the counter electrode is formed. The following description will be given with reference to these figures.

[0413] FIG. 24 shows a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode layer 640 and the like are formed is laminated on the counter substrate 601. 4 shows the state in which liquid crystal has been injected.

[0414] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. On the pixel electrode layer 624, an alignment film 648 is formed. An alignment film 646 is also formed on the counter electrode layer 640 and the protrusions 644. A liquid crystal layer 650 is formed between opposing substrates 601 .

[0415] On the substrate 600, a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 6 The pixel electrode layer 624 includes a TFT 628, a wiring 616, and a storage capacitor 630. The insulating film 620 covering the insulating film 30 and the insulating film 622 covering the insulating film 620 are penetrated by contacts. The TFT 628 is connected to the wiring 618 through a hole 623. The storage capacitor 630 may be a thin-film transistor. The first capacitance wiring 604 formed at the same time as the gate wiring 602, the gate insulating film 606, and the wiring It is composed of a second capacitance wiring 617 formed at the same time as the lines 616 and 618 .

[0416] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been made.

[0417] 25 shows a planar structure on a substrate 600. The pixel electrode layer 624 is made of the material shown in the first embodiment. The pixel electrode layer 624 is formed using a slit 625. The slit 625 is formed by This is to control the crystal orientation.

[0418] The TFT 629 and the pixel electrode layer 626 and the storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode layer 624, and the storage capacitor portion 630 can be formed in the same manner. Both the TFT 628 and the TFT 629 are connected to the wiring 616. The pixel of the panel is composed of pixel electrode layer 624 and pixel electrode layer 626. The pixel electrode layer 624 and the pixel electrode layer 626 are sub-pixels.

[0419] 26 shows a planar structure of the opposing substrate side. An opposing electrode layer 640 is formed on a light-shielding film 632. The counter electrode layer 640 is preferably formed using the same material as the pixel electrode layer 624. On the counter electrode layer 640, protrusions 644 are formed to control the alignment of the liquid crystal.

[0420] The equivalent circuit of this pixel structure is shown in Figure 27. TFT628 and TFT629 both have gate The line 602 is connected to the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected to each other. By making the positions different, the operations of the liquid crystal elements 651 and 652 can be made different. That is, the potentials of the capacitance wiring 604 and the capacitance wiring 605 are individually controlled. The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0421] When a voltage is applied to the pixel electrode layer 624 having the slit 625, The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (diagonal electric field). By arranging the 644 in an alternating pattern, a diagonal electric field is effectively generated, and the liquid crystal By controlling the orientation, the direction in which the liquid crystal is oriented can be made to differ depending on the location. The viewing angle of the LCD panel is expanded by creating a multi-domain structure.

[0422] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 28 to 31. do.

[0423] 28 and 29 show the pixel structure of a VA type liquid crystal display panel. FIG. 28 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The following description will refer to both figures.

[0424] In this pixel structure, one pixel has multiple pixel electrodes, each of which is connected to a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independent. The control circuit has a configuration in which the

[0425] The pixel electrode layer 624 is formed by contact holes penetrating the insulating film 620 and the insulating film 622. In the filter 623, the wiring 618 is connected to the TFT 628. In the contact hole 627 penetrating the insulating film 620 and the insulating film 622, , and a wiring 619 is connected to the TFT 629. The gate wiring 603 of T629 is separated so that different gate signals can be applied. On the other hand, the wiring 616 functioning as a data line is connected to the TFT 628 and the TFT 629. The TFT 628 and the TFT 629 are the thin film transistors shown in the first to fourth embodiments. A transistor can be used as appropriate. In addition, a capacitance wiring 690 is provided. A gate insulating film 606 is formed on the gate wiring 602, the gate wiring 603 and the capacitance wiring 690. It has been made.

[0426] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes. A pixel electrode layer 626 is formed so as to surround the outside of the pixel electrode layer 624. The timing of applying a voltage to the electrode layer 626 is different for the TFTs 628 and 629. The alignment of the liquid crystal is controlled by adjusting the pixel structure. The equivalent circuit of this pixel structure is shown in Figure 31. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is connected to the gate wiring 603. In addition, both the TFT 628 and the TFT 629 are connected to the wiring 616. By applying different gate signals to the gate wiring 602 and the gate wiring 603, the liquid crystal element 651 and the liquid crystal element In other words, the operation of the TFT 628 and the operation of the TFT 629 can be different. By controlling the operation of the liquid crystals individually, the alignment of the liquid crystals in the liquid crystal elements 651 and 652 can be precisely adjusted. It can be controlled to widen the viewing angle.

[0427] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 30 shows the planar structure of the opposing substrate side. The opposing electrode layer 640 is shared between different pixels. The electrode is connected to the substrate, and has a slit 641 formed therein. The element electrode layer 624 and the slits 625 on the pixel electrode layer 626 side are arranged so as to interdigitate with each other. By doing so, it is possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. This allows the orientation direction of the liquid crystal to vary depending on the location, thereby widening the viewing angle.

[0428] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626. An alignment film 646 is also formed on the layer 640. The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are formed. The pixel electrode layer 626 and the liquid crystal layer 627 are overlapped to form a first liquid crystal element. The layer 650 and the counter electrode layer 640 overlap each other to form a second liquid crystal element. The pixel structure of the display panel shown in FIG. 28 to FIG. 31 has a first liquid crystal element and a second liquid crystal element in one pixel. It has a multi-domain structure with multiple subdomains.

[0429] Next, we will explain the in-plane switching type liquid crystal display device. In the in-plane switching type, This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be expanded to approximately 180 degrees. A liquid crystal display device to be used will be described.

[0430] FIG. 32 shows a structure in which an electrode layer 607, a TFT 628, and a pixel electrode layer 624 connected to the TFT 628 are formed. The substrate 600 and the opposing substrate 601 are overlapped and liquid crystal is injected. A colored film 636, a flattening film 637, etc. are formed on the counter substrate 601. No counter electrode layer is provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between them via an alignment film 646 and an alignment film 648 .

[0431] On the substrate 600, an electrode layer 607, a capacitance wiring 604 connected to the electrode layer 607, and a T The capacitance wiring 604 is formed at the same time as the gate wiring 602 of the TFT 628. The TFT 628 can be formed using the thin film transistor shown in any one of the first to fifth embodiments. The electrode layer 607 can be formed by using the pixel electrode layer 4 shown in any of the first to fourth embodiments. The electrode layer 607 can be made of the same material as that of the pixel electrode 27. A gate insulating film 606 is formed on the electrode layer 607 and the capacitor wiring 604. is formed.

[0432] The wiring 616 and the wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in a liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source region or drain region of the TFT 628 is connected to the source and drain regions. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0433] An insulating film 620 is formed on the wiring 616 and the wiring 618. A pixel electrode connected to the wiring 618 is formed in a contact hole 623 in the insulating film 620. The pixel electrode layer 624 is the same as the pixel electrode layer 427 shown in Embodiment 1. It is formed using the same material.

[0434] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed between the electrode layer 607 and the pixel electrode layer 624.

[0435] 33 is a plan view showing the configuration of a pixel electrode. The surface structure is shown in Figure 32. The pixel electrode layer 624 is provided with a slit 625. The liquid crystal alignment layer 625 is for controlling the alignment of the liquid crystal. In this case, the electric field is applied to the electrode layer 607 and The gate insulating layer 607 is located between the pixel electrode layer 624 and the pixel electrode layer 624. The thickness of the gate insulating film 606 is 50 to 200 nm. Since the thickness of the liquid crystal layer is about 10 μm, the thickness of the substrate 600 is substantially parallel to the substrate 600. An electric field is generated in the horizontal direction. This electric field controls the alignment of the liquid crystal. The liquid crystal molecules are rotated horizontally using an electric field in a nearly parallel direction. Since the display is horizontal even in this state, the effect of contrast on the viewing angle is minimal, and the viewing angle is wide. In addition, since the electrode layer 607 and the pixel electrode layer 624 are both light-transmitting electrodes, , the aperture ratio can be improved.

[0436] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0437] Figures 34 and 35 show the pixel structure of an IPS type liquid crystal display device. Figure 35 is a plan view. The cross-sectional structure corresponding to the section line VW shown in the figure is shown in FIG. The following description will be given with reference to these two figures.

[0438] FIG. 34 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, The opposing substrate 601 is overlapped and liquid crystal is injected. A coloring film 636, a flattening film 637, etc. are formed on the opposing substrate 601 side. No polar layer is provided. An alignment film 646 and an alignment film 647 are provided between the substrate 600 and the counter substrate 601. A liquid crystal layer 650 is formed via 48 .

[0439] A common potential line 609 and a TFT 628 are formed on the substrate 600. 9 can be formed simultaneously with the gate wiring 602 of the TFT 628. For this, the thin film transistor described in any of Embodiments 1 to 4 can be applied.

[0440] The wiring 616 and the wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in a liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source region or drain region of the TFT 628 is connected to the source and drain regions. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0441] An insulating film 620 is formed on the wiring 616 and the wiring 618. A pixel electrode connected to the wiring 618 is formed in a contact hole 623 in the insulating film 620. The pixel electrode layer 624 is formed in the same manner as the pixel electrodes shown in the first to fourth embodiments. As shown in FIG. 35, the pixel electrode layer 624 is formed of a common potential The wire 609 is formed so that a lateral electric field is generated together with the comb-shaped electrode formed at the same time. The comb-tooth portion of the electrode layer 624 alternately interdigitates with the comb-shaped electrode formed at the same time as the common potential line 609. formed to fit.

[0442] When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by this electric field. Rotate the molecules horizontally. In this case, the liquid crystal molecules are horizontal in any state, so the viewing angle This has little effect on contrast, etc., and results in a wider viewing angle.

[0443] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is provided with a gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. The capacitance electrode 615 and the pixel electrode layer 624 are formed through a contact hole 63. It is connected via 3.

[0444] Next, a configuration of a TN type liquid crystal display device will be described.

[0445] Figures 36 and 37 show the pixel structure of a TN type liquid crystal display device. Figure 37 is a plan view. The cross-sectional structure corresponding to the cutting line KL shown in the figure is shown in FIG. The following description will be given with reference to these two figures.

[0446] The pixel electrode layer 624 is connected to the TFT 628 through the wiring 618 in the contact hole 623. The wiring 616 functioning as a data line is connected to a TFT 628. Any of the TFTs described in Embodiments 1 to 4 can be used as the TFT 628 .

[0447] The pixel electrode layer 624 is formed using a structure similar to that of the pixel electrodes described in any of the first to fourth embodiments. The wiring 604 can be formed simultaneously with the gate wiring 602 of the TFT 628. A gate insulating film 606 is formed on the gate wiring 602 and the capacitance wiring 604. The capacitance is formed between the capacitance wiring 604 and the capacitance electrode 615 via the gate insulating film 606. The capacitance electrode 615 and the pixel electrode layer 624 are connected via a contact hole 633. .

[0448] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. The liquid crystal layer 650 is provided between the pixel electrode layer 624 and the counter electrode layer 640 with an alignment film 648 and an alignment layer 649. It is formed through a membrane 646 .

[0449] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been made.

[0450] The colored film 636 may be formed on the substrate 600 side. A polarizing plate is attached to the surface opposite to the surface on which the transistors are formed, and a counter substrate 601 A polarizing plate is attached to the surface opposite to the surface on which the counter electrode layer 640 is formed.

[0451] Through the above steps, a liquid crystal display device can be manufactured as a display device. The liquid crystal display device has a high aperture ratio.

[0452] (Embodiment 15) In this embodiment, an example in which an oxide semiconductor layer is surrounded by a nitride insulating film as viewed from a cross section is shown in FIG. FIG. 38 is different from FIG. 1 in the top shape and end position of the oxide insulating layer 466. Since the two are the same except for the difference in the configuration of the edge layer, the same reference numerals are used for the same parts, and the same parts are Detailed explanation will be omitted.

[0453] The thin film transistor 460 arranged in the driving circuit is a channel-etch type thin film transistor. On a substrate 450 having an insulating surface, a gate electrode layer 461 and a gate electrode made of a nitride insulating film are formed. The gate insulating layer 402, at least the channel forming region 463, the first high resistance drain region 46 4a, and the oxide semiconductor layer 462 having the second high-resistance drain region 464b. Resistive drain region 408a, second low-resistive drain region 408b, source electrode layer 465a The thin film transistor 460 is also covered with a drain electrode layer 465b. An oxide insulating layer 466 is provided in contact with the formation region 463 .

[0454] The oxide insulating layer 466 is a channel protection layer 47 of a thin film transistor 470 disposed in the pixel. 6 is formed by a photolithography process, the outer gate insulating film of the thin film transistor 460 is The oxide insulating layer 466 is processed so that the layer 402 is exposed. The upper surface shape of the insulating layer 460 is wider than the upper surface shape of the organic semiconductor layer 460 and covers the thin film transistor 460. preferable.

[0455] A protective insulating layer made of a nitride insulating film is further formed so as to cover the upper surface and side surfaces of the oxide insulating layer 466. Form 453.

[0456] In the thin film transistor 460, the first low-resistance drain region 408a is in contact with the lower surface of the first low-resistance drain region 408a. The first high-resistance drain region 464a is formed in a self-aligned manner. A second high-resistance drain region 464b is formed in a self-aligned manner in contact with the lower surface of the drain region 408b. The channel formation region 463 is in contact with the oxide insulating layer 466 and has a thickness of is thinner than the first high-resistance drain region 464a and the second high-resistance drain region 464b. The first high-resistance drain region 464a and the second high-resistance drain region 464b are The region is a region of higher resistance than the region of the junction (type I region).

[0457] In addition, the channel formation region 463, the first high-resistance drain region 464a, and the second high-resistance A gate insulating layer 402 made of a nitride insulating film is formed in contact with the lower surface of the drain region 464b. It is being done.

[0458] The protective insulating layer 453 made of a nitride insulating film is a silicon nitride film obtained by a sputtering method, an oxynitride film, or the like. Moisture, hydrogen ions, and O H - The inorganic insulating film does not contain impurities such as fluorine and blocks them from entering from the outside. Use.

[0459] In this embodiment, the protective insulating layer 453 is formed of a nitride insulating film. A silicon nitride film with a thickness of 100 nm is formed on the front and side surfaces by RF sputtering. In addition, the protective insulating layer 453 is in contact with the gate insulating layer 402 made of a nitride insulating film. do.

[0460] By forming the structure shown in FIG. 38, the manufacturing process after forming the protective insulating layer 453 made of a nitride insulating film In the process, it is possible to prevent moisture from entering from the outside. For example, even after the device is completed as a liquid crystal display device, it will continue to prevent moisture from entering from the outside for a long period of time. This makes it possible to improve the reliability of the device.

[0461] Similarly, the thin film transistor 470 also has a protective insulating layer 453 made of a nitride insulating film. The oxide semiconductor layer 472 is formed by an RF sputtering method so as to surround the upper surface and the side surface of the oxide semiconductor layer 472. A 100 nm silicon nitride film is used. The protective insulating layer 453 is a gate insulating film made of a nitride. The insulating layer 402 is in contact with the insulating film 403 .

[0462] In addition, in this embodiment, a configuration in which one thin film transistor is surrounded by a nitride insulating film has been shown. However, the present invention is not limited to this, and a configuration in which a plurality of thin film transistors are surrounded by a nitride insulating film may be used. A plurality of thin film transistors in the region may be surrounded by a nitride insulating film. A protective insulating layer 453 and a gate insulating layer 454 are formed around the periphery of the pixel portion of the active matrix substrate. A region in contact with the layer 402 may be provided.

[0463] This embodiment mode can be freely combined with other embodiment modes. [Explanation of symbols]

[0464] 450 Substrate 451 Gate electrode layer 453 Protective Insulation Layer 454 Planarizing insulating layer 456 Pixel electrode layer 460 Thin Film Transistor 461 Gate electrode layer 462 Oxide semiconductor layer 463 Channel Formation Region 464a High-resistance drain region 464b High-resistance drain region 465a Source electrode layer 465b Drain electrode layer 466 Oxide Insulation Layer 467 Conductive Layer 470 Thin Film Transistor 471 Gate electrode layer 472 Oxide Semiconductor Layer 473 Channel Formation Region 474a High-resistance drain region 474b High-resistance drain region 475a Source electrode layer 475b Drain electrode layer 476 Oxide insulating layer (channel protection layer) 477 Pixel electrode layer

Claims

[Claim 1] a first transistor, a second transistor having a single gate structure, a capacitor, and a pixel electrode; one of a source electrode and a drain electrode of the second transistor is electrically connected to the pixel electrode; One electrode of the capacitance element is electrically connected to the pixel electrode, a first conductive layer having a region functioning as a first gate electrode of the first transistor; a first insulating layer on the first conductive layer; a second insulating layer on the first insulating layer; a first oxide semiconductor layer having a region located above the first conductive layer and including a channel formation region of the first transistor; a second conductive layer having a region located above the first oxide semiconductor layer and functioning as a second gate electrode of the first transistor; a second oxide semiconductor layer having a region in contact with a top surface of the second insulating layer and having a channel formation region of the second transistor; a third insulating layer in contact with an upper surface of the second oxide semiconductor layer; a third conductive layer electrically connected to the second oxide semiconductor layer; a fourth insulating layer on the third conductive layer; and a fourth conductive layer located in the same layer as the first conductive layer, having a region in contact with a lower surface of the first insulating layer, and made of the same material as the first conductive layer; a fifth conductive layer located above the first insulating layer and the second insulating layer, having an area overlapping the fourth conductive layer, and having the same material as the third conductive layer; the first insulating layer and the second insulating layer have a region that functions as a dielectric of the capacitive element; the pixel electrode has an area overlapping the fourth conductive layer and the fifth conductive layer, an upper surface of the third insulating layer has a region in contact with a lower surface of the third conductive layer; the first oxide semiconductor layer and the second oxide semiconductor layer contain indium, gallium, and zinc; the third conductive layer and the fifth conductive layer each include a light-transmitting conductive film, the first insulating layer comprises silicon nitride; the second insulating layer comprises silicon oxide; the third insulating layer comprises silicon oxide; The fourth insulating layer comprises silicon nitride.

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