Ceramic Electronic Components

Abstract

To provide a ceramic electronic component capable of improving insulation reliability while suppressing fracture of an internal electrode layer.SOLUTION: A ceramic electronic component comprises a multilayer chip in which a plurality of dielectric layers containing ceramic as a main component and a plurality of internal electrode layers are laminated. The plurality of internal electrode layers contains Ni as a main component, also contains Au and includes an Au-containing layer where an Au concentration with respect to all detection elements is 5 at% or more on an interface with the dielectric layers. When a thickness of the internal electrode layer is defined as T (nm), a thickness of the Au-containing layer is defined as t (nm) and the Au concentration with respect to a total quantity of Ni and Au in the entire internal electrode layer is defined as C (at%), a relation of C≤500×t / T is established.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a ceramic electronic component. [Background technology]

[0002] As electronic devices become smaller, ceramic electronic components such as multilayer ceramic capacitors mounted on electronic devices are also required to be smaller. To increase the capacitance, which is a basic characteristic, there are three possible methods: (1) increasing the dielectric constant of the dielectric layer, (2) increasing the capacitance-specified area, or (3) making the dielectric layer thinner. When the dielectric constant and element size are fixed, a thinner dielectric layer is advantageous because it allows a higher capacitance value per layer, and by making the dielectric layers and internal electrode layers thinner, it is possible to increase the number of layers to be stacked within a given thickness. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2003-7562 A [Patent Document 2] JP 2019-176117 A Summary of the Invention [Problem to be solved by the invention]

[0004] On the other hand, if the dielectric layer is made thinner, the electric field strength applied to the dielectric layer increases even with the same operating voltage, which is disadvantageous in terms of insulation reliability.As a measure to ensure insulation reliability in a thin dielectric layer, it has been proposed to add a precious metal that has poor wettability to the dielectric layer to the ceramic raw material or internal electrode paste, and form a thin layer of the added metal between the internal electrode layer and the dielectric layer (for example, see Patent Document 1).

[0005] Furthermore, if the internal electrode layer is made thin, it becomes more susceptible to fracture during firing, resulting in wasted areas that do not contribute to capacity.As a measure to ensure the continuity of the thin internal electrodes, a structure has been proposed in which other metals are added to the internal electrode paste, and the periphery of the crystal particles of the internal electrode and common material is coated with the added metal after firing (see, for example, Patent Document 2).

[0006] However, the techniques of Patent Documents 1 and 2 involve the addition of a large amount of Au, which may accelerate fracture of the internal electrode layers.

[0007] The present invention has been made in view of the above-mentioned problems, and has an object to provide a ceramic electronic component that can improve insulation reliability while suppressing fracture of internal electrode layers. [Means for solving the problem]

[0008] The ceramic electronic component according to the present invention comprises a laminated chip in which a plurality of dielectric layers mainly composed of ceramic and a plurality of internal electrode layers are laminated, the plurality of internal electrode layers are mainly composed of Ni and also contain Au, and an Au-containing layer having an Au concentration of 5 at% or more relative to all detected elements is provided at the interface with the dielectric layer, and when the thickness of the internal electrode layer is T (nm), the thickness of the Au-containing layer is t (nm), and the Au concentration relative to the total amount of Ni and Au in the entire internal electrode layer is C (at%), the relationship C≦500×t / T is established.

[0009] In the above ceramic electronic component, the thickness t (nm) may be 1 nm or less than 1 nm.

[0010] In the ceramic electronic component, the Au-containing layer as a whole may have an Au concentration of 5 at % or more and 15 at % or less relative to all detected elements.

[0011] In the ceramic electronic component, the Ni concentration may be higher than the Au concentration in a surface portion of the dielectric layer on the side of the internal electrode layers.

[0012] In the above-mentioned ceramic electronic component, the Au concentration relative to the total amount of Ni and Au in the entire internal electrode layer may be 20 at % or less.

[0013] In the ceramic electronic component, in a region of the internal electrode layer other than the Au-containing layer, the Au concentration relative to the total amount of Ni and Au may be 0.01 at % or more and 20 at % or less.

[0014] In the ceramic electronic component described above, the plurality of dielectric layers may contain barium titanate.

[0015] In the ceramic electronic component, the internal electrode layers may have a thickness T of 10 nm or more and 1000 nm or less.

[0016] Another ceramic electronic component according to the present invention comprises a laminated chip in which a plurality of dielectric layers mainly composed of ceramic and a plurality of internal electrode layers are laminated, the plurality of internal electrode layers are mainly composed of Ni and also contain Au, and an Au-containing layer having an Au concentration of 5 at% or more with respect to all detectable elements is provided at the interface with the dielectric layer, and in the plurality of internal electrode layers, a difference between the Au concentration with respect to all detectable elements in the entire Au-containing layer and the Au concentration with respect to all detectable elements in the entire region other than the Au-containing layer is 0.5 at% or more.

[0017] In the plurality of internal electrode layers of the ceramic electronic component, a difference between an Au concentration with respect to all detectable elements in the entire Au-containing layer and an Au concentration with respect to all detectable elements in the entire region other than the Au-containing layer may be 15 at % or less.

[0018] In the plurality of internal electrode layers of the ceramic electronic component, the Au concentration relative to all detected elements in the entire region other than the Au-containing layer may be 0 at % or more and 4.5 at % or less. Effect of the Invention

[0019] According to the present invention, it is possible to improve insulation reliability while suppressing fracture of the internal electrode layers. [Brief description of the drawings]

[0020] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Diagram 2] 2 is a cross-sectional view taken along line AA in FIG. 1. [Diagram 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 4 is a diagram illustrating an example of internal electrode layers in detail. [Diagram 5] 13(a) and (b) are diagrams illustrating a method for measuring the Au concentration. [Figure 6] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 7] 1(a) and (b) are diagrams illustrating the lamination process. [Figure 8] Experimental results on the diffusion of Ni and Au into a dielectric layer. [Figure 9] 1(a) to 1(c) are diagrams for explaining the mechanism by which an Au-containing layer is formed. [Figure 10] 11 is another example of the formation of an internal electrode pattern. [Figure 11] 4 is a TEM image of the vicinity of the outermost surface of an internal electrode layer of a sample of Example 2. [Figure 12] This is an image obtained by mapping and measuring the distribution of elements in the image in FIG. [Figure 13] 13 shows the results of line analysis of the concentration of each element in the range sandwiching the interface between the Ni layer and the dielectric layer for the sample of Example 2. [Figure 14] This is the result of expanding the horizontal axis range of the plot in Figure 13 and extracting only the Au signal. [Figure 15] 1 is a Weibull plot showing the results of a HALT test. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, an embodiment will be described with reference to the drawings.

[0022] (First embodiment) FIG. 1 is a partial cross-sectional perspective view of the multilayer ceramic capacitor 100 according to the first embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a, 20b provided on any two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces in the stacking direction of the laminated chip 10. However, the external electrodes 20a, 20b are spaced apart from each other.

[0023] The laminated chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately laminated. The edges of the internal electrode layers 12 are alternately exposed to the end face on which the external electrode 20a of the laminated chip 10 is provided and the end face on which the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. As a result, the laminated ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are laminated via the internal electrode layers 12. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layers 12 are arranged on the outermost layer in the lamination direction, and the upper and lower surfaces of the laminate are covered by the cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the material of the cover layer 13 is the same as that of the dielectric layers 11 and the ceramic material.

[0024] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0025] The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaTiO3 (strontium titanate) which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≦x≦1, 0≦y≦1, 0≦z≦1), etc. can be used.

[0026] 2, a region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region that generates capacitance in the multilayer ceramic capacitor 100. Therefore, the region that generates capacitance is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0027] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b being interposed therebetween is referred to as the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a being interposed therebetween is also the end margin 15. In other words, the end margin 15 is a region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode being interposed therebetween. The end margin 15 is a region that does not generate capacitance.

[0028] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. That is, the side margins 16 are regions provided to cover the ends of the multiple internal electrode layers 12 stacked in the above-mentioned laminated structure that extend to the two side surfaces. The side margins 16 are also regions that do not generate electrical capacitance.

[0029] It is preferable to form the dielectric layers 11 thin so as to realize a small-sized, high-capacity multilayer ceramic capacitor 100. For example, the thickness of each dielectric layer 11 is 0.05 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less, or 0.2 μm or more and 1 μm or less.

[0030] However, when the dielectric layer 11 is made thinner, the electric field strength applied to the dielectric layer 11 increases even with the same operating voltage, which is disadvantageous in terms of insulation reliability. As a measure to ensure insulation reliability in a thin dielectric layer 11, it is considered to add Au, which has poor wettability with respect to the dielectric layer 11, to the dielectric material for the dielectric layer 11 or the metal conductive paste for the internal electrode layer 12, and then sinter the mixture to form a thin layer of Au at the interface between the internal electrode layer 12 and the dielectric layer 11.

[0031] Here, we consider forming an Au layer of 1 nm or more at the interface between the internal electrode layer 12 and the dielectric layer 11. Although it depends on the thickness of the internal electrode layer 12, if an Au layer of 10 nm thickness exists on the front and back of an internal electrode layer 12 of Ni with a thickness of 500 nm, the concentration (Au amount relative to the total amount of Au and Ni) of only the amount of Au on the front and back is about 4 at%. Since not all of the added Au is accumulated at the interface between the dielectric layer 11 and the internal electrode layer 12, the Au concentration in the internal electrode layer 12 becomes even larger, especially when Au is added to a metal conductive paste. On the other hand, since the melting point of an alloy of Ni and Au is lower than the melting point of Ni, for example, when the Au concentration is 4 at%, a liquid phase is generated even at 1300°C or lower. In the firing process, the internal electrode layer 12 and the dielectric layer 11 are fired together at a temperature of 1000°C to 1300°C, which causes the internal electrode layer 12 to melt during firing, or even if it does not melt, metal migration is accelerated, accelerating the breakage and spheroidization of the electrodes. If these progress, the obtainable capacity decreases, and in severe cases, the positive and negative electrodes come into contact with each other, resulting in a short circuit failure. In addition, since the precious metal Au is expensive, adding a large amount of Au will result in a significant increase in costs compared to forming the internal electrode layer 12 with Ni alone.

[0032] Therefore, the multilayer ceramic capacitor 100 according to this embodiment has a structure that can suppress breakage of the internal electrode layers, while suppressing costs and improving insulation reliability.

[0033] In this embodiment, as illustrated in FIG. 4, the internal electrode layer 12 has an Au-containing layer 17 at the interface with the dielectric layer 11, the Au concentration of which is 5 at% or more relative to all detected elements. The Au-containing layer 17 may be entirely made of Au, or may contain other elements such as Ni. The portion of the internal electrode layer 12 other than the Au-containing layer 17 is a Ni layer 18 having an Au concentration of less than 5 at% relative to all detected elements. The Au-containing layer 17 does not need to be provided on the entire interface between the internal electrode layer 12 and the dielectric layer 11, but may be provided on at least a part of the interface. However, it is preferable that the Au-containing layer 17 is provided on the entire interface between the internal electrode layer 12 and the dielectric layer 11. The Au-containing layer 17 can be defined as a collection region of sample points having an Au concentration of 5 at% or more relative to all detected elements when the element concentration of each sample point is line-analyzed along the stacking direction in a TEM image, as illustrated in FIG. 5(a). The Ni layer 18 can be defined as a collection region of sample points where the Au concentration is less than 5 at% for all detected elements when each element concentration is line-analyzed along the lamination direction. The interval between each sample point is, for example, 0.05 nm. Since there is a risk of variation in the Au concentration for all detected elements, for example, as shown by the circles in FIG. 5(b), line analysis may be performed near the interface between the dielectric layer 11 and the internal electrode layer 12 at 10 points in different directions in which the internal electrode layer 12 extends, and the average value may be used. The average value may be calculated by averaging the values ​​at the same height in the lamination direction at the 10 points.

[0034] In this embodiment, in the cross section of the internal electrode layer 12 in the lamination direction, the relationship C≦500×t / T is established when the thickness of the internal electrode layer 12 is T (nm), the thickness of the Au-containing layer 17 is t (nm), and the Au concentration relative to the total amount of Ni and Au in the entire internal electrode layer 12 is C (at%). When the Au-containing layer 17 is provided on both the upper and lower surfaces of the internal electrode layer 12, the thickness t is the thickness of one Au-containing layer 17. The thickness of the Au-containing layer 17 may be the average value of the thickness observed in a TEM image within a range of 15 nm in the direction in which the internal electrode layer 12 extends.

[0035] According to this embodiment, since the Au-containing layer 17 having a high concentration of the precious metal Au is disposed at the portion of the internal electrode layer 12 where the dielectric layer 11 contacts, the insulation reliability can be improved by the action of the interface barrier. In addition, since the relationship C≦500×t / T is established, the Au concentration in the internal electrode layer 12 can be kept low, the melting point of the Au-Ni alloy can be maintained at a predetermined temperature or higher, and damage to the internal electrode layer 12 due to firing can be reduced. As a result, the fracture of the internal electrode layer 12 can be suppressed, and the desired element characteristics can be ensured.

[0036] This also reduces the amount of expensive gold used, which can reduce product costs. Furthermore, because gold is a material with established recycling technology, it can be recycled from abundant sources, including urban mines, reducing the environmental impact of natural mines.

[0037] From the viewpoint of reducing the amount of Au in the internal electrode layer 12, it is preferable that the thickness t of the Au-containing layer 17 is small. Therefore, it is preferable to set an upper limit on the thickness t of the Au-containing layer 17. For example, the thickness t of the Au-containing layer 17 is preferably 1 nm or less, more preferably 0.8 nm or less, and further preferably 0.6 nm or less.

[0038] The Au concentration with respect to all detected elements is preferably 8 at % or more, and more preferably 10 at % or more, throughout the entire Au-containing layer 17. The Au concentration with respect to all detected elements throughout the entire Au-containing layer 17 can be determined by calculating the average value of the Au concentration with respect to all detected elements at each sample point when the element concentration is line-analyzed at each sample point along the stacking direction.

[0039] If the amount of Au in the Au-containing layer 17 is too large, problems such as a decrease in the melting point may occur. Therefore, it is preferable to set an upper limit on the Au concentration relative to all detectable elements in the Au-containing layer 17. For example, the Au concentration relative to all detectable elements in the Au-containing layer 17 is preferably 15 at% or less, more preferably 13 at% or less, and even more preferably 12 at% or less.

[0040] From the viewpoint of reducing the amount of Au used, it is preferable to set an upper limit on the Au concentration relative to the total amount of Ni and Au in the entire internal electrode layer 12. For example, in the entire internal electrode layer 12, the Au concentration relative to the total amount of Ni and Au is preferably 20 at% or less, more preferably 2 at% or less, and further preferably 1 at% or less.

[0041] From the viewpoint of reducing the amount of Au used, it is preferable to set an upper limit on the Au concentration relative to the total amount of Ni and Au in the Ni layer 18. For example, the Au concentration relative to the total amount of Ni and Au in the Ni layer 18 is preferably 20 at% or less, more preferably 1 at% or less, and even more preferably 0.5 at% or less. Note that Au is also contained in the Ni layer 18 by providing the Au-containing layer 17. For example, the Au concentration relative to the total amount of Ni and Au in the Ni layer 18 is 0.01 at% or more.

[0042] The thickness T of the internal electrode layer 12 is, for example, 10 nm or more and 1000 nm or less, 20 nm or more and 500 nm or less, or 50 nm or more and 300 nm or less.

[0043] Although details will be described later, when the dielectric layer 11 and the internal electrode layer 12 are fired, Ni and Au may diffuse into the perovskite ceramic contained in the dielectric layer 11. However, since Ni diffuses more easily than Au, the Ni concentration is higher than the Au concentration in the surface portion of the dielectric layer 11 on the internal electrode layer 12 side.

[0044] Second embodiment In the second embodiment, a difference between the Au concentration of all detected elements in the entire Au-containing layer 17 and the Au concentration of all detected elements in the entire Ni layer 18 is 0.5 at% or more.

[0045] In this embodiment, the Au-containing layer 17 having a high concentration of the precious metal Au is disposed at the portion of the internal electrode layer 12 where the dielectric layer 11 contacts, and therefore the insulation reliability can be improved by the action of the interface barrier. In addition, since the difference between the Au concentration of all the detected elements in the entire Au-containing layer 17 and the Au concentration of all the detected elements in the entire Ni layer 18 is 0.5 at% or more, the Au concentration in the internal electrode layer 12 can be kept low, the melting point of the Au-Ni alloy can be maintained at a predetermined temperature or higher, and damage to the internal electrode layer 12 due to firing can be reduced. As a result, the fracture of the internal electrode layer 12 can be suppressed, and the desired element characteristics can be ensured.

[0046] This also reduces the amount of expensive gold used, which can reduce product costs. Furthermore, because gold is a material with established recycling technology, it can be recycled from abundant sources, including urban mines, reducing the environmental impact of natural mines.

[0047] The difference between the Au concentration with respect to all detectable elements in the entire Au-containing layer 17 and the Au concentration with respect to all detectable elements in the entire Ni layer 18 is preferably 5 at % or more, and more preferably 10 at % or more.

[0048] If the amount of Au in the Au-containing layer 17 is too large, problems such as a decrease in melting point may occur. Therefore, it is preferable to set an upper limit on the difference between the Au concentration for all detectable elements in the entire Au-containing layer 17 and the Au concentration for all detectable elements in the entire Ni layer 18. For example, the difference between the Au concentration for all detectable elements in the entire Au-containing layer 17 and the Au concentration for all detectable elements in the entire Ni layer 18 is preferably 15 at% or less, more preferably 13 at% or less, and even more preferably 12 at% or less.

[0049] From the viewpoint of reducing the amount of Au used, it is preferable that the Au concentration relative to all detectable elements is small in the entire Ni layer 18. For example, the Au concentration relative to all detectable elements in the entire Ni layer 18 is preferably 0 at% or more and 4.5 at% or less, more preferably 3 at% or less, and further preferably 2 at% or less.

[0050] Next, a method for manufacturing the multilayer ceramic capacitor 100 according to the first and second embodiments will be described.

[0051] (Raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known so far as a method for synthesizing the main component ceramic of the dielectric layer 11, such as a solid-phase method, a sol-gel method, a hydrothermal method, and the like. In this embodiment, any of these methods can be adopted.

[0052] A predetermined additive compound is added to the obtained ceramic powder according to the purpose. The additive compound may be an oxide of magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm) and ytterbium (Yb)), or an oxide containing cobalt (Co), nickel, lithium (Li), boron (B), sodium (Na), potassium (K) or silicon (Si), or a glass containing cobalt, nickel, lithium, boron, sodium, potassium or silicon.

[0053] For example, a compound containing an additive compound is wet-mixed with a ceramic raw material powder, and then dried and pulverized to prepare a ceramic material. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. Through the above steps, a dielectric material is obtained.

[0054] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. The obtained slurry is used to coat a dielectric green sheet 52 having a thickness of, for example, 0.5 μm to 1.0 μm on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

[0055] Next, as illustrated in FIG. 7(a), an internal electrode pattern 53 is formed on a dielectric green sheet 52. In FIG. 7(a), as an example, four layers of internal electrode patterns 53 are formed on the dielectric green sheet 52 at a predetermined interval. The film formation method is not particularly limited, but for example, vacuum film formation such as sputtering using a Ni-Au alloy, simultaneous sputtering using individual targets, etc. can be used. Alternatively, a paste in which Au metal powder is mixed into a paste of Ni metal powder may be applied. The dielectric green sheet 52 on which the internal electrode patterns 53 are formed is defined as a lamination unit.

[0056] Next, while peeling off the dielectric green sheet 52 from the base material 51, the lamination units are laminated as shown in FIG. 7(b).

[0057] Next, a predetermined number of cover sheets (e.g., 2 to 10 layers) are laminated on the top and bottom of the laminate obtained by laminating the lamination units, and are thermocompression bonded, and then cut into a predetermined chip size (e.g., 1.0 mm x 0.5 mm). In the example of Fig. 7(b), cutting is performed along the dotted lines. The cover sheet may have the same components as the dielectric green sheet 52, or may have a different additive compound.

[0058] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in a N2 atmosphere, after which a metal paste that would become the undercoat layers of the external electrodes 20a and 20b was applied thereto by a dipping method, and the ceramic laminate was then subjected to a dipping treatment in a nitrogen atmosphere under an oxygen partial pressure of 10 -5 ~10 -8 The laminated ceramic capacitor 100 is thus obtained, and is then fired in a reducing atmosphere of 1 atm at 1100 to 1300° C. for 10 minutes to 2 hours.

[0059] (Reoxidation treatment process) After that, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0060] (Plating process) Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, Sn, etc. by plating.

[0061] According to the manufacturing method of the multilayer ceramic capacitor 100 of this embodiment, when the internal electrode pattern 53 is fired, the metal components contained therein diffuse into the ceramic having a perovskite structure contained in the dielectric layer 11. However, Au is less stable in the ceramic having a perovskite structure than Ni. Therefore, Ni tends to diffuse more easily into the dielectric layer 11 than Au, and therefore an Au-containing layer 17 is formed at the interface between the internal electrode layer 12 and the dielectric layer 11.

[0062] FIG. 8 shows the experimental results of diffusion of Ni and Au into the dielectric layer 11 when barium titanate is used as the main ceramic component of the dielectric green sheet 52 and Ni and Au are used as the metal components of the internal electrode pattern 53. In FIG. 8, the horizontal axis indicates the distance from the internal electrode layer 12. Therefore, the horizontal axis indicates the distance from the surface toward the inside of the dielectric layer 11. The vertical axis indicates the concentration relative to the amount of Ti. The atomic ratio of Ni to Au in the internal electrode pattern 53 is 96:2. From the results of FIG. 8, the amount of Au in the dielectric layer 11 is less than the ratio of Ni:Au=96:2. From these results, it can be seen that Ni is easily diffused and Au is difficult to diffuse into ceramics having a perovskite structure.

[0063] 9(a) to 9(c) are diagrams for explaining the mechanism by which the Au-containing layer 17 is formed. FIG. 9(a) is a diagram before firing. As illustrated in FIG. 9(a), before firing, neither Ni nor Au is diffused into the ceramic having a perovskite structure in the dielectric green sheet 52. FIG. 9(b) is a diagram during firing. As illustrated in FIG. 9(b), Ni close to the dielectric green sheet 52 diffuses into the ceramic, but Au is difficult to diffuse into the ceramic. As a result, Au accumulates at the atomic level at the interface between the dielectric green sheet 52 and the internal electrode pattern 53, and the Au concentration at the interface increases. It is considered that when Au is concentrated at the interface, the diffusion of Ni into the ceramic is also suppressed. FIG. 9(c) is a diagram after firing. As illustrated in FIG. 9(c), an Au-containing layer with a high Au concentration is formed at the interface between the dielectric layer 11 and the internal electrode layer 12. It is noted that Au may remain inside the internal electrode layer 12.

[0064] As described above, according to the manufacturing method of the multilayer ceramic capacitor 100 of this embodiment, the internal electrode layer 12 has the Au-containing layer 17 at the interface with the dielectric layer 11, the Au concentration of which is 5 at% or more relative to all detectable elements. By adjusting the thickness of the dielectric green sheet 52, the thickness of the internal electrode pattern 53, the ratio of Ni and Au in the internal electrode pattern 53, and the like, the relationship C≦500×t / T can be established in the multilayer ceramic capacitor 100 after firing. In addition, the difference between the Au concentration relative to all detectable elements in the entire Au-containing layer 17 and the Au concentration relative to all detectable elements in the entire Ni layer 18 can be set to 0.5 at% or more.

[0065] For example, by using sputtering when forming the internal electrode pattern 53 on the dielectric green sheet 52, it is possible to improve the uniformity of the state immediately after the film formation, and it is possible to stably form the thin Au-containing layer 17. Alternatively, by using an alloy paste with a fine particle size and a highly uniform particle size and concentration, it is possible to improve the uniformity of the state immediately after the film formation, and it is possible to stably form the thin Au-containing layer 17.

[0066] Or, when considering the sinterability of the dielectric layer 11 and the diffusion of the internal electrode layer 12, the balance between these temperature dependencies is different. That is, at a certain temperature and time, the growth of the Au-containing layer 17 can be suppressed while the sintering of the dielectric layer 11 is sufficiently advanced. On the other hand, under other firing conditions, when the sintering is sufficiently advanced, the Au-containing layer 17 grows thick. Therefore, by appropriately adjusting the firing temperature, firing time, heating rate, etc. in the firing process, the Au-containing layer 17 can be stably formed.

[0067] 10, when the internal electrode pattern 53 is formed, high-concentration portions 532 having a higher Au concentration than the Ni pattern 531 may be formed on the upper and lower surfaces of the Ni pattern 531 having a low Au concentration. The Ni pattern 531 and the high-concentration portions 532 may be formed by sputtering or paste printing. The high-concentration portions 532 may be formed only from Au.

[0068] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may be used. EXAMPLES

[0069] The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were examined.

[0070] Example 1 Additives were added to barium titanate powder, and the dielectric material was obtained by thoroughly wet mixing and grinding in a ball mill. A butyral-based organic binder, toluene and ethyl alcohol were added to the dielectric material, and a dielectric green sheet was applied to a PET substrate by the doctor blade method. An internal electrode pattern with a thickness of 200 nm was formed on the surface of the dielectric green sheet by sputtering using an Au-Ni alloy target. A mask method using a metal mask was adopted for patterning. The Au concentration in the alloy was defined as the amount of Au relative to the total amount of Au and Ni, and was set to 1.0 at%. 100 layers of the dielectric green sheet with the internal electrode patterns formed were stacked so that the internal electrode patterns were shifted alternately, cut to a specified size, and a metal conductive paste for external electrodes was applied to the two end faces where the internal electrode patterns were exposed, followed by firing to obtain a multilayer ceramic capacitor.

[0071] The thickness of each internal electrode layer was 200 nm. The thickness of the internal electrode layer was measured by observing a range of 5 μm in length with a cross-sectional SEM, and the average thickness was derived. In the internal electrode layer, an Au-containing layer with an Au concentration of 5 at% or more relative to all detected elements was formed at the interface with the dielectric layer. The thickness of the Au-containing layer was 0.8 nm. The thickness of the Au-containing layer was measured by observing a range of 15 nm in length with a cross-sectional TEM, and the average thickness was derived. 500×t / T was 2.

[0072] Example 2 In Example 2, the amount of Au in the Au-Ni alloy target was 2.0 at%. Other conditions were the same as in Example 1. In Example 2, the thickness of each internal electrode layer was 200 nm. In the internal electrode layer, an Au-containing layer with an Au concentration of 5 at% or more relative to all detected elements was formed at the interface with the dielectric layer. The thickness of the Au-containing layer was 0.8 nm. When the diffusion of Au progresses sufficiently, the diffusion stops at a certain thickness at a certain temperature, so that an Au-containing layer of the same thickness is formed regardless of the total amount of Au. 500×t / T was 2. The capacity and life of the obtained element were equivalent to those of Example 1.

[0073] Example 3 In Example 3, the Au amount in the Au-Ni alloy target was 2.0 at%. The firing temperature was higher than that in Example 1. Other conditions were the same as in Example 1. In Example 3, the thickness of each internal electrode layer was 200 nm. In the internal electrode layer, an Au-containing layer having an Au concentration of 5 at% or more relative to all detected elements was formed at the interface with the dielectric layer. The thickness of the Au-containing layer was 1.0 nm. Since the firing temperature was increased, the thickness of the Au-containing layer was larger than that of Example 2, which had the same total Au amount. 500×t / T was 2.5. The capacity of the obtained element was equivalent to Examples 1 and 2, and the load life was improved. It is considered that the interface barrier was stabilized because the thickness of the Au-containing layer was increased.

[0074] Example 4 In Example 4, the Au amount in the Au-Ni alloy target was 1.0 at%. The firing time was shorter than that of Example 1. Other conditions were the same as those of Example 1. In Example 4, the thickness of each internal electrode layer was 200 nm. In the internal electrode layer, an Au-containing layer having an Au concentration of 5 at% or more relative to all detected elements was formed at the interface with the dielectric layer. The thickness of the Au-containing layer was 0.5 nm. Since the firing time was shortened, the thickness of the Au-containing layer was smaller than that of Example 1, which had the same total Au amount. 500×t / T was 1.25. The capacity of the obtained element was equivalent to Examples 1 to 3, and the load life was slightly worse than that of Example 1. It is considered that the interface barrier became unstable because the thickness of the Au-containing layer became smaller.

[0075] Example 5 In Example 5, an Au target and a Ni target were prepared separately. In sputtering, an Au target and a Ni target were used simultaneously. The Au concentration in the internal electrode pattern was 1.0 at%. Other conditions were the same as in Example 1. In Example 5, the thickness of each internal electrode layer was 200 nm. In the internal electrode layer, an Au-containing layer having an Au concentration of 5 at% or more relative to all detected elements was formed at the interface with the dielectric layer. The thickness of the Au-containing layer was 0.8 nm. 500×t / T was 2. The capacity and load life of the obtained element were equivalent to those of Example 1.

[0076] Example 6 In Example 6, an Au target and a Ni target were prepared separately. Au → Ni → Au were deposited on a dielectric green sheet in this order, and a laminated structure was formed in which the Ni surface was covered with 1.0 nm thick Au. The Au concentration was 1.0 at% in the entire deposited internal electrode pattern. Other conditions were the same as in Example 1. In Example 6, the thickness of each internal electrode layer was 200 nm. In the internal electrode layer, an Au-containing layer with an Au concentration of 5 at% or more relative to all detected elements was formed at the interface with the dielectric layer. The thickness of the Au-containing layer was 0.8 nm. The Au layer of 1 nm at the time of deposition was diffused during firing, and was 0.8 nm at the time of finishing. 500 × t / T was 2. The capacity and load life of the obtained element were equivalent to those of Example 1.

[0077] Example 7 In Example 7, Au-Ni alloy paste was printed on a dielectric green sheet. The amount of Au in the alloy was 1.0 at%. Other conditions were the same as in Example 1. In Example 7, the thickness of each internal electrode layer was 200 nm. In the internal electrode layer, an Au-containing layer having an Au concentration of 5 at% or more relative to all detected elements was formed at the interface with the dielectric layer. The thickness of the Au-containing layer was 0.8 nm. 500×t / T was 2. The capacity and load life of the obtained element were equivalent to those of Example 1.

[0078] Comparative Example 1 In Comparative Example 1, a pure Ni target was used. Other conditions were the same as in Example 1. In Comparative Example 1, the thickness of each internal electrode layer was 200 nm. The capacitance of the obtained element was equivalent to that of Example 1, but the load life was inferior. This is thought to be because the effect of the interface barrier by the Au-containing layer does not work.

[0079] Comparative Example 2 In Comparative Example 2, the Pt amount in the Pt-Ni alloy target was 0.5 at%. Other conditions were the same as in Example 1. In Comparative Example 2, the thickness of each internal electrode layer was 200 nm. In the internal electrode layer, a Pt-containing layer was not formed at the interface with the dielectric layer. The capacity of the obtained element was equivalent to that of Example 1, but the load life was inferior. Although Pt is an element that easily creates a barrier, it is considered that the interface barrier is dominated by Ni because there is no segregation to the interface.

[0080] Comparative Example 3 In Comparative Example 3, the amount of Au in the Au-Ni alloy target was 2.5 at%. Other conditions were the same as in Example 1. In Comparative Example 3, the thickness of each internal electrode layer was 200 nm. In the internal electrode layer, an Au-containing layer with an Au concentration of 5 at% or more relative to all detected elements was formed at the interface with the dielectric layer. The thickness of the Au-containing layer was 0.8 nm. As in Example 2, since diffusion has progressed sufficiently, the thickness of the Au layer settles at a constant 0.8 nm even if the initial Au concentration is high. 500×t / T was 2. The initial characteristics of the obtained element were open. It is considered that the amount of Au added was too large, so the melting point decreased and the internal electrodes were broken. Since the initial characteristics were open, the load life could not be evaluated.

[0081] FIG. 11 is a TEM (transmission electron microscope) image of the inner electrode layer near the outermost surface of the sample of Example 2. In this image, the heavier the element or the higher the density, the stronger the brightness. As shown in FIG. 11, a region with strong brightness was confirmed at the interface between the Ni layer and the dielectric layer. It can also be seen that the crystal arrangement is well matched with the Ni base material in the region with strong brightness. It can be seen that the region with strong brightness is about three atomic layers from the interface. FIG. 12 is an image obtained by mapping and measuring the distribution of elements in the image of FIG. 11. The upper left diagram of FIG. 12 is a part of FIG. 11. The upper right diagram of FIG. 12 is the observation result for Ti. The lower left diagram of FIG. 12 is the observation result for Au. The lower right diagram of FIG. 12 is the observation result for Ni. It can be seen that the Au signal is concentrated on the outermost surface of the Ni layer, and its thickness is about 0.5 nm. From the above, it was confirmed that a 0.5 nm Au-containing layer was formed in Example 2.

[0082] FIG. 13 shows the result of line analysis of each element concentration in the range sandwiching the interface between the Ni layer and the dielectric layer for the sample of Example 2. The vertical axis shows the concentration of the element of interest relative to all detected elements at that point. Therefore, the vertical axis does not represent Au / (Au+Ni). Note that the measured concentration value of Ti is enlarged by 5 times and plotted. The measured concentration value of Au is enlarged by 10 times and plotted. As can be seen in FIG. 13, it can be seen that the Au signal shows a maximum value not directly on the interface but at a location about 0.5 nm into the Ni side from the interface. FIG. 14 shows the result of expanding the horizontal axis range of the plot in FIG. 13 and extracting only the Au signal. As can be seen in FIG. 14, in addition to the Au signal being locally large near the interface, a clear difference in the Au concentration was confirmed on both sides of the interface.

[0083] The load life of each sample of Examples 1 to 7 and Comparative Examples 1 to 3 was evaluated by performing a HALT test (accelerated life test) at 125C / 18V. FIG. 15 is a Weibull plot showing the results of the HALT test for the samples of Example 2, Comparative Example 1, and Comparative Example 2. The horizontal axis indicates the time until failure. The vertical axis indicates the cumulative failure rate. As can be seen in FIG. 15, compared with the element having an internal electrode made only of Ni, the element using Au has a larger absolute value of the life time and a steeper slope of the plot (smaller life variation). In FIG. 15, "●" indicates the result of Comparative Example 1, "×" indicates the result of Comparative Example 2, and "■" indicates the result of Example 2.

[0084] Table 1 shows the measurement results of the capacitance value and the load life for each sample of Examples 1 to 7 and Comparative Examples 1 to 3. The capacitance value was measured using an LCR meter under the conditions of a frequency of 1 kHz and an amplitude of 0.5 V. The load life was determined by applying a load of 125 C / 18 V and judging the time when the leakage current exceeded 1 mA as the failure time. [Table 1]

[0085] Example 8 Additives were added to barium titanate powder, and the material was obtained by thoroughly wet mixing and grinding in a ball mill. A butyral-based organic binder and toluene and ethyl alcohol were added to the dielectric material, and a dielectric green sheet was applied to a PET substrate using the doctor blade method. An internal electrode pattern was formed on the surface of the dielectric green sheet by sputtering using an Au-Ni alloy target. A mask method using a metal mask was used for patterning. 100 layers of the dielectric green sheet with the internal electrode patterns formed on them were stacked so that the internal electrode patterns were shifted alternately, cut to a specified size, and a metal conductive paste for the external electrodes was applied to the two end faces where the internal electrode patterns were exposed, followed by firing to obtain a multilayer ceramic capacitor.

[0086] The Au concentration in the entire Au-containing layer where the Au concentration in all detected elements was 5 at% or more was 11 at%. The Au concentration in the entire Ni layer where the Au concentration in all detected elements was less than 5 at% was 1 at%. The difference between these concentrations was 10 at%.

[0087] Example 9 In Example 9, the internal electrode pattern was also formed by sputtering using an Au-Ni alloy target. The Au concentration relative to all detected elements in the entire Au-containing layer where the Au concentration relative to all detected elements was 5 at% or more was 5.2 at%. The Au concentration relative to all detected elements in the entire Ni layer where the Au concentration relative to all detected elements was less than 5 at% was 1 at%. The difference between these concentrations was 4.2 at%. The other conditions were the same as in Example 8.

[0088] Example 10 In Example 10, the internal electrode pattern was also formed by sputtering using an Au-Ni alloy target. The Au concentration relative to all detected elements in the entire Au-containing layer where the Au concentration relative to all detected elements was 5 at% or more was 5.2 at%. The Au concentration relative to all detected elements in the entire Ni layer where the Au concentration relative to all detected elements was less than 5 at% was 4.5 at%. The difference between these concentrations was 0.7 at%. The other conditions were the same as in Example 8.

[0089] Example 11 In Example 11, the internal electrode pattern was also formed by sputtering using an Au-Ni alloy target. The Au concentration relative to all detected elements in the entire Au-containing layer where the Au concentration relative to all detected elements was 5 at% or more was 16 at%. The Au concentration relative to all detected elements in the entire Ni layer where the Au concentration relative to all detected elements was less than 5 at% was 1 at%. The difference between these concentrations was 15 at%. The other conditions were the same as in Example 8.

[0090] Example 12 In Example 12, an Au target and a Ni target were prepared separately, and an internal electrode pattern was formed by sputtering. The Au concentration relative to all detectable elements in the entire Au-containing layer where the Au concentration relative to all detectable elements was 5 at% or more was 11 at%. The Au concentration relative to all detectable elements in the entire Ni layer where the Au concentration relative to all detectable elements was less than 5 at% was 1 at%. The difference between these concentrations was 10 at%. The other conditions were the same as in Example 8.

[0091] (Example 13) In Example 13, an Au target and a Ni target were prepared separately, and an internal electrode pattern was formed by sputtering. On a dielectric green sheet, films were formed in the order of Au → Ni → Au, and a laminated structure was formed in which the Ni surface was covered with Au. The Au concentration relative to all detected elements in the entire Au-containing layer in which the Au concentration relative to all detected elements was 5 at% or more was 11 at%. The Au concentration relative to all detected elements in the entire Ni layer in which the Au concentration relative to all detected elements was less than 5 at% was 1 at%. The difference between these concentrations was 10 at%. The other conditions were the same as in Example 8.

[0092] Example 14 In Example 14, Au-Ni alloy paste was printed on a dielectric green sheet. The Au concentration relative to all detectable elements in the entire Au-containing layer where the Au concentration relative to all detectable elements was 5 at% or more was 11 at%. The Au concentration relative to all detectable elements in the entire Ni layer where the Au concentration relative to all detectable elements was less than 5 at% was 1 at%. The difference between these concentrations was 10 at%. The other conditions were the same as in Example 8.

[0093] Example 15 In Example 15, an internal electrode pattern was formed by sputtering using an Au-Ni alloy target. The Au concentration relative to all detected elements in the entire Au-containing layer where the Au concentration relative to all detected elements was 5 at% or more was 17 at%. The Au concentration relative to all detected elements in the entire Ni layer where the Au concentration relative to all detected elements was less than 5 at% was 1 at%. The difference between these concentrations was 16 at%. The other conditions were the same as in Example 8.

[0094] Comparative Example 4 In Comparative Example 4, an internal electrode pattern was formed by sputtering using an Au-Ni alloy target. In Comparative Example 4, an Au-containing layer in which the Au concentration relative to all detected elements was 5 at% or more was not formed. In the entire region in which the Au concentration relative to all detected elements was relatively high, the Au concentration relative to all detected elements was 4.9 at%. In the entire region in which the Au concentration relative to all detected elements was relatively low, the Au concentration relative to all detected elements was 4.4 at%. The difference between these concentrations was 0.5 at%. Other conditions were the same as in Example 8.

[0095] Comparative Example 5 In Comparative Example 5, an internal electrode pattern was formed by sputtering using an Au-Ni alloy target. The Au concentration relative to all detectable elements in the entire Au-containing layer where the Au concentration relative to all detectable elements was 5 at% or more was 5.2 at%. The Au concentration relative to all detectable elements in the entire Ni layer where the Au concentration relative to all detectable elements was less than 5 at% was 4.8 at%. The difference between these concentrations was 0.4 at%. The other conditions were the same as in Example 8.

[0096] Using the same method as in Examples 1 to 7 and Comparative Examples 1 to 3, the capacitance value and the load life were measured for Examples 8 to 15 and Comparative Examples 4 and 5. The results are shown in Table 2. As shown in Table 2, in Examples 8 to 15, the capacitance value and the load life were high. This is considered to be because the difference between the Au concentration relative to all detected elements in the entire Au-containing layer and the Au concentration relative to all detected elements in the entire Ni layer was 0.5 at% or more, thereby suppressing the breakage of the internal electrode layer and improving the insulation reliability. In addition, compared to Example 15, the load life was longer in Examples 8 to 14. From this result, it can be seen that it is preferable that the difference between the Au concentration relative to all detected elements in the entire Au-containing layer and the Au concentration relative to all detected elements in the entire Ni layer is 15 at% or less. [Table 2]

[0097] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0098] 10 Stacked Chip 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 Capacity area 15 End Margin 16 Side Margin 17 Au-containing layer 18 Ni layer 20a,20b external electrode 51 Base material 52 Dielectric green sheet 53 Internal electrode pattern 100 Multilayer ceramic capacitors

Claims

1. The laminated chip includes a plurality of dielectric layers mainly made of ceramic and a plurality of internal electrode layers laminated together, the plurality of internal electrode layers are mainly composed of Ni and also contain Au, and have an Au-containing layer at an interface with the dielectric layer, the Au concentration being 5 at % or more relative to all detectable elements; A ceramic electronic component, characterized in that, when the thickness of the internal electrode layer is T (nm), the thickness of the Au-containing layer is t (nm), and the Au concentration relative to the total amount of Ni and Au in the entire internal electrode layer is C (at %), the relationship C≦500×t / T is satisfied.

2. 2. The ceramic electronic component according to claim 1, wherein the thickness t (nm) is 1 nm or less than 1 nm.

3. 3. The ceramic electronic component according to claim 1, wherein the Au concentration relative to all detected elements in the entire Au-containing layer is 5 at % or more and 15 at % or less.

4. 4. The ceramic electronic component according to claim 1, wherein a Ni concentration is higher than a Au concentration in a surface portion of the dielectric layer on the side of the internal electrode layers.

5. 5. The ceramic electronic component according to claim 1, wherein the Au concentration relative to the total amount of Ni and Au in the entire internal electrode layer is 20 at % or less.

6. 6. The ceramic electronic component according to claim 1, wherein in a region of the internal electrode layer other than the Au-containing layer, the Au concentration relative to the total amount of Ni and Au is 0.01 at % or more and 20 at % or less.

7. 7. The ceramic electronic component according to claim 1, wherein the plurality of dielectric layers contain barium titanate.

8. 8. The ceramic electronic component according to claim 1, wherein a thickness T of the internal electrode layer is 10 nm or more and 1000 nm or less.

9. The laminated chip includes a plurality of dielectric layers mainly made of ceramic and a plurality of internal electrode layers laminated together, the plurality of internal electrode layers are mainly composed of Ni and also contain Au, and have an Au-containing layer at an interface with the dielectric layer, the Au concentration being 5 at % or more relative to all detectable elements; a difference between the Au concentration with respect to all detectable elements in the entire Au-containing layer and the Au concentration with respect to all detectable elements in the entire region other than the Au-containing layer in the plurality of internal electrode layers is 0.5 at % or more.

10. 10. The ceramic electronic component according to claim 9, wherein in the plurality of internal electrode layers, a difference between an Au concentration with respect to all detected elements in the entire Au-containing layer and an Au concentration with respect to all detected elements in the entire region other than the Au-containing layer is 15 at % or less.

11. 11. The ceramic electronic component according to claim 9, wherein in the plurality of internal electrode layers, the Au concentration relative to all detected elements in the entire region other than the Au-containing layer is 0 at % or more and 4.5 at % or less.

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