Semiconductor Device

Abstract

To provide a semiconductor device having a reduced occupied area, capable of operating at low power, and capable of holding data even if power supply stops.SOLUTION: A semiconductor device includes a first transistor 101, a second transistor 102, and one capacitance 103. Data is written by accumulating charges in the capacitance through the second transistor, and the data is held by turning off the second transistor. By the first transistor whose gate is connected to a holding node R between the second transistor and the capacitance, the data is read out without a damage. Moreover, the second transistor and the capacitance are provided overlapping on the first transistor and one electrode of the second transistor and one electrode of the capacitance are connected electrically to the gate of the first transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, including memory devices, electro-optical devices, semiconductor circuits, electronic components, and electronic equipment. This is one aspect of a semiconductor device. [Background technology]

[0003] One of the semiconductor devices that uses semiconductor elements is a memory device. Volatile memory devices lose their contents when the power supply is cut off, while non-volatile memory devices retain their contents even when the power supply is cut off. They can be broadly classified into non-volatile memory devices that store information and non-volatile memory devices that store information.

[0004] A typical example of a volatile memory device is a dynamic random access memory (DRAM). Access Memory) and SRAM (Static Random Access These volatile storage devices are Although the contents of the memory are lost, the power consumption is low because it does not require a large voltage like non-volatile memory. is relatively small.

[0005] DRAM can apply one transistor and one capacitance to one memory element, so it can occupy The area can be reduced, but the data retention period is extremely short and refresh operations must be performed frequently. This means that power consumption cannot be reduced sufficiently.

[0006] SRAM is capable of high speed operation, but each memory element requires at least six transistors. In addition, as transistors become smaller, Since the off-state current of the transistor is increased, the power consumption during the data retention period can be sufficiently reduced. There is a problem that it cannot be reduced.

[0007] A typical example of a non-volatile storage device is a flash memory. By storing charge in the floating gate, data retention is almost permanent. However, flash memory is a storage device that can store data. The high voltage required for erasing and storing data consumes a lot of power, and the speed of these operations is also becoming Furthermore, writing and erasing require applying a high electric field to the insulating film to create a tunnel. By generating a current, charge is injected into the floating gate, so rewriting is possible. There is also a problem that the deterioration of the insulating film progresses depending on the number of times.

[0008] In recent years, transistors manufactured using oxide semiconductors with a wide band gap have An extremely large off-resistance was discovered, and this was used to develop memory elements that make up memory devices and signal processing devices. It has been proposed to fabricate a circuit using the same (see Patent Documents 2 to 4).

[0009] These memory elements are connected in series with transistors because the off-resistance of the transistors is high. It takes a long time for the charge stored in the capacitance element to disappear, and This reduces the current consumption required for memory retention in the flip-flop circuits used in Alternatively, the extremely large capacitance required for DRAM could be achieved. Since no elements are required, the circuit can be made smaller, simplifying the manufacturing process and improving yields. . [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Japanese Patent Publication No. 57-105889 [Patent Document 2] US Patent Application Publication No. 2011 / 0121878 [Patent Document 3] US Patent Application Publication No. 2011 / 0134683 [Patent Document 4] US Patent Application Publication No. 2011 / 0175646 Summary of the Invention [Problem to be solved by the invention]

[0011] In recent years, with the increasing integration of elements constituting semiconductor devices, there is a demand for reducing the area occupied by the elements. By reducing the area occupied by semiconductor devices, the number of devices per substrate can be increased, The cost of a single semiconductor device can be reduced. In a memory device, the area occupied by the memory element is small. The smaller the memory size, the more densely memory elements can be arranged, increasing the amount of data per unit area. It is possible to do so.

[0012] In addition, in order to reduce the power consumption of devices to which semiconductor devices are applied, From this perspective, there is a demand for a semiconductor device that can operate even when the power is turned off. There is a demand for data to be retained.

[0013] The present invention has been made under such technical background. An object of one embodiment is to provide a semiconductor device with a reduced occupation area. Another object of the present invention is to provide a semiconductor device that can operate with electric power. An object of the present invention is to provide a semiconductor device that can retain data even after a power failure.

[0014] One aspect of the present invention is to solve at least one of the above problems. [Means for solving the problem]

[0015] A semiconductor device according to one embodiment of the present invention includes a first transistor, a second transistor, and a The configuration has a capacity of

[0016] In addition, the semiconductor device stores data by storing charge in a capacitor via a second transistor. The second transistor is turned off to retain the data. In addition, the potential of a node (also called a storage node) between the second transistor and the capacitor is The gate electrode of the first transistor is provided with a voltage Vcc to detect the conduction state of the first transistor. This allows data to be read without destroying it.

[0017] Furthermore, the second transistor and the capacitor are provided on top of the first transistor. Preferably, the gate electrode of the first transistor is provided so as to overlap with the gate electrode of the second transistor. One electrode of the transistor (either the source electrode or the drain electrode) and one electrode of the capacitor is electrically connected to the gate electrode of the first transistor.

[0018] That is, a semiconductor device according to one embodiment of the present invention includes a first transistor and a second transistor. The first transistor includes a first semiconductor layer and a capacitor. a first insulating layer in contact with the first semiconductor layer; and a first electrode layer in contact with the first insulating layer and overlapping the first semiconductor layer. The second transistor is provided over the first electrode layer, and a second semiconductor layer electrically connected to the electrode layer; and a second insulating layer in contact with a side surface of the second semiconductor layer. a second electrode in contact with the edge layer and the second insulating layer and covering at least a portion of a side surface of the second semiconductor layer; a third electrode provided on the second semiconductor layer and electrically connected to the second semiconductor layer; The capacitor further includes a fourth electrode layer overlying the first electrode layer and a second electrode layer overlying the first electrode layer. and a dielectric layer between the first electrode layer and the fourth electrode layer.

[0019] With this configuration, a semiconductor device with a reduced occupied area can be realized.

[0020] Furthermore, when writing or erasing data to or from the semiconductor device, the second transistor Since only a voltage is required to turn the device on, the high voltage required for flash memory is eliminated. Therefore, it is possible to provide a semiconductor device that can operate with extremely low power. can.

[0021] In addition, the first semiconductor layer in the semiconductor device is preferably made of single crystal silicon. preferable.

[0022] With this configuration, the data stored in the semiconductor device can be read out as follows: It can be done extremely quickly.

[0023] In addition, a semiconductor device according to another embodiment of the present invention includes a first transistor and a second transistor. The first transistor includes a fifth electrode layer and a second electrode layer overlaid on the fifth electrode layer. a first semiconductor layer electrically connected to the fifth electrode layer; a first insulating layer in contact with the side surface of the first semiconductor layer; a first electrode layer provided on the first semiconductor layer and electrically connected to the first semiconductor layer; and a sixth electrode layer electrically connecting the first and second transistors to each other. a second semiconductor layer that is disposed on top of the first electrode layer and electrically connected to the first electrode layer; a second insulating layer in contact with a side surface of the second semiconductor layer; a second electrode layer provided on the second semiconductor layer and electrically connected to the second semiconductor layer; and a third electrode layer electrically connected to the first electrode layer. and a dielectric layer between the first electrode layer and the fourth electrode layer.

[0024] With this configuration, the area occupied by the first transistor itself can be reduced. Therefore, the area occupied by the semiconductor device itself can be further reduced.

[0025] In any one of the above semiconductor devices, the second semiconductor layer has a band larger than that of silicon. It preferably comprises a wide gap semiconductor.

[0026] In this way, a transistor with a reduced off-state current is used as the second transistor. Therefore, it can be used for a long period of time even when the power supply is stopped. It is possible to maintain the potential held at the holding node. It is possible to provide a semiconductor device capable of retaining data even when the power supply is stopped.

[0027] The semiconductor of the second semiconductor layer is preferably an oxide semiconductor.

[0028] The oxide semiconductor preferably contains In, Ga, and Zn.

[0029] In this way, in particular, an oxide semiconductor is used as the semiconductor constituting the channel of the second transistor. It is preferable to use a conductor such as an oxide semiconductor, which has a wider band gap than silicon, as a low Therefore, a low off-state current can be achieved.

[0030] In particular, when an oxide semiconductor containing In, Ga, or Zn is used for a transistor, Even amorphous oxide semiconductors formed at low temperatures have a higher thermal conductivity than other oxide semiconductors. It has excellent electrical properties (high field effect mobility, small S value, etc.) and high reliability. Here, for example, zinc oxide, which is one of the oxide semiconductors, is polycrystalline at low temperatures. The grain boundaries are easily oriented in a direction that allows desired electrical properties such as field effect mobility and S value to be obtained. It is difficult to do so.

[0031] In addition, in a semiconductor device using a semiconductor having a wider band gap than silicon, The dielectric layer is preferably made of the same film as the second semiconductor layer.

[0032] The semiconductor used for the second semiconductor layer has an extremely high resistance, so the dielectric that constitutes the capacitance Therefore, by adopting the above-mentioned structure, the first transistor can be used as a A second transistor and a capacitor can be formed on the gate electrode of the first transistor by a common process. Therefore, the manufacturing process of the semiconductor device can be simplified, and the manufacturing yield can be increased at low cost. The semiconductor device can be realized.

[0033] In any one of the above semiconductor devices, a driving circuit is provided below the first transistor. It is preferable to provide a path.

[0034] In this way, by forming a semiconductor device having a driver circuit in the lower part, In comparison with the case where the configuration of the second transistor or the capacitor and the drive circuit are arranged without overlapping each other, As a result, the area occupied by the semiconductor device can be reduced.

[0035] In any one of the above semiconductor devices, the first transistor and the second transistor It is preferable that a plurality of layers of the semiconductor device including the capacitor and the capacitor are stacked.

[0036] In this manner, a plurality of semiconductor devices according to one embodiment of the present invention can be stacked. By using such a stacked semiconductor device, it is possible to achieve extremely high integration of the semiconductor device. This makes it possible to significantly increase the amount of data that can be stored per occupied area of ​​a semiconductor device. Cut.

[0037] Note that in this specification, a memory device is one embodiment of a semiconductor device. It also refers to a device that at least retains the stored state of data. A device including a plurality of storage devices is also an aspect of the storage device. The driving circuit and the module on which the IC (integrated circuit) is mounted are also included in the memory device. do. Effect of the Invention

[0038] According to the present invention, it is possible to provide a semiconductor device that occupies a reduced area. In addition, a semiconductor device capable of retaining data even when the power supply is stopped can be provided. A body device can be provided. [Brief description of the drawings]

[0039] [Figure 1]1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Diagram 2] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Diagram 3] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Diagram 5] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A to 1C illustrate an example of a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C illustrate an example of a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C illustrate an example of a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C illustrate an example of a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C illustrate an example of a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C illustrate an example of a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A to 1C illustrate electronic devices according to one embodiment of the present invention. [Figure 18] 1A to 1C illustrate electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0040] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the present invention can be realized by the following embodiments. However, the present invention should not be construed as being limited to the above description. In the drawings, the same reference numerals are used to denote the same parts or parts having similar functions. , and a repeated explanation will be omitted.

[0041] In each figure described in this specification, the size, layer thickness, or area of ​​each component is indicated by the following formula: The figures may be exaggerated for clarity and are not necessarily limited to scale. stomach.

[0042] A transistor is a type of semiconductor device that controls the amplification of current or voltage and the conduction or non-conduction of electricity. In this specification, the transistor can realize a switching operation that controls the , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT: Thin Film Transistor ).

[0043] In addition, the functions of "source" and "drain" may differ when using transistors with different polarities. In some cases, such as when the direction of the current changes during circuit operation, the two may be interchanged. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably. It is possible.

[0044] In this specification, either the source or the drain of a transistor The first electrode is called the source or drain, and the other is called the second electrode. The gate is also called the "gate" or the "second electrode." It is also called the "gate electrode."

[0045] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." In this case, "something that has some electrical effect" includes a case where the device is connected via the "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. Switching elements such as inverters, resistor elements, coils, capacitor elements, and other elements with various functions This includes children, etc.

[0046] In this specification, a node is a circuit that allows electrical connection of elements constituting a circuit. Therefore, "the node to which A is connected" means A is a wiring that is electrically connected to A and can be considered to have the same potential as A. Elements that allow electrical connections to be made within the device (e.g., switches, transistors, capacitors, insulators, etc.) Even if one or more elements (such as inductors, resistors, diodes, etc.) are placed, as long as they are at the same potential as A That wiring can be considered as the node to which A is connected.

[0047] In this specification, two or more components may be formed simultaneously from the same material. When these components are in the same layer, they are defined as existing in the same layer. If a layer is formed and then processed (e.g. by etching) into components A and B, these It is a component that exists on the same layer.

[0048] (Embodiment 1) In this embodiment, a configuration example of a memory device will be described as an example of a semiconductor device of one embodiment of the present invention. The following description will be given with reference to the drawings.

[0049] FIG. 1A is a circuit diagram of a main part of a memory device of one embodiment of the present invention. , a transistor 101 , a transistor 102 and a capacitor 103 .

[0050] The memory device includes a gate electrode of a transistor 101, a first electrode of a transistor 102, and The storage node R is electrically connected to one electrode of the capacitor 103. can.

[0051] A wiring S2 is electrically connected to the first electrode of the transistor 101, and a second electrode The wiring electrically connected to the electrode is called wiring D. The wire that is electrically connected to the second electrode is referred to as wire W1, and the wire that is electrically connected to the second electrode is referred to as wire S1. The wiring electrically connected to the other electrode of the capacitor 103 is referred to as wiring W2.

[0052] When writing data to the memory device, a current that turns on the transistor 102 is applied to the wiring W1. A predetermined potential is input to the second electrode of the transistor 102 from the wiring S1. This allows a predetermined potential to be written to the retention node R via the transistor 102. After that, when a potential for turning off the transistor 102 is input to the wiring W1, The potential written to the node R is maintained.

[0053] In addition, depending on the potential held at the holding node R, a gate electrode is connected to the holding node R. The transistor 101 is either in an on state or an off state. A potential for reading is input to one of the wirings S2 and D, and the potential of the other is detected. In this way, reading can be performed.

[0054] In this way, when writing or erasing data to or from a storage device according to one embodiment of the present invention, A voltage sufficient to turn on the transistor 102 is used. In other words, the hold node The voltage required to write to R controls the on or off state of transistor 101. Therefore, in driving the memory device of one embodiment of the present invention, Unlike flash memory, it does not require high voltage, so it is a memory with extremely low power consumption. A memory device can be realized.

[0055] Here, the transistor 102 is a transistor using silicon as a semiconductor in which a channel is formed. A transistor that has a reduced leakage current (off current) in the off state compared to a transistor. Specifically, a silicon semiconductor is used as the semiconductor in which the channel is formed. The transistor uses a semiconductor with a wider band gap than silicon. Compound semiconductors are semiconductors that have a band gap. For example, oxide semiconductors and nitride semiconductors semiconductors, etc.

[0056] Specifically, to obtain a very high off-resistance, silicon (band gap 1.1 A band gap of 2.5 to 4 electron volts is preferred. It is preferable to use a wide band gap semiconductor having a voltage of 3 electron volts or more and 3.8 electron volts or less. For example, oxide semiconductors such as indium oxide and zinc oxide, gallium nitride, etc. or a sulfide semiconductor such as zinc sulfide.

[0057] In particular, an oxide semiconductor is used as a semiconductor forming the channel of the transistor 102. The oxide semiconductor has a large energy gap of 3.0 eV or more. In a transistor obtained by processing a semiconductor under appropriate conditions, the source The leakage current (off-state current) per 1 μm of channel width between the source and drain is When the voltage between the terminals is 3.5V and the temperature conditions during use (for example, 25°C), the 1×10 -19 A) or less, or 10zA (1×10 -20 A) and below, and even 1zA (1×10 -21 A) or less. Therefore, the semiconductor device with low power consumption can be manufactured. It is possible to achieve this.

[0058] In particular, when an oxide semiconductor containing In, Ga, or Zn is used for a transistor, Even amorphous oxide semiconductors formed at low temperatures have a higher thermal conductivity than other oxide semiconductors. It has excellent electrical properties (high field effect mobility, small S value, etc.) and high reliability. Here, for example, zinc oxide, which is one of the oxide semiconductors, is polycrystalline at low temperatures. The grain boundaries are easily oriented in a direction that allows desired electrical properties such as field effect mobility and S value to be obtained. It is difficult to do so.

[0059] In this manner, by using a transistor with reduced off-state current as the transistor 102, This allows the potential held at the holding node R to be held for a long period of time. Furthermore, data can be retained even if the power supplied to the storage device is stopped.

[0060] FIG. 1B is a schematic diagram of a memory device according to one embodiment of the present invention.

[0061] The memory device is provided with a transistor 101, a transistor 102, and a capacitor 103 stacked on top of each other. It is being done.

[0062] The transistor 101 is a transistor in which a single crystal semiconductor is used as a semiconductor in which a channel is formed. The transistor 101 is a semiconductor layer 115 and a The first electrode layer 112 and the second electrode layer 113 are connected to each other, and the gate electrode 114 is in contact with the semiconductor layer 115. A gate insulating layer 114 and a channel forming region of a semiconductor layer 115 are formed on and in contact with the gate insulating layer 114. The channel direction of the transistor 101 is a semiconductor It is parallel to the top surface of layer 115 .

[0063] The transistor 102 is provided over the gate electrode layer 111. A semiconductor layer 125 electrically connected to the semiconductor layer 111 and a semiconductor An electrode layer 122 electrically connected to the semiconductor layer 125 and provided in contact with the side surface of the semiconductor layer 125. A gate insulating layer 124 and a semiconductor layer 125 are in contact with the gate insulating layer 124 and face the side surface of the semiconductor layer 125. and a gate electrode layer 121 formed by stacking the gate electrodes 121 and the gate electrodes 121. The transistor 102 is a so-called vertical Therefore, the channel direction of the transistor 102 is 10 1 and perpendicular to the upper surface of the semiconductor layer 115.

[0064] The capacitor 103 includes an electrode layer 132 provided on the gate electrode layer 111 and a gate and a dielectric layer 134 sandwiched between the base electrode layer 111 and the electrode layer 132. The channel of the transistor 101 is formed by the semiconductor layer 125 of the transistor 102 and the inductor of the capacitor 103. It overlaps with the conductive layer 134 .

[0065] Here, the electrode layer 122 is electrically connected to the wiring S1 in FIG. The gate electrode layer 121 is connected to the wiring W1, the electrode layer 132 is connected to the wiring W2, and the first electrode layer 112 is connected to the wiring W3. The second electrode layer 113 is electrically connected to the wiring S2 and the second electrode layer 113 is electrically connected to the wiring D. The pole layer 111 corresponds to the retention node R.

[0066] As shown in FIG. 1B, a vertical transistor is formed on the gate electrode layer 111 of the transistor 101. The transistor 102 and the capacitor 103 are stacked to form an occupancy A memory device with a reduced area can be realized. 2 and one of the electrodes of the capacitor 103. The structure is simplified, and production can be carried out at a lower cost.

[0067] In particular, by using a single crystal semiconductor for the transistor 101 that performs the reading operation, This enables faster read operations.

[0068] In addition, the semiconductor layer 125 is made of a material having a band gap wider than that of silicon. When using this material, the resistance is extremely high, so it is also used as a dielectric layer that constitutes a capacitor. At this time, as shown in FIG. It is preferable to apply a dielectric layer 134 of the same material as 25 to the capacitor 103. It is preferable that the semiconductor layer 125 and the dielectric layer 134 are present as the same layer. By adopting such a structure, the transistor 102 and the capacitor 103 can be manufactured by a common manufacturing process. This makes it possible to simplify the manufacturing process of the memory device, resulting in low cost and high yield. The above-mentioned storage device may be implemented.

[0069] As shown in FIG. 2(A), a thin film of an insulating material is used as the dielectric layer 134 of the capacitor 103. By using a thin film of an insulating material for the dielectric layer 134, Since the thickness can be made thin, the capacitance value of the capacitor 103 can be increased.

[0070] Here, the channel length of the transistor 102 is adjusted by changing the thickness of the semiconductor layer 125. Therefore, the gate electrode layer 111 and the electrode layer 122 can be controlled with the miniaturization. Even if the line width becomes extremely small, the thickness of the semiconductor layer 125 can be adjusted to allow arbitrary channel width. The length of the loop can be set to 1.

[0071] In addition, although the semiconductor layer 125 is shown as having a rectangular column shape in FIG. 1B and FIG. 2A, In FIG. 2B, the semiconductor layer 125 is shown in a cylindrical shape. FIG. 2(C) is a schematic diagram of the gate electrode layer 12 in FIG. 1 and the gate insulating layer 124 are shown by dashed lines.

[0072] If the semiconductor layer 125 has a rectangular column shape, for example, a channel formed near the side surface of the semiconductor layer 125 may be formed. Since the effective width of the gate can be increased, the on-state current of the transistor 102 can be increased. In addition, when the semiconductor layer 125 is formed in a cylindrical shape as shown in FIG. Since there are no protruding parts on the side surface, the gate electric field is uniformly applied to the entire side surface. As a result, the transistor 102 can be made highly reliable. If it is desired to increase the on-state current, the shape of the bottom surface of the semiconductor layer 125 can be changed to, for example, a star-shaped polygon. , At least one interior angle exceeds 180° (concave polygon), and the effective channel The rule width may be increased.

[0073] In FIG. 1B, the gate electrode layer 121 is a semiconductor The insulating layer 125 is provided facing a part of the side surface of the semiconductor layer 125. For example, the gate electrode layer 121 may be formed so as to cover a part of the semiconductor layer 125. Alternatively, the gate electrode layer 121 may be provided only on one side of the semiconductor layer 125. As shown in FIG. 2(B) and FIG. 2(C), If the side surface of the semiconductor layer 125 is surrounded in this manner, the effective channel of the transistor 102 Since the width can be made large, the on-current can be increased.

[0074] The memory device described as an example in this embodiment has a transistor 101 and a capacitor A capacitor 103 is laminated, and a vertical transistor is used as the transistor 102. Therefore, the storage device occupies a very small area. Since it does not require a high voltage, it is a memory device that can operate with extremely low power consumption.

[0075] In addition, by using a transistor with reduced off-state current as the transistor 102, This makes it possible to retain data even if the power supply is stopped, and the data can be stored for an extremely long period of time. It is possible to realize a storage device that can hold the above.

[0076] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0077] (Embodiment 2) In this embodiment, another configuration example of a memory device will be described as an example of a semiconductor device according to one embodiment of the present invention. The following description will be given with reference to the drawings. Note that the same parts as those in the above embodiment will be omitted. The explanation will be omitted or simplified.

[0078] <Configuration example> FIG. 3A is a circuit diagram of a main part of a memory device exemplified in this embodiment.

[0079] Here, a configuration including two transistors and one capacitor is collectively called one memory element. We have decided to do so.

[0080] The memory device shown in FIG. 3A includes a transistor 101a, a transistor 102a, and a capacitor. A memory element 110a including a transistor 103a, a transistor 101b, a transistor 102b, and The memory element 110b includes a capacitor 103b. The configuration can be similar to that of the storage device exemplified in the first embodiment.

[0081] The memory device includes a gate of the transistor 102a and a gate of the transistor 102b. A wiring W1 electrically connects one electrode of the capacitor 103a and one electrode of the capacitor 103b. The wiring W2, the first electrode of the transistor 102a, and the second electrode of the transistor 101a a wiring S11 electrically connected to the first electrode of the transistor 102b and a A wiring S12 electrically connected to a first electrode of the transistor 101b and a and a wiring S2 electrically connected to the second electrode of each of the transistors 101b. It is being done.

[0082] In this way, the wiring S1 and the wiring D illustrated in the first embodiment are integrated into a wiring S11 (or By making the wiring S12 common between adjacent memory elements, the number of wirings is reduced. can be reduced.

[0083] For simplicity, a configuration including two memory elements will be described in FIG. 3(A). However, in reality, these two pairs of memory elements are periodically arranged along the wiring W1 and wiring S2. It is preferable that the above is done.

[0084] Next, the operation of the memory device shown in FIG.

[0085] When writing data, the transistors 102a and 102b are connected to the wiring W1. Next, a desired potential is applied to each of the wirings S11 and S12. By applying a voltage to the transistor 102a or the transistor 102b, Data can be written to the retention node of the storage element.

[0086] When reading, a common potential is applied to the wiring S2. A potential that turns on the transistor 101a or the transistor 101b is held at the node. When the hold node is held, the potential of the wiring S11 or the wiring S12 changes. When the potential of the wiring S11 or the wiring S1 Therefore, the potential of the wiring S11 or S12 is not changed. By detecting the voltage with a detector or other device, the data written in each memory element can be read. Cut.

[0087] Here, when reading from another memory element arranged along the wiring S2, It is necessary to reliably turn off the transistor 101a and the transistor 101b. By applying a desired potential to the wiring W2, the The potential of the retention node is set to the transistor 101a or the transistor 101b in an off state. In this manner, the readout of the other memory elements arranged along the wiring S2 is performed. This can be done reliably.

[0088] The above is a description of the operation of the storage device.

[0089] FIG. 3B is a schematic top view of the memory device exemplified in this embodiment.

[0090] FIG. 3B shows a wiring layer 201 functioning as the wiring W1 and a wiring layer 202 functioning as the wiring W2. a wiring layer 203a functioning as the wiring S11; The wiring layer 203b and the wiring layer 204 functioning as the wiring S2 are shown.

[0091] In addition, a transistor 102a is provided in a region where the wiring layer 201 and the wiring layer 203a overlap each other. Similarly, a transistor 10 is formed in the region where the wiring layer 201 and the wiring layer 203b overlap each other. 2b is in the area where the wiring layer 202 and the wiring layer 203a overlap, and the capacitance 103a is in the area where the wiring layer 202 and the wiring layer 203a overlap. Capacitors 103b are provided in the areas where the wiring layers 203b overlap.

[0092] 4(A) to (C) respectively show the cross sections A-A', B-B', and FIG. 4(A) shows a schematic cross-sectional view taken along the line CC'. FIG. 4( a ) is a schematic cross-sectional view of a region including a transistor 102a and a capacitor 103a. B) is a region including transistors 102a and 102b along the wiring layer 201. FIG. 4(C) is a schematic cross-sectional view of the wiring layer 202, the capacitor 103a, and the connection electrode 103b. 2 is a schematic cross-sectional view of a region including the pole layer 213b and the connection electrode layer 213c.

[0093] In the memory element 110a, a transistor is provided on a gate electrode layer 111a of the transistor 101a. A transistor 102a and a capacitor 103a are stacked. A transistor 102b and a capacitor 103b are formed on a gate electrode layer 111b of the transistor 101b. It is layered.

[0094] Here, the transistor 101a and the transistor 101b are semiconductors in which channels are formed. This is a transistor that uses a single crystal semiconductor as a conductor.

[0095] The transistor 101a includes a semiconductor layer 115 and a first The first electrode layer 112a and the second electrode layer 113, and the gate insulating layer 114 in contact with the semiconductor layer 115 are 14, and a gate electrode layer 111a that is in contact with the gate insulating layer 114 and overlaps with the semiconductor layer 115. Yes.

[0096] Similarly, the transistor 101b includes a semiconductor layer 115, a first electrode layer 112b, and a The semiconductor device further includes a second electrode layer 113, a gate insulating layer 114, and a gate electrode layer 111b.

[0097] The first electrode layer 112b of the transistor 101b is connected to the wiring layer 213c via the connection electrode layer 213c. The first electrode layer 112a of the transistor 101a is electrically connected to the first electrode layer 112a of the transistor 101a. Similarly, the wiring layer 203a is electrically connected to the connecting electrode layer 213c (not shown). In addition, the second electrode layer 11 is common to the transistor 101a and the transistor 101b. 3 is electrically connected to the wiring layer 204 via the connection electrode layer 213b.

[0098] As shown in FIGS. 4A to 4C, the gate electrode layer 111a and the gate electrode layer 11 A sidewall insulating layer may be provided on the side surface of 1b.

[0099] The transistor 102a includes a semiconductor layer 125 in contact with the upper surface of the gate electrode layer 111a and a semiconductor The electrode layer 122 is in contact with the top surface of the semiconductor layer 125, and the gate insulating layer 123 is in contact with the side surface of the semiconductor layer 125. Further, the semiconductor layer 125 is in contact with the gate insulating layer 124 and has a side surface surrounded by the semiconductor layer 125. A wiring layer 201 is provided. A part of the wiring layer 201 is connected to the gate of the transistor 102a. Therefore, the gate electrode of the transistor 102a functions as a gate electrode of the transistor 101. a and the electrode layer 122 of the transistor 102a.

[0100] Similarly, the transistor 102b has a semiconductor layer 125 in contact with the gate electrode layer 111b and an The electrode layer 122 and the gate insulating layer 124 are included, and the side surface of the semiconductor layer 125 is surrounded by the wiring layer 201. The gate electrode of the transistor 102b is also formed on the gate electrode layer 1 of the transistor 101b. 11b and the electrode layer 122 of transistor 102b.

[0101] The electrode layer 122 of the transistor 102a is connected to the wiring layer 203a via the connection electrode layer 213a. The electrode layer 122 of the transistor 102b is also electrically connected to the It is electrically connected to the wiring layer 203b via the pole layer 213a.

[0102] The capacitor 103a is a dielectric layer 13 in contact with the gate electrode layer 111a of the transistor 101a. 4. Also, a wiring layer 202 is provided in contact with the upper surface of the dielectric layer 134. A part of the dielectric layer 134 functions as one electrode of the capacitor 103a. The dielectric layer 134 is made of the same layer as the conductor layer 125. It exists as the same layer as

[0103] Similarly, the capacitor 103b has a dielectric layer 134 on and in contact with the gate electrode layer 111b. A wiring layer 202 is provided in contact with the upper surface of 134 .

[0104] As shown in FIGS. 4(A) to 4(C), the electrode layers and wiring layers constituting the memory device are electrically In order to separate the layers, an insulating layer is provided between each electrode layer, between wiring layers, or between an electrode layer and a wiring layer. Any one of 212a to 212h is provided.

[0105] In addition, the substrate constituting the semiconductor layer 115 has a structure in which the transistors each having the semiconductor layer 115 are provided with a An element isolation layer 211 is provided for electrical isolation.

[0106] In the memory device exemplified in this embodiment, the electrode layers and The width of the wiring layer, the spacing between the electrode layers, between the wiring layers, or between the electrode layer and the wiring layer, are determined by the fabrication method used. The minimum processing dimension in the method can be used. Here, the minimum processing dimension is F. Therefore, the value of F is preferably 100 nm or less, more preferably 50 nm or less, and even more preferably shall be 30 nm or less.

[0107] In this configuration example, the transistor 102a, which is a vertical transistor, and the capacitor 103a The occupied area of ​​F 2 can be reduced to

[0108] In this way, one electrode layer of the transistor 101a and the transistor 101b is shared. This allows the two storage elements to be arranged as close as possible to each other. A transistor 102a and a capacitor 103 are disposed on the gate electrode layer 111a of the transistor 101a. By stacking the layers a, the area occupied by one memory element can be reduced.

[0109] The above is a description of the configuration example of the storage device exemplified in this embodiment.

[0110] <Modification> In the above configuration example, the dielectric layer constituting the capacitance is the same as the semiconductor layer of the vertical transistor. The dielectric layer and the semiconductor layer are present as the same layer. The following describes the case where a thin film of an insulating material is used as the dielectric layer.

[0111] FIG. 5 shows a schematic cross-sectional view of the capacitor 103a shown in FIG. 4(A) with a different configuration. It should be noted that the configuration is the same as the above-described configuration example except for the configuration of the capacitor 103a.

[0112] The capacitor 103a is a dielectric layer 13 in contact with the gate electrode layer 111a of the transistor 101a. 4 and an electrode layer 132 in contact with the upper surface of the dielectric layer 134. A wiring layer 202 is provided in contact with the

[0113] The dielectric layer 134 is made of a thin film of an insulating material. This allows the dielectric layer 134 to be formed thin, thereby increasing the capacitance per unit area. do.

[0114] 5, the dielectric layer 134 is disposed on the gate insulating layer 12 of the transistor 102a. It is preferable that the electrode layer 132 is present as the same layer as the wiring layer 201. In this way, the dielectric layer 134 and the electrode layer 132 are preferably the same. By forming the capacitor 103a and the transistor 102a on the same layer, Since the resistor 102a can be formed in the same process, the manufacturing process is simplified. can.

[0115] This concludes the description of this modified example.

[0116] <Production process example> An example of a method for manufacturing the memory device exemplified in the above configuration example will be described below with reference to the drawings. In this example of the fabrication process, only an outline is shown, with some exceptions. For details, please refer to the For this purpose, reference should be made to well-known semiconductor integrated circuit fabrication techniques.

[0117] 6 to 9 show schematic top views and schematic cross-sectional views at each stage of this fabrication process example. For example, FIG. 6(A) shows a schematic top view at that stage, and FIG. 6(B) shows a schematic top view at that stage. 1A) shows a schematic cross-sectional view taken along the cutting lines A-A' and B-B'.

[0118] First, a substrate containing a semiconductor material is prepared. The substrate containing a semiconductor material is silicon or Single crystal semiconductor substrates such as silicon carbide, polycrystalline semiconductor substrates, silicon germanium, etc. Compound semiconductor substrates, SOI substrates, etc. can be used. Here, we will explain an example of using a single crystal silicon substrate as the substrate. The term "OI substrate" refers to a substrate having a structure in which a silicon semiconductor layer is provided on an insulating surface. In the literature, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the SOI substrate includes an insulating substrate such as a glass substrate. The term also includes a structure in which a semiconductor layer is provided via a layer.

[0119] Next, an element isolation layer 211 is formed on the substrate. The element isolation layer 211 is formed by a known LOCO method. Formed using S (Local Oxidation of Silicon) process etc. In addition, before and after this process, the transistors 101a and An impurity that imparts n-type conductivity to control the threshold voltage of the transistor 101b The substrate may be doped with an element or an impurity element that gives p-type conductivity. When the body material is silicon, impurities that give n-type conductivity include phosphorus and arsenic. On the other hand, impurities that impart p-type conductivity include, for example, boron, Aluminum, gallium, etc. can be used.

[0120] In addition, after the element isolation layer 211 is formed, it is preferable to flatten the substrate surface. For example, , CMP (Chemical Mechanical Polishing) and other polishing A treatment or an etching treatment may be used.

[0121] Next, an insulating film is formed on the surface of the substrate, and a conductive film is formed on the insulating film.

[0122] The insulating film is a gate insulating film for the transistors 101a and 101b to be formed later. The insulating layer 114 is an oxide film obtained by using a CVD method, a sputtering method, or the like. Silicon, silicon oxynitride, silicon oxynitride, silicon nitride, hafnium oxide, oxide Aluminum, tantalum oxide, yttrium oxide, hafnium silicate (HfSi x O y (x>0, y>0), nitrogen-doped hafnium silicate, nitrogen-doped hafnium HfAl x O y (x>0, y>0)) It is recommended to use a laminated structure. In addition, high-density plasma treatment and heat treatment (thermal oxidation treatment and thermal nitridation treatment) The insulating film may be formed by oxidizing or nitriding the surface of the substrate using a method such as the above. High density plasma treatment is a process that uses rare gases such as He, Ar, Kr, and Xe, oxygen, and oxynitride. The etching can be performed by using a mixed gas of hydrogen, ammonia, nitrogen, etc. is not particularly limited, but can be, for example, 1 nm or more and 100 nm or less.

[0123] The conductive film is a gate electrode of the transistor 101a and the transistor 101b to be formed later. The pole layers 111a and 111b are made of aluminum, copper, titanium, tantalum, tantalum, etc. It can be formed using a metal material such as stainless steel, chromium, nickel, molybdenum, or the like. Alternatively, a conductive film may be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method of formation is not particularly limited, and may be a deposition method, a CVD method, a sputtering method, a spin coating method, etc. In this embodiment, a metal material is used as the conductive film. Here, we will show an example of when to use the fee.

[0124] The conductive film is formed later as a Since it also functions as one of the electrodes, the electron affinity of the semiconductor material used for the semiconductor layer 125 should be taken into consideration. It is preferable to select the material taking into consideration the above. The uppermost conductive film (the layer in contact with the semiconductor layer 125) is provided with the transistor 102a and the transistor 102b. Alternatively, a conductive film made of a material suitable for the electrode of the transistor 102b may be used.

[0125] Next, unnecessary portions of the conductive film are etched to remove the gate electrode layer 111a and the gate electrode The pole layer 111b is formed.

[0126] Next, the side walls in contact with the side surfaces of the gate electrode layer 111a and the gate electrode layer 111b are The sidewall insulating layer is formed on the gate electrode layer 111a and the gate electrode layer 111b. After forming an insulating film covering 111b, a highly anisotropic etching process is applied to the insulating film. By this, it is possible to form the layer in a self-aligned manner.

[0127] In addition, the gate insulating layer 114 is etched when the sidewall insulating layer is formed. Among the insulating films to be formed, the gate electrode layer 111a, the gate electrode layer 111b and the sidewall The portions that do not overlap the gate insulating layer are simultaneously etched, so that the gate insulating layer 114 is is formed.

[0128] By providing the sidewall insulating layer, impurities can be prevented from being added in the process of adding impurities, which will be described later. Impurity regions can be formed by doping the pure elements at different concentrations. This is preferable because it can suppress the influence of short channel effects. In this case, the transistor size can be reduced by using a structure without sidewalls. It can be made smaller.

[0129] Next, the gate electrode layer 111a, the gate electrode layer 111b, and the sidewall insulating layer are formed on the The silicon substrate is used as a silicon wafer, and impurities such as phosphorus and arsenic are added to form a first electrode layer 112a and a first electrode layer 112b. A first electrode layer 112b and a second electrode layer 113 are formed. To form an n-channel junction, impurity elements such as boron or aluminum can be added. When forming a GaN-type transistor, impurity elements such as phosphorus or arsenic may be added. The concentration of the added impurities can be set appropriately, but as semiconductor elements become highly miniaturized, In the case where an impurity element is added, it is desirable to increase its concentration. It is desirable to improve defects that occur when impurity elements are activated or added by performing a treatment. I wish.

[0130] Through the above steps, the transistor 101a and the transistor 101b can be formed.

[0131] Thereafter, an insulating film that will later become the insulating layer 212a is formed, and then the gate electrode layer 111a and the gate A planarization process is performed so that the base electrode layer 111b is exposed, and an insulating layer 212a is formed.

[0132] The insulating film that becomes the insulating layer 212a may be made of silicon oxide, silicon oxynitride, or silicon oxynitride. Inorganic insulating materials such as silicon nitride, aluminum oxide, hafnium oxide, and tantalum oxide A single film or a laminated film containing the above-mentioned can be used. If it is possible to form the insulating layer using an organic insulating material such as polyimide or acrylic resin, the insulating layer may be formed using the organic insulating material. do.

[0133] The schematic top view and cross-sectional view at this stage are shown in Figure 6(A) and (B), respectively. Equivalent.

[0134] Next, a second half is formed on the gate electrode layer 111a, the gate electrode layer 111b, and the insulating layer 212a. A semiconductor film that will become the conductor layer 125 is formed. The thickness of the semiconductor film is determined by the thickness of the film in the subsequent flattening process. Considering the thickness reduction, the thickness is set to be thicker than the desired channel length. It is preferable to form

[0135] As the material for the semiconductor film, a semiconductor material such as silicon can be used. It is preferable to use a semiconductor material with a band gap wider than that of silicon. Compound semiconductors are semiconductors that have band gaps. For example, oxide semiconductors and nitride semiconductors Semiconductors, etc.

[0136] The off-resistance of a transistor is determined by the thermally excited capacitance in the semiconductor layer in which the channel is formed. The state where there are no carriers due to donors or acceptors ( Even though silicon is an intrinsic semiconductor, its band gap is 1.1 electron volts. Therefore, the concentration of thermally excited carriers at room temperature (300K) is 1×10 11 cm -3 That's about it.

[0137] On the other hand, in the case of a semiconductor with a band gap of 3.2 eV, for example, the thermally excited carriers The concentration is 1×10 -7 cm -3 When the electron mobility is the same, the resistivity increases with the carrier concentration. Since the resistivity is inversely proportional to the band gap, the resistivity of a semiconductor with a band gap of 3.2 eV is higher than that of silicon. It is 18 orders of magnitude larger.

[0138] Transistors using such wide band gap semiconductors have extremely low off-state currents. Such transistors can be used as transistor 102a and transistor 102b. 02b, the potential held at the storage node of each memory element can be increased for an extremely long period of time. It is possible to hold the information for a certain period of time.

[0139] In this embodiment, an oxide semiconductor film is formed as the semiconductor film by a sputtering method. Specifically, a sputtering method was used with an In-Ga-Zn oxide semiconductor target. More forming.

[0140] Note that a material that can be used for the oxide semiconductor film is not limited to the above. The conductor preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that the alloy contains In and Zn.

[0141] In addition, a stabilizer for reducing variations in the electrical characteristics of transistors using oxide semiconductors has been developed. In addition to these, gallium (Ga), tin (Sn), and hafnium (Hf) are used as risers. , aluminum (Al), or lanthanides. is preferred.

[0142] Lanthanides include lanthanum (La), cerium (Ce), praseodymium (Pr), Neodymium (Nd), Samarium (Sm), Europium (Eu), Gadolinium (Gd) , terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (E r), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0143] For example, indium oxide, tin oxide, zinc oxide, etc. can be used as the oxide semiconductor. can.

[0144] In addition, oxide semiconductors include In-Zn oxides, Sn-Zn oxides, and Al-Zn oxides. Oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide An oxide or the like can be used.

[0145] In addition, oxide semiconductors include In-Ga-Zn oxide (also written as IGZO), I n-Sn-Zn oxide, Sn-Ga-Zn oxide, In-Al-Zn oxide, In -Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In- Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-E In-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn-based oxides, In-Ho-Zn-based oxides, In-Er-Zn-based oxides, In-Tm- Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, Al-Ga-Z n-based oxides, Sn-Al-Zn-based oxides, etc. can be used.

[0146] In addition, oxide semiconductors include In-Sn-Ga-Zn oxides and In-Hf-Ga-Zn n-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al-Zn-based oxides, In -Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide, etc. can be used. .

[0147] In addition, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than Ga and Zn may be contained.

[0148] In addition, an oxide semiconductor film is formed using an oxide semiconductor obtained by adding SiO2 to the above metal oxide. It is also possible.

[0149] The oxide semiconductor film is InMO3(ZnO) m (m>0) oxide semiconductor Here, M is one selected from Ga, Al, Mn, and Co. represents one or more metallic elements.

[0150] For example, atoms of In:Ga:Zn=1:1:1 or In:Ga:Zn=2:2:1 In-Ga-Zn oxides having the same composition or oxides having a similar composition can be used.

[0151] Alternatively, In:Sn:Zn=1:1:1, In:Sn:Zn=2:1:3, or I In-Sn-Zn oxides with an atomic ratio of n:Sn:Zn=2:1:5 and oxides with similar compositions Compounds may also be used.

[0152] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In order to obtain the required semiconductor characteristics, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. It is preferable to make the following appropriate.

[0153] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, in the case of In-Ga-Zn oxides, the mobility can be improved by reducing the defect density in the bulk. It can be raised.

[0154] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b +c=1), the atomic ratio of the oxide is In:Ga:Zn=A:B:C (A+B+ C=1) is close to the oxide composition when a, b, and c are (aA) 2 +(bB) 2 +(cC) 2 ≦r 2 It means that the above condition is satisfied, and r can be set to, for example, 0.05. The same is true for oxides.

[0155] The oxide semiconductor may be single-crystal or non-single-crystal. In the case of non-single-crystal, it may be amorphous or polycrystalline. Alternatively, the amorphous structure may include a portion having crystallinity. Since amorphous has many defects, non-amorphous is preferable.

[0156] Amorphous oxide semiconductors can be used to obtain flat surfaces relatively easily. This can reduce interface scattering when a transistor is fabricated using this, and can be fabricated relatively easily and relatively High mobility can be obtained.

[0157] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced. By improving the flatness of the surface, it is possible to obtain a mobility higher than that of an amorphous oxide semiconductor. .

[0158] Here, the oxide semiconductor film contains an alkali metal, a hydrogen atom, a hydrogen molecule, water, a hydroxyl group, or water. It is preferable to form the film so that impurities such as elemental compounds are not mixed in as much as possible. The above-mentioned impurities are prevented from being mixed into the sputtering target and the gas used for film formation. During film formation, the inside of the film formation device is fully evacuated and the substrate temperature is heated during film formation. As a result, the impurity concentration in the formed oxide semiconductor film can be reduced.

[0159] In addition, after the oxide semiconductor film is formed, a dehydration treatment (dehydrogenation treatment) is performed to obtain an oxide semiconductor film. Hydrogen or moisture is removed from the conductive film to purify it so that it contains as few impurities as possible. In order to compensate for the increased oxygen vacancies caused by the hydration process (dehydrogenation process), oxygen is added to the oxide semiconductor. It is preferable to carry out a treatment to add oxygen to the film. or a method in which an oxide semiconductor film is placed in the vicinity of a film that releases oxygen by heating and then heat treatment is performed. In this specification, when oxygen is supplied to the oxide semiconductor film, Alternatively, oxygen contained in the oxide semiconductor film may be stoichiometrically added. When the amount is more than the composition, it is sometimes referred to as excessive oxygen treatment.

[0160] In this manner, the oxide semiconductor film is dehydrated by dehydration treatment (dehydrogenation treatment). By removing oxygen and filling the oxygen vacancies with oxygen addition treatment, the i-type (intrinsic) or In such an oxide semiconductor film, the oxide semiconductor film can be almost i-type. In the 1×1 0 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / cm 3 less than 1.45×10 10 / cm 3 It will be less than.

[0161] In this way, the hydrogen concentration is sufficiently reduced and highly purified, and sufficient oxygen is supplied. The present invention provides an oxide semiconductor film having a reduced defect level in an energy gap caused by oxygen vacancies. For example, at room temperature (25°C), The off-state current (here, the value per unit channel width (1 μm)) is 100 zA (1 zA (Zeptoampere) is 1 x 10 -21 A) or less, preferably 10zA or less. At 85°C, it is 100zA (1×10 -19 A) or less, preferably 10zA (1×10 - 20 In this way, the oxide semiconductor that is i-type (intrinsic) or substantially i-type is By using a conductive film, a transistor with extremely excellent off-state current characteristics can be obtained.

[0162] Subsequently, the unnecessary portions of the semiconductor film are etched to form the semiconductor layer 125 and the dielectric layer 134. Complete.

[0163] The etching of the semiconductor film is preferably performed using a hard mask. An inorganic film that will later become a hard mask is formed on the semiconductor layer 125 and the dielectric layer 126 on the inorganic film. A resist is formed so as to overlap the region where 34 is to be formed. Then, ashing is performed to reduce the width of the resist, which is called slimming processing. It is preferable to minimize the width of the semiconductor layer 125 or the dielectric layer 134 by performing a slimming process. The semiconductor layer 125 and the dielectric layer 134 can therefore be When the width of the gate electrode layer 111a or the gate electrode layer 111b is formed at the minimum processing dimension F, However, it may be provided in the inner area.

[0164] The hard mask is obtained by etching the inorganic film in the area not covered by the resist. After the hard mask is formed, the resist may be removed.

[0165] The etching of the semiconductor film is highly anisotropic with respect to the areas not covered by the hard mask. In this case, the etching is performed by using an etching method. In this way, the columnar (including cylindrical and polygonal) The semiconductor layer 125 can be formed.

[0166] After that, the hard mask is removed. If the resist on the hard mask is not removed, In this case, the hard mask is removed after removing the resist.

[0167] Next, an insulating film is formed to cover the side and upper surfaces of the semiconductor layer 125. , which functions as the gate insulating layer 124. Therefore, the portion in contact with the side surface of the semiconductor layer 125 It is preferable that the insulating film is formed to have a uniform thickness. The insulating film can be formed by a deposition method such as a deposition method or a sputtering method. Impurities containing hydrogen atoms, such as water, hydrogen, and hydrogen compounds, are present in the semiconductor layer 125 and at the interface with the semiconductor layer 125. It is preferable that the amount of the ion exchange resin is sufficiently reduced.

[0168] Here, the insulating film is formed by high-density plating using microwaves (for example, at a frequency of 2.45 GHz). Zuma CVD is preferable because it can form a dense, high-quality insulating film with high dielectric strength. The contact between the highly purified oxide semiconductor and the high-quality gate insulating layer reduces the interface state. can be reduced to improve the interface characteristics.

[0169] Examples of the insulating film include silicon oxide, silicon nitride oxide, silicon oxynitride, silicon nitride, and hafnium oxide. tungsten, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate ( HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate (HfS i x O y N z (x>0, y>0, z>0)), nitrogen doped hafnium aluminate (HfAl x O y N z (x>0, y>0, z>0)) etc., in a single layer or laminated form. It can be formed by

[0170] A schematic top view and a schematic cross-sectional view at this stage correspond to Figs. 7(A) and (B), respectively. do.

[0171] Next, a conductive film that will become the wiring layer 201 is formed on the insulating film that constitutes the gate insulating layer 124. Then, an unnecessary portion of the conductive film is etched. Next, the insulating film that will later become the insulating layer 212b is formed. Next, the semiconductor layer 125 and the dielectric layer 134 are By performing a planarization process so that the upper surface of the wiring layer 201 and the insulating layer 212b are exposed, is formed.

[0172] The conductive film that becomes the wiring layer 201 is formed on the gate electrode layer 111a and the gate electrode layer 111b. The conductive layer 202 may be formed by the same material and method as the conductive layer 203. The same applies to the conductive films used for the wiring layer 203a, the wiring layer 203b, and the wiring layer 204.

[0173] The insulating film constituting the insulating layer 212b is made of the same material as the insulating film used for the insulating layer 212a. In the following, the insulating layer 212c, the insulating layer 212d, the insulating layer 212 The same applies to the insulating films used for the insulating layers 212e, 212f, 212g, and 212h.

[0174] Next, the semiconductor layer 125, the dielectric layer 134, the gate insulating layer 124, the wiring layer 201, and the insulating layer 134 are formed. An insulating film that will become the insulating layer 212c is formed on the edge layer 212b. c) forming an opening reaching the semiconductor layer 125 or the dielectric layer 134 in the insulating film; As a result, the insulating layer 212c is formed.

[0175] Next, a conductive film that will later become the wiring layer 202 or the electrode layer 122 is formed on the semiconductor layer 125, the dielectric layer 126, and the like. A conductive film is then formed on the layer 134 and the insulating layer 212c. The unnecessary portions of the conductive film are then etched away. By this, the wiring layer 202 and the electrode layer 122 are formed.

[0176] Through the above steps, a transistor 1 is formed on the gate electrode layer 111a of the transistor 101a. At the same time, the gate electrode layer of the transistor 101b is formed. A transistor 102b and a capacitor 103b are formed on 111b.

[0177] A schematic top view and a schematic cross-sectional view at this stage correspond to Figs. 8(A) and (B), respectively. do.

[0178] Subsequently, a layer that becomes an insulating layer 212d is formed on the wiring layer 202, the electrode layer 122, and the insulating layer 212c. An insulating film is formed. Then, the insulating film is flattened so that the upper surfaces of the wiring layer 202 and the electrode layer 122 are exposed. By carrying out the chemical treatment, an insulating layer 212d is formed.

[0179] Subsequently, an insulating film that will become the insulating layer 212e is deposited to form the insulating layer 212e.

[0180] Next, an opening is formed in the insulating layer 212e so as to reach the electrode layer 122. A conductive film that will become a connection electrode layer 213a is formed on the electrode layer 122 and the insulating layer 212. By performing a planarization process so that the top surface of the electrode layer 122 is exposed, A connecting electrode layer 213a is formed.

[0181] At the same time, the insulating layer 212e, the insulating layer 212d, the insulating layer 212c, and the insulating layer 21 2b, the insulating film constituting the gate insulating layer 124, and the insulating layer 212a, the first electrode layer 11 2a or the first electrode layer 112b, an opening is formed. A connection electrode layer 213c (see FIG. 4) electrically connected to the first electrode layer 112a or the first electrode layer 112b. ) is formed.

[0182] Next, a wiring layer is formed on the insulating layer 212e, the connection electrode layer 213a, and the connection electrode layer 213c. After forming the conductive film that will become the wiring layer 203a and the wiring layer 203b, unnecessary portions of the conductive film are removed by etching. By performing the step of etching, the wiring layer 203a and the wiring layer 203b are formed.

[0183] Thereafter, an insulating layer 212f is formed on the insulating layer 212e, the wiring layer 203a, and the wiring layer 203b. After forming the insulating film, the insulating film is flattened so that the upper surfaces of the wiring layer 203a and the wiring layer 203b are exposed. An insulating layer 212f is formed by carrying out a flattening process.

[0184] Next, an insulating layer 212g is formed on the insulating layer 212f, the wiring layer 203a, and the wiring layer 203b. An insulating film is then formed to form an insulating layer 212g.

[0185] Next, the insulating layer 212g, the insulating layer 212f, the insulating layer 212e, the insulating layer 212d, and the insulating layer 212c, the insulating layer 212b, the insulating film constituting the gate insulating layer 124, and the insulating layer 212a An opening (not shown) is then formed in the insulating layer 2 so as to reach the second electrode layer 113. A conductive film that will become the connection electrode layer 213b is formed on the insulating layer 212g and the second electrode layer 113. The upper surface of 12g is exposed by planarization, so that the second electrode layer 113 and the Then, a connection electrode layer 213b (not shown) is formed to electrically connect the electrodes (see FIG. 4(C)).

[0186] Next, the wiring layer 204 and the connection electrode layer 213b (not shown) are formed on the insulating layer 212g and the connection electrode layer 213b. After forming the conductive film, unnecessary portions of the conductive film are etched away to form a wiring layer. 204 is formed (see FIG. 4(C)).

[0187] After that, an insulating layer 212h may be formed to cover the insulating layer 212g and the wiring layer 204. After forming the insulating film that will become the insulating layer 212h, the upper surface of the insulating film is flattened by a flattening process. The insulating layer 212h may be formed by flattening.

[0188] A schematic top view and a schematic cross-sectional view at this stage correspond to Figs. 9(A) and (B), respectively. do.

[0189] Through the above steps, the memory element 110a and the memory element 110b shown in the configuration example of this embodiment are A memory device including 10b can be manufactured.

[0190] Here, in the above, the semiconductor layer 125 and the dielectric layer 134 are formed using a hard mask. However, the semiconductor layer 125 and the dielectric layer 134 may be formed by a different method. A different manufacturing method from the above will be described below with reference to FIG.

[0191] First, the transistor 101a and the insulating layer 212a are formed in the same manner as described above.

[0192] Next, an insulating layer 212i and a wiring layer 20 are formed on the insulating layer 212a and the gate electrode layer 111a. The insulating layer 212i is formed by stacking conductive films that will become the gate electrode layer 111a. and the wiring layer 201.

[0193] Next, an opening reaching the gate electrode layer 111a is formed in the conductive film and the insulating layer 212i. A schematic cross-sectional view at this stage corresponds to FIG. 10(A).

[0194] Next, an insulating layer that will later become the gate insulating layer 124 is formed so as to contact the side and bottom surfaces of the opening. Alternatively, the upper and side surfaces of the conductive film may be oxidized to form an insulating film. .

[0195] Thereafter, the insulating film is subjected to a highly anisotropic etching process to form the conductive film. The upper surfaces of the film and the gate electrode layer 111a are exposed, and the insulating film is left only on the side wall of the opening. In this manner, the gate insulating layer 124 is formed in contact with the side wall of the opening. This can be done.

[0196] Next, a gate insulating layer 124 is formed on the conductive film and the gate electrode layer 111a. A semiconductor film that will become the semiconductor layer 125 and the dielectric layer 134 is then formed on the conductive film. By performing a planarization process so that the surface is exposed, the semiconductor layer 125 and the dielectric layer are formed in the opening. A cross-sectional schematic diagram at this stage corresponds to FIG. do.

[0197] Next, the conductive film, the gate insulating layer 124, the semiconductor layer 125, and the upper surface of the dielectric layer 134 are A resist is formed on the conductive film, and unnecessary portions of the conductive film are etched to form the wiring layer 201. Form.

[0198] Thereafter, an insulating film that will become the insulating layer 212b is formed, and the wiring layer 201, the semiconductor layer 125, the dielectric layer 212b, and the like are formed. A planarization process is performed so that the top surfaces of the layer 134 and the gate insulating layer 124 are exposed. Then, an insulating layer 212b is formed. The schematic cross-sectional view at this stage corresponds to FIG.

[0199] Thereafter, the insulating layer 212c, the electrode layer 122, and the wiring layer 202 are formed according to the above-mentioned method. The schematic cross-sectional view at this stage corresponds to FIG. 10(D).

[0200] Through the above steps, a transistor 102a and a capacitor 103a are formed on the transistor 101a. It can be formed.

[0201] By using this method, the gate can be reliably formed without using slimming processing. The semiconductor layer 125 and the dielectric layer 134 may be formed in the inner region of the electrode layer 111a. .

[0202] This concludes the description of this example of the manufacturing process.

[0203] <Modification> In the following, we will fabricate a memory device using a thin film of insulating material as the dielectric layer of the capacitor, as shown in Figure 5. An example of the method will be described with reference to the drawings. Explanation of duplicated parts will be omitted.

[0204] 11A to 11C are schematic cross-sectional views of this modified example at each stage.

[0205] First, the transistor 101a is formed by the method described in the above example of the manufacturing process.

[0206] Next, the semiconductor layer 125 is formed on the gate electrode layer 111a. In the previous example, the dielectric layer 134 was formed of the same material as the semiconductor layer 125 at the same time. Note that this does not result in

[0207] Next, an insulating film that constitutes the gate insulating layer 124 is formed. A cross-sectional schematic diagram at this stage is shown in FIG. )

[0208] Next, in the process of forming the wiring layer 201, the wiring By forming an island-shaped pattern made of the same conductive film as the line layer 201, the electrode layer 132 In this way, an insulating film is formed between the gate electrode layer 111a and the electrode layer 132. A capacitor 103a can be formed with the dielectric layer 134 sandwiched therebetween. The schematic diagram of the surface corresponds to FIG. 11(B).

[0209] Next, the insulating layer 212b and the insulating layer 212c are formed. Then, the insulating layer 212c is When forming an opening reaching the conductor layer 125, an opening reaching the electrode layer 132 is also formed at the same time. Form.

[0210] Next, the electrode layer 122 and the wiring layer 202 are formed. The wiring layer 202 is provided on the insulating layer 212c. An electrical connection is made to the electrode layer 132 through the opening. corresponds to FIG. 11(C).

[0211] From this point on, the process is carried out based on the above-mentioned example of the manufacturing process to form the dielectric layer 134. A memory device including a capacitor 103 to which an insulating film is applied can be fabricated.

[0212] According to this method, it is possible to form a vertical transistor without increasing the number of photomasks or the manufacturing process. Since the capacitor can be fabricated at the same time as the resistor, memory devices can be manufactured at low cost and with high yield. You can create a device.

[0213] This concludes the description of this modified example.

[0214] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0215] (Embodiment 3) In this embodiment, as an example of a semiconductor device according to one embodiment of the present invention, a semiconductor device different from that in the above embodiment will be described. An example of the configuration of the storage device will be described with reference to the drawings. For the parts that overlap with the above description, the explanation will be omitted or will be simplified.

[0216] FIG. 12A is a circuit diagram of a main part of a memory device exemplified in this embodiment.

[0217] The memory device includes a transistor 101 , a transistor 102 , and a capacitor 103 .

[0218] In addition, a first electrode of the transistor 101 and a first electrode of the transistor 102 are electrically connected to each other. a wiring S1 electrically connected to a second electrode of the transistor 101; A wiring W1 connected to the gate of the transistor 102 is electrically connected to one electrode of the capacitor 103. and a wiring W2.

[0219] FIG. 12(B) is a schematic top view of the memory device exemplified in this embodiment. 12(C) is a schematic cross-sectional view taken along line DD' in FIG. 12(B).

[0220] The memory device shown in FIG. 12B and FIG. 12C is the same as the memory device exemplified in the second embodiment. 1, the transistor 101 is replaced with a vertical transistor.

[0221] The memory device includes a wiring layer 204 provided on an insulating surface, and a vertical A transistor 101 which is a type transistor, and a gate electrode layer 11 of the transistor 101 A transistor 102 and a capacitor 103 are provided on the same substrate 1, and a gate voltage of the transistor 102 is A wiring layer 201 that functions as one electrode of the capacitor 103 and a wiring layer 202 that functions as one electrode of the capacitor 103. and a transistor 101 and a capacitor 103 are provided on the transistor 101 and the capacitor 103. and a wiring layer 203 electrically connected to the sta 102.

[0222] The wiring layer 201 functions as the wiring W1 shown in FIG. The wiring layer 203 functions as the wiring S1, and the wiring layer 204 functions as the wiring S2. 2. The gate electrode layer 111 corresponds to a storage node.

[0223] As shown in FIG. 12B and FIG. 12C, the wiring layer 204 is Since the wiring layer 204 and the wiring layer 203 can be provided in a layer below the wiring layer 203, the wiring layer 204 and the wiring layer 203 can be provided in a layer below the wiring layer 203. At this time, the wiring layer 204 and the wiring layer 203 are provided with the transistor 101. The layer in which the transistor 102 and the capacitor 103 are provided is formed through the layer in which the transistor 102 and the capacitor 103 are provided. Therefore, the distance between these wiring layers can be sufficiently large. Therefore, the capacitance between the wiring layers can be ignored. In this way, by forming two wiring layers one on top of the other, This allows the area occupied by the storage device to be extremely small.

[0224] In FIG. 12C, the gate electrode layer 111 and the wiring layer 204 are connected to the gate insulating layer 114. The gate electrode layer 111 and the insulating film forming the gate electrode 112 are electrically insulated from each other. An insulating layer may be separately formed between the line layer 204 to reduce the capacitance therebetween. The wiring layer 204 and the second electrode layer 113 are connected by a connection electrode layer penetrating the insulating layer. The above configuration may be adopted.

[0225] The transistor 101 is provided over a wiring layer 204 and is electrically connected to the wiring layer 204. a second electrode layer 113 that is connected to the second electrode layer 113; a semiconductor layer 115 electrically connected to the semiconductor layer 11; 5, a first electrode layer 112 electrically connected to the semiconductor layer 115, the first electrode layer 112, and and a gate insulating layer 114 provided in contact with the side surface of the second electrode layer 113; and a gate electrode layer 111 provided opposite the side surface of the channel layer 115. The direction is perpendicular to the insulating surface.

[0226] The semiconductor layer 115 is made of an amorphous semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or the like. It is possible.

[0227] A typical example of an amorphous semiconductor is hydrogenated amorphous silicon. A typical example of a polycrystalline semiconductor is polysilicon (polycrystalline silicon). Polysilicon is mainly made of polysilicon that is formed through a process temperature of 800℃ or higher. The so-called high-temperature polysilicon used as the material and the polysilicon formed at a process temperature of 600°C or less were used. The main material is silicon, which is called low-temperature polysilicon, and elements that promote crystallization. It contains polysilicon, which is made by crystallizing amorphous silicon using a silicon nitride. A crystalline semiconductor or a semiconductor layer partially containing a crystalline phase can also be used.

[0228] The semiconductor layer 115 may be formed using the above-mentioned oxide semiconductor. In this case, the first electrode layer 112 and the second electrode layer 113 do not need to be provided.

[0229] The transistor 101 is formed by using the above-mentioned method for manufacturing the transistor 102. At this time, instead of the single layer of semiconductor constituting the semiconductor layer 125, a second electrode The semiconductor film to which an impurity is added that constitutes the pole layer 113 and the semiconductor that constitutes the semiconductor layer 115 The first electrode layer 112 is made of a semiconductor film containing an impurity. In this way, the transistor 101 can be formed.

[0230] The transistor 102 and the capacitor 103 may have the structures exemplified in the above embodiment. can.

[0231] In this way, by making the transistor 101 a vertical transistor, Ta 101 to F 2 Similarly, the transistor 102 and the capacitor The amount of 103 is also F 2 This allows the device to be highly integrated within a small area. Even in this case, it is possible to realize a storage device with an extremely reduced occupied area.

[0232] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0233] (Embodiment 4) In this embodiment, as an example of a semiconductor device according to one embodiment of the present invention, a semiconductor device different from that in the above embodiment will be described. An example of the configuration of the storage device will be described with reference to the drawings. For the parts that overlap with the above description, the explanation will be omitted or will be simplified.

[0234] A memory device according to one embodiment of the present invention includes a first transistor 101 and a second transistor 102. A layer of a memory device (or a layer of a semiconductor device) having a capacitance 103. Hereinafter, the memory layer By stacking multiple layers of semiconductor devices, it is possible to achieve a high degree of integration. A driving circuit may be provided below the memory layer. An example of a structure in which a memory layer is layered and a structure in which a driver circuit is provided below a memory layer will be described.

[0235] <Configuration example 1> The top view of the storage device exemplified in this configuration example is shown in FIG. 3B. -A' and a schematic cross-sectional view taken along line B-B' correspond to FIG.

[0236] The memory device is formed on an insulating surface, and the transistor 101a and the transistor The difference is the configuration of the filter 101b in the second embodiment (for example, FIGS. 4A and 4B). It is different from a storage device.

[0237] The transistor 101a includes a semiconductor layer 115 formed on an insulating surface and a semiconductor layer 115 The first electrode layer 11 is provided in contact with the side surface of the semiconductor layer 115 and electrically connected to the semiconductor layer 115. 2a, the second electrode layer 113, and a gate insulating layer provided in contact with the upper surface of the semiconductor layer 115. 114 and a gate electrode layer 111a provided in contact with the upper surface of the gate insulating layer 114. can.

[0238] Similarly, the transistor 101b includes a semiconductor layer 115, a first electrode layer 112b, and a second The semiconductor device further comprises an electrode layer 113, a gate insulating layer 114, and a gate electrode layer 111b.

[0239] In addition, the element isolation layer 211 is disposed between the semiconductor layer 115, the first electrode layer 112a, and the first electrode layer 112b. 12b and the side surface of the second electrode layer 113.

[0240] The semiconductor layer 115 may be formed using any of the semiconductors exemplified in Embodiment 3. can be done.

[0241] In addition, a method for manufacturing an SOI substrate is preferably applied to the semiconductor used for the semiconductor layer 115. In addition, a single crystal semiconductor is used.

[0242] The method for producing SOI substrates is to implant oxygen ions into a mirror-polished wafer and then heat it at high temperature. By heating, an oxide layer is formed at a certain depth from the surface, and the oxide layer formed on the surface is A method of annihilating defects, by heat treatment of microvoids formed by hydrogen ion irradiation A method of cleaving a semiconductor substrate by using growth, or a method of growing a single crystal semiconductor on an insulating surface by crystal growth A method for forming a layer or the like can be used.

[0243] A transistor 102a and a capacitor 103a are provided on the gate electrode layer 111a. In addition, a transistor 102b and a capacitor 103b (not shown) are formed on the gate electrode layer 111b. is provided.

[0244] Here, at least a transistor 101a, a transistor 102a, and a capacitor 103a The layers constituting the memory layer 250 are collectively referred to as the memory layer 250. The memory layer 250 has a plurality of memory devices arranged in parallel in a direction parallel to the growth surface. includes a wiring layer that electrically connects transistors and capacitors.

[0245] In this manner, the transistor 101a and the transistor 101b can be formed on an insulating surface. By making it possible to stack multiple memory layers 250 or to stack a memory layer 250 under the memory layer 250, This allows the layer to be provided with a driving circuit.

[0246] FIG. 14 shows a memory cell 260 formed by a conventional CMOS process. 2 shows the configuration of a storage device in which a storage layer 250a and a memory layer 250b are stacked.

[0247] The memory layer 250a is provided on the drive circuit section 260 via an interlayer insulating layer 251a. The memory layer 250b is provided on the memory layer 250a via an interlayer insulating layer 251b. It is being done.

[0248] The surfaces of the interlayer insulating layer 251a and the interlayer insulating layer 251b are planarized. In addition, it is preferable to use a memory layer 250a and the driving circuit section 260. In order to reduce the parasitic capacitance between the interlayer insulating layer 251a and the interlayer insulating layer 250b, It is preferable to use an insulating material with a low dielectric constant for 51b or to form it sufficiently thick. .

[0249] Each wiring layer included in the memory layer 250a and the memory layer 250b is The driving circuit section 260 is electrically connected via a connection electrode layer, and the driving circuit section 260 This controls operations such as writing, erasing, and reading data.

[0250] In this way, by using a configuration in which multiple memory layers are stacked, the occupied area of ​​the memory device can be reduced. The amount of data per pixel can be increased. In addition, the driving circuit is placed below the memory layer. This makes it possible to suppress an increase in the occupied area.

[0251] This concludes the description of this configuration example.

[0252] <Modification> In addition, a vertical transistor is used as the transistor 101 in the example of Embodiment 3. In this case, multiple memory layers can be stacked as in the above configuration example, and a driving circuit can be placed on the lower layer. It is possible to provide.

[0253] FIG. 15 shows a memory device in which a vertical transistor is used as the transistor 101. An example of the configuration is shown below.

[0254] As in the above configuration example, the memory layer 250a is connected to the drive circuit section 2 via the interlayer insulating layer 251a. The memory layer 250b is provided on the memory cell 60 via an interlayer insulating layer 251b. The insulating layer 250a is provided on the insulating layer 250b.

[0255] Here, the memory layer 250a and the memory layer 250b are A storage device with a significantly reduced area is applied. By stacking multiple layers, the amount of data per unit area can be made extremely large. can be done.

[0256] This concludes the description of this modified example.

[0257] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0258] (Embodiment 5) As an example of an oxide semiconductor that can be used for the semiconductor layer 125 in the above embodiment, The use of a semiconductor film having such a structure can improve the electrical characteristics of a transistor. The membrane was CAAC-OS (C Axis Aligned Crystalline O It is preferable to use a CAA A semiconductor device to which a C-OS film is applied will be described.

[0259] The CAAC-OS film is neither completely single crystalline nor completely amorphous. The film is an oxide semiconductor film with a crystalline-amorphous mixed phase structure having a crystalline part and an amorphous part in the amorphous phase. The crystal part must be small enough to fit within a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by a microscope, the amorphous part and the The boundary between the crystal and the crystalline part is not clear. Therefore, the CAAC-OS film does not have any in-boundary defects. The resulting decrease in electron mobility is suppressed.

[0260] The crystal parts in the CAAC-OS film have c-axes that are normal vectors to the surface on which the CAAC-OS film is formed. The three are aligned parallel to the normal vector of the torus or surface and perpendicular to the ab plane. It has a square or hexagonal atomic arrangement, and the metal atoms are arranged in layers or in a layered fashion when viewed perpendicular to the c-axis. In the crystal structure, metal atoms and oxygen atoms are arranged in layers. The direction of the a and b axes may be different. In this specification, when it is simply described as being vertical, The range of 85° to 95° is also included. The range of 5° or more and 5° or less is also included.

[0261] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the AC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the formation surface. By adding impurities to the AAC-OS film, the crystal part becomes non-crystalline in the impurity-added region. It may also crystallize.

[0262] The c-axis of the crystal part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The shape of the CAAC-OS film (the shape of the film) is Depending on the cross-sectional shape of the mating surface or the cross-sectional shape of the surface, they may face in different directions. The direction of the c-axis of the crystal part is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the crystal or the surface. Alternatively, it is formed by carrying out a crystallization treatment such as a heat treatment after the film is formed.

[0263] The electrical characteristics of transistors using CAAC-OS films change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0264] Note that part of oxygen contained in the oxide semiconductor film may be replaced with nitrogen.

[0265] In addition, in oxide semiconductors with crystalline parts such as CAAC-OS, defects in the bulk are reduced. By improving the flatness of the surface, the transfer rate can be reduced to a level equal to or greater than that of an amorphous oxide semiconductor. In order to improve the flatness of the surface, an oxide semiconductor is formed on the flat surface. Specifically, it is preferable to form a surface having an average surface roughness (Ra) of 1 nm or less, and preferably It is advisable to form it on the surface with a thickness of 0.3 nm or less, more preferably 0.1 nm or less.

[0266] In addition, Ra is defined in JIS B 0601:2001 (ISO4287:1997). It is a three-dimensional extension of the arithmetic mean roughness defined above so that it can be applied to curved surfaces. It can be expressed as "the average of the absolute values ​​of the deviation from the reference surface to the specified surface" and is given by the following formula (1): is defined.

[0267]

number

[0268] Here, the specified surface is the surface to be measured for roughness, and has coordinates (x1, y1, f(x1, y1)),(x1,y2,f(x1,y2)),(x2,y1,f(x2,y1)),( The specified surface is the xy plane, and the rectangular area is represented by four points, x2, y2, f(x2, y2), The area of ​​the rectangle projected onto the surface is S0, and the height of the reference surface (the average height of the specified surface) is Z0. a is taken with an atomic force microscope (AFM). It is measurable.

[0269] As a method for obtaining the above-mentioned CAAC-OS film, for example, a method for forming the CAAC-OS film by heating a substrate (e.g. The oxide semiconductor film was formed with the substrate temperature at 170° C., and the c-axis orientation was approximately perpendicular to the surface. There is a way to make it happen.

[0270] Note that the oxide semiconductor film may have a structure in which a plurality of oxide semiconductor films are stacked. Either the oxide semiconductor film or the second oxide semiconductor film has a crystal structure different from that of the CAAC-OS. That is, a CAAC-OS and a single-crystal oxide semiconductor may be used. , a polycrystalline oxide semiconductor, or an amorphous oxide semiconductor may be appropriately combined. In addition, at least one of the first oxide semiconductor film and the second oxide semiconductor film is amorphous. By applying a high-temperature oxide semiconductor, the internal stress and external stress of the stacked oxide semiconductor film can be reduced. This reduces the variation in transistor characteristics and further improves the reliability of the transistor. On the other hand, amorphous oxide semiconductors have impurities that act as donors, such as hydrogen. It is easy to absorb oxygen and oxygen vacancies occur easily, so it is easy to become n-type. The oxide semiconductor film on the insulating layer side is made of a crystalline oxide semiconductor such as CAAC-OS. It is preferable.

[0271] In addition, the oxide semiconductor film has a stacked structure of three or more layers, and the oxide semiconductor film has crystallinity. The amorphous oxide semiconductor film may be sandwiched between two insulating films. Alternatively, the oxide semiconductor film may be formed by stacking an amorphous oxide semiconductor film and an amorphous oxide semiconductor film alternately. When the above-mentioned structure is a laminated structure of a plurality of films, each of them may be appropriately combined and used. can be done.

[0272] As described above, by using the CAAC-OS film as the oxide semiconductor film, In the dehydrogenation process, hydrogen can be easily removed from the top surface of the CAAC-OS film. In addition, in the heat treatment, the desorption of oxygen is reduced and a large amount of hydrogen is selectively desorbed. It is possible.

[0273] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0274] (Embodiment 6) In this embodiment, the memory device disclosed in the above embodiment is used as an example of a semiconductor device. At least a part of the CPU (Central Processing Unit) I will explain it below.

[0275] FIG. 16A is a block diagram showing a specific configuration of a CPU. The CPU is provided on a board 1190 with an ALU 1191 (ALU: Arithmetic log ic unit, arithmetic circuit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bu s I / F), rewritable ROM 1199, and ROM interface 1189( The substrate 1190 may be a semiconductor substrate, an SOI substrate, or a glass substrate. The ROM 1199 and the ROM interface 1189 are provided on a separate chip. Of course, the CPU shown in FIG. 16(A) is an example showing a simplified configuration. In fact, CPUs have a wide variety of configurations depending on their applications.

[0276] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0277] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads or writes register 1196 depending on the CPU state. .

[0278] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. Supplied to various circuits.

[0279] In the CPU shown in FIG. 16A, a register 1196 and the like are provided with memory cells. The memory device shown in any one of the above-mentioned embodiments 1 to 4 can be used as the memory cell. The memory cell of the register 1196 includes a logic element for inverting a logical value and a The present invention is provided with both of the storage devices disclosed in.

[0280] In the CPU shown in FIG. 16A, the register controller 1197 controls the ALU 119 According to the instruction from 1, the holding operation in the register 1196 is selected. In the memory cell of the stator 1196, the data is inverted by a logic element that inverts the logical value. Select whether to hold the data or to hold the data in a storage device. Reverse the logical value. When the logic element is selected to hold data, the memory cell in the register 1196 When data retention in the storage device is selected, The data is rewritten to the storage device, and the power supply voltage to the memory cell in the register 1196 The supply of the product may be stopped.

[0281] Regarding the power supply shutdown, as shown in FIG. 16(B) or FIG. 16(C), , a switching element is provided between a node to which a power supply potential VDD or a power supply potential VSS is applied. The circuits in FIG. 16(B) and FIG. 16(C) are explained below. Make a statement.

[0282] In FIG. 16B and FIG. 16C, a resistor 1196 controls the supply voltage to the memory cell. A switching element is provided to control the supply.

[0283] The register 1196 shown in FIG. 16B includes a switching element 1141 and a memory cell 1 Specifically, each of the memory cells 11 The memory cell 42 includes both a logic element for inverting a logical value and the memory device described above. Each memory cell 1142 in the group 1143 is connected to a HA through a switching element 1141. A power supply potential VDD of the high level is supplied to each of the memory cell groups 1143. The memory cell 1142 is supplied with the potential of the signal IN and the potential of the low-level power supply potential VSS. It is being done.

[0284] In FIG. 16B, a transistor is used as the switching element 1141. The switching of the transistor is controlled by a signal SigA applied to its gate electrode. can be.

[0285] In FIG. 16B, the switching element 1141 has only one transistor. However, the present invention is not limited to this configuration, and a plurality of transistors may be included. In the case where the switching element 1141 has a plurality of transistors functioning as switching elements, In this case, the plurality of transistors may be connected in parallel or in series. Alternatively, a combination of series and parallel connections may be used.

[0286] In addition, in FIG. 16C, each memory cell 1142 included in the memory cell group 1143 is A low-level power supply potential VSS is supplied to the resistor 1141 via a switching element 1142. The switching element 1141 switches the memory cell group 1143. The supply of a low-level power supply potential VSS to each memory cell 1142 having the can.

[0287] Between the memory cell group and a node to which the power supply potential VDD or the power supply potential VSS is applied, When a switching element is installed and the CPU operation is temporarily stopped and the supply of power voltage is stopped, Even in this case, data can be retained, and power consumption can be reduced. Specifically, for example, a user of a personal computer may input a command using an input device such as a keyboard. The data in the memory cells can be read and written without loss even when the input of information to the The operation can be stopped, thereby reducing power consumption.

[0288] In addition, electronic devices that use such CPUs consume less power, e.g. For example, a relatively small amount of electricity can be obtained from solar cells or non-contact power supply (also called wireless power supply). For example, the electronic device can be operated by a solar cell module or a non-connected A touch-feed module and a secondary battery ( The configuration will include a lithium-ion battery.

[0289] Here, we have taken the CPU as an example, but the same can also be said for DSP (Digital Signal Processor), custom LSI, FPGA (Field Programmable Gate Array) It can also be applied to LSIs such as 3-D gate arrays.

[0290] (Embodiment 7) The memory device and semiconductor device disclosed in this specification can be used in various electronic devices (including gaming machines). The electronic devices include display devices such as televisions and monitors, lighting devices, Desktop or notebook personal computer, word processor, DVD (D Still images or images stored on a recording medium such as Digital Versatile Disc (DVSD) Video playback devices, portable CD players, radios, tape recorders, headsets, etc. Cordless telephone stereos, stereos, cordless telephone handsets, transceivers, portable radios, mobile phones , car phones, portable game consoles, calculators, personal digital assistants, electronic organizers, electronic books, electronic translators , voice input devices, video cameras, digital still cameras, electric shavers, microwave ovens, etc. High-frequency heating devices, electric rice cookers, electric washing machines, vacuum cleaners, air conditioners, etc. Cooking equipment, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, Electric refrigerators and freezers, freezers for storing DNA, smoke detectors, radiation detectors, dialysis machines, and other medical equipment In addition, emergency lights, traffic lights, conveyor belts, elevators, escalators, etc. Industrial equipment such as computers, industrial robots, and power storage systems are also included. Vehicles propelled by electric motors using power from engines and non-aqueous secondary batteries are also The above-mentioned mobile object is, for example, an electric vehicle (EV). , hybrid electric vehicles (HEVs) that combine an internal combustion engine and an electric motor, and plug-in hybrid vehicles (PHEV), tracked vehicles that use these tires and wheels as tracks, and electric-assist bicycles. Including motorized bicycles, motorcycles, electric wheelchairs, golf carts, small or large boats, submarines Navy ships, helicopters, aircraft, rockets, satellites, space probes, planetary probes, and spacecraft. Specific examples of these electronic devices are shown in Figs. 17 and 18.

[0291] FIG. 17A shows a portable music player. The main body 3021 has a display unit 3023 and a The device is provided with a fixing portion 3022 for mounting, an operation button 3024, an external connection port 3025, etc. The storage device exemplified in the above embodiment may also include a speaker. By applying the semiconductor device to the memory or CPU built in the main body 3021, This makes it possible to create a more power-efficient portable music player (PDA).

[0292] Furthermore, the portable music player shown in FIG. 17(A) may be equipped with an antenna, a microphone function, and a wireless function. In addition, by linking it with a mobile phone, you can enjoy wireless hands-free driving while driving a passenger car. Conversation by telephone is also possible.

[0293] FIG. 17B shows a computer, which includes a main body 9201 including a CPU, a housing 9202, a display 9203, keyboard 9204, external connection port 9205, pointing device 9 206, etc. By using the memory device or the semiconductor device such as the CPU described in the above embodiment, This makes it possible to realize a computer with reduced power consumption.

[0294] In FIG. 18A, a television device 8000 includes a housing 8001 and a display unit 8002. A display unit 8002 displays images and a speaker unit 8003 outputs audio. The memory device or the semiconductor device exemplified in the above embodiment can be packaged in a housing. The display unit 8002 can be used as a driver circuit for operating the display unit 8002 incorporated in the body 8001. It is.

[0295] The display unit 8002 is a light-emitting device having light-emitting elements such as a liquid crystal display device or an organic EL element in each pixel. Device, electrophoretic display device, DMD (Digital Micromirror Devi Semiconductor display devices such as LCD (LED) and PDP (Plasma Display Panel) can be used.

[0296] The television device 8000 may include a receiver, a modem, and the like. The device 8000 can receive general television broadcasts using a receiver, and also has a modem. By connecting to a wired or wireless communication network via The communication of information is carried out in a two-way manner (from sender to receiver, or between receivers, etc.) or in a two-way manner (between sender and receiver, or between receivers, etc.) It is also possible to do so.

[0297] The television device 8000 also includes a CPU and a memory for performing information communication. The television device 8000 may include the storage device exemplified in the above embodiment and the CP. It is possible to use semiconductor devices such as U.

[0298] In FIG. 18(A), an air conditioner having an indoor unit 8200 and an outdoor unit 8204 The CPU is an example of an electronic device using a semiconductor device such as the CPU described in the above embodiment. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CPU 8203, etc. In FIG. 18A, when the CPU 8203 is provided in the indoor unit 8200, However, the CPU 8203 may be provided in the outdoor unit 8204. In addition, a CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204 . By using the CPU exemplified in the above embodiment, a power-saving air conditioner can be This can be achieved.

[0299] In FIG. 18A, an electric refrigerator-freezer 8300 includes the CPU exemplified in the above embodiment. The electronic device is an example of an electronic device including the semiconductor device. , a housing 8301, a door for a refrigerator compartment 8302, a door for a freezer compartment 8303, a CPU 8304, etc. In FIG. 18A, a CPU 8304 is provided inside a housing 8301. The semiconductor device such as the CPU illustrated in the embodiment is a CPU 8304 of an electric refrigerator-freezer 8300. By using this, power consumption can be reduced.

[0300] 18B and 18C show an example of an electric vehicle, which is an example of an electronic device. The electric vehicle 9700 is equipped with a secondary battery 9701. The power output is adjusted by a control circuit 9702 and is supplied to a driving device 9703. The control circuit 9702 is controlled by a processing unit 9704 having a ROM, RAM, CPU, etc. (not shown). The semiconductor device such as the memory device or CPU exemplified in the above embodiment is controlled by the electric self-control. By using it in the processing device 9704 of the vehicle 9700, power saving can be achieved.

[0301] The driving device 9703 is a DC motor or an AC motor alone, or a motor and an internal combustion engine, The processing device 9704 is configured by combining the above. Information on driving (such as acceleration, deceleration, stopping, etc.) and information on driving (such as uphill and downhill slopes, Based on input information (load information, etc.), a control signal is output to the control circuit 9702. 9702 controls the power supplied from the secondary battery 9701 in response to a control signal from the processor 9704. The energy is adjusted to control the output of the drive unit 9703. If an AC motor is installed, In this case, although not shown, an inverter for converting direct current to alternating current is also built in.

[0302] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done. [Explanation of symbols]

[0303] 101 Transistor 101a Transistor 101b Transistor 102 Transistor 102a Transistor 102b Transistor 103 capacity 103a capacity 103b capacity 110a Memory element 110b Memory element 111 Gate electrode layer 111a Gate electrode layer 111b Gate electrode layer 112 First electrode layer 112a First electrode layer 112b First electrode layer 113 Second electrode layer 114 Gate insulating layer 115 Semiconductor layer 121 Gate electrode layer 122 Electrode layer 124 Gate Insulation Layer 125 Semiconductor Layer 132 Electrode layer 134 Dielectric Layer 201 Wiring layer 202 Wiring layer 203 Wiring layer 203a wiring layer 203b Wiring layer 204 Wiring layer 211 Element isolation layer 212a Insulating layer 212b Insulating layer 212c Insulating layer 212d Insulating layer 212e Insulating layer 212f Insulation layer 212g insulation layer 212h Insulation layer 212i Insulation layer 213a Connection electrode layer 213b Connection electrode layer 213c Connection electrode layer 250 Memory Tier 250a Memory Tier 250b memory layer 251a Interlayer insulation layer 251b Interlayer insulation layer 260 Drive circuit section 1141 Switching element 1142 memory cell 1143 Memory Cell Group 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 3021 Main unit 3022 Fixed part 3023 Display section 3024 Operation button 3025 External connection port 8000 Television Equipment 8001 Case 8002 Display section 8003 Speaker section 8200 indoor unit 8201 Case 8202 Ventilator 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Case 8302 Refrigerator door 8303 Freezer door 8304 CPU 9201 Main unit 9202 Case 9203 Display section 9204 Keyboard 9205 External connection port 9206 Pointing Device 9700 Electric Vehicle 9701 Secondary battery 9702 Control circuit 9703 Drive unit 9704 Processing Equipment

Claims

1. A memory cell group is included. The memory cell group includes a plurality of memory cells, The memory cell includes a logic element that inverts a logical value and a memory device, The storage device includes: A first transistor; a second transistor disposed above the first transistor; a first insulating layer; a gate electrode of the first transistor is electrically connected to a retention node; one of a source electrode and a drain electrode of the second transistor is electrically connected to the retention node; The second transistor is an oxide semiconductor layer having a channel formation region; a gate electrode layer having a region facing the oxide semiconductor layer with the first insulating layer interposed therebetween; a first electrode layer functioning as one of the source electrode and the drain electrode; a second electrode layer functioning as the other of the source electrode and the drain electrode; the first insulating layer has a region in contact with the oxide semiconductor layer, the first insulating layer has a region that functions as a gate insulating layer of the second transistor; The second transistor is a vertical transistor.

2. A memory cell group is included. The memory cell group includes a plurality of memory cells, The memory cell includes a logic element that inverts a logical value and a memory device, The storage device includes: A first transistor; a second transistor disposed above the first transistor; a first insulating layer; a gate electrode of the first transistor is electrically connected to a retention node; one of a source electrode and a drain electrode of the second transistor is electrically connected to the retention node; The second transistor is an oxide semiconductor layer having a channel formation region; a gate electrode layer having a region facing the oxide semiconductor layer with the first insulating layer interposed therebetween; a first electrode layer functioning as one of the source electrode and the drain electrode; a second electrode layer functioning as the other of the source electrode and the drain electrode; the first insulating layer has a region in contact with the oxide semiconductor layer, the first insulating layer has a region that functions as a gate insulating layer of the second transistor; the first insulating layer of the second transistor has a cylindrical region; The second transistor is a vertical transistor.

3. A memory cell group is included. The memory cell group includes a plurality of memory cells, The memory cell includes a logic element that inverts a logical value and a memory device, The storage device includes: A first transistor; a second transistor disposed above the first transistor; Capacity and a first insulating layer; a gate electrode of the first transistor is electrically connected to a retention node; one of a source electrode and a drain electrode of the second transistor is electrically connected to the retention node; one electrode of the capacitance is electrically connected to the retention node; The second transistor is an oxide semiconductor layer having a channel formation region; a gate electrode layer having a region facing the oxide semiconductor layer with the first insulating layer interposed therebetween; a first electrode layer functioning as one of the source electrode and the drain electrode; a second electrode layer functioning as the other of the source electrode and the drain electrode; the first insulating layer has a region in contact with the oxide semiconductor layer, the first insulating layer has a region that functions as a gate insulating layer of the second transistor; The second transistor is a vertical transistor.

4. A memory cell group is included. The memory cell group includes a plurality of memory cells, The memory cell includes a logic element that inverts a logical value and a memory device, The storage device includes: A first transistor; a second transistor disposed above the first transistor; Capacity and a first insulating layer; a gate electrode of the first transistor is electrically connected to a retention node; one of a source electrode and a drain electrode of the second transistor is electrically connected to the retention node; one electrode of the capacitance is electrically connected to the retention node; The second transistor is an oxide semiconductor layer having a channel formation region; a gate electrode layer having a region facing the oxide semiconductor layer with the first insulating layer interposed therebetween; a first electrode layer functioning as one of the source electrode and the drain electrode; a second electrode layer functioning as the other of the source electrode and the drain electrode; the first insulating layer has a region in contact with the oxide semiconductor layer, the first insulating layer has a region that functions as a gate insulating layer of the second transistor; the first insulating layer of the second transistor has a cylindrical region; The second transistor is a vertical transistor.

5. A memory cell group is included. The memory cell group includes a plurality of memory cells, The memory cell includes a logic element that inverts a logical value and a memory device, The storage device includes: A first transistor; a second transistor disposed above the first transistor; a first insulating layer; a gate electrode of the first transistor is electrically connected to a retention node; one of a source electrode and a drain electrode of the second transistor is electrically connected to the retention node; The second transistor is an oxide semiconductor layer having a channel formation region; a gate electrode layer having a region facing the oxide semiconductor layer with the first insulating layer interposed therebetween; a first electrode layer functioning as one of the source electrode and the drain electrode; a second electrode layer functioning as the other of the source electrode and the drain electrode; the first insulating layer has a region in contact with the oxide semiconductor layer, the first insulating layer has a region that functions as a gate insulating layer of the second transistor; the second transistor is a vertical transistor, data is written to the retention node via the second transistor; The data is held in the holding node by turning off the second transistor.

6. A memory cell group is included. The memory cell group includes a plurality of memory cells, The memory cell includes a logic element that inverts a logical value and a memory device, The storage device includes: A first transistor; a second transistor disposed above the first transistor; a first insulating layer; a gate electrode of the first transistor is electrically connected to a retention node; one of a source electrode and a drain electrode of the second transistor is electrically connected to the retention node; The second transistor is an oxide semiconductor layer having a channel formation region; a gate electrode layer having a region facing the oxide semiconductor layer with the first insulating layer interposed therebetween; a first electrode layer functioning as one of the source electrode and the drain electrode; a second electrode layer functioning as the other of the source electrode and the drain electrode; the first insulating layer has a region in contact with the oxide semiconductor layer, the first insulating layer has a region that functions as a gate insulating layer of the second transistor; the first insulating layer of the second transistor has a cylindrical region; the second transistor is a vertical transistor, data is written to the retention node via the second transistor; The data is held in the holding node by turning off the second transistor.

7. A memory cell group is included. The memory cell group includes a plurality of memory cells, The memory cell includes a logic element that inverts a logical value and a memory device, The storage device includes: A first transistor; a second transistor disposed above the first transistor; Capacity and a first insulating layer; a gate electrode of the first transistor is electrically connected to a retention node; one of a source electrode and a drain electrode of the second transistor is electrically connected to the retention node; one electrode of the capacitance is electrically connected to the retention node; The second transistor is an oxide semiconductor layer having a channel formation region; a gate electrode layer having a region facing the oxide semiconductor layer with the first insulating layer interposed therebetween; a first electrode layer functioning as one of the source electrode and the drain electrode; a second electrode layer functioning as the other of the source electrode and the drain electrode; the first insulating layer has a region in contact with the oxide semiconductor layer, the first insulating layer has a region that functions as a gate insulating layer of the second transistor; the second transistor is a vertical transistor, data is written to the retention node via the second transistor; The data is held in the holding node by turning off the second transistor.

8. A memory cell group is included. The memory cell group includes a plurality of memory cells, The memory cell includes a logic element that inverts a logical value and a memory device, The storage device includes: A first transistor; a second transistor disposed above the first transistor; Capacity and a first insulating layer; a gate electrode of the first transistor is electrically connected to a retention node; one of a source electrode and a drain electrode of the second transistor is electrically connected to the retention node; one electrode of the capacitance is electrically connected to the retention node; The second transistor is an oxide semiconductor layer having a channel formation region; a gate electrode layer having a region facing the oxide semiconductor layer with the first insulating layer interposed therebetween; a first electrode layer functioning as one of the source electrode and the drain electrode; a second electrode layer functioning as the other of the source electrode and the drain electrode; the first insulating layer has a region in contact with the oxide semiconductor layer, the first insulating layer has a region that functions as a gate insulating layer of the second transistor; the first insulating layer of the second transistor has a cylindrical region; the second transistor is a vertical transistor, data is written to the retention node via the second transistor; The data is held in the holding node by turning off the second transistor.

9. In any one of claims 3, 4, 7 and 8, a third electrode layer functioning as the other electrode of the capacitance has a region whose outer periphery in a plane parallel to the surface of the first electrode layer is circular or rectangular.

10. In any one of claims 1 to 4, data is written to the retention node via the second transistor; The data is held in the hold node when the second transistor is turned off and power supply is stopped.

11. In any one of claims 1 to 10, a second insulating layer; the second insulating layer has a region in contact with an upper surface of the first electrode layer, the first insulating layer has a region in contact with an upper surface of the first electrode layer and a region in contact with a side surface of the second insulating layer, The gate electrode layer has a region above the second insulating layer.

12. In any one of claims 1 to 11, A third insulating layer is provided. the third insulating layer has a region provided above the gate electrode layer, the second electrode layer has a region in contact with an upper surface of the third insulating layer; the second electrode layer has a region in contact with the oxide semiconductor layer, the second electrode layer has a region overlapping with the gate electrode layer in a plan view.

13. In any one of claims 1 to 12, a region where the oxide semiconductor layer and the first electrode layer are in contact with each other is provided in a region inside a periphery of the first electrode layer when viewed from above.

14. In any one of claims 1 to 13, the gate electrode layer of the second transistor has a region surrounding the oxide semiconductor layer in a top view.

15. In any one of claims 1 to 14, The second electrode layer is provided above the first electrode layer.

16. In any one of claims 1 to 15, The second electrode layer has a region overlapping with the first electrode layer in a top view.

17. In any one of claims 1 to 16, the gate electrode layer of the second transistor has a region between the first electrode layer and the second electrode layer in a cross-sectional view.

18. In any one of claims 1 to 17, a channel formation region of the second transistor having a region overlapping with a channel formation region of the first transistor.

19. In any one of claims 1 to 18, the oxide semiconductor layer has an i-type or substantially i-type region.

20. In any one of claims 1 to 19, The oxide semiconductor layer has a crystal part, the crystal portion has a c-axis aligned in a direction parallel to a normal vector of a surface on which the oxide semiconductor layer is formed.

21. In claim 20, The parallel direction includes an angle between the normal vector and the c-axis in the range of -5° to 5°.

22. In any one of claims 1 to 21, The oxide semiconductor layer may be formed of any one of the following oxides: indium oxide, tin oxide, zinc oxide, In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, In-Ga-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, In-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, A semiconductor device having any one of an In-Gd-Zn based oxide, an In-Tb-Zn based oxide, an In-Dy-Zn based oxide, an In-Ho-Zn based oxide, an In-Er-Zn based oxide, an In-Tm-Zn based oxide, an In-Yb-Zn based oxide, an In-Lu-Zn ​​based oxide, an Al-Ga-Zn based oxide, an Sn-Al-Zn based oxide, an In-Sn-Ga-Zn based oxide, an In-Hf-Ga-Zn based oxide, an In-Al-Ga-Zn based oxide, an In-Sn-Al-Zn based oxide, an In-Sn-Hf-Zn based oxide, or an In-Hf-Al-Zn based oxide.

23. In any one of claims 1 to 22, a channel length direction of the second transistor is perpendicular to an upper surface of the first electrode layer.

24. In claim 23, The vertical direction includes a range of 85° to 95° with respect to a top surface of the first electrode layer.

25. In any one of claims 1 to 24, the oxide semiconductor layer has a region whose periphery is circular in a plane parallel to a surface of the first electrode layer.

26. In any one of claims 1 to 24, the oxide semiconductor layer has a region whose periphery in a plane parallel to a surface of the first electrode layer is a polygon.

27. In any one of claims 1 to 26, The semiconductor device, wherein the memory cells are arranged in a one-dimensional direction.

28. In any one of claims 1 to 27, a first wiring provided above the second transistor; a second wiring provided above the second transistor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring via a first connection electrode layer; the other of the source electrode and the drain electrode of the first transistor is electrically connected to a second wiring via a second connection electrode layer.

29. In any one of claims 1 to 27, a first wiring provided above the second transistor; the first wiring has a region overlapping with the second electrode layer via an insulating layer; the second electrode layer is electrically connected to a first wiring via a third connection electrode layer.

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