Semiconductor Device

Abstract

In the present invention, a first output transistor (MNOUT) is connected between an output node (No) connected to an output terminal (103) and a ground terminal (102), and a second output transistor (MPOUT, MNOUT) is connected between a power supply terminal (101) and the output node (No). When disconnection occurs at the ground terminal (102), at least the first output transistor (MNOUT) turns off in response to a disconnection detection signal (CMPG, CMPBG) from a disconnection detection circuit (105G), and a signal (EN) input to each circuit changes, thereby causing a semiconductor device (100A) to transition to a power off state.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In recent years, there has been a demand for improved fail-safe functions in the event of a disconnection in semiconductor devices such as LSIs (Large Scale Integrated Circuits) and ICs (Integrated Circuits) mounted on industrial equipment.

[0003] For example, U.S. Patent No. 5,942,677 (Patent Document 1) describes a fail-safe configuration for the event of a wire breakage in a knock sensor system in which an output signal from a knock sensor is processed by an IC and input to a downstream microprocessor. Specifically, the document describes a detection circuit configuration for detecting a wire breakage in the output signal line from the knock sensor to the IC, and control forcibly setting the output voltage from the IC to the microprocessor to a voltage (0 [V]) outside the normal voltage range (0.5 to 5 [V]) (when no wire breakage has occurred) when the wire breakage is detected.

[0004] In Patent Document 1, when an output signal line of a knock sensor is broken, it is possible to reliably cause a downstream IC to recognize the occurrence of the break. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 5,942,677 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in a semiconductor device, breaks may occur in the power supply wiring and the ground wiring in addition to breaks in the signal lines described in Patent Document 1. The detection circuit in Patent Document 1 cannot detect such breaks in the power supply wiring and the ground wiring, and furthermore, does not take into consideration a fail-safe function against such breaks.

[0007] On the other hand, a typical configuration of a semiconductor device is one in which an output terminal for electrically contacting the outside of the semiconductor device is connected to a power supply wiring and a ground wiring via a transistor of an output stage for driving the voltage of the output terminal. A back gate terminal (body) of the transistor constituting the output stage is usually connected to the power supply wiring or the ground wiring.

[0008] The output terminal may be pulled up or down outside the semiconductor device, and therefore, when one of the power supply wiring and the ground wiring is broken inside the semiconductor device, there is a risk that an abnormal current will flow between the other wiring that is not broken and the pull-up or pull-down destination outside the semiconductor device due to a current path formed by turning on the body diode of the transistor in the output stage.

[0009] The present disclosure has been made to solve such problems, and an object of the present disclosure is to prevent the occurrence of abnormal current when a break occurs in a power supply wiring or a ground wiring. [Means for solving the problem]

[0010] An aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a first power supply terminal receiving a first power supply voltage (GND), a second power supply terminal receiving a second power supply voltage (VCC) higher than the first power supply voltage, an output terminal electrically contactable from the outside of the semiconductor device, a first circuit having first and second output transistors, an open circuit detection circuit, and an output transistor control circuit. The first output transistor is electrically connected between the output node and the first power supply terminal to allow a current corresponding to a first control voltage input to the gate to flow from an output node connected to the output terminal to the first power supply terminal. The second output transistor is electrically connected between the second power supply terminal and the output node to allow a current corresponding to a second control voltage input to the gate to flow from the second power supply terminal to the output node. The open circuit detection circuit is configured to detect at least one of a first open circuit in a path of the first power supply voltage related to the first power supply terminal and a second open circuit in a path of the second power supply voltage related to the second power supply terminal. The output transistor control circuit is disposed corresponding to at least one of the first and second output transistors. The output transistor control circuit arranged corresponding to the first output transistor is configured to cut off a path through which a first control voltage is input to a gate of the first output transistor and turn off the first output transistor when a first disconnection is detected. The output transistor control circuit arranged corresponding to the second output transistor is configured to cut off a path through which a second control voltage is input to a gate of the second output transistor and turn off the second output transistor when a second disconnection is detected. Furthermore, the semiconductor device transitions to a power-off state in response to the detection of the disconnection by the disconnection detection circuit. The disconnection detection circuit has a power-off mechanism that cuts off a current flowing between the first power supply terminal and the second power supply terminal inside the disconnection detection circuit when the semiconductor device is in a power-off state. Effect of the Invention

[0011] According to the present disclosure, when a first open circuit on the first power supply voltage side or a second open circuit on the second power supply voltage side occurs when a pull-up resistor or a pull-down resistor is connected to an output terminal outside the semiconductor device, the output transistor control circuit forcibly turns off the first or second output transistor and places the semiconductor device in a power-off state to prevent a voltage rise at the first power supply terminal or a voltage drop at the second power supply terminal, thereby preventing abnormal current from occurring between the pull-up resistor and the open first power supply terminal, or between the pull-down resistor and the open second power supply terminal. [Brief description of the drawings]

[0012] [Figure 1] 1 is a schematic circuit diagram illustrating a configuration of a semiconductor device according to a comparative example in which an output terminal is pulled down. [Diagram 2] 2 is a circuit diagram of the semiconductor device shown in FIG. 1 when a ground wiring side is disconnected. [Diagram 3] FIG. 1 is a block diagram illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 4] 4 is a circuit diagram illustrating a configuration example of a bias circuit shown in FIG. 3. [Diagram 5] 5 is a circuit diagram illustrating a modified example of the configuration of the bias circuit shown in FIG. [Figure 6] FIG. 4 is a conceptual diagram illustrating the operation of the bias circuit shown in FIG. [Figure 7] 4 is a circuit diagram illustrating a configuration example of a comparator shown in FIG. 3. [Figure 8] 4 is a circuit diagram illustrating a configuration example of a delay circuit shown in FIG. 3. [Figure 9] 4 shows an example of operational waveforms of the semiconductor device according to the first embodiment. [Figure 10] FIG. 4 is a block diagram illustrating a modified example of the configuration of the semiconductor device shown in FIG. [Figure 11] FIG. 11 is a block diagram illustrating a power-off function of the circuit added in FIG. 10. [Figure 12]4 is a block diagram illustrating another modified example of the configuration of the semiconductor device shown in FIG. 3. FIG. [Figure 13] FIG. 2 is a conceptual diagram for explaining voltage-current characteristics of a diode. [Figure 14] FIG. 13 is a block diagram illustrating a configuration of a semiconductor device according to a modification of the first embodiment. [Figure 15] 15 is a circuit diagram for explaining a configuration example of a power-on reset (POR) circuit in FIG. 14. [Figure 16] 1 is a schematic circuit diagram illustrating a configuration of a semiconductor device according to a comparative example in which an output terminal is pulled up. [Figure 17] 17 is a circuit diagram of the semiconductor device shown in FIG. 16 when a break occurs on the ground wiring side. [Figure 18] FIG. 11 is a block diagram illustrating a configuration of a semiconductor device according to a second embodiment. [Figure 19] 19 is a circuit diagram illustrating a configuration example of a bias circuit shown in FIG. 18. [Figure 20] FIG. 20 is a circuit diagram illustrating a modified example of the configuration of the bias circuit shown in FIG. 19. [Figure 21] 19 is a conceptual diagram illustrating the operation of the bias circuit shown in FIG. 18. [Figure 22] 19 is a circuit diagram illustrating a configuration example of a comparator shown in FIG. 18. [Diagram 23] 19 is a circuit diagram illustrating a configuration example of a delay circuit shown in FIG. 18. [Figure 24] 13 is an example of operational waveforms of the semiconductor device according to the second embodiment. [Diagram 25] FIG. 19 is a block diagram illustrating a modification of the configuration of the semiconductor device shown in FIG. [Figure 26] FIG. 26 is a block diagram illustrating a power-off function of the circuit added in FIG. 25. [Figure 27] FIG. 19 is a block diagram illustrating another modified example of the configuration of the semiconductor device shown in FIG. [Figure 28] FIG. 13 is a block diagram illustrating a configuration of a semiconductor device according to a modification of the second embodiment. [Figure 29]FIG. 11 is a block diagram illustrating a configuration of a semiconductor device according to a third embodiment. [Diagram 30] FIG. 13 is a block diagram illustrating a configuration of a semiconductor device according to a modification of the third embodiment. [Diagram 31] 11 is a circuit diagram illustrating a modified example of a pull-down mechanism in the semiconductor device according to the present embodiment. FIG. [Diagram 32] 11 is a circuit diagram illustrating a modified example of a pull-up mechanism in the semiconductor device according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference characters, and their description will not be repeated in principle.

[0014] Embodiment 1 In the first embodiment, a circuit configuration for dealing with a break in a ground wiring in a semiconductor device will be described.

[0015] (Abnormal current caused by disconnection of ground wiring) First, with reference to FIGS. 1 and 2, an abnormal current that occurs when a break occurs in the ground wiring inside the semiconductor device in a configuration in which the output terminal of the semiconductor device is pulled down outside the semiconductor device will be described.

[0016] FIG. 1 is a schematic circuit diagram illustrating a configuration of a semiconductor device 100 according to a comparative example. The semiconductor device 100 shown in FIG. 1 includes a power supply terminal 101, a ground terminal 102, an output terminal 103, a power supply node NP, a GND node NG, and an operational amplifier circuit 150.

[0017] The power supply terminal 101 is electrically connected to a power supply 10 that supplies a power supply voltage VCC (for example, 5 [V]) by a power supply wiring. The ground terminal 102 is electrically connected to a reference voltage node 11 that supplies a ground voltage GND (0 [V]). The power supply node NP is connected to the power supply terminal 101 and is a general term for wiring (lines) that supply the power supply voltage VCC within the semiconductor device. Similarly, the GND node NG is connected to the ground terminal 102 and is a general term for wiring (lines) that supply the ground voltage GND within the semiconductor device. Inside the semiconductor device, the power supply terminal 101 and the power supply node NP are electrically equivalent, and the ground terminal 102 and the GND node NG are also electrically equivalent, unless a break occurs. In the following, the voltage of the power supply node NP is denoted as AVCC, and the voltage of the GND node NG is denoted as AGND.

[0018] In the first embodiment, it is assumed that a pull-up resistor 201 or a pull-down resistor 202 is connected to the output terminal 103 outside the semiconductor device. As described above, in the first embodiment, it is assumed that the output terminal 103 is electrically connected to the reference voltage node 11 via the pull-down resistor 202 outside the semiconductor device.

[0019] The operational amplifier circuit 150 includes a differential amplifier section 160 and an output stage 170. The operational amplifier circuit 150 is shown as a representative example of a circuit element connected between a power supply node NP and a GND node NG, and has the output stage 170 which can be a path for an abnormal current, which will be described later.

[0020] The differential amplifier 160 has an inverting input node Ni1 and a non-inverting input node Ni2, and an inverting output node No1 and a non-inverting output node No2. The voltage difference generated at the inverting output node No1 and the non-inverting output node No2 is an amplified voltage difference between the inverting input node Ni1 and the non-inverting input node Ni2. For example, analog voltages of opposite phases are input to the inverting input node Ni1 and the non-inverting input node Ni2. The internal configuration of the differential amplifier 160 can be arbitrarily applied to a circuit configuration of a general differential amplifier using field effect transistors (MOS transistors).

[0021] The output stage 170 has a P-type transistor (output transistor) MPOUT and an N-type transistor (output transistor) MNOUT. The output transistor MPOUT is connected between a power supply node NP and an output node No connected to the output terminal 103. The output transistor MNOUT is connected between the output node No and a GND node NG. The gate of the output transistor MPOUT is connected to an inverting output node No1 (- side) of the differential amplifier unit 160, and the gate of the output transistor MNOUT is connected to a non-inverting output node No2 (+ side) of the differential amplifier unit 160.

[0022] The output transistors MPOUT, MNOUT are driven according to the output voltage of the differential amplifier section 160, i.e., the voltages of the inverting output node No1 (- side) and the non-inverting output node No2 (+ side), thereby generating the output voltage VOUT of the operational amplifier circuit 150 at the output node No.

[0023] The semiconductor device 100 operates as an operational amplifier system that outputs an output voltage VOUT of the operational amplifier circuit 150 corresponding to an input signal to the operational amplifier circuit 150 from an output terminal 103 to the outside of the semiconductor device 100. As described above, when analog voltages of opposite phases are input to the inverting input node Ni1 and the non-inverting input node Ni2, an output voltage VOUT is obtained by amplifying the analog voltage (negative input) to a range from the ground voltage GND to the power supply voltage VCC.

[0024] Hereinafter, the state in which the power supply voltage VCC and the ground voltage GND are normally supplied to the semiconductor device will also be referred to as "normal state."

[0025] First, the normal operation of the semiconductor device 100 will be described. For example, an analog voltage such as an audio signal, an image signal, or a signal obtained by amplifying a sensor input (for example, a signal obtained by converting and amplifying the output of a Hall element) is input to the inverting input node Ni1 (- side) and the non-inverting input node Ni2 (+ side) of the differential amplifier 160. Alternatively, an analog voltage converted from a digital signal by a D / A converter (not shown) arranged in the front stage of the operational amplifier circuit 150 may be input to the differential amplifier 160.

[0026] Voltages having a voltage difference according to the input voltages to the inverting input node Ni1 (negative side) and the non-inverting input node Ni2 (positive side) are generated at the inverting output node No1 (negative side) and the non-inverting output node No2 (positive side) of the differential amplifier 160. The currents of the output transistors MNOUT and MPOUT change according to the voltages of the inverting input node Ni1 (negative side) and the non-inverting input node Ni2 (positive side), so that an output voltage VOUT according to the input signal is generated at the output node No and output from the output terminal 103.

[0027] The output voltage VOUT is assumed to be an analog output, not a digital output of GND (0 [V]) or VCC, since it follows the output voltage of the operational amplifier circuit 150. A voltage in the range of about GND (0 [V]) + 20 [mV] to about VCC (for example, 5 [V]) - 20 [mV] based on the input signal (analog voltage or D / A converted voltage of a digital signal) is output from the output terminal 103 in the form of a DC or AC voltage (sine wave or pulse wave).

[0028] Next, the operation of the semiconductor device 100 when the ground voltage GND is no longer supplied will be described.

[0029] FIG. 2 shows a circuit diagram when a break occurs on the ground wiring side of the semiconductor device 100 shown in FIG. 1 (hereinafter also referred to as GND break).

[0030] 2, when a break occurs between the reference voltage node 11 and the ground terminal 102, the ground terminal 102 is opened, and the GND node NG goes into a high impedance (Hi-Z) state. As a result, the semiconductor device 100 is supplied with only the power supply voltage VCC, so that the voltage AGND at the GND node NG gradually rises over time and eventually converges to VCC (5 V).

[0031] On the other hand, body diodes Dp and Dn are formed in the output transistors MPOUT (P type) and MNOUT constituting the output stage 170, respectively. The body diode Dp is formed so that the forward direction is from the output node No to the power supply node NP. On the other hand, the body diode Dn is formed so that the forward direction is from the GND node NG to the output node No. Under normal conditions, the power supply node NP is fixed to the power supply voltage VCC, and the GND node NG is fixed to the ground voltage GND, so that both the body diodes Dp and Dn are reverse biased.

[0032] When the GND is broken, the voltage AGND of the GND node NG rises, which may cause the body diode Dn of the output transistor MNOUT to become conductive. Therefore, when the pull-down resistor 202 is connected to the output terminal 103 outside the semiconductor device 100, there is a concern that an abnormal current Iabn1, indicated by the dotted line in the figure, may be continuously generated through the pull-down resistor 202 via the path of the GND node NG (voltage rise)-body diode Dn of the output transistor MNOUT-output node No-pull-down resistor 202-reference voltage node 11 (GND).

[0033] If such a current occurs, the current through the body diode may induce latch-up, which may not only result in excessive current consumption but also damage the chip, and may also cause the output voltage VOUT of the output terminal 103 to become unstable.

[0034] (Prevention of Abnormal Current When GND is Disconnected According to the First Embodiment) FIG. 3 is a block diagram illustrating the configuration of a semiconductor device 100A according to the first embodiment.

[0035] As shown in FIG. 3, the semiconductor device 100A of the first embodiment further includes, in addition to the configuration of the semiconductor device 100 shown in FIG. 1, an open circuit detection circuit 105G, a delay circuit 130G, output transistor control circuits 180P, 180N, and a pull-down transistor MNOG as configurations for preventing abnormal current when the GND is broken.

[0036] The output transistor control circuit 180P has P-type transistors MPC1 and MPC2. The transistor MPC1 is connected between the gate of the output transistor MPOUT and the power supply node NP. When the transistor MPC1 is turned on, the gate and source of the output transistor MPOUT are at the same potential, so that the output transistor MPOUT is turned off. The transistor MPC2 is connected between the gate of the output transistor MPOUT and the inverting output node No1. When the transistor MPC2 is turned on, the output voltage from the differential amplifier 160 to the inverting output node No1 (- side) is input to the gate of the output transistor MPOUT.

[0037] The output transistor control circuit 180N has N-type transistors MNC1 and MNC2. The transistor MNC1 is connected between the gate of the output transistor MNOUT and the GND node NG. When the transistor MNC1 is turned on, the gate and source of the output transistor MNOUT are at the same potential, so that the output transistor MNOUT is turned off. The transistor MNC2 is connected between the gate of the output transistor MNOUT and the non-inverting output node No2. When the transistor MNC2 is turned on, the output voltage from the differential amplifier 160 to the non-inverting output node No2 (+ side) is input to the gate of the output transistor MNOUT.

[0038] The pull-down transistor MNOG is connected between an output node No connected to the output terminal 103 and a GND node NG. That is, the pull-down transistor MNOG is connected in parallel with the output transistor MNOUT between the output node No and the GND node NG.

[0039] In this embodiment, the ground voltage GND corresponds to an example of a "first power supply voltage", the power supply voltage VCC corresponds to an example of a "second power supply voltage", the ground terminal 102 corresponds to an example of a "first power supply terminal", and the power supply terminal 101 corresponds to an example of a "second power supply terminal". Furthermore, the operational amplifier circuit 150 having the output transistors MPOUT and MNOUT corresponds to an example of a "first circuit", the output transistor MNOUT on the ground terminal 102 side corresponds to a "first output transistor", and the output transistor MPOUT on the power supply terminal 101 side corresponds to a "second output transistor". Furthermore, the input voltage from the differential amplifier unit 160 to the gate of the output transistor MNOUT (i.e., the voltage of the non-inverting output node No2) in a normal state corresponds to an example of a "first control voltage", and the input voltage from the differential amplifier unit 160 to the gate of the output transistor MPOUT (i.e., the voltage of the inverting output node No1) corresponds to an example of a "second control voltage".

[0040] The disconnection detection circuit 105G generates disconnection detection signals CMPG and CMPBG, which are control signals for the output transistor control circuits 180P and 180N, based on the voltage AVCC of the power supply node NP and the voltage AGND of the GND node NG.

[0041] As will become clear from the following description, the disconnection detection signal CMPG is initialized to a logical low level (hereinafter simply referred to as "L level") and is then maintained at the L level during normal operation when no GND disconnection has occurred. On the other hand, when a GND disconnection occurs, the disconnection detection signal CMPG changes from the L level to the H level. The disconnection detection signal CMPBG is an inverted signal of the disconnection detection signal CMPG, and is maintained at the H level during normal operation, but is set to the L level when a GND disconnection occurs.

[0042] The open circuit detection signal CMPG is input to the gates of the transistors MPC2, MNC1 of the output transistor control circuits 180P, 180N. The open circuit detection signal CMPBG is input to the gates of the transistors MPC1, MNC2 of the output transistor control circuits 180P, 180N. It is therefore understood that in the output transistor control circuits 180P, 180N, the pair of transistors MPC1 and MNC1 and the pair of transistors MPC2 and MNC2 are turned on and off in a complementarily manner.

[0043] The delay circuit 130G generates delayed signals CMPGD and CMPBGD by delaying the disconnection detection signals CMPG and CMPBG, respectively, according to a predetermined delay time Td. The delayed signal CMPGD is input to the gate of the pull-down transistor MNOG.

[0044] Next, the configuration of the disconnection detection circuit 105G will be described in detail with reference to FIG. 3 as well as FIG. 4 to FIG. 8. The disconnection detection circuit 105G includes a bias circuit 110G, a comparator 120G, and a D flip-flop 125G. A disconnection detection signal CMPBG is input as an EN (enable) signal to each of the bias circuit 110G, the comparator 120G, and the D flip-flop 125G. When the EN signal is at H level, each of the bias circuit 110G, the comparator 120G, and the D flip-flop 125G executes each circuit operation described below. On the other hand, when the EN signal is at L level, each of the bias circuit 110G, the comparator 120G, and the D flip-flop 125G enters a power-off state and stops each circuit operation. In the power-off state, no current is consumed except for a minute leakage current generated by a transistor in an off state.

[0045] The bias circuit 110G generates bias voltages VING and VREFG based on the voltage AVCC and the voltage AGND.

[0046] 4 and 5 show a configuration example of the bias circuit 110G and a modification thereof. 4, the bias circuit 110G has resistance elements R0G, R1G, R2G, and R3G, P-type transistors MP1G and MP2G, an N-type transistor MN0G, and a P-type transistor MCPG for power-off. In the bias circuit 110G, the transistor MCPG corresponds to one embodiment of a "power-off mechanism."

[0047] The transistor MCPG is connected between the power supply node NP and node N0G. A signal ENIB, which is an inverted version of the open circuit detection signal CMPBG input as the EN signal, is input to the gate of the transistor MCPG. That is, the logical level of the signal ENIB is the same as that of the open circuit detection signal CMPG. The transistor MCPG is turned on during circuit operation (EN=H level), while being turned off in the power-off state (EN=L level). The operation of the bias circuit 110G during circuit operation in which the node N0G is connected to the power supply node NP will be described below.

[0048] The resistor elements R0G and R1G are connected in series between the node N0G and the node N1G where the bias voltage VING is generated. The resistor element R2G is connected between the node N1G and the GND node NG. Therefore, the bias voltage VING is a divided voltage difference between the voltage AVCC and the voltage AGND.

[0049] The transistors MP1G and MP2G are connected in series between the node N0G and the node N2G where the bias voltage VREFG is generated, and together with the transistor MN0G and the resistor element R3G, form a series path between the power supply node NP and the GND node NG. Each of the transistors MP1G and MPG2 is diode-connected. The transistor MN0G and the resistor element R3G are connected in series between the node N2G and the GND node NG. The transistor MN0G is configured to have a threshold voltage Vt such that a drain current flows when the gate-source voltage is 0 [V]. For example, the transistor MN0G can be configured by a native NMOS transistor (or a depletion type NMOS transistor). The gate of the transistor MN0G is connected to the GND node NG. As a result, the transistor MN0G in the on state and the resistor element R3G operate as a constant current source connected between the node N2G and the GND node NG.

[0050] FIG. 6 shows a graph conceptually illustrating the behavior of the bias voltages VING and VREFG with respect to changes in the voltage AGND, in order to explain the operation of the bias circuit 110G.

[0051] 6, the bias voltage VING is proportional to the voltage difference between the voltages AVCC and AGND. Therefore, when a GND disconnection occurs, the bias voltage VING also rises as the voltage AGND rises while the voltage AVCC remains constant.

[0052] On the other hand, in the series path including node N2G, transistors MP1G and MP2G act as diodes through which the constant current by transistors MN0G and resistor element R3G passes, so the bias voltage VREFG is generated using the forward voltage of the diodes by transistors MP1G and MP2G. Therefore, if the voltage AVCC remains unchanged, the influence of the decrease in the voltage AGND on the bias voltage VREFG is small. For this reason, the bias voltage VREFG becomes substantially a constant level with respect to the change in the voltage AGND. Thus, even when the voltage AGND rises at the time of GND disconnection, it does not change much from the normal state (when GND disconnection does not occur). In this way, compared with the bias voltage VING, the bias voltage VREFG has low sensitivity to the voltage change (rise) of the GND node NG. That is, the bias voltage VREFG corresponds to an embodiment of the "first bias voltage", and the bias voltage VING corresponds to an embodiment of the "second bias voltage".

[0053] Therefore, it is understood that by appropriately setting the voltage division ratio by resistor elements R0G to R2G, VING < VREFG during normal operation (when GND disconnection does not occur), while on the contrary, VING > VREFG when the voltage AGND rises due to GND disconnection. In this way, the bias circuit 110G operates so as to generate the bias voltages VING and VREFG whose high-low relationship is reversed between the normal state and the GND disconnection state.

[0054] The configuration for generating the bias voltage VREFG in FIG. 4 can also be modified to the configuration shown in FIG. 5. For example, as shown in FIG. 5(a), a similar bias voltage VREFG can be generated with a simple configuration by a P-type transistor MP1G (diode-connected) connected between node N0G and node N2G and a resistor element R3G connected between node N2G and the GND node NG.

[0055] Alternatively, as shown in FIG. 5(b), a simple configuration can also generate a similar bias voltage VREFG by an N-type transistor MN1G (diode connection) connected between node N0G and node N2G and a resistor element R3G connected between node N2G and GND node NG.

[0056] Note that according to the configuration example of FIG. 4, compared with the modified examples of FIGS. 5(a) and 5(b), while the circuit elements increase, the independence (low sensitivity) of the bias voltage VREFG with respect to the change in voltage AGND is improved.

[0057] In the bias circuit 110G, in the power-off state where EN = L level, when the transistor MCPG is turned off, node N0G is disconnected from the power supply node NP. As a result, inside the bias circuit 110G, the current path between the power supply node NP and the GND node NG is interrupted. Thereby, the current (consumption current) flowing from the power supply node NP to the GND node NG is fixed to zero, and thus the power-off function of the bias circuit 110G is realized.

[0058] Referring to FIG. 3 again, the bias voltages VING and VREFG generated by the bias circuit 110G are input to the (+) input terminal and the (-) input terminal of the comparator 120G, respectively. The comparator 120G generates an output signal VCMPG having a logic level according to the comparison result of the voltages of the (-) input terminal and the (+) input terminal. When the voltage of the (+) input terminal is lower than the voltage of the (-) input terminal, that is, when VING < VREFP, VCMPG is set to the L level. Therefore, when no GND disconnection occurs (normal), VCMPG is set to the L level.

[0059] On the other hand, when the voltage of the (+) input terminal is higher than the voltage of the (-) input terminal, that is, when VING > VREFP, VCMPG is set to the H level. Therefore, when a GND disconnection occurs, VCMPG is set to the H level.

[0060] 7 shows a circuit diagram for explaining a configuration example of the comparator 120G. The comparator 120G also has the power-off function in response to the above-mentioned EN signal.

[0061] 7, the comparator 120G has P-type transistors MP10-MP13 and N-type transistors MN10-MN14 for configuring a two-stage amplifier. Furthermore, the comparator 120G further has P-type transistors MCP0-MCP3 and N-type transistors MCN0-MCN3 for a power-off function. These transistors MCP0-MCP3 and MCN0-MCN3 configure one embodiment of a "power-off mechanism" in the comparator 120G.

[0062] The transistors MP10 and MN10 are connected in series between the power supply node NP and node N10. The transistors MP11 and MN11 are connected in series between the power supply node NP and node N10 in parallel with the transistors MP10 and MN10. The gate of the transistor MN10 corresponds to the (+) input terminal in Fig. 3, and receives the bias voltage VING from the bias circuit 110G. The gate of the transistor MN11 corresponds to the (-) input terminal in Fig. 3, and receives the bias voltage VREFG from the bias circuit 110G.

[0063] The transistor MN12 is connected between the node N10 and a GND node NG. A constant bias voltage VBN is input to the gate of the transistor MN12, and the transistor MN12 operates as a constant current source.

[0064] The transistors MP12 and MN13 are connected in series between the power supply node NP and the GND node NG via the node N11. The transistors MP13 and MN14 are connected in series between the power supply node NP and the GND node NG via the node N12. The transistors MP11 and MP12 configure a current mirror by having their gates interconnected. Similarly, the transistors MP10 and MP13 also configure a current mirror.

[0065] The transistor MN13 is connected between the node N11 and a GND node NG, and the transistor MN14 is connected between the node N12 and a GND node NG. The transistors MN13 and MN14 configure a current mirror by having their gates interconnected.

[0066] Next, the arrangement of transistors related to the power-off function will be described. P-type transistor MCP0 is connected between the power supply node NP and the gates of P-type transistors MP10 and MP13. Similarly, P-type transistor MCP2 is connected between the power supply node NP and the gates of P-type transistors MP11 and MP12. An ENI signal having the same logic level as the EN signal is input to the gates of transistors MCP0 and MCP2.

[0067] The N-type transistor MCN0 is connected between the GND node NG and the gate of the N-type transistor MN12. The N-type transistor MCN2 is connected between the GND node NG and the gates of the N-type transistors MN13 and MN14. An ENIB having a logic level opposite to that of the EN signal is input to the gates of the transistors MCN0 and MCN2.

[0068] A P-type transistor MCP1 is connected between the connection point of the transistors MP10 and MN10 and the gates of the transistors MP10 and MP13. Similarly, a P-type transistor MCP3 is connected between the connection point of the transistors MP11 and MN11 and the gates of the transistors MP11 and MP12. An N-type transistor MCN1 is connected between the connection point of the transistors MP12 and MN13 and the gates of the transistors MN13 and MN14. ENIB is input to the gates of the transistors MCP1 and MCP3, and ENIB is input to the gate of the transistor MCN2.

[0069] Therefore, during circuit operation at the EN = H level (ENI = H level, ENIB = L level), transistors MCP0, MCP2, MCN0, and MCN2 are turned off, while transistors MCP1, MCP3, and MCN1 are turned on. As a result, the two-stage amplifier formed by P-type transistors MP10 to MP13 and N-type transistors MN10 to MN14 operates.

[0070] During the operation of the two-stage amplifier, the current of transistor MN10 and the current of transistor MN11 shunt the constant current generated by transistor MN12 according to the high and low relationship of the bias voltages VING and VREFG. Therefore, according to the gate voltage difference between transistors MN10 and MN11, a current difference occurs between the currents of transistors MP10 and MN10 and the currents of transistors MP11 and MN11.

[0071] Since transistors MP10 and MP13, transistors MP11 and MP12, and transistors MN13 and MN14 each form a current mirror, the current difference between transistors MN10 and MN11 caused by the gate voltage difference between transistors MN10 and MN11 described above is amplified, resulting in a voltage difference between nodes N11 and N12. As a result, a voltage difference amplified from the difference between the gate voltage of transistor MN10 (voltage of the (+) input terminal) and the gate voltage of transistor MN11 (voltage of the (-) input terminal) occurs between nodes N11 and N12.

[0072] The voltage of node N12 is amplified by a two-stage (even-stage) inverter and output as a binary output signal VCMPG from comparator 120G. As a result, in the configuration example of FIG. 7, when VING < VREFG, VCMPG = AGND (L level), while when VING > VREFG, VCMPG = AVCC (H level).

[0073] An N-type transistor MCN3 for a reset operation is connected between node N12 and a GND node NG. An RST signal is input to the gate of transistor MCN3. As shown in FIG. 3, a disconnection detection signal CMPG having an opposite logical level to the disconnection detection signal CMPBG input as an EN signal can be used as the reset signal RST. Alternatively, EMIB may be input to the gate of transistor MCN3 in common with transistors MCN0 and MCN2. Since transistor MCN3 is turned off during circuit operation (EM=H level), a voltage obtained by amplifying the voltage difference between bias voltages VING and VREFG appears at node N12.

[0074] In contrast, during power off when EN=L level (ENI=L level, ENIB=H level), the transistors MCP0, MCP2, MCN0, and MCN2 are turned on, while the transistors MCP1, MCP3, and MCN1 are turned off. As a result, the voltage AVCC is input to the gates of the P-type transistors MP10 to MP13, and the voltage AGND is input to the gates of the N-type transistors MN12 to MN14.

[0075] As a result, the P-type transistors MP10 to MP13 and the N-type transistors MN12 to MN14 are turned off. This stops the circuit operation of the two-stage amplifier, and cuts off the current path between the power supply node NP and the GND node NG inside the comparator 120G. In this way, the current (current consumption) flowing from the power supply node NP to the GND node NG is fixed to zero, thereby realizing the power-off function of the comparator 120G. In the power-off mechanism of FIG. 7, since a transistor through which a current always flows during circuit operation is not added in order to cut off the current, it is possible to prevent an increase in power consumption during circuit operation due to the power-off function.

[0076] When the power is off (ENIB=H level), the transistor MCN3 is turned on, so that the node N12 is connected to the GND node NG. As a result, the output signal VCMPG is reset to the L level.

[0077] Referring to FIG. 3 again, the output signal VCMPG of the comparator 120G is input to the D flip-flop 125G. The D flip-flop 125G operates when the EN signal = H level and stops and enters the power-off state when the EN signal = L level. The output signal (OUT) of the D flip-flop 125G is the disconnection detection signal CMPG. The inverted output signal (OUTB) of the D flip-flop 125G is the disconnection detection signal CMPBG having a logic level opposite to that of the disconnection detection signal CMPG.

[0078] The D flip-flop 125G initializes the disconnection detection signal CMPG = L level (CMPBG = H level) in response to the input of the reset signal FRST. For example, the reset signal FRST can be input when the semiconductor device 100A is started up.

[0079] When the semiconductor device 100A is started up, if there is no GND disconnection, in the bias circuit 110G, since VING < VREFG, the output signal VCMPG of the comparator 120G is at the L level, and the VCMPG = L level is maintained as long as there is no GND disconnection.

[0080] Therefore, in the D flip-flop 125G, after the above initialization, the disconnection detection signal CMPG is maintained at the L level (CMPBG = H level) while the input signal (IN) is maintained at the L level.

[0081] On the contrary, when a GND disconnection occurs and VING changes to VING > VREFG in the bias circuit 110G, the output signal VCMPG of the comparator 120G, that is, the input signal (IN) of the D flip-flop 125G changes from the L level to the H level, and accordingly, the disconnection detection signal CMPG changes from the L level to the H level. Conversely, the disconnection detection signal CMPBG changes from the H level to the L level.

[0082] In this way, the disconnection detection circuit 105G sets the disconnection detection signal CMPG to L level (CMPBG to H level) during normal operation. Also, the EN signals of the bias circuit 110G, the comparator 120G, and the D flip-flop 125G are set to H level (circuit operating state). On the other hand, the disconnection detection circuit 105G sets the disconnection detection signal CMPG to H level (CMPBG to L level) during GND disconnection. Also, the EN signals of the bias circuit 110G, the comparator 120G, and the D flip-flop 125G are set to L level (power off state).

[0083] The delay circuit 130G generates delayed signals CMPGD and CMPBGD by delaying the disconnection detection signals CMPG and CMPBG from the disconnection detection circuit 105G, respectively.

[0084] FIG. 8 shows an example of the configuration of the delay circuit 130G. 8, the delay circuit 130G can be configured by N inverters INV1 to INVN (N: an even number equal to or greater than 2) connected in series. The first-stage inverter INV1 receives the disconnection detection signal CMPG from the D flip-flop 125G, and the final-stage inverter INVN outputs a delayed signal CMPGD of the disconnection detection signal CMPG.

[0085] The delay time Td provided by the delay circuit 130G can be adjusted by the number of inverter stages (N). It is also possible to output a delayed signal CMPBGD of the disconnection detection signal CMPBG from the inverter INV(N-1) one stage before the final stage. Alternatively, in order to accurately align the delay times, an N-stage inverter for generating the delayed signal CMPBGD may be provided in addition to the inverters INV1 to INVN in FIG. 8.

[0086] Next, the operation of the semiconductor device 100A according to the first embodiment when the GND is disconnected will be described with reference to FIG. 9 and FIG.

[0087] As shown in FIG. 9, before the GND disconnection occurs at time t1, AGCC = VCC and AGND = GND are stable. In such a normal state, in the bias circuit 110G, VI N G < VREFG, so the disconnection detection signal CMPG = L level. Therefore, as shown in FIG. 3, in each of the bias circuit 110G, the comparator 120G, and the D flip-flop 125G, the EN signal (disconnection detection signal CMPBG) is set to the H level, and the circuit operation is executed.

[0088] Also, in the operational amplifier circuit 150, in the output transistor control circuits 180P and 180N, while the transistors MPC1 and MNC1 are turned off, the transistors MPC2 and MNC2 are turned on. Thereby, the operational amplifier circuit 150 executes a normal circuit operation of outputting an output voltage VOUT according to the input voltages to the inverting output node No1 (- side) and the non-inverting output node No2 (+ side) of the differential amplification unit 160.

[0089] As shown in FIG. 9, when the GND disconnection occurs at time t1, the voltage AGND of the GND node NG is no longer fixed to the ground voltage GND and gradually increases. In FIG. 9, for the sake of notation, a waveform in which AGND immediately rises from time t1 is illustrated, but actually, immediately after the occurrence of the GND disconnection, there is also a case where the voltage AGND is the ground voltage GND.

[0090] In response to the increase in the voltage AGND, in the bias circuit 110G, while the bias voltage VREFG does not change, the bias voltage VING increases. As a result, in the operation example of FIG. 9, at time t2, the bias voltage VING becomes higher than the bias voltage VREFG. Accordingly, the disconnection detection signal CMPG changes from the L level to the H level. On the contrary, the disconnection detection signal CMPBG used for the EN signal changes from the H level to the L level. In response to this, in the semiconductor device 100A, a control operation corresponding to the GND disconnection is started.

[0091] Referring again to FIG. 3, in the output transistor control circuits 180P and 180N of the operational amplifier circuit 150, the transistors MPC2 and MN2 are turned off, whereas the transistor MPC 1 , MNC1 is turned on. As a result, each of the output transistors MPOUT and MNOUT is turned off since the gate and source are at the same potential.

[0092] Furthermore, in response to the change of the disconnection detection signal CMPG to H level (CMPBG to L level), the semiconductor device 100A transitions to a power-off state. In the power-off state, EN is set to L level, the bias circuit 110G, the comparator 120G, and the D flip-flop 125G in FIG. 3 are powered off, and the current generated between the power supply node NP and the GND node NG is cut off.

[0093] 9, due to this current blocking effect, even if a GND disconnection occurs after time t2, the current flowing into the GND node NG is blocked, so the voltage AGND drops and the output voltage VOUT also drops. By preventing the voltage AGND from rising, the occurrence of the abnormal current Iabn1 described in FIG. 2 can be prevented.

[0094] At time t3, when the delay time Td by the delay circuit 130G has elapsed from time t2, the delayed signal CMPGD output by the delay circuit 130G changes from L level to H level. As shown in Fig. 3, at time t3, which is delayed from time t2, the delayed signal CMPGD is set to H level, and the pull-down transistor MNOG is turned on in response. This allows the GND node NG, where the GND disconnection has occurred, to be electrically connected to the reference voltage node 11 outside the semiconductor device 100A via the output node No and the output terminal 103. That is, the pull-down transistor MNOG can configure one embodiment of a "pull-down mechanism."

[0095] As a result, after time t3, the GND node NG and the output terminal 103 are pulled down, so that it becomes possible to stabilize (VOUT=GND) the voltage of the output terminal 103 after it has been lowered. Also, by fixing the voltage AGND of the GND node NG where the disconnection has occurred to the ground voltage GND, it is possible to further enhance the effect of preventing the occurrence of the abnormal current Iabn1 after time t3.

[0096] On the other hand, if a current is generated in the output node No or the GND node NG at time t3, the current will be guided to a short-circuit loop path including the output transistor MNOUT and the pull-down transistor MNOG, which are connected in parallel when the pull-down transistor MNOG is turned on.

[0097] Therefore, after the semiconductor device 100A transitions to the power-off state at time t2, it is necessary to sufficiently reduce the current to approximately zero before turning on the pull-down transistor MNOG. In other words, the delay time Td between times t2 and t3 is set according to the time required for the current to sufficiently decrease after the power-off state is established. For example, the delay time Td can be set in advance based on the results of an actual device test, etc.

[0098] As a result, in the semiconductor device of embodiment 1, in response to detection of a GND break at time t2 in FIG. 9, the output transistor MNOUT is forcibly turned off and the semiconductor device 100A transitions to a power-off state to avoid an increase in the voltage AGND, thereby preventing the occurrence of abnormal current Iabn1 (FIG. 2) due to a GND break.

[0099] Furthermore, by delaying the turn-off of the output transistor MNOUT and turning on the pull-down transistor MNOG after the current flowing into the GND node NG has sufficiently decreased, the voltage of the output terminal 103 can be stabilized (VOUT=GND).

[0100] The following describes the current conditions when the semiconductor device 100A is in a power-off state and when the pull-down transistor MNOG is turned on.

[0101] FIG. 10 shows a configuration in which a circuit 200 other than the elements in FIG. 3 is provided as a modification of the semiconductor device 100A.

[0102] 10, in addition to the disconnection detection circuit 105G and the operational amplifier circuit 150 shown in FIG 3, a circuit 200 connected between the power supply node NP and the GND node NG is further arranged. The circuit 200 has a power-off function in response to an EN signal shared with the bias circuit 110G, the comparator 120G, and the D flip-flop 125G.

[0103] FIG. 11 shows a block diagram for explaining the power-off function of the circuit 200. 11, the circuit 200 shown in Fig. 10 includes a shutoff transistor 205 and a circuit element 206 connected between a power supply node NP and a GND node NG. The shutoff transistor 205 is, for example, a P-type transistor, and receives an inverted signal of an EN signal at its gate.

[0104] The cutoff transistor 205 is connected in series with the circuit element 206, and when the cutoff transistor 205 is turned off, the current path between the power supply node NP and the GND node NG via the circuit element 206 is cut off.

[0105] During normal operation when the open circuit detection signal CMPG is maintained at an L level (the open circuit detection signal CMPBG is maintained at an H level), the cutoff transistor 205 is turned on, and by supplying a current to the circuit element 206, the circuit 200 can perform the desired circuit operation.

[0106] On the other hand, when the GND is broken, the cutoff transistor 205 is turned off in response to the change of the break detection signal CMPG to H level (the break detection signal CMPBG to L level). This puts the circuit 200 into a power-off state, and the current flowing from the power supply node NP to the GND node NG via the circuit element 206 can be cut off. This makes it possible to prevent the voltage AGND from rising due to the circuit 200 when the GND is broken. That is, in the circuit 200, the cutoff transistor 205 corresponds to one embodiment of a "power-off mechanism".

[0107] Alternatively, in the circuit 200, a mechanism for connecting the gate of each transistor connected between the power supply node NP and the GND node NG to the power supply node NP or the GND node NG in response to the disconnection detection signal CMPG, CMPBG is provided, so that a power-off function can be realized by adding a configuration for forcibly turning off the transistor, as in the comparator 120G described in FIG. 7. The circuit 200 corresponds to one embodiment of the "second circuit".

[0108] 3, the output transistors MPOUT, MNOUT of the operational amplifier circuit 150 are provided with an off function in response to the disconnection detection signals CMPG, CMPBG. Although no mention is made of a power-off function for the differential amplifier unit 160, it is also possible to realize a "power-off mechanism" by forcibly turning off multiple transistors (not shown) that constitute the differential amplifier unit 160 in response to the disconnection detection signals CMPG, CMPBG using a mechanism similar to that of FIG.

[0109] Incidentally, the power-off state of the semiconductor device 100A does not necessarily require that all circuits be provided with the above-mentioned power-off function.

[0110] For example, as shown in FIG. 12, the semiconductor device 100A can be configured to include a circuit group 200x (105G, 130G, 150) shown in FIG. 3, at least one circuit 200 (FIG. 11) having a power-off function, and at least one circuit 210 not having a power-off function.

[0111] The circuit 210 receives, as the EN signal, a signal ENC that is not affected by the disconnection detection signals CMPG and CMPBG. Alternatively, the EN signal does not need to be input to the circuit 210. Therefore, in the circuit 210, a current corresponding to the circuit operation is generated both during normal operation and when the GND is disconnected, but the current is relatively small.

[0112] For example, as described above, in the operational amplifier circuit 150, the current flowing through the output transistors MNOUT and MPOUT is dominant, so it is also possible to choose not to provide a power-off function in the differential amplifier section 160.

[0113] In this way, when a circuit group in a power-off state when a GND break occurs and a circuit group (201) that does not have a power-off function and generates a current flowing into the GND node NG are mixed, the total current value Ittl of the semiconductor device 100A, i.e., the entire IC, flowing between the power supply node NP and the GND node NG when the GND break occurs is reduced to a current level at which a current path via the body diode Dn of the output transistor MNOUT is not formed, thereby preventing the occurrence of an abnormal current Ibn1 (FIG. 2). That is, the power-off state of the semiconductor device 100A can be defined as a state in which the total current value Ittl in the power-off state is lower than the limit current value Ilmt set corresponding to the current level. That is, the power-off state of the semiconductor device 100A can be defined by determining the circuits having the power-off function so that the total current value Ittl is lower than the limit current value Ilmt.

[0114] The limit current value Ilmt can be determined in advance in accordance with the characteristics of the body diode of the output transistor, for example, as shown in FIG.

[0115] The voltage-current characteristics of the body diode of the output transistor MNOUT are shown in Fig. 13. The voltage Vf of the anode with respect to the cathode and the forward current If of the body diode Dn are defined as shown in Fig. 13(a).

[0116] 13(b), it is understood that in the region of If≧Id, a forward voltage Vb (Vb>0) is generated in the body diode Dn, that is, the body diode Dn is conductive. Therefore, when a GND break occurs, the total current value Ittl flowing into the GND node NG in the entire semiconductor device 100A must be at a current level that does not generate a forward voltage in the body diode Dn. In other words, the total current value Ittl must be lower than the current value Id, that is, the lower limit current value that generates a forward voltage in the body diode Dn.

[0117] Therefore, if the total current value Ittl when the semiconductor device 100A transitions to the power-off state in response to the detection of a GND break is lower than the limit current value Ilmt set lower than the lower limit current value Id, it is not necessary to power off all of the circuits connected between the power supply terminal 101 and the ground terminal 102 inside the semiconductor device 100A. In other words, the power-off state of the semiconductor device 100A is equivalent to providing at least some of the multiple circuits connected between the power supply node NP and the GND node NG with a power-off function in response to the detection of a GND break so that the total current value Ittl is lower than the limit current value Ilmt. For example, it is possible to determine which of the circuits should be provided with the power-off function in order to realize the power-off state of the semiconductor device 100A by measuring the current value in an implementation test. In addition, the delay time Td by the delay circuit 130G can also be set in advance to correspond to the time required from the start of the power-off state at time t2 in Figure 9 until the total current value Ittl settles to a level lower than the original limit current value Ilmt.

[0118] A variation of the first embodiment. In the semiconductor device, when the semiconductor device is connected to the power supply 10 at power-on, the voltage AVCC of the power supply node NP rises. Therefore, during the period until the voltage AVCC rises at power-on, there is a concern that the bias voltages VING and VREFG may be inverted as described in FIG. 6, which may result in erroneous detection of a GND disconnection. In the modified example of the first embodiment, a configuration for suppressing erroneous detection of a disconnection at power-on, i.e., at the start-up of the semiconductor device 100A, will be described.

[0119] FIG. 14 is a block diagram illustrating a configuration of a semiconductor device 100B according to a modification of the first embodiment.

[0120] As shown in FIG. 14, in the first embodiment, Variations of The semiconductor device 100B according to this embodiment differs from the semiconductor device 100A described in the first embodiment in that it further includes a POR (power-on reset) circuit 140.

[0121] The POR circuit 140 generates a POROUT signal according to the voltage VACC of the power supply node NP. The initial value of the POROUT signal when power is turned on is L level, and when the voltage AVCC rises to or exceeds a predetermined voltage, the POROUT signal changes from L level to H level.

[0122] FIG. 15 shows an example of the configuration of the POR circuit 140 in FIG. 15, the POR circuit 140 includes resistor elements R10 to R12 and an N-type transistor MNPOR. The resistor elements R10 and R11 are connected in series between a power supply node NP and a GND node NG via a node Npi. Therefore, a voltage obtained by dividing the voltage difference between the voltage AVCC of the power supply node NP and the voltage AGND of the GND node NG is generated at the node Npi.

[0123] The resistor element R12 is connected between the power supply node NP and a node Npo, and the N-type transistor MNPOR is connected between the node Npo and a GND node NG. The gate of the transistor MNPOR is connected to the node Npi.

[0124] Immediately after starting up the semiconductor device 100A, AVCC and AGND are at the same level, and thereafter, the voltage at node Npi also rises as the voltage AVCC rises to the power supply voltage VCC of the power supply 10. For this reason, before the rise of the voltage AVCC, that is, during the period when the voltage at node Npi is lower than the threshold voltage of the transistor MNPOR, the transistor MNPOR is turned off, and the voltage at the power supply node NP is transmitted to the node Npo.

[0125] On the other hand, when the voltage AVCC rises and the voltage of the node Npi becomes higher than the threshold voltage of the transistor MNPOR, the transistor MNPOR is turned on and the voltage of the GND node NG is transmitted to the node Npo.

[0126] The output of the inverter to which the voltage of the node Npo is input is output as a POROUT signal from the POR circuit 140. By optimizing the voltage division ratio of the resistance elements R10 and R11, the POROUT signal is set to an L level until the voltage AVCC rises, and is maintained at an H level after the voltage AVCC rises.

[0127] In the POR circuit 140, the current flowing between the power supply node NP and the GND node NG is sufficiently suppressed by increasing the sum of the electric resistance values ​​of the resistive elements R10 and R11. Therefore, the POR circuit 140 can be configured without the power-off function described in the first embodiment.

[0128] 14 again, in the semiconductor device 100B, the EN signal input to the bias circuit 110G, the comparator 120G, and the D flip-flop 125G is generated by AND (logical product) of the disconnection detection signal CMPBG and the POROUT signal, similar to the first embodiment. The semiconductor device 100B may also further include the circuit 200 (with power-off function) to which the EN signal is input, as described in FIGS. 10 and 11.

[0129] Therefore, in the modification of the first embodiment, the EN signal is maintained at the L level during the period when POROUT is at the L level, that is, until the voltage AVCC rises when the power is turned on. As a result, the bias circuit 110G, the comparator 120G, and the D flip-flop 125G do not start operating. Also, the POROUT signal can be applied to the reset signal RST of the D flip-flop 125G.

[0130] As a result, during the period when POTOUT is at L level, i.e., the period until the voltage AVCC rises when the power is turned on, the operation of the open circuit detection circuit 105G is equivalently put on hold, thereby preventing the open circuit detection signals CMPG and CMPGB from changing from their respective initial values ​​of L level and H level.

[0131] Since the POROUT signal is maintained at the H level after the voltage AVCC rises, the EN signal has the same logic level as the disconnection detection signal CMPBG that changes from the H level to the L level when the GND is disconnected, similarly to embodiment 1. Therefore, the semiconductor device 100B can operate in the same manner as the semiconductor device 100A according to embodiment 1.

[0132] In this way, according to the semiconductor device relating to the modified example of embodiment 1, in addition to the effects of embodiment 1, it is possible to prevent erroneous detection of a GND break when power is turned on, thereby stabilizing operation at startup.

[0133] Embodiment 2 In the second embodiment, a circuit configuration for dealing with a break in a power supply line in a semiconductor device will be described.

[0134] (Abnormal current caused by a break in the power supply wiring) First, referring to FIG. 16 and FIG. 17, the output terminal of the semiconductor device is pulled up from the outside of the semiconductor device. up In the semiconductor device, power supply The abnormal current that occurs when a break occurs in the wiring will be described.

[0135] FIG. 16 shows a schematic circuit diagram illustrating the configuration of a semiconductor device 100 according to a comparative example similar to that shown in FIG.

[0136] 1, the semiconductor device 100 includes a power supply terminal 101, a ground terminal 102, an output terminal 103, a power supply node NP, a GND node NG, and an operational amplifier circuit 150. In FIG. 16, the output terminal 103 is connected to the ground terminal 101 via a pull-up resistor 201 outside the semiconductor device. power supply 10 The difference from FIG. 1 is that the

[0137] Fig. 17 shows a circuit diagram when a break occurs on the power supply wiring side of the semiconductor device 100 shown in Fig. 16 (hereinafter, also referred to as a VCC break). The operation of the semiconductor device 100 when the power supply voltage VCC is no longer supplied will be described with reference to Fig. 17.

[0138] 17, when a break occurs between the power supply 10 and the power supply terminal 101, the power supply terminal 101 is opened, and the power supply node NP goes into a high impedance (Hi-Z) state. As a result, the semiconductor device 100 is supplied with only the ground voltage GND, so that the voltage AVCC of the power supply node NP gradually decreases over time and eventually converges to GND (0 V).

[0139] As described in the first embodiment, the body diodes Dp and Dn formed in the output transistors MPOUT (P type) and MNOUT, respectively, constituting the output stage 170, are reverse-biased in the normal state.

[0140] However, when VCC is disconnected, the voltage AVCC of the power supply node NP drops, which may cause the body diode Dp of the output transistor MPOUT to become conductive. Therefore, when a pull-up resistor 201 is connected to the output terminal 103 outside the semiconductor device 100, there is a concern that an abnormal current Iabn2, indicated by a dotted line in the figure, may be continuously generated through the pull-up resistor 201 via the path of the power supply 10 (VCC)-pull-up resistor 201-output terminal 103-output node No-body diode Dp of the output transistor MPOUT-power supply node NP (voltage drop).

[0141] (Prevention of Abnormal Current When VCC is Disconnected According to Second Embodiment) FIG. 18 is a block diagram illustrating the configuration of a semiconductor device 100C according to the second embodiment.

[0142] As shown in FIG. 18, the semiconductor device 100C of the second embodiment further includes, in addition to the configuration of the semiconductor device 100 shown in FIG. 16, a disconnection detection circuit 105V, a delay circuit 130V, output transistor control circuits 180P, 180N, and a pull-up transistor MPOV as configurations for preventing abnormal current when a VCC is disconnected.

[0143] The output transistor control circuits 180P and 180N respectively have P-type transistors MPC1, MPC2 and N-type transistors MNC1, MMC2 connected to the output transistors MPOUT, MNOUT in the same manner as in FIG. 3 (semiconductor device 100A).

[0144] The pull-up transistor MPOV is connected between an output node No connected to the output terminal 103 and a power supply node NP. That is, the pull-up transistor MPOV is connected in parallel with the output transistor MPOUT between the output node No and the power supply node NP.

[0145] The open circuit detection circuit 105V generates the open circuit detection signals CMPV and CMPBV based on the voltage AVCC of the power supply node NP and the voltage AGND of the GND node NG. As will be apparent from the following description, the open circuit detection signal CMPV is initialized to an L level and then maintained at an L level during normal operation when no VCC open circuit has occurred. On the other hand, when a VCC open circuit occurs, the open circuit detection signal CMPV changes from an L level to an H level. The open circuit detection signal CMPBV is an inverted signal of the open circuit detection signal CMPV, and while it is maintained at an H level during normal operation, it is set to an L level when a VCC open circuit occurs.

[0146] The open circuit detection signal CMPV is input to the gates of the transistors MPC2, MNC1 of the output transistor control circuits 180P, 180N. The open circuit detection signal CMPBV is input to the gates of the transistors MPC1, MNC2 of the output transistor control circuits 180P, 180N. As in the first embodiment, in the output transistor control circuits 180P, 180N, the pair of transistors MPC1 and MNC1 and the pair of transistors MPC2 and MNC2 are turned on and off complementarily.

[0147] The delay circuit 130V generates delayed signals CMPVD and CMPBVD by delaying the disconnection detection signals CMPV and CMPBV, respectively, according to a predetermined delay time Td. The delayed signal CMPBVD is input to the gate of the pull-up transistor MPOV.

[0148] Next, the configuration of the disconnection detection circuit 105V will be described in detail with reference to Fig. 19 to Fig. 23 in addition to Fig. 18. The disconnection detection circuit 105V includes a bias circuit 110V, a comparator 120V, and a D flip-flop 125V. The disconnection detection signal CMPBV is input as an EN signal to each of the bias circuit 110V, the comparator 120V, and the D flip-flop 125V. That is, when the EN signal is at an L level, each of the bias circuit 110V, the comparator 120V, and the D flip-flop 125V is in a power-off state and stops the operation of each circuit.

[0149] The bias circuit 110V generates bias voltages VINV and VREFV based on the voltages AVCC and AGND.

[0150] 19 and 20 show a configuration example of the bias circuit 110V and a modification thereof. 19, the bias circuit 110V has resistance elements R0V, R1V, R2V, and R3V, a P-type transistor MP0V, N-type transistors MN1V and MN2V, and a P-type transistor MCPV for power-off. In the bias circuit 110V, the transistor MCPV corresponds to one embodiment of a "power-off mechanism."

[0151] The transistor MCPV is connected between the power supply node NP and node N0V. A signal ENIB, which is an inverted version of the open circuit detection signal CMPBV input as the EN signal, is input to the gate of the transistor MCPV. That is, the logical level of the signal ENIB is the same as that of the open circuit detection signal CMPV. The transistor MCPV is turned on when the circuit is operating (EN=H level), and is turned off in the power-off state (EN=L level). The operation of the bias circuit 110V during circuit operation when the node N0V is connected to the power supply node NP will be described below.

[0152] The resistor elements R0V and R1V are connected in series between the node N0V and the node N1V where the bias voltage VINV is generated. The resistor element R2V is connected between the node N1V and the GND node NG. Therefore, the bias voltage VINV is a divided voltage difference between the voltages AVCC and AGND.

[0153] The transistor MP0V and the resistor element R3V are connected in series between the node N0V and the node N2V where the bias voltage VREFV is generated. The transistor MP0V is configured to have a threshold voltage Vt such that a drain current flows when the gate-source voltage is 0 [V]. For example, the transistor MP0V can be configured by a native PMOS transistor (or a depletion type PMOS transistor). The gate of the transistor MP0V is connected to the node N0V. As a result, the transistor MP0V in the on state and the resistor element R3V operate as a constant current source connected between the node N0V and the node N2V. The transistors MN1V and MN2V are connected in series between the node N2V and the GND node NG, and together with the transistor MP0V and the resistor element R3V, form a series path between the power supply node NP and the GND node NG. Each of the transistors MN1V and MN2V is diode-connected.

[0154] FIG. 21 shows a graph conceptually illustrating the behavior of bias voltages VINV and VREFV with respect to changes in voltage AVCC, in order to explain the operation of bias circuit 110V.

[0155] 21, the bias voltage VINV is proportional to the voltage difference between the voltages AVCC and AGND. Therefore, when a VCC disconnection occurs, the bias voltage VINV also decreases as the voltage AVCC decreases while the voltage AGND remains constant.

[0156] On the other hand, in the series path including node N2V, transistors MN1V and MN2V act as diodes through which the constant current by transistors MP0V and resistor element R3V passes. Therefore, bias voltage VREFV is generated using the forward voltage of the diodes formed by transistors MN1V and MN2V. Thus, if voltage AGND remains unchanged, the impact of the decrease in voltage AVCC on bias voltage VREFV is small. For this reason, bias voltage VREFV becomes substantially a constant level with respect to the change in voltage AVCC. So, even when voltage AVCC drops during the occurrence of VCC disconnection, it does not change much from the normal state (when VCC disconnection does not occur). In this way, compared with bias voltage VINV, bias voltage VREFV has low sensitivity to the voltage change (decrease) of power supply node NP. That is, bias voltage VREFV corresponds to an embodiment of the "first bias voltage", and bias voltage VINV corresponds to an embodiment of the "second bias voltage".

[0157] Therefore, by appropriately setting the voltage division ratio by resistor elements R0V to R2V, it can be understood that VINV > VREFV during normal operation (when VCC disconnection does not occur), while on the contrary, VINV < VREFV when voltage AVCC drops due to VCC disconnection. In this way, bias circuit 110V operates to generate bias voltages VINV and VREFV whose high-low relationship is reversed between the normal state and the VCC disconnection state.

[0158] The configuration for generating bias voltage VREV in FIG. 19 can also be modified to the configuration shown in FIG. 20. For example, as shown in FIG. 20(a), a similar bias voltage VREFV can be generated with a simple configuration by resistor element R3V connected between node N0V and node N2V and P-type transistor MP1V (diode-connected).

[0159] Alternatively, as shown in Fig. 20(b), a similar bias voltage VREFV can also be generated with a simple configuration by a resistor element R3V connected between node N0V and node N2V and an N-type transistor MN1V (diode connection) connected between node N2V and the GND node NG.

[0160] Note that according to the configuration example of Fig. 19, compared with the modification examples of Figs. 20(a) and (b), while the circuit elements increase, the independence (low sensitivity) of the bias voltage VREFV with respect to the change in the voltage AVCC is improved.

[0161] In the bias circuit 110V, in the power-off state where EN = L level, the transistor MCPV is turned off, and as a result, node N0V is disconnected from the power supply node NP. As a result, inside the bias circuit 110V, the current path between the power supply node NP and the GND node NG is cut off, and the power-off function of the bias circuit 110V is realized.

[0162] Referring to Fig. 18 again, the bias voltages VINV and VREFV generated by the bias circuit 110V are input to the (-) input terminal and the (+) input terminal of the comparator 120V, respectively. The comparator 120V has the same function as the comparator 120G described in the first embodiment, and generates an output signal VCMPV according to the comparison result of the voltages at the (-) input terminal and the (+) input terminal. Therefore, when VCC disconnection does not occur (normal) and VINV > VREFV, VCMPV is set to the L level. On the other hand, when VCC disconnection occurs and VINV < VREFV, VCMPV is set to the H level.

[0163] Fig. 22 shows a circuit diagram for explaining a configuration example of the comparator 120V. As shown in FIG. 22, the comparator 120V has the same configuration as the comparator 120G shown in FIG. 7. That is, the comparator 120V includes P-type transistors MP10 to MP13 and N-type transistors MN10 to MN14 for constituting a two-stage amplifier, and P-type transistors MCP0 to MCP3 and N-type transistors MCN0 to MCN3 for a power-off function.

[0164] Since the arrangement and connection modes of these transistors MP10 to MP13, MN10 to MN14, and transistors MCP0 to MCP3, MCN0 to MCN3 are the same as those in FIG. 7, detailed descriptions will not be repeated. Also, similar to the comparator 120G (FIG. 7), the voltage of node N12 is amplified by a two-stage (even-stage) inverter and output from the comparator 120V as a binary output signal VCMPV.

[0165] In the comparator 120V, a bias voltage VREFV from the bias circuit 110V is input to the gate of the transistor MN10 corresponding to the (+) input terminal in FIG. 18. On the other hand, a bias voltage VINV from the bias circuit 110V is input to the gate of the transistor MN11 corresponding to the (-) input terminal in FIG. 18.

[0166] Also in the comparator 120V, during the circuit operation when EN = H level (ENI = H level, ENIB = L level), a voltage difference amplified from the difference between the gate voltage of the transistor MN10 ((+) input terminal voltage) and the gate voltage of the transistor MN11 ((-) input terminal voltage) will occur between nodes N11 and N12. Therefore, when VINV > VREFV, VCMPV = AGND (L level), while when VINV < VREFV, VCMPV = AVCC (H level).

[0167] On the other hand, when the power is off and EN=L level (ENI=L level, ENIB=H level), the P-type transistors MP10 to MP13 and the N-type transistors MN12 to MN14 are turned off, thereby stopping the circuit operation of the two-stage amplifier, and cutting off the current path between the power supply node NP and the GND node NG inside the comparator 120V. This realizes the power-off function of the comparator 120V. Also, in the comparator 120V, when the power is off (ENIB=H level), the output signal VCMPV is reset to the L level by turning on the transistor MCN3.

[0168] 18 again, the output signal VCMPV of the comparator 120V is input to the D flip-flop 125V. Like the D flip-flop 125G, the D flip-flop 125V operates when the EN signal is at H level, and stops and enters a power-off state when the EN signal is at L level. In the second embodiment, the output signal (OUT) of the D flip-flop 125V is the disconnection detection signal CMPV. The inverted output signal (OUTB) of the D flip-flop 125V is the disconnection detection signal CMPBV having a logical level opposite to that of the disconnection detection signal CMPV.

[0169] The D flip-flop 125V initializes the disconnection detection signal CMPV to the L level (CMPBV to the H level) in response to the input of the reset signal FRST similar to that in the first embodiment.

[0170] When the semiconductor device 100C is started up, if no VCC open circuit occurs, then in the bias circuit 110V, VINV>VREFV, so that the output signal VCMPV of the comparator 120V is at L level, and VCMPV is maintained at L level unless a VCC open circuit occurs.

[0171] Therefore, after the above initialization, in the D flip-flop 125V, while the input signal (IN) is maintained at the L level, the disconnection detection signal CMPV is maintained at the L level (CMPBV is maintained at the H level).

[0172] On the other hand, when a VCC disconnection occurs and VINV < VREFV changes in the bias circuit 110V, the output signal VCMPV of the comparator 120V, that is, the input signal (IN) of the D flip-flop 125V changes from the L level to the H level, and accordingly, the disconnection detection signal CMPV changes from the L level to the H level. Conversely, the disconnection detection signal CMPBV changes from the H level to the L level.

[0173] In this way, the disconnection detection circuit 105V is set to the disconnection detection signal CMPV = L level (CMPBV = H level) during normal operation. Also, the EN signals of the bias circuit 110V, the comparator 120V, and the D flip-flop 125V are set to the H level (circuit operating state). On the other hand, the disconnection detection circuit 105V is set to the disconnection detection signal CMPV = H level (CMPBV = L level) when the VCC is disconnected. Also, the EN signals of the bias circuit 110V, the comparator 120V, and the D flip-flop 125V are set to the L level (power-off state).

[0174] The delay circuit 130V generates delay signals CMPVD and CMPBVD by delaying the disconnection detection signals CMPV and CMPBV from the disconnection detection circuit 105V, respectively.

[0175] Fig. 23 shows a configuration example of the delay circuit 130V. As shown in Fig. 23, the delay circuit 130V can be configured by N (N: an even number of 2 or more) inverters INV1 to INVN connected in series, similar to the delay circuit 130G (Fig. 8). In the delay circuit 130V, the disconnection detection signal CMPV from the D flip-flop 125V is input to the first-stage inverter INV1, and the final-stage inverter INVN outputs the delay signal CMPVD of the disconnection detection signal CMPV.

[0176] The delay time Td by the delay circuit 130V can be adjusted by the number of inverter stages (N), similarly to the delay circuit 130G. It is also possible to output a delayed signal CMPBVD of the disconnection detection signal CMPBV from the inverter INV(N-1) one stage before the final stage. Alternatively, an N-stage inverter for generating the delayed signal CMPBVD may be provided in addition to the inverters INV1 to INVN in FIG.

[0177] Next, the operation of the semiconductor device 100C according to the second embodiment when a VCC line is disconnected will be described with reference to FIGS.

[0178] As shown in Fig. 24, before the VCC disconnection occurs at time t1, AVCC is stable at VCC and AGND is stable at GND. During such normal times, VIV>VREFV in the bias circuit 110V, and therefore the disconnection detection signal CMPV is at L level. Therefore, as shown in Fig. 3, in each of the bias circuit 110V, the comparator 120V, and the D flip-flop 125V, the EN signal (disconnection detection signal CMPBV) is set to H level, and the circuit operation is performed.

[0179] Furthermore, in the operational amplifier circuit 150, in the output transistor control circuits 180P and 180N, the transistors MPC1 and MNC1 are turned off, while the transistors MPC2 and MNC2 are turned on, so that normal circuit operation is performed.

[0180] As shown in Fig. 24, when a VCC disconnection occurs at time t1, the voltage AVCC of the power supply node NP is no longer fixed to the power supply voltage VCC and gradually drops. For convenience of illustration, Fig. 24 shows a waveform in which AVCC drops immediately from time t1, but in reality, VCC Immediately after the occurrence of a disconnection, the voltage AVCC may be the power supply voltage VCC.

[0181] In response to the drop in the voltage AVCC, in the bias circuit 110V, the bias voltage VREFV does not change, while the bias voltage VINV drops. As a result, in the operation example of FIG. 24, at time t2, the bias voltage VINV becomes lower than the bias voltage VREFV. In response, the disconnection detection signal CMPV changes from the L level to the H level. Conversely, the disconnection detection signal CMPBV used for the EN signal changes from the H level to the L level. In response, in the semiconductor device 100C, a control operation corresponding to the VCC disconnection is started.

[0182] Referring again to FIG. 18, in the output transistor control circuits 180P and 180N of the operational amplifier circuit 150, the transistors MPC2 and MN2 are turned off, whereas the transistor MPC 1 , MNC1 is turned on. As a result, each of the output transistors MPOUT and MNOUT is turned off since the gate and source are at the same potential.

[0183] Furthermore, in response to the change of the disconnection detection signal CMPV to H level (CMPBV to L level), the semiconductor device 100C transitions to a power-off state. In the power-off state, EN is set to L level, and the bias circuit 110V, the comparator 120V, and the D flip-flop 125V in Fig. 18 are powered off, and the current generated between the power supply node NP and the GND node NG is cut off.

[0184] 23, due to this current cutoff effect, even if VCC is disconnected after time t2, the current flowing out from the power supply node NP is cut off, so that the voltage AVCC rises and the output voltage VOUT also rises. By preventing a drop in the voltage AVCC, the occurrence of the abnormal current Iabn2 described in FIG. 17 can be prevented.

[0185] At time t3, when the delay time Td by the delay circuit 130V has elapsed from time t2, the delayed signal CMPBVD output by the delay circuit 130V changes from H level to L level. As shown in Fig. 18, at time t3, which is delayed from time t2, the delayed signal CMPBVD is set to L level, and the pull-up transistor MPOV is turned on in response. This makes it possible to electrically connect the power supply node NP where the VCC disconnection has occurred to the power supply 10 outside the semiconductor device 100C via the output node No and the output terminal 103. That is, the pull-up transistor MPOV can constitute one embodiment of a "pull-up mechanism."

[0186] As a result, after time t3, the power supply node NP and the output terminal 103 are pulled up, so that it becomes possible to stabilize (VOUT=VCC) the voltage of the output terminal 103 after it has been increased. Also, by fixing the voltage AVCC of the power supply node NP where the disconnection has occurred to the power supply voltage VCC, it is possible to further enhance the effect of preventing the occurrence of the abnormal current Iabn2 after time t3.

[0187] On the other hand, if a current is generated in the output node No or the power supply node NP at time t3, the current will be guided to a short-circuit loop path including the output transistor MPOUT and the pull-up transistor MPOV, which are connected in parallel when the pull-up transistor MPOV is turned on.

[0188] Therefore, after the semiconductor device 100C transitions to the power-off state at time t2, it is necessary to sufficiently reduce the current to approximately zero before turning on the pull-up transistor MPOV. As in the first embodiment, the delay time Td can be set in advance based on the results of an actual device test, etc., in accordance with the time required from when the semiconductor device 100C transitions to the power-off state until the total current value Ittl falls to or below the limit current value Ilmt.

[0189] As a result, in the semiconductor device of embodiment 2, in response to detection of a VCC disconnection at time t2 in FIG. 24, the output transistor MPOUT is forcibly turned off and the semiconductor device 100C transitions to a power-off state, thereby avoiding a drop in the voltage AVCC, and thereby preventing the occurrence of abnormal current Iabn2 (FIG. 17) due to the VCC disconnection.

[0190] Furthermore, by delaying the turn-off of the output transistor MPOUT and turning on the pull-up transistor MPOV after the current flowing through the power supply node NP has sufficiently decreased, the voltage at the output terminal 103 can be stabilized (VOUT=VCC).

[0191] As shown in Fig. 25, the semiconductor device 100C according to the second embodiment may further include a circuit 200 similar to that shown in Fig. 11. As described in Fig. 11, the circuit 200 is connected between the power supply node NP and the GND node NG, and has a power-off function in response to an EN signal common to the bias circuit 110V, the comparator 120V, and the D flip-flop 125V.

[0192] 26, the circuit 200 shown in FIG. 25 has a cutoff transistor 205 and a circuit element 206 connected between a power supply node NP and a GND node NG. The cutoff transistor 205 is, for example, a P-type transistor, and receives an inverted signal of an EN signal at its gate. The second embodiment differs from the first embodiment (FIG. 12) in that the open circuit detection signal CMPBV is input as the EN signal.

[0193] In the semiconductor device 100C according to the second embodiment, the current path between the power supply node NP and the GND node NG via the circuit element 206 can also be cut off by turning off the cutoff transistor 205. That is, the cutoff transistor 205 can configure one embodiment of a "power-off mechanism."

[0194] During normal operation when the open circuit detection signal CMPV is maintained at an L level (the open circuit detection signal CMPBV is maintained at an H level), the cutoff transistor 205 is turned on, and by supplying a current to the circuit element 206, the circuit 200 can perform the desired circuit operation.

[0195] On the other hand, when VCC is disconnected, the cutoff transistor 205 is turned off in response to the disconnection detection signal CMPV changing to H level (the disconnection detection signal CMPBV changing to L level). This puts the circuit 200 into a power-off state, and the current flowing between the power supply node NP and the GND node NG via the circuit element 206 can be turned off. This makes it possible to prevent the voltage AVCC from dropping due to the circuit 200 when VCC is disconnected.

[0196] Alternatively, in the second embodiment, in the circuit 200, similar to the comparator 120G described in FIG. 7, a mechanism is added to forcibly turn off each transistor connected between the power supply node NP and the GND node NG by connecting the gate of the transistor to the power supply node NP or the GND node NG in response to the open circuit detection signals CMPV, CMPBV, thereby realizing a power-off function.

[0197] Also in the semiconductor device 100C, as described in the first embodiment, it is possible to configure a "power-off mechanism" for the differential amplifier section 160 of the operational amplifier circuit 150 in response to the open circuit detection signals CMPV, CMPBV using a mechanism similar to that shown in FIG.

[0198] In the semiconductor device 100C as well, the power-off state does not necessarily require that all circuits be provided with the power-off function described above.

[0199] For example, as shown in Fig. 27, a semiconductor device 100C can be configured to include a circuit group 200y (105V, 130V, 150) shown in Fig. 18, at least one circuit 200 (Fig. 26) having a power-off function, and at least one circuit 210 not having a power-off function. In the circuit 210, a relatively small current is generated in response to the circuit operation both during normal operation and when VCC is disconnected, as in Fig. 12.

[0200] In this way, when there is a mixture of circuits that are in a power-off state when a VCC disconnection occurs and a circuit (210) that generates a current flowing through the power supply node NP without having a power-off function, the power-off state of the semiconductor device 100C can be defined by determining the circuits that have a power-off state so that the total current value Ittl of the semiconductor device 100C flowing between the power supply node NP and the GND node NG when the VCC disconnection occurs is lower than the limit current value Ilmt.

[0201] That is, in the second embodiment (when VCC is disconnected), as in the first embodiment (when GND is disconnected), the total current value Ittl flowing through the power supply node NP throughout the semiconductor device 100C when VCC is disconnected must be lower than the current value Id described in the first embodiment (FIG. 13), i.e., the lower limit current value at which a forward voltage occurs in the body diode Dp of the output transistor MPOUT.

[0202] If the total current value Ittl when the power-off state is set in response to the detection of VCC disconnection is lower than the limit current value Ilmt set lower than the lower limit current value Id, it is not necessary to power off all of the circuits connected between the power supply terminal 101 and the ground terminal 102 in the semiconductor device 100C when the VCC is disconnected. In other words, the power-off state of the semiconductor device 100C is equivalent to providing at least a part of the circuits connected between the power supply node NP and the GND node NG with a power-off function in response to the detection of VCC disconnection so that the total current value Ittl is lower than the limit current value Ilmt. In the second embodiment, it is also possible to determine which of the circuits should be provided with the power-off function in order to realize the power-off state of the semiconductor device 100C by current value measurement or the like in an implementation test.

[0203] A variation of the second embodiment. In the modification of the second embodiment, a configuration for suppressing erroneous detection of disconnection when power is turned on, that is, when the semiconductor device 100C is started up, will be described.

[0204] FIG. 28 is a block diagram illustrating a configuration of a semiconductor device 100D according to a modification of the second embodiment.

[0205] As shown in FIG. 28, in the second embodiment Variations of The semiconductor device 100D according to the present embodiment differs from the semiconductor device 100C described in the second embodiment in that a POR circuit 140 is further provided.

[0206] 14 and 15, and generates a POROUT signal according to the voltage VACC of the power supply node NP. That is, the initial value of the POROUT signal when power is turned on is L level, and when the voltage AVCC rises to or above a predetermined voltage, the POROUT signal changes from L level to H level.

[0207] In the semiconductor device 100D, the EN signal input to the bias circuit 110V, the comparator 120V, and the D flip-flop 125V is generated by AND (logical product) of the disconnection detection signal CMPBV and the POROUT signal, similar to the second embodiment. The semiconductor device 100D may also further include the circuit 200 (with power-off function) to which the EN signal is input, as described with reference to FIGS. 25 and 26.

[0208] Therefore, in the modified example of the second embodiment, the EN signal is maintained at the L level during the period when POROUT is at the L level, that is, until the voltage AVCC rises when the power is turned on. As a result, the bias circuit 110V, the comparator 120V, and the D flip-flop 125V do not start operating. Also, the POROUT signal can be applied to the reset signal RST of the D flip-flop 125V.

[0209] As a result, during the period when POTOUT is at L level, i.e., the period until the voltage AVCC rises when the power is turned on, the operation of the open circuit detection circuit 105V is equivalently put on hold, thereby preventing the open circuit detection signals CMPV and CMPBV from changing from their respective initial values ​​of L level and H level.

[0210] Since the POROUT signal is maintained at the H level after the voltage AVCC rises, the EN signal has the same logic level as the disconnection detection signal CMPBV that changes from the H level to the L level when the VCC is disconnected, similarly to the second embodiment. Therefore, the semiconductor device 100D can operate similarly to the semiconductor device 100C according to the second embodiment.

[0211] In this way, according to the semiconductor device of the variation of the second embodiment, in addition to the effects of the second embodiment, it is possible to prevent erroneous detection of a VCC disconnection when power is turned on, thereby stabilizing operation at startup.

[0212] Embodiment 3 In the third embodiment, a configuration of a semiconductor device for dealing with both GND and VCC breaks will be described.

[0213] FIG. 29 is a block diagram illustrating a configuration of a semiconductor device 100E according to the third embodiment.

[0214] As shown in FIG. 29, in addition to the configuration of the semiconductor device 100 in FIG. 1, the semiconductor device 100E of the third embodiment includes an open circuit detection circuit 105G and a delay circuit 130G similar to the semiconductor device 100A (FIG. 3), an open circuit detection circuit 105V and a delay circuit 130V similar to the semiconductor device 100C (FIG. 18), output transistor control circuits 180P, 180N, and both a pull-down transistor MNOG and a pull-up transistor MPOV.

[0215] The disconnection detection circuit 105G generates disconnection detection signals CMPG, CMPBG similar to those in the first embodiment for detecting a GND disconnection. The delay circuit 130G generates delayed signals CMPGD, CMPBGD by adding a delay time to the disconnection detection signals CMPG, CMPBG. Similarly, the disconnection detection circuit 105V generates disconnection detection signals CMPV, CMPBV similar to those in the second embodiment for detecting a VCC disconnection. The delay circuit 130V generates delayed signals CMPGD, CMPBGD by adding a delay time Td to the disconnection detection signals CMPV, CMPBV. CMP Generate PVD, CMPBVD.

[0216] In the third embodiment, a disconnection detection signal CMP is further generated as a result of an OR (logical sum) operation of the disconnection detection signals CMPV and CMPG. The initial value of the disconnection detection signal CMP is an L level. VCC While neither the disconnection nor the GND disconnection occurs, the disconnection detection signal CMP is maintained at the L level. VCC When at least one of a disconnection and a GND disconnection occurs, the disconnection detection signal CMPB changes from L level to H level. The disconnection detection signal CMPB is an inverted signal of the disconnection detection signal CMP. That is, the disconnection detection signal CMPB is set to H level under normal conditions, while VCC When at least one of the disconnection and the GND disconnection occurs, the disconnection detection signal CMPB changes from H level to L level. In the semiconductor device 100E, the disconnection detection signal CMPB is input to the disconnection detection circuits 105G, 105V, etc. as an EN signal.

[0217] The output transistor control circuits 180P and 180N respectively have P-type transistors MPC1 and MPC2 and N-type transistors MNC1 and MNC2 connected to the output transistors MPOUT and MNOUT in the same manner as in FIG. 3 (semiconductor device 100A). A disconnection detection signal CMP is input to the gates of the transistors MPC2 and MNC1. A disconnection detection signal CMPB is input to the gates of the transistors MPC1 and MNC2.

[0218] The pull-down transistor MNOG is connected between the output node No and the GND node NG, and receives the delayed signal CMPGD at its gate, similar to Fig. 3. That is, the pull-down transistor MNOG operates in the same manner as in the first embodiment when GND is disconnected.

[0219] 18, the pull-up transistor MPOV is connected between the output node No and the power supply node NP, and receives the delayed signal CMPBVD at its gate. That is, the pull-up transistor MPOV operates in the same manner as in the second embodiment when VCC is disconnected.

[0220] Also in the semiconductor device 100E, it is possible to place between the power supply node NP and the GND node NG a circuit 200 having a power-off function when a break is detected in response to an EN signal, as described in Figures 11, 12, 25, and 26, and / or a circuit 210 not having a power-off function when a break is detected, as described in Figures 13 and 27.

[0221] In the semiconductor device 100E, in a normal state (CMP=L, CMBP=H) when neither VCC nor GND disconnection occurs, the transistor MPC 1 , MNC1 are turned off, while the transistors MPC2, MN2 are turned on. This causes the operational amplifier circuit 150 to perform the normal operation in the first and second embodiments. In addition, since EN is set to the H level, the disconnection detection circuits 105G, 105V and the circuit 200 perform the normal circuit operation.

[0222] In the semiconductor device 100E, when the GND is disconnected, the disconnection detection signal CMP is set to the H level, so that in the output transistor control circuits 180P and 180N, the transistors MPC2 and MN2 are turned off, whereas in the output transistor control circuits 180P and 180N, the transistor MPC 1 , MNC1 is turned on, which turns off each of the output transistors MPOUT and MNOUT.

[0223] Furthermore, following the disconnection detection signal CMPB, the EN signal of each circuit is set to L level, and the semiconductor device 100E transitions to a power-off state. Thereafter, the pull-down transistor MNOG operates in response to the delayed signal CMPGD in the same manner as in the first embodiment, and the output terminal 103 and the GND node NG are pulled down. In this manner, the control operation at the time of a GND disconnection described in the first embodiment is also performed in the semiconductor device 100E according to the third embodiment.

[0224] In the semiconductor device 100E, when the VCC is disconnected, the disconnection detection signal CMP is set to the H level, so that in the output transistor control circuits 180P and 180N, the transistors MPC2 and MN2 are turned off in the same manner as when the GND is disconnected, while the transistor MPC 1 , MNC1 is turned on. As a result, the output transistors MPOUT and MNOUT are turned off, and the EN signal of each circuit is set to L level, causing the semiconductor device 100E to transition to a power-off state. Thereafter, the pull-up transistor MPOV operates in response to the delayed signal CMPBVD in the same manner as in the second embodiment, thereby pulling up the output terminal 103 and the power supply node NP. In this manner, VCC The control operation at the time of disconnection is also performed in the semiconductor device 100E according to the third embodiment.

[0225] In addition, the power-off state of the semiconductor device 100E can be defined, similarly to the semiconductor devices 100C and 100E in the first and second embodiments, using the relationship between the total current value Ittl (FIG. 12) of the semiconductor device 100E when the EN signal is set to the L level and the characteristics of the body diodes Dp, Dn of the output transistors MPOUT, MNOUT.

[0226] As a result, in the semiconductor device 100E of the third embodiment, regardless of whether the pull-up resistor 201 or the pull-down resistor 202 is connected to the output terminal 103, the generation of abnormal current can be prevented by the control operation of the first embodiment when the GND is disconnected, or the control operation of the second embodiment when the VCC is disconnected.

[0227] A variation of the third embodiment. FIG. 30 is a block diagram illustrating a configuration of a semiconductor device according to a modification of the third embodiment.

[0228] FIG. 30 is a block diagram illustrating a configuration of a semiconductor device 100F according to a modification of the third embodiment.

[0229] As shown in FIG. Variation of 3 The semiconductor device 100F according to this embodiment differs from the semiconductor device 100E described in the third embodiment in that it further includes a POR circuit 140.

[0230] The POR circuit 140 is configured similarly to the modifications of the first and second embodiments, and generates a POROUT signal according to the voltage VACC of the power supply node NP. That is, the initial value of the POROUT signal when power is turned on is L level, and when the voltage AVCC rises to or exceeds a predetermined voltage, the POROUT signal changes from L level to H level.

[0231] In the semiconductor device 100F, the EN signal input to the disconnection detection circuits 105G, 105V, etc. is generated by AND (logical product) of the disconnection detection signal CMPB and the POROUT signal, similar to the third embodiment. The semiconductor device 100F may also further include a circuit 200 (with a power-off function) to which the EN signal is input.

[0232] Therefore, in the modification of the third embodiment, the EN signal is maintained at the L level during the period when POROUT is at the L level, that is, until the voltage AVCC rises when the power is turned on. As a result, the open circuit detection circuits 105G and 105V do not start operating, so that the open circuit detection signals CMPG, CMPV, and CMP and the open circuit detection signals CMPBG, CMPBV, and CMPB can be prevented from changing from their initial values ​​during the period until the voltage AVCC rises when the power is turned on.

[0233] After the voltage AVCC rises, the POROUT signal is maintained at the H level, so the EN signal is 1 or Similarly to the embodiment 2, when a GND or VCC disconnection occurs, the level changes from H to L. Therefore, the semiconductor device 100F can operate in the same manner as the semiconductor device 100E according to the third embodiment.

[0234] In this way, according to the semiconductor device of the modified example of embodiment 3, in addition to the effects of embodiment 3, it is possible to prevent erroneous detection of a disconnection when power is turned on, thereby stabilizing operation at startup.

[0235] In this way, according to the third embodiment and its modifications, even if it is not known outside the semiconductor device whether pull-up resistor 201 or pull-down resistor 202 is connected to output terminal 103, the versatility of the semiconductor device can be improved by configuring the semiconductor device so as to be able to handle both the abnormal current that occurs when GND is disconnected under pull-down as described in FIG. 2 and the abnormal current that occurs when VCC is disconnected under pull-up as described in FIG. 17.

[0236] On the other hand, if a circuit design is permitted on the premise that pull-up resistor 201 is connected to output terminal 103 (pull-down resistor 202 is not connected), the number of circuit elements can be reduced by applying semiconductor devices 100A and 100B according to the first embodiment or its modified examples. Similarly, if a circuit design is permitted on the premise that pull-down resistor 202 is connected to output terminal 103 (pull-up resistor 201 is not connected), the number of circuit elements can be reduced by applying semiconductor devices 100C and 100D according to the modified examples of the second embodiment.

[0237] In the present embodiment, the semiconductor devices 100A and 100B for dealing with GND disconnection and the semiconductor devices 100C and 100D for dealing with VCC disconnection have been described with reference to an example configuration in which both the output transistor control circuit 180P for the output transistor MPOUT and the output transistor control circuit 180N for the output transistor MNOUT are disposed. This enhances the effect of preventing abnormal current by forcibly turning off both the output transistors MPOUT and MNOUT in both cases of disconnection and GND disconnection.

[0238] However, in principle, while it is necessary to turn off the output transistor MNOUT in response to a GND break, it is possible to prevent the abnormal current Iabn1 (FIG. 2) without turning off the output transistor MPOUT. That is, in the semiconductor devices 100A and 100B according to the first embodiment and its modifications, it is also possible in principle to omit the arrangement of the output transistor control circuit 180P.

[0239] On the other hand, while it is necessary to turn off the output transistor MPOUT in response to a VCC disconnection, it is possible that the abnormal current Iabn2 (FIG. 17) can be prevented without turning off the output transistor MNOUT. That is, in the semiconductor devices 100C and 100D according to the second embodiment and its modifications, it is possible in principle to omit the arrangement of the output transistor control circuit 180N.

[0240] Furthermore, in the first to third embodiments and their modified examples, examples have been described in which the "pull-down mechanism" and the "pull-up mechanism" are respectively configured by the pull-down transistor MNOG and the pull-up transistor MPOV, but it is also possible to configure the "pull-down mechanism" and the "pull-up mechanism" without disposing the pull-down transistor MNOG and the pull-up transistor MPOV.

[0241] FIG. 31 shows a modification of the "pull-down mechanism" in the semiconductor device 100A shown in FIG.

[0242] The modified example of FIG. 31 differs from the configuration shown in FIG. 3 in that an output transistor control circuit 181N is provided instead of the output transistor control circuit 180N (FIG. 3), and in that the pull-down transistor MNOG (FIG. 3) is omitted.

[0243] The output transistor control circuit 181N differs from the output transistor control circuit 180N in that in addition to the N-type transistors MNC1 and MNC2, it further has a P-type transistor MPC3, and in that a control signal CMPGG is input to the gate of transistor MNC1 instead of the open circuit detection signal CMPG (Figure 3).

[0244] The transistor MPC3 is connected between the power supply node NP and the gate of the output transistor MNOUT, and the delayed signal CMPBGD is input to the gate of the transistor MPC3. Since the delayed signal CMPBGD is an inverted signal of the delayed signal CMPGD, in FIG. 9, it is at H level until time t3, but is set to L level after time t3.

[0245] The control signal CMPGG input to the gate of the transistor MNC1 is generated by ANDing the disconnection detection signal CMPG and the delayed signal CMPBGD. Therefore, the control signal CMPGG is set to H level between times t2 and t3 in FIG. 9, but is maintained at L level during the other periods.

[0246] 9, the output transistor control circuit 181N turns off the output transistor MNOUT by turning on the transistor MNC1 from time t2 to t3. The newly provided transistor MPC3 is maintained in the off state until time t3 by the delayed signal CMPBGD (H level). Therefore, in the period until time t3, the operation of the output transistor control circuit 181N is the same as that of the output transistor control circuit 180N.

[0247] After time t3, in the output transistor control circuit 181N, the transistor MPC3 is turned on, and the voltage AVCC of the power supply node NP is input to the gate of the output transistor MNOUT. Meanwhile, the transistor MNC1 is turned off, and the output transistor MNOUT is turned on by the gate-source voltage generated by the voltage AVCC. This allows the output transistor MNOUT to electrically connect the GND node NG, where the GND disconnection has occurred, to the reference voltage node 11 outside the semiconductor device via the output node No and the output terminal 103. That is, by using the output transistor MNOUT controlled by the output transistor control circuit 181N, one embodiment of the "pull-down mechanism" can be configured without additionally disposing a pull-down transistor MNOG.

[0248] FIG. 32 shows a modification of the "pull-up mechanism" in the semiconductor device 100C shown in FIG.

[0249] The modified example of FIG. 32 differs from the configuration shown in FIG. 18 in that an output transistor control circuit 181P is provided instead of the output transistor control circuit 180P (FIG. 18) and in that the pull-up transistor MPOV (FIG. 18) is omitted.

[0250] The output transistor control circuit 181P differs from the output transistor control circuit 180P in that in addition to the P-type transistors MPC1 and MPC2, it further has an N-type transistor MNC3, and in that a control signal CMPVV is input to the gate of transistor MPC1 instead of the open circuit detection signal CMPBV (Figure 18).

[0251] The transistor MNC3 is connected between the GND node NG and the gate of the output transistor MPOUT, and receives the delayed signal CMPVD at its gate. The delayed signal CMPVD is an inverted signal of the delayed signal CMPBVD, and is therefore at L level until time t3 in FIG. 24, but is set to H level after time t3.

[0252] The control signal CMPVV input to the gate of the transistor MPC1 is generated by ORing the disconnection detection signal CMPBV and the delayed signal CMPVD. Therefore, the control signal CMPVV is set to L level between times t2 and t3 in FIG. 24, but is maintained at H level during the other periods.

[0253] Therefore, in response to detection of a VCC disconnection at time t2 in Fig. 24, the output transistor control circuit 181P turns on the transistor MPC1 to turn off the output transistor MPOUT from time t2 to t3. Furthermore, the newly provided transistor MNC3 is maintained in the off state until time t3 by the delayed signal CMPBVD (L level). Therefore, in the period until time t3, the operation of the output transistor control circuit 181P is the same as that of the output transistor control circuit 180P.

[0254] After time t3, in the output transistor control circuit 181P, the transistor MNC3 is turned on, and the voltage AGND of the GND node NG is input to the gate of the output transistor MPOUT. Meanwhile, the transistor MPC1 is turned off, and the output transistor MPOUT is turned on by the gate-source voltage generated by the voltage AGND. This allows the output transistor MPOUT to electrically connect the power supply node NP where the VCC disconnection has occurred to the power supply 10 outside the semiconductor device via the output node No and the output terminal 103. That is, by using the output transistor MPOUT controlled by the output transistor control circuit 181P, one embodiment of the "pull-up mechanism" can be configured without additionally disposing a pull-up transistor MPOV.

[0255] Also, in each of Figures 10, 14, 25, and 28 to 30, at least one of the "pull-down mechanism" and "pull-up mechanism" arranged can be configured according to the modified example of Figure 31 or Figure 32.

[0256] In this embodiment, a countermeasure against an abnormal current in the output stage 170 (output transistors MPOUT, MNOUT) of the operational amplifier circuit 150 has been exemplified, but this embodiment can be applied to a configuration in which an output voltage from any circuit block, not limited to the differential amplifier unit 160, is input to the output stage 170. In other words, the configuration for dealing with a GND disconnection or a VCC disconnection according to this embodiment can be applied without particularly limiting the circuit block disposed in the preceding stage of the output stage 170 that generates the "first control voltage" and the "second control voltage" input to the gates of the output transistors MPOUT, MNOUT.

[0257] In particular, in the semiconductor devices 100A to 100F described above, an analog output configuration in which the output voltage of the differential amplifier 160 is input to the output stage 170 has been exemplified, but even in a digital output semiconductor device, it is possible to prevent abnormal current when a break occurs by applying the configurations described in the first to third embodiments and their modifications. That is, a circuit block that outputs a "first control voltage" and a "second control voltage" that turn on (current>0) or off (current=0) each of the output transistors MPOUT and MNOUT may be disposed in the preceding stage of the output stage 170.

[0258] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The technical scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0259] 10 power supply, 11 reference voltage node, 100, 100A to 100F semiconductor device, 101 power supply terminal, 102 ground terminal, 103 output terminal, 105G, 105V disconnection detection circuit, 110G, 110V bias circuit, 120G, 120V comparator, 125G, 125V flip-flop, 130G, 130V delay circuit, 150 operational amplifier circuit, 160 differential amplifier section, 170 output stage, 180N, 180P output transistor control circuit, 200x, 200y circuit group, 201 pull-up resistor, 202 pull-down resistor, 205 cut-off transistor, 206 circuit element, CMP, CMPB, CMPBG, CMPBV, CMPG, CMPV disconnection detection signal, CMPBGD, CMPBVD, CMPGD, CMPVD Delay signal, Dn, Dp body diode, GND ground voltage, Iabn1, Iabn2 abnormal current, Ittl total current value (whole IC), MNOG pull-down transistor, MNOUT, MPOUT output transistor, MPOV pull-up transistor, NG GND node, NP power supply node, No output node, No1 inverting output node, No2 non-inverting output node, Td delay time, VING, VINV, VREFV, VREV bias voltage, VOUT output voltage.

Claims

1. A semiconductor device comprising: a first power supply terminal for receiving a first power supply voltage; a second power supply terminal for receiving a second power supply voltage higher than the first power supply voltage; an output terminal that can be electrically contacted from outside the semiconductor device and that is pulled up or down outside the semiconductor device; a first circuit having first and second output transistors; the first output transistor is electrically connected between the output node and the first power supply terminal to allow a current corresponding to a first control voltage input to a gate of the first output transistor to flow from an output node connected to the output terminal to the first power supply terminal; the second output transistor is electrically connected between the second power supply terminal and the output node to cause a current corresponding to a second control voltage input to a gate of the second output transistor to flow from the second power supply terminal to the output node; The semiconductor device includes: an open circuit detection circuit for detecting at least one of a first open circuit in a path of the first power supply voltage related to the first power supply terminal and a second open circuit in a path of the second power supply voltage related to the second power supply terminal; an output transistor control circuit arranged corresponding to at least one of the first and second output transistors, the output transistor control circuit arranged corresponding to the first output transistor is configured to, when the first disconnection is detected, cut off a path through which the first control voltage is input to a gate of the first output transistor and turn off the first output transistor; the output transistor control circuit arranged corresponding to the second output transistor is configured to, when the second disconnection is detected, cut off a path through which the second control voltage is input to a gate of the second output transistor and turn off the second output transistor; the semiconductor device transitions to a power-off state in response to detection of a disconnection by the disconnection detection circuit; The semiconductor device, wherein the open circuit detection circuit has a power-off mechanism that cuts off a current flowing between the first power supply terminal and the second power supply terminal inside the open circuit detection circuit when the semiconductor device is in a power-off state.

2. The semiconductor device includes: a pull-down mechanism provided together with the output transistor control circuit arranged corresponding to the first output transistor, and a pull-up mechanism provided together with the output transistor control circuit arranged corresponding to the second output transistor, the pull-down mechanism operates with a delay from a timing when the semiconductor device transitions to the power-off state in response to the detection when the break detection circuit detects the first break, and electrically connects the first power supply terminal to the output terminal that is pulled down outside the semiconductor device; 2. The semiconductor device according to claim 1, wherein when the break detection circuit detects the second break, the pull-up mechanism operates with a delay from the timing at which the semiconductor device transitions to the power-off state in response to the detection, to electrically connect the second power supply terminal to the output terminal that is pulled up outside the semiconductor device.

3. a second circuit connected between the first and second power supply terminals; 3. The semiconductor device according to claim 1, wherein the second circuit has a power-off mechanism that cuts off current flowing between the first power supply terminal and the second power supply terminal within the second circuit when the semiconductor device is in the power-off state.

4. The semiconductor device according to any one of claims 1 to 3, wherein in the power-off state of the semiconductor device, a total current value flowing between the first power supply terminal and the second power supply terminal inside the semiconductor device is smaller than a limiting current value set corresponding to a current level that does not generate a forward voltage in a body diode formed in each of the first and second output transistors.

5. at least a part of a circuit group including the disconnection detection circuit and the first circuit, which is connected between the first power supply terminal and the second power supply terminal, has the power-off mechanism; 5. The semiconductor device according to claim 4, wherein the at least a portion of the circuits in which the power-off mechanism is provided are determined so that a total current value in the power-off state of the semiconductor device is lower than the limit current value.

6. the output transistor control circuits are arranged corresponding to the first and second output transistors, the output transistor control circuit arranged corresponding to the first output transistor is configured to input, when the first or second break is detected, a voltage for turning off the first output transistor, instead of the first control voltage, to a gate of the first output transistor; The semiconductor device according to any one of claims 1 to 5, wherein the output transistor control circuit arranged corresponding to the second output transistor is configured to input a voltage that turns off the second output transistor to a gate of the second output transistor, instead of the second control voltage, when the first or second break is detected.

7. The semiconductor device according to any one of claims 1 to 6, wherein, when the semiconductor device is powered on, the open circuit detection circuit waits to detect at least one of the open circuits until the voltage of the second power supply terminal rises to a predetermined voltage level or higher.

8. the disconnection detection circuit detects at least one of the first and second disconnections based on a comparison between a first bias voltage and a second bias voltage that changes according to a voltage difference between the first and second power supply terminals; The semiconductor device according to any one of claims 1 to 7, wherein the first bias voltage is generated so that a voltage change occurs that is smaller than a voltage change that occurs in the second bias voltage for a common amount of change in the voltage difference between the first and second power supply terminals.

9. the first bias voltage for detecting the first disconnection is generated using a forward voltage of a diode connected between the second power supply terminal and a node at which the first bias voltage is generated, the diode being included in a series path connected between the first and second power supply terminals; the first bias voltage for detecting the second disconnection is generated using a forward voltage of a diode connected between the first power supply terminal and a node at which the first bias voltage is generated, the diode being included in a series path connected between the first and second power supply terminals; 9. The semiconductor device according to claim 8, wherein said second bias voltage is generated by voltage division of said voltage difference between said first and second power supply terminals.

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