Semiconductor Device

Abstract

To reduce the standby power or suppress the malfunction in a logic circuit performing clock gating.SOLUTION: A logic circuit includes a transistor that is turned off in a state that a potential difference exists between a source terminal and a drain terminal in a period for which a clock signal is not supplied. A channel formation region of the transistor is formed of an oxide semiconductor with reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019(atoms / cm3) or less. Thus, the leakage current of the transistor can be reduced. As a result, the standby power can be reduced and the malfunction can be suppressed in the logic circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a logic circuit having a channel formation region made of an oxide semiconductor. The present invention also relates to a semiconductor device having the logic circuit. Regarding.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, and electro-optical devices, semiconductor circuits, and electrical equipment are all classified as semiconductor devices. [Background technology]

[0003] Generally, Si-wafer and SOI (Silicon On Insulator) As microfabrication advances, the operating voltage of circuits that have transistors made using The higher the power consumption, the lower the power consumption.

[0004] Power consumption is mainly determined by the gate capacitance of the transistor, the capacitance between transistors, and the capacitance between circuit blocks. Dynamic power consumed by charging and discharging parasitic capacitance generated in the connecting wiring, etc., and The static power consumed even when the device is not in operation (hereafter referred to as standby power) is become.

[0005] One method for reducing power consumption is a technique called clock gating ( For example, see Patent Document 1. Clock gating is a method of reducing power consumption. This technology stops the supply of clock signals to a circuit during the period when that circuit is not operating. This reduces the power consumed by the parasitic capacitance of the wiring through which the clock signal is supplied. It is possible. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2008-219882 A Summary of the Invention [Problem to be solved by the invention]

[0007] Standby power is generally the power consumed by circuits that are not in operation (hereafter referred to as non-operating circuits) and the power consumed by Leakage current of a transistor (generally, the leakage current between the source and drain when the gate-source voltage is 0V) The power consumed by the load is divided into two parts: the power consumed by the load (current flowing through the load) and the power consumed by the load (current flowing through the load).

[0008] The clock gating described above can reduce dynamic power consumption, but it also has a drawback in that it It is not possible to reduce the static power consumption due to the clock current in non-operating circuits. Dynamic power consumption includes the charging and discharging of parasitic capacitance in the wiring that supplies the clock signal. Furthermore, in a circuit that performs clock gating, Therefore, the state of each element constituting the non-operating circuit is maintained. The proportion of standby power consumed by power dissipation caused by current flow will increase. The current increases the probability of logic circuits malfunctioning.

[0009] In view of the above-described problems, one embodiment of the present invention provides a logic circuit that performs clock gating. One object of the present invention is to reduce standby power consumption or suppress malfunctions caused by leakage current. do. [Means for solving the problem]

[0010] One embodiment of the present invention is to provide an oxide semiconductor having an impurity (hydrogen or By removing the water, etc., an intrinsic or substantially intrinsic semiconductor, such as a silicon semiconductor, A transistor in which a channel formation region is formed using an oxide semiconductor having a larger energy gap than that of a The present invention applies the same resistor to an N-type transistor in a logic circuit.

[0011] Specifically, the hydrogen contained in the oxide semiconductor is 5×10 19 (atoms / cm 3 )below , preferably 5 x 10 18 (atoms / cm 3 ) or less, more preferably 5 × 10 17 ( atoms / cm 3 ) or less, and remove hydrogen or OH groups contained in the oxide semiconductor. , carrier density is 5×10 14 / cm 3 Less than or equal to 5×10 12 / cm 3 The following A logic circuit is configured using transistors in which a channel formation region is formed using an oxide semiconductor. It is something that can be done.

[0012] The energy gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more. More preferably, it is set to 3 eV or more, and impurities such as hydrogen that form donors are reduced as much as possible, and the carrier Rear density 5×10 14 / cm 3 Less than or equal to 5×10 12 / cm 3 The following will be true: to.

[0013] Such a highly purified oxide semiconductor can be used for a channel formation region of a transistor. Therefore, even when the channel width is 10 mm, the drain voltage is 1 V and 10 V. In the gate voltage range of -5V to -20V, the drain current is 1×10 -1 3 That is, the highly purified oxide semiconductor is used as a transistor. By applying this to the channel formation region of a MOSFET, the leakage current can be significantly reduced. Cut.

[0014] That is, one embodiment of the present invention is a clock signal input period, a clock signal and a second period during which no input is made to the source, a transistor that is turned off when a potential difference exists between a terminal and a drain terminal, The channel formation region of the sta- tor has a hydrogen concentration of 5 × 10 19 (atoms / cm 3 ) below oxidation The logic circuit is characterized by being made of semiconductors. Effect of the Invention

[0015] In the logic circuit according to one embodiment of the present invention, the source terminal and a transistor that is turned off when a potential difference exists between the drain terminals. The channel formation region of the transistor is formed of an oxide semiconductor having a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms / cm 3 ) below Therefore, the leakage current of the transistor can be reduced. It is possible to reduce the standby power consumption of the logic circuit and to suppress malfunction.

[0016] In particular, in a logic circuit in which clock gating is performed, the state in the logic circuit is That is, a particular transistor is maintained between the source terminal and the drain terminal. Such a transistor will remain off for a long time in the presence of a potential difference. The application of the transistor as the above-mentioned effect is significant.

[0017] In addition, the power consumption of the entire circuit is reduced to operate the logic circuit of one embodiment of the present invention. This reduces the load on the external circuit. This makes it possible to expand the functionality of the body device. [Brief description of the drawings]

[0018] [Figure 1] FIG. 2 illustrates an example of a configuration of a logic circuit described in Embodiment 1. [Diagram 2] 1A illustrates an example of a configuration of a logic circuit described in Embodiment 2, and FIG. 1B illustrates an example of a timing chart of the logic circuit. [Diagram 3] 13A and 13B are diagrams showing an example of a circuit configuration of an AND gate described in the second embodiment. [Figure 4] 1A shows an example of the configuration of a flip-flop, and FIGS. 1B and 1C show an example of the circuit configuration of a NAND gate, which are described in a second embodiment. FIG. [Diagram 5] 1A illustrates an example of a configuration of a logic circuit described in Embodiment 3, and FIG. 1B illustrates an example of a timing chart of the logic circuit. [Figure 6] 1A and 1B are diagrams showing an example of a circuit configuration of a NOR gate described in a third embodiment; [Figure 7] 1A illustrates an example of a configuration of a logic circuit described in Embodiment 4, and FIG. 1B illustrates an example of a timing chart of the logic circuit. [Figure 8] 1A shows an example of the configuration of a latch in a logic circuit described in embodiment 4, and FIGS. 1B and 1C show examples of the circuit configuration of an inverter. FIG. [Figure 9] FIG. 13 illustrates an example of a configuration of a logic circuit described in Embodiment 5. [Figure 10]FIG. 13 illustrates an example of a configuration of a logic circuit described in Embodiment 6. [Figure 11] 11 is a cross-sectional view showing a configuration example of a P-type transistor and an N-type transistor described in Embodiment 7. [Figure 12] 13A to 13H are cross-sectional views illustrating an example of a manufacturing process of a P-type transistor described in Embodiment 7. [Figure 13] 13A to 13G are cross-sectional views illustrating an example of a manufacturing process of an N-type transistor described in Embodiment 7. [Figure 14] 13A to 13D are cross-sectional views illustrating an example of a manufacturing process of an N-type transistor described in Embodiment 7. [Figure 15] 11 is a cross-sectional view showing a configuration example of a P-type transistor and an N-type transistor described in Embodiment 7. [Figure 16] 13A and 13B are cross-sectional views illustrating configuration examples of a P-type transistor and an N-type transistor described in Embodiment 7. [Figure 17] 13A and 13B are cross-sectional views illustrating configuration examples of a P-type transistor and an N-type transistor described in Embodiment 7. [Figure 18] 13A and 13B are diagrams illustrating configuration examples of a P-type transistor and an N-type transistor described in Embodiment 7. [Figure 19] 1A and 1B are a plan view and a cross-sectional view illustrating a configuration example of a transistor described in Embodiment 8. [Figure 20] 1A to 1E are cross-sectional views illustrating an example of a manufacturing process of a transistor described in Embodiment 8. [Figure 21] 1A to 1E are cross-sectional views illustrating an example of a manufacturing process of a transistor described in Embodiment 9. [Figure 22] 13A to 13D are cross-sectional views illustrating an example of a manufacturing process of a transistor described in Embodiment 10. [Diagram 23] 14A to 14F are diagrams illustrating an example of a semiconductor device described in Embodiment 11. [Figure 24] FIG. 2 is a graph showing initial characteristics of an example of a thin film transistor described in Example 1. [Diagram 25]3A and 3B are top views of an evaluation element of an example of a thin film transistor described in Example 1. [Figure 26] 4A and 4B are diagrams showing the Vg-Id characteristics of an evaluation element of an example of a thin-film transistor described in Example 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and may be modified in any form without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0020] The source and drain terminals of a transistor depend on the structure and operating conditions of the transistor. It is difficult to identify which is the source terminal and which is the drain terminal. Therefore, in this document, one of the source terminal and the drain terminal is referred to as a first terminal. The other of the source terminal and the drain terminal is referred to as a second terminal for distinction.

[0021] In addition, the size, layer thickness, or area of ​​each component shown in the drawings of each embodiment may differ from the actual size, layer thickness, or area shown in the drawings of each embodiment. In some cases, the figures are exaggerated for clarity. Therefore, the figures are not necessarily limited to the scale. In addition, ordinal numbers such as "first," "second," and "third" used in this specification are not limited to the structure. It is added to avoid confusion of the constituent elements, and is not a numerical limitation. do.

[0022] (Embodiment 1) In this embodiment, an example of a logic circuit in which clock gating is performed will be described. Specifically, the period during which the clock signal is input and the period during which the clock signal is not input are An example of a logic circuit that performs arithmetic processing using the clock signal is shown in FIG. He explains.

[0023] The logic circuit 10 shown in FIG. 1 includes a wiring for supplying a pulse signal (PS) (hereinafter, a pulse signal line A first input terminal 11 electrically connected to a data signal (Data) A second input terminal 12 electrically connected to a wiring (hereinafter also referred to as a data signal line) The logic circuit 10 receives a clock signal via a pulse signal line and an output terminal 13. There are periods when the clock signal (CK) is supplied and periods when the clock signal is not supplied. The logic circuit shown in FIG. 1 is a logic circuit in which clock gating is performed. When the clock signal is not supplied, the clock signal is at a high level potential or a low level potential. A signal that is fixed and changes from high to low and from low to high This means that no power is provided.

[0024] Furthermore, the logic circuit 10 of the present embodiment shown in FIG. 1 includes a main logic circuit section 14 and a clock A state in which a potential difference exists between the source terminal and the drain terminal for a period during which no signal is supplied. The main logic circuit section 14 includes a transistor 15 that is turned on when the transistor , and is composed of a plurality of elements such as capacitive elements and resistive elements.

[0025] The channel formation region of the transistor 15 has a hydrogen concentration of 5×10 19 (atoms / cm 3 ) or less, preferably 5 × 10 18 (atoms / cm 3 ) The following are more preferable is 5 x 10 17 (atoms / cm 3 ) It is composed of the following oxide semiconductors. That is, the transistor 15 has a very low concentration of hydrogen, which acts as a carrier donor. The transistor has a channel formation region made of a highly purified oxide semiconductor. The hydrogen concentration in the oxide semiconductor layer was measured by secondary ion mass spectrometry (SIMS). This was performed using the International Ion Mass Spectroscopy (IonMS) .

[0026] The logic circuit of the present embodiment is a logic circuit in which clock gating is performed, During the period when lock gating is performed (i.e., the period when no clock signal is input), Therefore, the transistor is turned off when there is a potential difference between the source terminal and the drain terminal. In the transistor, a channel formation region is formed using an oxide semiconductor. The hydrogen concentration in semiconductors is 5×10 19 (atoms / cm 3 ) or less, preferably 5 × 10 18 (atoms / cm 3 ) or less, more preferably 5 × 10 17 (atoms / cm 3 ) or less. Therefore, the off-state current of the transistor is controlled to 1×10 -13 [A] That is, the charge leakage through the transistor can be reduced to below 1000 . As a result, standby power consumption during the period can be reduced and This makes it possible to suppress malfunctions of logic circuits between the two.

[0027] In particular, in a logic circuit in which clock gating is performed, the state in the logic circuit is That is, a particular transistor is maintained between the source terminal and the drain terminal. Such a transistor will remain off for a long time in the presence of a potential difference. The application of the transistor as the above-mentioned effect is significant.

[0028] In addition, by reducing the power consumption of the logic circuit, the logic circuit of this embodiment can be operated without any trouble. This reduces the load on the external circuit. The functionality of the device can be expanded.

[0029] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine the contents of the above with parts of the above or with the contents of other embodiments or parts of the above. do.

[0030] (Embodiment 2) In this embodiment, an example of the logic circuit shown in Embodiment 1 will be described. 2 to 4 for a logic circuit having an AND gate and a flip-flop. He explains.

[0031] <Logic circuit configuration example> In the logic circuit 200 of this embodiment shown in FIG. 2A, a first input terminal receives an enable signal (EN) (hereinafter also referred to as an enable signal line), The input terminal of the clock signal (CK) is connected to the wiring (hereinafter referred to as the clock signal line). An AND gate 201 electrically connected to a first input terminal electrically connected to a data signal line a flip-flop having a first input terminal electrically connected to the output terminal of the AND gate 201; and a flop 202.

[0032] The flip-flop 202 in the logic circuit of this embodiment uses a feedback effect. The flip-flop 202 is a circuit that can hold one bit of data. The signal becomes the output signal of the logic circuit 200.

[0033] <Example of logic circuit operation> The operation of the logic circuit shown in FIG. 2(A) is explained with reference to the timing chart shown in FIG. 2(B). This will be explained in light of the above.

[0034] During the period T1, the enable signal line functions as a line that supplies a high-level signal. Therefore, the output signal (AND(Out)) of the AND gate 201 is That is, the second input terminal of the flip-flop 202 receives a clock signal (CK). The flip-flop 202 receives the clock signal (CK). Specifically, the flip-flop 202 operates when the clock signal (CK) is low. The data signal (D0 or D1) is captured when the data changes from low to high, and the clock signal is When the clock signal (CK) changes from high to low, the corresponding data signal is output.

[0035] During the period T2, the enable signal line functions as a line that supplies a low-level signal. Therefore, the output signal (AND(Out)) of the AND gate 201 is at a low level. That is, the second input terminal of the flip-flop 202 receives a low-level signal. At this time, the output signal (Out) of the logic circuit maintains the data signal (D1). do.

[0036] During the period T3, the enable signal line again serves as a wiring for supplying a high-level signal. It functions. That is, similar to period T1, flip-flop 202 captures the data signal (D2 or D3) when the clock signal (C K) changes from the low level to the high level, and outputs the data signal when the clock signal (CK) changes from the high level to the low level. Outputs the data signal.

[0037] In the logic circuit of this embodiment, the clock signal input to flip-flop 20 2 is controlled by the enable signal (EN). That is, it is a logic circuit in which clock gating is performed on flip-flop 202.

[0038] Note that the logic circuit of this embodiment reads data when the clock signal input to flip-flop 202 changes to the high level, and holds the read data during one clock period. Therefore, the output signal (Out) of the logic circuit is temporarily held even after the elapse of period T1 or period T3 during which flip-flop 202 is operating.

[0039] <Circuit Configuration Example of AND Gate and Flip-Flop> A specific circuit configuration example of AND gate 201 included in the logic circuit shown in Fig. 2(A) is shown in Figs. 3 (A) and (B), and a specific circuit configuration example of flip-flop 202 is shown in Figs. 4(A) to ( C).

[0040] The AND gate shown in Fig. 3(A) includes transistors 211 to 216. Note that transistors 211, 214, and 215 are P-type transistors, and transistors 212, 213, and 216 are N-type transistors.

[0041] Transistor 211 has its gate terminal electrically connected to the enable signal line, and its first terminal is electrically connected to the wiring that supplies the high power supply potential (VDD) (hereinafter also referred to as the high power supply potential line) will be done.

[0042] The transistor 212 has a gate terminal connected to the enable signal line and the gate of the transistor 211. a first terminal electrically connected to the second terminal of the transistor 211; can be.

[0043] The transistor 213 has a gate terminal electrically connected to the clock signal line and a first terminal The second terminal of the transistor 212 is electrically connected to the low power supply potential (VSS). The power supply line is electrically connected to a wiring that supplies the power supply voltage (hereinafter, also referred to as a low power supply potential line).

[0044] The gate terminal of the transistor 214 is connected to the clock signal line and the gate of the transistor 213. terminal, the first terminal being electrically connected to a high power supply potential line, and the second terminal being The second terminal of the transistor 211 and the first terminal of the transistor 212 are electrically connected to each other.

[0045] The transistor 215 has a gate terminal connected to the second terminal of the transistor 211 and a gate terminal connected to the second terminal of the transistor 212. 12 and the second terminal of the transistor 214, the first terminal being electrically connected to a high voltage It is electrically connected to a power supply potential line.

[0046] The transistor 216 has a gate terminal connected to the second terminal of the transistor 211 and a gate terminal connected to the second terminal of the transistor 212. 12, the second terminal of transistor 214, and the gate terminal of transistor 215. a first terminal electrically connected to the second terminal of the transistor 215; The terminal is electrically connected to a low power supply potential line.

[0047] In this AND gate, the second terminal of the transistor 215 and the second terminal of the transistor 216 The potential of the node electrically connected to the first terminal of the AND gate is the output signal (AND(Out )).

[0048] In this specification, the high power supply potential (VDD) and the low power supply potential (VSS) When comparing the two, if the high power supply potential (VDD) is higher than the low power supply potential (VSS), For example, the low power supply potential (VSS) may be a ground potential or 0V. For example, any positive potential can be applied as the high power supply potential (VDD).

[0049] The AND gate shown in FIG. 3B includes transistors 221 to 225. Note that the transistors 221 to 225 are N-type transistors. In addition, the transistors 221 to 225 are enhancement transistors having a positive threshold voltage. It is a modulation type transistor.

[0050] The transistor 221 has a gate terminal and a first terminal electrically connected to a high power supply potential line. .

[0051] The transistor 222 has a gate terminal electrically connected to the enable signal line and a first terminal is electrically connected to the second terminal of the transistor 221.

[0052] The transistor 223 has a gate terminal electrically connected to the clock signal line and a first terminal The second terminal of the transistor 222 is electrically connected to the low power supply line. Connected.

[0053] The transistor 224 has a gate terminal and a first terminal electrically connected to the high power supply potential line. .

[0054] The transistor 225 has a gate terminal connected to the second terminal of the transistor 221 and the transistor 222, the first terminal of which is electrically connected to the second terminal of transistor 224. The first terminal is electrically connected to the low power supply potential line.

[0055] In this AND gate, the second terminal of the transistor 224 and the second terminal of the transistor 225 The potential of the node electrically connected to the first terminal of the AND gate is the output signal (AND(Out )).

[0056] The gate terminal and the first terminal of the transistor 221 and the transistor 224 are high-voltage It is an enhancement type transistor electrically connected to the power supply line. The transistor 221 and the transistor 224 maintain the on state regardless of the period. The transistor 221 and the transistor 224 are used as resistive elements.

[0057] In addition, the first input terminal and the second input terminal of the AND gate are interchangeable. That is, The terminals defined as being electrically connected to the enable signal lines in the above description are referred to as clock signal lines. The terminal is electrically connected to the line and is also electrically connected to the clock signal line. It is possible to configure the device such that the input / output terminals are electrically connected to the corresponding pins of the power supply.

[0058] The flip-flop shown in FIG. 4A includes NAND gates 231 to 23 Has 4.

[0059] The NAND gate 231 has a first input terminal electrically connected to the data signal line and a second input terminal electrically connected to the data signal line. The input terminal is electrically connected to the output terminal of the AND gate.

[0060] The NAND gate 232 has a first input terminal electrically connected to the output terminal of the NAND gate 231. , and the second terminal is connected to the output terminal of the AND gate and the second input terminal of the NAND gate 231. It is electrically connected to the terminal.

[0061] A first input terminal of the NAND gate 233 is connected to the output terminal of the NAND gate 231 and the NA It is electrically connected to the first input terminal of the ND gate 232 .

[0062] A first input terminal of the NAND gate 234 is electrically connected to the output terminal of the NAND gate 233. a first input terminal electrically connected to the output terminal of the NAND gate 232; The output terminal is electrically connected to a second input terminal of the NAND gate 233 .

[0063] The flip-flop shown in FIG. 4(A) is a delay type flip-flop. The flip-flop of this embodiment is a delay type that uses only the Q terminal as an output terminal. The flip-flop is connected to the Q terminal and the QB terminal (the output terminal of the NAND gate 234). It may also be configured to have two output terminals.

[0064] The flip-flop shown in FIG. 4A is an example, and the flip-flop of this embodiment mode The flip-flop is not limited to this configuration. Any circuit configuration may be used as long as it is capable of holding one bit of data by utilizing the feedback effect.

[0065] 4B and 4C are applicable to the NAND gates 231 to 234. A specific example of such a circuit is shown below.

[0066] The NAND gate shown in FIG. 4B includes transistors 241 to 244. The transistors 241 and 244 are P-type transistors. 42 and 243 are N-type transistors.

[0067] The transistor 241 has a gate terminal electrically connected to the first input terminal of the NAND gate. The first terminal is electrically connected to a high power supply potential line.

[0068] The transistor 242 has a gate terminal connected to the first input terminal of the NAND gate and a transistor a first terminal electrically connected to the gate terminal of the transistor 241 and a second terminal of the transistor 241; are electrically connected.

[0069] The transistor 243 has a gate terminal electrically connected to the second input terminal of the NAND gate. a first terminal electrically connected to the second terminal of the transistor 242, and a second terminal electrically connected to the low power supply It is electrically connected to a potential line.

[0070] The transistor 244 has a gate terminal connected to the second input terminal of the NAND gate and a gate terminal connected to the second input terminal of the NAND gate. The first terminal is electrically connected to the gate terminal of the transistor 243, and the second terminal is electrically connected to the high power supply potential line. , the second terminal is electrically connected to the second terminal of the transistor 241 and the first terminal of the transistor 242. is connected to.

[0071] In the NAND gate, the second terminal of the transistor 241, the second terminal of the transistor 242 The potential of the node where the first terminal of the transistor 241 and the second terminal of the transistor 244 are electrically connected is NAN This is output as the output signal of the D gate.

[0072] The NAND gate shown in FIG. 4C includes transistors 251 to 253. Note that the transistors 251 to 253 are n-type transistors. In addition, the transistors 251 to 253 are enhancers having positive threshold voltages. It is a sensing type transistor.

[0073] The transistor 251 has a gate terminal and a first terminal electrically connected to a high power supply potential line. .

[0074] The transistor 252 has a gate terminal electrically connected to the first input terminal of the NAND gate. and the first terminal is electrically connected to the second terminal of the transistor 251.

[0075] The transistor 253 has a gate terminal electrically connected to the second input terminal of the NAND gate. a first terminal electrically connected to the second terminal of the transistor 252, and a second terminal electrically connected to the low power supply It is electrically connected to a potential line.

[0076] In the NAND gate, the second terminal of the transistor 251 and the The potential of the node electrically connected to the first terminal of the NAND gate is output as the output signal of the NAND gate. can be.

[0077] In addition, the first input terminal and the second input terminal of the NAND gate are interchangeable. The terminal defined in the above description as being electrically connected to the first input terminal of the NAND gate a second input terminal of the NAND gate electrically connected to the second input terminal of the NAND gate; The terminal that is specified to be electrically connected to the input terminal is electrically connected to the first input terminal of the NAND gate. It is possible to configure the circuit in such a manner that the input terminal is connected to the input terminal.

[0078] The logic circuit of this embodiment has NAND gates 231 to 234. At least one channel forming region of the transistors 242, 243, 252, and 253 is an oxide. The hydrogen concentration of the oxide semiconductor is 5×10 19 (ato ms / cm 3 ) or less, preferably 5 × 10 18 (atoms / cm 3 ) The following are more preferred Or 5×10 17 (atoms / cm 3 ) or less. The off-state current of the switch is 1×10 -13 It is possible to reduce the noise level to below [A]. The charge leakage through the transistor during the clock gating period is As a result, standby power consumption during the period can be reduced and This makes it possible to suppress malfunctions of logic circuits between the two.

[0079] Furthermore, as the AND gate 201 included in the logic circuit of this embodiment, The flip-flop 202 is formed by applying the AND gate shown in FIG. By applying a delay type flip-flop composed of D gates, the logic All of the transistors that make up the circuit can be N-type transistors. The N-type transistor is the above transistor (the channel formation region has a hydrogen concentration of 5×10 19 (atoms / cm 3 ) a transistor formed using the following oxide semiconductor This allows the logic circuit to be made up of only N-type transistors while still achieving low power consumption. In addition, by configuring the logic circuit only with N-type transistors, the fabrication process This can reduce the yield of the logic circuit and reduce the manufacturing cost. It can be done.

[0080] In addition, by reducing the power consumption of the logic circuit, the logic circuit of this embodiment can be operated without any trouble. This reduces the load on the external circuit. The functionality of the device can be expanded.

[0081] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine the contents of the above with parts of the above or with the contents of other embodiments or parts of the above. do.

[0082] (Embodiment 3) In this embodiment, an example of the logic circuit shown in Embodiment 1 will be described. 5 and 6 for a logic circuit having a NOR gate and a flip-flop. He explains as he goes.

[0083] <Logic circuit configuration example> In the logic circuit 500 of this embodiment shown in FIG. 5A, a first input terminal receives an enable signal The second input terminal is electrically connected to the line that supplies the inverted clock signal (CKB). 5, a NOR gate 501 electrically connected to a first inverted clock signal line (hereinafter also referred to as an inverted clock signal line) and The first input terminal is electrically connected to the data signal line, and the second input terminal is and a flip-flop 502 electrically connected to the output terminal.

[0084] The flip-flop 502 in the logic circuit of this embodiment uses a feedback effect. The flip-flop 502 is a circuit that can hold one bit of data. The signal becomes the output signal of the logic circuit 500.

[0085] <Example of logic circuit operation> The operation of the logic circuit shown in FIG. 5(A) will be described with reference to the timing chart shown in FIG. 5(B). This will be explained in light of the above.

[0086] During the period T4, the enable signal line functions as a line that supplies a low-level signal. Therefore, the output signal (NOR(Out)) of the NOR gate 501 is That is, the second input terminal of the flip-flop 502 receives a clock signal (CK). The flip-flop 502 receives the clock signal (CK). Specifically, the flip-flop 502 operates when the clock signal (CK) is low. The data signal (D4 or D5) is captured when the data changes from low to high level, and the clock signal When the clock signal (CK) changes from high to low, the corresponding data signal is output.

[0087] During the period T5, the enable signal line functions as a line that supplies a high-level signal. Therefore, the output signal (NOR(Out)) of the NOR gate 501 is at a low level. That is, the second input terminal of the flip-flop 502 receives a low-level signal. At this time, the output signal (Out) of the logic circuit maintains the data signal (D5). do.

[0088] During the period T6, the enable signal line is again used as a line for supplying a low level signal. It functions. That is, similar to period T4, flip-flop 502 captures the data signal (D6 or D7) when the clock signal (C K) changes from the low level to the high level, and outputs the data signal when the clock signal (CK) changes from the high level to the low level. Outputs the data signal when the clock signal (CK) changes from the high level to the low level.

[0089] In the logic circuit of this embodiment, the clock signal input to flip-flop 50 2 is controlled by the enable signal (EN). That is, it is a logic circuit in which clock gating is performed on flip-flop 502.

[0090] Note that the logic circuit of this embodiment reads data when the clock signal input to flip-flop 502 is at the high level, and holds the read data during one clock period. Therefore, the output signal (Out) of the logic circuit is temporarily held even after the elapse of period T4 or period T6 during which flip-flop 502 is operating. Reads data when the clock signal input to flip-flop 502 is at the high level, and holds the read data during one clock period. Therefore, the output signal (Out) of the logic circuit is temporarily held even after the elapse of period T4 or period T6 during which flip-flop 502 is operating.

[0091] <Circuit configuration example of NOR gate and flip-flop> A specific circuit configuration example of NOR gate 501 included in the logic circuit shown in FIG. 5(A) is shown in FIGS. 6(A) and (B). Note that for flip-flop 5 02 included in the logic circuit shown in FIG. 5(A), the Delay type flip-flop shown in FIG. 4(A) can be applied. Therefore, here, for the specific circuit configuration example of flip-flop 502, the above description will be incorporated by reference. Hereinafter, a specific circuit configuration example of NOR gate 501 will be described with reference to FIGS. 6(A) and (B). 02, the Delay type flip-flop shown in FIG. 4(A) can be applied. Therefore, here, for the specific circuit configuration example of flip-flop 502, the above description will be incorporated by reference. Hereinafter, a specific circuit configuration example of NOR gate 501 will be described with reference to FIGS. 6(A) and (B).

[0092] The NOR gate shown in FIG. 6(A) has transistors 511 to 514.​​​​ The transistors 511 and 512 are P-type transistors, and the transistor 51 3, 514 is an N-type transistor.

[0093] The transistor 511 has a gate terminal electrically connected to the enable signal line and a first terminal is electrically connected to the wiring that supplies the high power supply potential (VDD) (hereinafter also referred to as the high power supply potential line) will be done.

[0094] The transistor 512 has a gate terminal electrically connected to the inverted clock signal line and a first terminal The terminal is electrically connected to the second terminal of the transistor 511.

[0095] The transistor 513 has a gate terminal connected to the inverted clock signal line and the gate of the transistor 512. a first terminal electrically connected to the first terminal of the transistor 512; The second terminal is electrically connected to the low power supply potential line.

[0096] The transistor 514 has a gate terminal connected to the enable signal line and the gate of the transistor 511. a first terminal electrically connected to the second terminal of the transistor 512 and a second terminal of the transistor 513 and a second terminal is electrically connected to the low power supply potential line.

[0097] In the NOR gate, the second terminal of the transistor 512 and the The potential of the node where the first terminal and the first terminal of the transistor 514 are electrically connected is a NOR gate. The signal is output as the port output signal (NOR(Out)).

[0098] The NOR gate shown in FIG. 6B includes transistors 521 to 523. Note that the transistors 521 to 523 are n-channel transistors. In addition, the transistors 521 to 523 are enhancement transistors having positive threshold voltages. It is a modulation type transistor.

[0099] The transistor 521 has a gate terminal and a first terminal electrically connected to a high power supply potential line. .

[0100] The transistor 522 has a gate terminal electrically connected to the inverted clock signal line and a first terminal The second terminal is electrically connected to the low power supply line. are connected to the network.

[0101] The transistor 523 has a gate terminal electrically connected to the enable signal line and a first terminal is electrically connected to the second terminal of the transistor 521 and the first terminal of the transistor 522. , the second terminal is electrically connected to the low power supply potential line.

[0102] In the NOR gate, the second terminal of the transistor 521 and the The potential of the node where the first terminal and the first terminal of the transistor 523 are electrically connected is a NOR gate. The signal is output as the port output signal (NOR(Out)).

[0103] The transistor 521 has a gate terminal and a first terminal electrically connected to a high power supply potential line. Therefore, the transistor 521 is an enhancement type transistor. In other words, the transistor 521 is used as a resistive element. It has been done.

[0104] In addition, the first input terminal and the second input terminal of the NOR gate are interchangeable. That is, The terminals defined as being electrically connected to the enable signal lines in the above description are referred to as inverted clock A terminal that is specified to be electrically connected to a signal line and also to be electrically connected to an inverted clock signal line It is possible to configure the above-mentioned configuration such that the enable signal line is electrically connected to the enable signal line.

[0105] The logic circuit of this embodiment is a transistor having a channel formation region formed of an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms / cm 3 ) or less, preferably 5 × 10 18 (atoms / cm 3 ) or less, more preferably 5×1 0 17 (atoms / cm 3 Therefore, the off-state voltage of the transistor is Flow 1×10 -13 It is possible to reduce the clock frequency to [A] or less. and suppressing leakage of charge through the transistor during the period when the switching is performed. As a result, it is possible to reduce standby power consumption during the period and This makes it possible to suppress malfunctions of the logic circuits.

[0106] Furthermore, as the NOR gate 501 included in the logic circuit of this embodiment, The flip-flop 502 is a NOR gate as shown in FIG. By applying a delay type flip-flop composed of D gates, the logic All of the transistors that make up the circuit can be N-type transistors. The N-type transistor is the above transistor (the channel formation region has a hydrogen concentration of 5×10 19 (atoms / cm 3) a transistor formed using the following oxide semiconductor This allows the logic circuit to be made up of only N-type transistors while still achieving low power consumption. In addition, by configuring the logic circuit only with N-type transistors, the fabrication process This can reduce the yield of the logic circuit and reduce the manufacturing cost. It can be done.

[0107] In addition, by reducing the power consumption of the logic circuit, the logic circuit of this embodiment can be operated without any trouble. This reduces the load on the external circuit. The functionality of the device can be expanded.

[0108] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine the contents of the above with parts of the above or with the contents of other embodiments or parts of the above. do.

[0109] (Embodiment 4) In this embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Referring to FIG. 7 and FIG. 8, a logic circuit having a latch and a flip-flop will be described. He explains.

[0110] <Logic circuit configuration example> In the logic circuit 600 of this embodiment shown in FIG. 7A, a first input terminal receives an enable signal a wrapper having a first input terminal electrically connected to the inverted clock signal line and a second input terminal electrically connected to the inverted clock signal line; A first input terminal of the switch 601 is electrically connected to a data signal line, and a second input terminal of the switch 601 is electrically connected to a latch. The flip-flop 602 is electrically connected to the output terminal of the flip-flop 601.

[0111] The flip-flop 602 in the logic circuit of this embodiment uses a feedback effect. The flip-flop 602 is a circuit that can hold one bit of data. The signal becomes the output signal of the logic circuit 600.

[0112] In addition, the latch 601 of this embodiment can be used in any case as long as it can latch data. Here, when a high-level signal is supplied to the first input terminal, A circuit that latches and outputs the inverted signal of the signal input to the input terminal is applied to the latch 601. do.

[0113] <Example of logic circuit operation> The operation of the logic circuit shown in FIG. 7(A) will be described with reference to the timing chart shown in FIG. 7(B). This will be explained in light of the above.

[0114] During the period T7, the enable signal line functions as a line that supplies a high-level signal. At this time, the output signal (Latch(Out)) of the latch 601 is a clock signal (C That is, the second input terminal of the flip-flop 602 receives a clock signal (C K) is input. The flip-flop 602 is driven by the input clock signal (CK). Specifically, the flip-flop 602 operates when the clock signal (CK) is at a low level. The data signal (D8 or D9) is captured when it changes from high level to low level, and the clock signal ( CK) changes from high to low, the corresponding data signal is output.

[0115] During the period T8, the enable signal line functions as a line that supplies a low-level signal. At this time, the output signal (Latch(Out)) of the latch 601 is held at a low level. That is, a low level signal is input to the second input terminal of the flip-flop 602. At this time, the output signal (Out) of the logic circuit maintains the data signal (D9).

[0116] During the period T9, the enable signal line is again used as a wiring for supplying a high-level signal. That is, as in the period T7, the flip-flop 602 operates in response to the clock signal (C K) changes from low to high level. When the clock signal (CK) changes from high to low, the corresponding data signal Output.

[0117] In the logic circuit of this embodiment, the flip-flop 60 is turned on by the enable signal (EN). In other words, the clock signal (CK) input to the flip-flop 602 is controlled. This is a logic circuit for which clock gating is performed.

[0118] In addition, in the logic circuit of this embodiment, the clock signal input to the flip-flop 602 When the input is high, data is read and the read data is held for one clock cycle. Therefore, the output signal (Out) of the logic circuit is generated when the flip-flop 602 is operating. The signal is temporarily held even after the period T7 or the period T9 during which the signal is temporarily held has elapsed.

[0119] <Examples of latch and flip-flop circuit configurations> FIG. 8A shows a specific circuit configuration example of the latch 601 included in the logic circuit shown in FIG. 7(A) to (C). Note that the flip-flop 602 included in the logic circuit shown in FIG. In this case, the delay type flip-flop shown in FIG. 4(A) can be applied. Therefore, here, the specific circuit configuration example of the flip-flop 602 is described above. The following description will be made by way of reference to the specific circuit configuration of the latch 601 with reference to FIG. The following explanation will be given with reference to A) to (C).

[0120] The latch shown in FIG. 8A includes a transistor 611 and an inverter 612 and an inverter 613. The transistor 611 is an N-type transistor.

[0121] The transistor 611 has a gate terminal electrically connected to the enable signal line and a first terminal is electrically connected to the inverted clock signal line.

[0122] The inverter 612 has an input terminal electrically connected to the second terminal of the transistor 611. .

[0123] The inverter 613 has an input terminal electrically connected to the output terminal of the inverter 612, and an output The output terminal is electrically connected to the second terminal of the transistor 611 and the input terminal of the inverter 612. will be done.

[0124] In this latch, the output signal of the inverter 612 is the output signal of the latch (Latch (Out)).

[0125] 8B and 8C show circuit diagrams applicable to the inverter 612 and the inverter 613. A specific example is given.

[0126] The inverter shown in FIG. 8B includes a transistor 621 and a transistor 622. The transistor 621 is a P-type transistor, and the transistor 622 is an N-type It is a transistor.

[0127] The transistor 621 has a gate terminal electrically connected to the input terminal of the inverter and a first The terminal is electrically connected to a high power supply potential line.

[0128] The transistor 622 has a gate terminal connected to the input terminal of the inverter and the a first terminal electrically connected to the gate terminal of the transistor 621 and a second terminal electrically connected to the gate terminal of the transistor 621; The first terminal is electrically connected to the low power supply potential line.

[0129] In the inverter, the second terminal of the transistor 621 and the The potential of the node electrically connected to the first terminal is output as an output signal.

[0130] The inverter shown in FIG. 8C includes a transistor 631 and a transistor 632. The transistors 631 and 632 are N-type transistors. The transistors 631 and 632 are enhancement transistors having positive threshold voltages. It is a ment type transistor.

[0131] The transistor 631 has a gate terminal and a first terminal electrically connected to the high power supply potential line. .

[0132] The transistor 632 has a gate terminal electrically connected to the input terminal of the inverter and a first The terminal is electrically connected to the second terminal of the transistor 631, and the second terminal is connected to the low power supply line. are electrically connected.

[0133] In the inverter, the second terminal of the transistor 631 and the The potential of the node electrically connected to the first terminal is output as an output signal.

[0134] In the above description, the transistor 611 is an N-type transistor. However, the transistor 611 may be a P-type transistor. By inverting the table signal, it is possible to perform operations similar to those described above.

[0135] The logic circuit of this embodiment is a transistor having a channel formation region formed of an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms / cm 3 ) or less, preferably 5 × 10 18 (atoms / cm 3 ) or less, more preferably 5×1 0 17 (atoms / cm 3 Therefore, the off-state voltage of the transistor is Flow 1×10 -13 It is possible to reduce the clock frequency to [A] or less. and suppressing leakage of charge through the transistor during the period when the switching is performed. As a result, it is possible to reduce standby power consumption during the period and This makes it possible to suppress malfunctions of the logic circuits.

[0136] Furthermore, the latch 601 included in the logic circuit of this embodiment is the latch shown in FIG. A latch constituted by an inverter is applied as a flip-flop 602, as shown in FIG. ) to apply the delay type flip-flop composed of the NAND gate shown in This allows all the transistors that make up the logic circuit to be N-type transistors. These N-type transistors are the transistors described above (the channel formation region is in a hydrogen-rich Degree is 5×10 19 (atoms / cm 3) Transistors made of the following oxide semiconductors: By using N-type transistors, the logic circuit can be constructed only with N-type transistors. It is possible to reduce power consumption. In addition, the logic circuit can be constructed using only N-type transistors. Therefore, the manufacturing process can be reduced, and the yield of the logic circuit can be improved. The manufacturing costs can be reduced.

[0137] In addition, by reducing the power consumption of the logic circuit, the logic circuit of this embodiment can be operated without any trouble. This reduces the load on the external circuit. The functionality of the device can be expanded.

[0138] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine the contents of the above with parts of the above or with the contents of other embodiments or parts of the above. do.

[0139] (Embodiment 5) In this embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Referring to FIG. 9, a logic circuit having an AND gate and a number of flip-flops is shown. He explains.

[0140] The logic circuit 800 of this embodiment shown in FIG. 9 includes an AND gate 801 and a flip-flop. and a flip-flop group 805 including flip-flops 802 to 804.

[0141] The AND gate 801 has a first input terminal electrically connected to an enable signal line and a second input terminal electrically connected to an enable signal line. The input terminal of the clock signal line is electrically connected to the clock signal line.

[0142] The flip-flop 802 has a first input terminal electrically connected to a data signal line and a second input terminal electrically connected to a data signal line. The input terminal of is electrically connected to the output terminal of the AND gate 801.

[0143] A first input terminal of the flip-flop 803 is connected to the output terminal of the flip-flop 802. The first input terminal is electrically connected to the output terminal of the AND gate 801. .

[0144] A first input terminal of a flip-flop 804 is connected to the output terminal of the flip-flop 803. The first input terminal is electrically connected to the output terminal of the AND gate 801. .

[0145] The output signal of the flip-flop 804 is the same as the output signal (Out) of the logic circuit 800. become.

[0146] In addition, the flip-flops 802 to 804 in the logic circuit of this embodiment have a feedback function. For example, the Dela shown in Figure 4 is a circuit that can hold one bit of data. A y-type flip-flop can be applied.

[0147] In the logic circuit of this embodiment, the flip-flop group 8 is enabled by the enable signal (EN). In other words, the clock signal input to the flip-flop group 805 is controlled. This is a logic circuit in which clock gating is performed.

[0148] In addition, the flip-flops in the second and subsequent stages included in the flip-flop group 805 are the first The input terminal is electrically connected to the output terminal of the previous flip-flop. In the logic circuit of the embodiment, during the period in which the clock signal is input, ) is a shift register that shifts the flip-flops sequentially.

[0149] The logic circuit of this embodiment is a transistor having a channel formation region formed of an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms / cm 3 ) or less, preferably 5 × 10 18 (atoms / cm 3 ) or less, more preferably 5×1 0 17 (atoms / cm 3 Therefore, the off-state voltage of the transistor is Flow 1×10 -13 It is possible to reduce the clock frequency to [A] or less. and suppressing leakage of charge through the transistor during the period when the switching is performed. As a result, it is possible to reduce standby power consumption during the period and This makes it possible to suppress malfunctions of the logic circuits.

[0150] Furthermore, the logic circuit of this embodiment includes an AND gate 801 and a group of flip-flops. All of the transistors constituting 805 can be N-type transistors. The N-type transistor is the above transistor (the channel formation region has a hydrogen concentration of 5×10 1 9 (atoms / cm 3 ) a transistor formed using the following oxide semiconductor This allows the logic circuit to be made up of only N-type transistors while still achieving low power consumption. In addition, by configuring the logic circuit with only N-type transistors, the fabrication process is This can reduce the number of defects, thereby improving the yield of the logic circuit and reducing the manufacturing cost. It can be reduced.

[0151] In addition, by reducing the power consumption of the logic circuit, the logic circuit of this embodiment can be operated without any trouble. This reduces the load on the external circuit. The functionality of the device can be expanded.

[0152] Note that in this embodiment mode, a logic circuit having three flip-flops is shown. However, the number of flip-flops included in the logic circuit of this embodiment mode is not limited to three. That is, the logic circuit of this embodiment includes a first flip-flop to an n-th flip-flop (n is a natural number). The logic circuit also includes a flip-flop having the kth flip-flop. (n is a natural number less than or equal to n) is a flip-flop whose first input terminal is the k-1th flip-flop. The second input terminal of the AND gate 801 is electrically connected to the output terminal of the AND gate 802. are electrically connected.

[0153] In this embodiment, the first input terminal of the flip-flop in the second stage or later is connected to the flip-flop in the previous stage. The logic circuit of this embodiment has a configuration in which the output signal of a flip-flop is input. The configuration is not limited to the above. For example, a flip-flop may be externally controlled from outside the logic circuit 800. The first input terminal of the flip-flop may be configured to receive a signal from The output terminal of the flip-flop other than the previous stage is electrically connected to the output terminal of the flip-flop The flip-flop may be electrically connected to an output terminal of the flip-flop. The first input of one flip-flop is not directly connected to the output of the other flip-flop, but is connected to an intermediate Alternatively, the signal may be transmitted via another circuit.

[0154] In addition, the circuit configuration of a plurality of flip-flops included in the logic circuit of this embodiment is common. It is not necessary to change the circuit configuration for each flip-flop depending on the application.

[0155] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine the contents of the above with parts of the above or with the contents of other embodiments or parts of the above. do.

[0156] (Embodiment 6) In this embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Refer to FIG. 10 for a logic circuit having an AND gate and a number of flip-flops. He explains as he goes.

[0157] The logic circuit 900 of this embodiment shown in FIG. 10 includes a flip-flop 901 and an AND gate. A control unit 903 including a gate 902 and a flip-flop having flip-flops 904 to 906. and a loop group 907.

[0158] A first input terminal of the flip-flop 901 supplies a first data signal (Data1). The second input terminal is electrically connected to a wiring (hereinafter also referred to as a first data signal line) It is electrically connected to a clock signal line.

[0159] The first input terminal of the AND gate 902 is electrically connected to the output terminal of the flip-flop 901. and the second input terminal is electrically connected to an enable signal line.

[0160] A first input terminal of the flip-flop 904 supplies a second data signal (Data2). The second input terminal is electrically connected to a wiring (hereinafter also referred to as a second data signal line) Electrically connected to the output terminal of the AND gate 902 .

[0161] A first input terminal of the flip-flop 905 is connected to the output terminal of the flip-flop 904. and a second input terminal electrically connected to the output terminal of AND gate 902. .

[0162] A first input terminal of a flip-flop 906 is connected to the output terminal of the flip-flop 905. and a second input terminal electrically connected to the output terminal of AND gate 902. .

[0163] The output signal of the flip-flop 906 is the output signal (Out) of the logic circuit 900. become.

[0164] In addition, the flip-flops 901, 904 to 906 in the logic circuit of this embodiment are This is a circuit that can hold one bit of data by using the feedback effect. For example, the circuit shown in Figure 4 A delay type flip-flop can be applied.

[0165] The logic circuit of this embodiment is configured to operate in response to a first data signal (Data1) and a clock signal. and an enable signal (EN). The clock signal input to the flip-flop group 907 is controlled by the This is a logic circuit in which clock gating is performed on the flop group 907 .

[0166] In addition, the flip-flops in the second and subsequent stages included in the flip-flop group 907 are the first The input terminal is electrically connected to the output terminal of the previous flip-flop. In the logic circuit of the embodiment, during the period in which the clock signal is input, a second data signal (D ata2) is a shift register that shifts the flip-flops sequentially.

[0167] The logic circuit of this embodiment is a transistor having a channel formation region formed of an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms / cm 3 ) or less, preferably 5 × 10 18 (atoms / cm 3 ) or less, more preferably 5×1 0 17 (atoms / cm 3 Therefore, the off-state voltage of the transistor is Flow 1×10 -13 It is possible to reduce the clock frequency to [A] or less. and suppressing leakage of charge through the transistor during the period when the switching is performed. As a result, it is possible to reduce standby power consumption during the period and This makes it possible to suppress malfunctions of the logic circuits.

[0168] Furthermore, the control unit 903 and the flip-flop group 907 included in the logic circuit of this embodiment All of the transistors constituting the FET can be N-type transistors. The transistor is the above transistor (the channel formation region has a hydrogen concentration of 5×10 19 (a toms / cm 3 ) a transistor formed using the following oxide semiconductor This allows the logic circuit to be made up of only N-type transistors while still achieving low power consumption. In addition, by configuring the logic circuit only with N-type transistors, the manufacturing process can be simplified. This can reduce the number of steps required to manufacture the logic circuit, thereby improving the yield and reducing the manufacturing cost. It is possible.

[0169] In addition, by reducing the power consumption of the logic circuit, the logic circuit of this embodiment can be operated without any trouble. This reduces the load on the external circuit. The functionality of the device can be expanded.

[0170] In this embodiment, the flip-flop group 907 has three flip-flops. However, the flip-flops in the flip-flop group 907 of this embodiment are The number of flip-flops is not limited to three. A flip-flop group has a first flip-flop to an n-th flip-flop (n is a natural number). The kth flip-flop (k is a natural number less than or equal to n) in the flip-flop group is also included. ) flip-flop has its first input terminal connected to the output terminal of the k-1th flip-flop. and a second input terminal electrically connected to the output terminal of AND gate 902. .

[0171] In this embodiment, the flip-flops in the second and subsequent stages of the flip-flop group 907 are The output signal of the previous flip-flop is input to the first input terminal of the flip-flop. However, the configuration of the flip-flop group in this embodiment is not limited to this configuration. Alternatively, a signal may be input to the flip-flop from outside the logic circuit 900. In addition, the first input terminal of a flip-flop is electrically connected to the output terminal of the flip-flop two stages before. A configuration in which the output terminal of a flip-flop other than the previous stage is electrically connected to the output terminal of the flip-flop other than the previous stage. Furthermore, the first input terminal of a flip-flop may be connected to the first input terminal of another flip-flop. The input terminal of the amplifier may not be directly connected to the output terminal of the amplifier, but may be connected via another circuit.

[0172] In addition, the circuit configuration of a plurality of flip-flops included in the logic circuit of this embodiment is common. It is not necessary to change the circuit configuration for each flip-flop depending on the application.

[0173] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine the contents of the above with parts of the above or with the contents of other embodiments or parts of the above. do.

[0174] (Embodiment 7) In this embodiment, an example of a transistor included in the logic circuit described in any of Embodiments 1 to 6 will be described. Specifically, the logic circuit has a P-type transistor, A transistor formed using a substrate containing a material is applied, and an oxide is used as an N-type transistor. An example in which a transistor formed using a nitride semiconductor is used will be described.

[0175] <Configuration example> FIG. 11 shows the P-type transistor and the N-type transistor of the logic circuit of this embodiment. vinegar.

[0176] The P-type transistor 160 shown in FIG. 11 is a transistor provided on a substrate 100 including a semiconductor material. A channel forming region 116 and a pair of impurity doped regions disposed on either side of the channel forming region 116 Regions 114a and 114b and a pair of high concentration impurity regions 120a and 120b ( A gate insulating layer 116 is formed on the channel forming region 116. 108a, a gate electrode layer 110a provided on the gate insulating layer 108a, and an impurity region A source electrode layer 130a electrically connected to the impurity region 114a and a source electrode layer 130b electrically connected to the impurity region 114b are provided. and a drain electrode layer 130b connected to the drain electrode layer 130.

[0177] Sidewall insulating layers 118 are provided on the sides of the gate electrode layer 110a. In addition, in the region of the substrate 100 including the semiconductor material that does not overlap with the sidewall insulating layer 118, has a pair of high concentration impurity regions 120a and 120b, A pair of metal compound regions 124a and 124b are present on the substrate 1. An element isolation insulating layer 106 is provided on the transistor 160 so as to surround the transistor 160. An interlayer insulating layer 126 and an interlayer insulating layer 128 are provided to cover the transistor 160. The source electrode layer 130a and the drain electrode layer 130b are formed by insulating the interlayer 126 and the interlayer Through an opening formed in the insulating layer 128, one of the pair of metal compound regions 124a, 124b That is, the source electrode layer 130a is electrically connected to the metal compound region 124. a, and is electrically connected to the high concentration impurity region 120a and the impurity region 114a. The drain electrode layer 130b is connected to the high concentration impurity region 120b via the metal compound region 124b. and is electrically connected to impurity region 114b.

[0178] In addition, the lower layer of the N-type transistor 164 described later is made of the same material as the gate insulating layer 108a. an insulating layer 108b made of the same material as the gate electrode layer 110a; The electrode layer 130 is made of the same material as the source electrode layer 130a and the drain electrode layer 130b. c is provided.

[0179] The N-type transistor 164 shown in FIG. a gate insulating layer 138 provided on the gate electrode layer 136d; an oxide semiconductor layer 140 provided over the layer 138; A source electrode layer 142a electrically connected to the oxide semiconductor layer 140 and a drain electrode layer 142b.

[0180] Here, the gate electrode layer 136d is formed on the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode layer 136d, the P-type transistor The electrode layer 136a in contact with the source electrode layer 130a and the drain electrode layer 136b in contact with the source electrode layer 130a are included in the transistor 160. An electrode layer 136b is formed in contact with the electrode layer 30b. 136c is formed.

[0181] In addition, a protective layer is provided on the transistor 164 so as to be in contact with part of the oxide semiconductor layer 140. A protective insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode layer 142a. An opening is provided that reaches the drain electrode layer 142b. An electrode layer 150d in contact with the source electrode layer 142a, an electrode layer 150b in contact with the drain electrode layer 142b, Similarly to the electrode layers 150d and 150e, a gate insulating layer 50e is formed. The electrode layer 13 is exposed through openings provided in the layer 138, the protective insulating layer 144, and the interlayer insulating layer 146. Electrode layer 150a in contact with electrode layer 136a, electrode layer 150b in contact with electrode layer 136b, and electrode layer 13 An electrode layer 150c is formed in contact with 6c.

[0182] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is highly purified. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 19 (atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 18 (atoms / cm 3 ) or less, and 5×10 17 (atoms / cm 3 ) or less It is more preferable that the hydrogen concentration in the oxide semiconductor layer 140 is sufficiently reduced and the oxide semiconductor layer 140 is highly purified. By using such a compound semiconductor layer, the transistor 164 can have excellent off-state current characteristics. For example, when the drain voltage Vd is +1V or +10V, and the gate voltage Vg is - In the range of 5V to -20V, the off-state current is 1×10 -13 [A] is as follows. By using the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and which is highly purified, The off-state current of the transistor 164 can be reduced. The hydrogen concentration in 40 was measured by secondary ion mass spectrometry (SIMS). The measurements were made using Mass Spectroscopy.

[0183] An insulating layer 152 is provided on the interlayer insulating layer 146. Electrode layers 154a, 154b, 154c, and 154d are provided so as to include The electrode layer 154a is in contact with the electrode layer 150a, and the electrode layer 154b is in contact with the electrode layer 150a. The electrode layer 154c is in contact with the electrode layer 150c and the electrode layer 150d. electrode layer 154d contacts electrode layer 150e.

[0184] The source electrode layer 130a of the P-type transistor 160 shown in this embodiment is an upper layer region. The electrode layer 136a, the electrode layer 150a, and the electrode layer 154a are electrically connected to the electrode layer 136a, the electrode layer 150a, and the electrode layer 154a provided in the region. Therefore, the source electrode layer 130a of the P-type transistor 160 is formed by these conductive layers. By appropriately forming the electrodes of the N-type transistor 164 provided in the upper layer region, It is possible to electrically connect the P-type transistor to any of the layers. Similarly, the drain electrode layer 130b is also formed on the N-type transistor 16 provided in the upper layer region. It is possible to electrically connect the electrode layer of the semiconductor device 4 to any of the electrode layers of the semiconductor device 4. Although not shown, the gate electrode layer 110a of the P-type transistor 160 is The N-type transistor 164 is electrically connected to one of the electrode layers of the N-type transistor 164 via the electrode layer provided on the Alternatively, the two devices may be connected in a mutually mutually exclusive manner.

[0185] Similarly, the source electrode layer 142a of the N-type transistor 164 shown in this embodiment is , and is electrically connected to the electrode layer 130c and the electrode layer 110b provided in the lower layer region. Therefore, the source electrode layer 142a of the N-type transistor 164 is formed by appropriately forming these conductive layers. By this, the gate electrode layer 110a of the P-type transistor 160 provided in the lower layer region , the source electrode layer 130a, or the drain electrode layer 130b. Although not shown in FIG. 11, the gate voltage of the N-type transistor 164 is The electrode layer 136d or the drain electrode layer 142b is connected to the P Alternatively, the second electrode layer 162 may be electrically connected to any of the electrode layers of the second transistor 160. Cut.

[0186] By providing a plurality of the above-mentioned P-type transistors 160 and N-type transistors 164, In this way, the logic circuits shown in the first to sixth embodiments can be configured. All of the N-type transistors 164 in the logic circuit are transistors formed using oxide semiconductors. It is not necessary to use a single transistor, but it can be changed as appropriate according to the characteristics required for each transistor. For example, semiconductor materials can be used for N-type transistors, which require high speed operation. It is required to apply a transistor formed using a substrate including the A transistor formed using an oxide semiconductor is used as an N-type transistor. It is possible.

[0187] <Production process example> Next, an example of a method for manufacturing the P-type transistor 160 and the N-type transistor 164 will be described. First, a method for fabricating a P-type transistor 160 will be described with reference to FIG. Then, a method for fabricating the N-type transistor 164 will be described with reference to FIGS. This will be explained with reference to 4.

[0188] First, a substrate 100 containing a semiconductor material is prepared (see FIG. 12(A)). The substrate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates can be used. Here, a single crystal silicon substrate is used as the substrate 100 containing a semiconductor material. In general, an "SOI substrate" is a substrate that has silicon on an insulating surface. In this specification, the term refers to a substrate having a silicon semiconductor layer on an insulating surface. This concept also includes substrates with semiconductor layers made of materials other than silicon. That is, the semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The OI substrate is configured with a semiconductor layer provided on an insulating substrate such as a glass substrate via an insulating layer. This also includes.

[0189] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 12(A)). The protective layer 102 is made of, for example, silicon oxide or silicon nitride. An insulating layer made of silicon oxide or silicon oxynitride can be used. Before and after, in order to control the threshold voltage of the semiconductor device, a non-conductive layer that imparts n-type conductivity is A pure element or an impurity element that imparts p-type conductivity may be added to the substrate 100. In the case of silicon, impurities that give n-type conductivity include, for example, phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron, aluminum, and the like. For example, minium, gallium, etc. can be used.

[0190] Next, etching is performed using the protective layer 102 as a mask. The part of the substrate 100 in the area where the ion implantation is not performed (exposed area) is removed. A semiconductor region 104 is formed (see FIG. 12(B)). It is preferable to use a gas such as zinc etchant, but wet etching may also be used. The etching solution can be appropriately selected depending on the material to be etched.

[0191] Next, an insulating layer is formed so as to cover the semiconductor region 104, and an insulating layer is formed in a region overlapping the semiconductor region 104. The insulating layer in the region is selectively removed to form an element isolation insulating layer 106 (FIG. 12(B) The insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride, etc. The insulating layer is removed by chemical mechanical polishing (CMP). There are polishing processes such as polishing and etching, After the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106, Afterwards, the protective layer 102 is removed.

[0192] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0193] The insulating layer will later become the gate insulating layer, and is deposited using CVD, sputtering, etc. Obtained silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or a multilayer structure of a film containing tungsten oxide, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. It is performed using a mixture of rare gases such as Xe, oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen. The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 100 nm or less. nm or less.

[0194] The layer containing the conductive material is a metal material such as aluminum, copper, titanium, tantalum, or tungsten. The insulating layer can be formed of a semiconductor material such as polycrystalline silicon that contains a conductive material. The method for forming the layer containing the conductive material is not particularly limited, and examples thereof include a deposition method, Various film formation methods such as CVD, sputtering, and spin coating can be used. In this embodiment, the layer containing a conductive material is formed using a metal material. This section shall show the following:

[0195] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 10. 8a, a gate electrode layer 110a is formed (see FIG. 12(C)).

[0196] Next, an insulating layer 112 is formed to cover the gate electrode layer 110a (see FIG. 12(C)). Then, boron (B) or aluminum (Al) is added to the semiconductor region 104 to form a shallow junction. A pair of impurity regions 114a and 114b having a depth of 114 mm are formed (see FIG. 12(C)). In this case, boron or aluminum is added to form a p-type transistor, but in the case of an n-type transistor, When forming a transistor, impurity elements such as phosphorus (P) and arsenic (As) are added. By forming the pair of impurity regions 114a and 114b, A channel formation region 116 is formed under the gate insulating layer 108a (see FIG. 12(C)). Here, the concentration of the added impurities can be set appropriately, but as semiconductor devices become more advanced, In the case where the insulating layer is made finer, it is desirable to increase the concentration. After forming 112, a pair of impurity regions 114a and 114b are formed. However, the step of forming the insulating layer 112 after forming the pair of impurity regions 114a and 114b is It is also possible to say this.

[0197] Next, the sidewall insulating layer 118 is formed (see FIG. 12(D)). The insulating layer 118 is formed by forming an insulating layer so as to cover the insulating layer 112 and then applying anisotropic By applying a highly efficient etching process, the structure can be formed in a self-aligned manner. At this time, the insulating layer 112 is partially etched to form a pair of upper surfaces of the gate electrode layer 110a and the insulating layer 112. It is preferable to expose the upper surfaces of the impurity regions 114a and 114b.

[0198] Next, the gate electrode layer 110a, the pair of impurity regions 114a and 114b, the sidewall An insulating layer is formed to cover the insulating layer 118 and the like. Boron (B) and aluminum (Al) are added to a part of 114b to form a pair of high-concentration In this case, the N-type transistor is also formed. When forming a transistor, impurity elements such as phosphorus (P) and arsenic (As) can be added. After that, the insulating layer is removed, and the gate electrode layer 110a and the sidewall insulating layer 11 are left. 8. A metal layer 122 is formed so as to cover the pair of high concentration impurity regions 120a, 120b, etc. (See FIG. 12(E)). The metal layer 122 is formed by vacuum deposition, sputtering, spin coating, or the like. The metal layer 122 can be formed by using various film formation methods such as a deposition method. 4 is formed using a metal material that reacts with the semiconductor material constituting the layer to form a low-resistance metal compound. Such metal materials include, for example, titanium, tantalum, and tungsten. Examples include nickel, cobalt, and platinum.

[0199] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A pair of metal compound regions 124a, 124b are in contact with the high concentration impurity regions 120a, 120b. b is formed (see FIG. 12(F)). When using a metal layer such as a fluorine atom, the portion of the gate electrode layer 110a that comes into contact with the metal layer 122 is also provided with a metal layer. A generic compound region is formed.

[0200] As the heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but chemical reactions involving the formation of metal compounds are preferred. In order to improve the controllability of the reaction, it is necessary to use a method that allows for very short heat treatment times. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in the region having a sufficiently high electrical conductivity. By doing so, the electrical resistance can be sufficiently reduced, and the element characteristics can be improved. After metal compound regions 124a, 124b are formed, metal layer 122 is removed.

[0201] Next, an interlayer insulating layer 126 and an interlayer insulating film 127 are formed to cover the respective components formed by the above-mentioned steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by using an oxide film. Silicon oxide, silicon nitride, silicon oxide, hafnium oxide, aluminum oxide, The insulating layer 11 can be formed using a material containing an inorganic insulating material such as tantalum chloride. It is also possible to form the layer using an organic insulating material such as polycarbonate or acrylic. The structure has a two-layer structure of an interlayer insulating layer 126 and an interlayer insulating layer 128. After the interlayer insulating layer 128 is formed, the surface of the interlayer insulating layer 128 may be subjected to a process such as CMP or etching. It is desirable to flatten the surface by using a method such as flattening.

[0202] Thereafter, openings are formed in the interlayer insulating layer, the openings reaching the pair of metal compound regions 124a and 124b. An opening is formed, and the source electrode layer 130a and the drain electrode layer 130b are formed in the opening. The source electrode layer 130a and the drain electrode layer 130b are, for example, After forming a conductive layer in the area including the opening using PVD or CVD, etching and It can be formed by removing a portion of the conductive layer using a method such as CMP. Cut.

[0203] When the source electrode layer 130a and the drain electrode layer 130b are formed, For example, a titanium film or a nitride film is applied to the area including the opening. When a thin titanium film is formed and then a tungsten film is formed to fill the opening, Then, unnecessary tungsten, titanium, titanium nitride, etc. are removed by CMP. In addition, the surface flatness of the source electrode layer 130a can be improved. By planarizing the surface including the drain electrode layer 130b, the following steps can be performed satisfactorily. It becomes possible to form favorable electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0204] In this case, the source electrode layer 1 in contact with the pair of metal compound regions 124a and 124b is Although only the drain electrode layer 30a and the drain electrode layer 130b are shown, in this step, A functional electrode layer (for example, electrode layer 130c in FIG. 11) and the like are also formed. The source electrode layer 130a and the drain electrode layer 130b can be formed by using the above-mentioned compound. There is no particular limitation on the material, and various conductive materials can be used. For example, molybdenum , titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium A conductive material such as rubber can be used.

[0205] As a result of the above, a P-type transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, an insulating layer, etc. may be further formed. The multi-layer wiring structure is made of a laminated structure of an interlayer insulating layer and a conductive layer. In this way, a highly integrated logic circuit can be provided. Therefore, it is also possible to form an N-type transistor using the substrate 100 containing a semiconductor material. That is, in the above-mentioned process, the impurity element to be added to the semiconductor region is phosphorus (P). By changing the impurity element to arsenic (As), an N-type transistor is formed. It is possible.

[0206] Next, referring to FIG. 13 and FIG. 14, an N-type transistor 164 is formed on the interlayer insulating layer 128. 13 and 14 show the steps of forming the interlayer insulating layer 128. Since this shows the manufacturing process of the seed electrode layer and the N-type transistor 164, The P-type transistor 160 and other components located below the resistor 164 are omitted.

[0207] First, the interlayer insulating layer 128, the source electrode layer 130a, the drain electrode layer 130b, and the electrode layer 1 An insulating layer 132 is formed on the insulating layer 30c (see FIG. 13(A)). The insulating layer 132 is formed by a PVD method or a C It can be formed by using a VD method or the like. Also, silicon oxide, silicon nitride oxide, or nitride Inorganic insulating materials such as silicon oxide, hafnium oxide, aluminum oxide, and tantalum oxide The material can be used to form the insulating film.

[0208] Next, the source electrode layer 130a, the drain electrode layer 130b, and An opening is formed that reaches the electrode layer 130c. At this time, the gate electrode layer 136d is to be formed later. An opening is also formed in the area where the conductive layer 13 is to be formed. 4 is formed (see FIG. 13(B)). The opening is formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. The etching method can be either wet etching or dry etching. Either method may be used, but from the viewpoint of fine processing, it is preferable to use dry etching. The conductive layer 134 can be formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 134 include molybdenum, titanium, chromium, and tantalum. Conductive materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium Examples of such materials include conductive materials, alloys thereof, and compounds (for example, nitrides).

[0209] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and C After forming a thin titanium nitride film by the VD method, a tungsten film is deposited to fill the opening. The titanium film formed by the PVD method is The oxide film at the interface is reduced, and the lower electrode layer (here, the source electrode layer 130a and the drain electrode layer The contact resistance between the insulating layer 130 and the electrode layer 130b, the electrode layer 130c, etc. is reduced. The titanium nitride film formed in the above has a barrier function to suppress the diffusion of conductive materials. After forming a barrier film using titanium or titanium nitride, a copper film is formed by plating. Good too.

[0210] After the conductive layer 134 is formed, the conductive layer 134 is removed by a method such as etching or CMP. 134 is removed to expose the insulating layer 132, and the electrode layers 136a, 136b, An electrode layer 136c and a gate electrode layer 136d are formed (see FIG. 13(C)). A part of the electrode layer 134 is removed to form the electrode layers 136a, 136b, 136c, and the gate When forming the electrode layer 136d, it is desirable to process it so that the surface is flat. As shown in FIG. 1, the insulating layer 132, the electrode layer 136a, the electrode layer 136b, the electrode layer 136c, the gate electrode By planarizing the surface of the electrode layer 136d, it is possible to form good electrodes, wiring, and insulation in the subsequent steps. It is possible to form an insulating layer, a semiconductor layer, etc.

[0211] Next, the insulating layer 132, the electrode layer 136a, the electrode layer 136b, the electrode layer 136c, and the gate electrode A gate insulating layer 138 is formed to cover the layer 136d (see FIG. 13(D)). The insulating layer 138 can be formed by using a CVD method, a sputtering method, or the like. The gate insulating layer 138 may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or aluminum oxide. It is preferable that the oxide layer contains tungsten oxide, hafnium oxide, tantalum oxide, etc. The gate insulating layer 138 may have a single layer structure or a stacked layer structure. The plasma CVD method uses silane (SiH4), oxygen, and nitrogen as the source gases to oxidize the The gate insulating layer 138 may be formed of silicon nitride. The thickness of the gate insulating layer 138 may be is not particularly limited, but may be, for example, 10 nm or more and 500 nm or less. In the case of the structure, for example, a first gate insulating layer having a thickness of 50 nm or more and 200 nm or less and a first A second gate insulating layer having a thickness of 5 nm to 300 nm is laminated on the gate insulating layer. This is preferable.

[0212] Note that an oxide semiconductor that has been made i-type or substantially i-type by removing impurities ( Since highly purified oxide semiconductors are extremely sensitive to interface states and interface charges, When such an oxide semiconductor is used for the oxide semiconductor layer, the interface with the gate insulating layer is heavily That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer is There will be a demand for quality improvement.

[0213] For example, the high-density plasma CVD method using microwaves (2.45 GHz) has a high dielectric strength and This is advantageous in that a high-quality gate insulating layer 138 with high purity can be formed. The close contact between the semiconductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. This is because it can be made to be a good one.

[0214] Of course, if it can form a good insulating layer as a gate insulating layer, it is possible to use it with high purification. Even when an oxide semiconductor layer is used, other methods such as sputtering and plasma CVD are used. The above method can be applied. In addition, the film quality and interface characteristics can be improved by heat treatment after formation. In any case, a layer having good film quality as the gate insulating layer 138 may be used. In addition, the interface state density with the oxide semiconductor layer can be reduced, and a good interface can be formed. All we need to do is form one.

[0215] Furthermore, at 85°C, 2 × 10 6 (V / cm), 12-hour gate bias-thermal stress test In a BT test, when impurities are added to an oxide semiconductor, the impurities and the oxide The bonds with the main component of the semiconductor are broken by a strong electric field (B: bias) and high temperature (T: temperature). The generated dangling bonds induce a drift in the threshold voltage (Vth).

[0216] In response to this, impurities in the oxide semiconductor, particularly hydrogen and water, are eliminated as much as possible, and the above-mentioned By improving the interface characteristics with the gate insulating layer, the transistor is stable even in BT tests. It is possible to obtain stars.

[0217] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by a method such as etching to form an island-shaped oxide semiconductor layer 140. (See FIG. 13(E)).

[0218] The oxide semiconductor layer may be In-Ga-Zn-O, In-Sn-Zn-O, or In- Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Z nO series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn It is preferable to use a Zn-O-based or Zn-O-based oxide semiconductor layer, and in particular an amorphous oxide semiconductor layer. In this embodiment, an In-Ga-Zn-O based metal oxide ter is used as the oxide semiconductor layer. An amorphous oxide semiconductor layer is formed by a sputtering method using the get. By adding silicon to an amorphous oxide semiconductor layer, crystallization of the layer can be suppressed. For example, a target containing 2% to 10% by weight of SiO2 is used to perform oxidation. A compound semiconductor layer may be formed.

[0219] As a target for forming an oxide semiconductor layer by a sputtering method, for example, A target made of a metal oxide mainly composed of zinc oxide can be used. Metal oxide target containing Ga and Zn (composition ratio: In2O3:Ga2O3 :ZnO=1:1:1[mol], In:Ga:Zn=1:1:0.5[atom]) Also, metal oxide targets containing In, Ga, and Zn can be used. Then, In:Ga:Zn=1:1:1[atom], or In:Ga:Zn=1:1: A target having a composition ratio of 2 [atom] may be used. Metal oxide target The filling rate is 90% or more and 100% or less, preferably 95% or more (e.g., 99.9%). By using a metal oxide target with a high filling rate, a dense oxide semiconductor layer is formed. will be done.

[0220] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Alternatively, it is preferable to use a mixed atmosphere of a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are preferably present at a level of several ppm. It is preferable to use a high-purity gas in which the concentration of contaminants has been reduced to about a few ppb.

[0221] When the oxide semiconductor layer is formed, the substrate is held in a treatment chamber that is kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating, the impurity concentration in the oxide semiconductor layer Also, damage caused by sputtering is reduced. The residual moisture in the chamber is removed and a sputtering gas from which hydrogen and water have been removed is introduced to form a metal oxide. The oxide semiconductor layer is formed by using the target as a target. It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump is used. A titanium sublimation pump or a titanium sublimation pump can be used as the exhaust means. A cryopump with a cold trap may be used. The process chamber is filled with, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since the oxide semiconductor formed in the processing chamber is exhausted, The concentration of impurities contained in the body layer can be reduced.

[0222] The formation conditions are, for example, a distance of 100 mm between the substrate and the target and a pressure of 0. 6 Pa, DC power 0.5 kW, oxygen atmosphere (oxygen flow rate 100%) In addition, if a pulsed direct current (DC) power supply is used, This reduces the amount of powdery material (also called particles or dust) that is generated during film formation, and the film thickness distribution is uniform. The thickness of the oxide semiconductor layer is preferably 2 nm or more and 200 nm or less. The thickness is 5 nm to 30 nm. Note that the appropriate thickness varies depending on the oxide semiconductor material used. Therefore, the thickness may be appropriately selected depending on the material used.

[0223] Before forming the oxide semiconductor layer by a sputtering method, argon gas was introduced into the preheater. A reverse sputtering process is performed to generate plasma, and the dust adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtered material by removing the sputtered material. Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The surface is then modified by bombarding it with ions. In the method, a high-frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. In addition, nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. is also good.

[0224] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both can be used in combination. In order to etch the material, the etching conditions (etching gas, etching solution, etc.) are adjusted according to the material. Etching time, temperature, etc. are set appropriately.

[0225] The etching gas used in the dry etching is, for example, a gas containing chlorine (a chlorine-based gas). For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CCl4, etc.). In addition, gases containing fluorine (fluorine-based gases, such as tetrafluoride Carbon (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), trifluoromethane (CH F3), hydrogen bromide (HBr), oxygen (O2), and helium (He) and A gas containing a rare gas such as argon (Ar) may also be used.

[0226] As a dry etching method, parallel plate type RIE (Reactive Ion Etc. fing method and ICP (Inductively Coupled Plasma) Inductively coupled plasma etching can be used. It can be etched into the desired shape. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate side, etc. are set appropriately.

[0227] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. In addition, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's fine.

[0228] Next, the oxide semiconductor layer is preferably subjected to a first heat treatment. The temperature of the first heat treatment can be set to 1000° C., so that the oxide semiconductor layer can be dehydrated or dehydrogenated. The temperature is set to 300° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the distortion point of the substrate. For example, The substrate is placed in an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. A heat treatment is performed at 450° C. for 1 hour in an atmosphere. During this time, the oxide semiconductor layer 140 is Ensure that there is no contact with the gas and that no water or hydrogen is re-mixed.

[0229] The heat treatment device is not limited to an electric furnace, and may be any device that utilizes heat conduction from a medium such as a heated gas, or The heating device may be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Annealing equipment such as RTA (Rapid Thermal Annealing) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the workpiece during heat treatment, such as a rare gas such as argon or nitrogen. Sexual gas is used.

[0230] For example, the first heat treatment is performed by subjecting the substrate to a base in an inert gas heated to a high temperature of 650° C. to 700° C. The plate is put in and heated for a few minutes, after which the GRTA process is carried out, in which the plate is removed from the inert gas. GRTA treatment allows high-temperature heat treatment in a short time. Since this is a heat treatment, it can be applied even under temperature conditions that exceed the distortion point of the substrate.

[0231] The first heat treatment is performed in a vacuum chamber mainly composed of nitrogen or a rare gas (helium, neon, argon, etc.). It is preferable to carry out the process in an atmosphere that does not contain water, hydrogen, etc. For example, the purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device may be , 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. That is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0232] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may become crystalline. For example, the crystallinity is 90% or more, or 80% or more. In some cases, the oxide semiconductor layer may be a microcrystalline oxide semiconductor layer having a crystallinity of 0% or more. Depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor layer that does not contain crystalline components. There are cases like this.

[0233] In addition, microcrystals (grain size 1 nm) are formed in the amorphous oxide semiconductor (for example, the surface of the oxide semiconductor layer). and 20 nm or less (typically 2 nm or more and 4 nm or less) are mixed. In some cases.

[0234] In addition, the electrical characteristics of the oxide semiconductor layer can be changed by arranging microcrystals in the amorphous state. For example, it is possible to use an In-Ga-Zn-O metal oxide target. When forming an oxide semiconductor layer, the crystal of In2Ga2ZnO7, which has electrical anisotropy, is used. By forming a microcrystal part in which grains are oriented, the electrical characteristics of an oxide semiconductor layer are changed. can be done.

[0235] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in a specific direction, the electrical conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. As a result, the insulating property in a direction perpendicular to the surface of the oxide semiconductor layer can be improved. Such a microcrystal portion has a function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. Possesses the ability.

[0236] Note that the oxide semiconductor layer having the above-described microcrystal portion is an oxide semiconductor layer formed by GRTA treatment. The Zn content can be reduced by heating the surface of the Zn alloy. By using a sputtering target smaller than the amount of .

[0237] The first heat treatment for the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In that case, the first heat treatment may be performed on the oxide semiconductor layer before the first heat treatment. The substrate is then removed from the mold and a photolithography process is performed.

[0238] The heat treatment may have a dehydration or dehydrogenation effect on the oxide semiconductor layer 140. Such dehydration treatment, dehydrogenation treatment, etc. The oxidation treatment is carried out by forming a source electrode layer and a drain electrode layer on the oxide semiconductor layer 140 after the oxide semiconductor layer is formed. After laminating the source electrode layer, or forming a protective insulating layer on the source electrode layer and the drain electrode layer, In addition, such a dehydration treatment can be performed at any time, such as after the dehydration treatment. The dehydrogenation treatment may be carried out not only once but also multiple times.

[0239] Next, the source electrode layer 142a and the drain electrode The source electrode layer 142a and the drain electrode layer 142b are formed (see FIG. 13F). In the example shown in FIG. 142b, a conductive layer is formed so as to cover the oxide semiconductor layer 140, and then the conductive layer is selectively removed. The insulating layer can be formed by selectively etching the insulating layer.

[0240] The conductive layer is formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. The conductive layer can be formed by a method such as a method for forming a conductive layer using aluminum, chromium, or the like. , copper, tantalum, titanium, molybdenum, tungsten, or any of the elements mentioned above. The alloys containing manganese, magnesium, zirconium, borium, etc. can be used. Alternatively, a material selected from one or more of thorium and lithium may be used. Aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, steel A material containing a single element selected from the group consisting of candium or a combination of multiple elements may be used. The layer may be a single layer structure or a laminated structure of two or more layers. For example, silicon a single-layer structure of an aluminum film containing titanium; a two-layer structure in which a titanium film is laminated on an aluminum film; One example is a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated.

[0241] Here, the exposure to light when forming the mask used for etching is performed using ultraviolet light, KrF laser light, or Ar It is preferable to use F laser light.

[0242] The channel length (L) of the transistor is determined by the distance between the bottom end of the source electrode layer 142a and the drain electrode It is determined by the distance between the bottom end of the layer 142b and the channel length (L) of less than 25 nm. When performing exposure to ultraviolet light, the wavelength is extremely short, ranging from a few nm to a few tens of nm. Exposure to form a mask is performed using ultra violet. The ion implantation method has high resolution and a large depth of focus. Therefore, the channel length of the transistor to be formed later can be reduced. It is also possible to set (L) to 10 nm or more and 1000 nm or less, thereby enabling high-speed circuit operation. It can be made.

[0243] In addition, when etching the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted as appropriate. Therefore, in this step, a part of the oxide semiconductor layer 140 is etched, and a groove (a recess In some cases, the oxide semiconductor layer may have a gate insulating film.

[0244] In addition, between the oxide semiconductor layer 140 and the source electrode layer 142a or between the oxide semiconductor layer 140 and the source electrode layer 142b, An oxide conductive layer may be formed between the drain electrode layer 142b and the oxide conductive layer. The metal layers for forming the source electrode layer 142a and the drain electrode layer 142b are continuously formed. The oxide conductive layer can be formed in the source region or the drain region. By providing such an oxide conductive layer, the source region or the drain region can be formed. Since the resistance of the gate region can be reduced, high-speed operation of the transistor can be achieved.

[0245] In order to reduce the number of masks used and the number of processes, the exposure method is used in which the transmitted light has multiple intensities. A resist mask is formed using a multi-tone optical mask, and this is used for etching. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used in multiple etching processes to process different patterns. By using the multi-tone mask, resist patterns corresponding to at least two different patterns can be produced. Therefore, the number of exposure masks can be reduced, and the corresponding The photolithography process can also be eliminated, simplifying the process.

[0246] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the exposed surface of the oxide semiconductor layer is treated by the plasma treatment. Water and other substances adhering to the surface are removed. In addition, plasma treatment is performed using a mixture of oxygen and argon gas. may be carried out.

[0247] Next, the protective insulating layer 1 in contact with a part of the oxide semiconductor layer 140 is removed without exposing it to the air. 44 is formed (see FIG. 13(G)).

[0248] The protective insulating layer 144 is formed by mixing impurities such as water and hydrogen into the protective insulating layer 144 using a method such as sputtering. The thickness of the layer is at least 1 nm. The protective insulating layer 144 can be formed of a material such as silicon oxide or silicon nitride. , silicon oxynitride, silicon nitride oxide, etc. Also, the structure may be a single layer structure. The substrate temperature when the protective insulating layer 144 is formed is set to room temperature or higher and 300 The temperature is preferably set to 0.4 ° C. or less, and the atmosphere is a rare gas (typically argon) atmosphere or an oxygen atmosphere. It is preferable to use an atmosphere of oxygen or a mixture of a rare gas (typically argon) and oxygen.

[0249] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer 140 or The hydrogen extracts oxygen from the oxide semiconductor layer 140, and the oxide semiconductor layer 14 The back channel side of MOSFET 0 becomes low-resistance, which may result in the formation of a parasitic channel. Therefore, in order to prevent the protective insulating layer 144 from containing hydrogen as much as possible, the formation method is It is important not to use

[0250] In addition, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The oxide semiconductor layer 140 and the protective insulating layer 144 are preferably formed so as not to contain hydrogen, a hydroxyl group, or moisture. This is to make it possible.

[0251] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The process chamber evacuated using a cryopump may contain hydrogen atoms, water (H Since compounds containing hydrogen atoms such as 2O) have been removed, the protective insulating material formed in the treatment chamber The concentration of impurities contained in the edge layer 144 can be reduced.

[0252] The sputtering gas used in forming the protective insulating layer 144 may be hydrogen, water, a hydroxyl group, or Impurities such as hydrides are removed to a few ppm (preferably a few ppb). It is preferable to use a high purity gas.

[0253] Then, a second heat treatment (preferably 2 It is preferable to carry out the heating at a temperature between 00°C and 400°C, for example between 250°C and 350°C. For example, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The variation in the electrical characteristics of the transistors can be reduced.

[0254] In addition, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed by holding the temperature constant or by heating from room temperature to 100°C. Repeat heating to a temperature of 200°C or more and cooling from the heating temperature to room temperature several times. This heat treatment may be carried out under reduced pressure before the formation of the protective insulating layer. If the heat treatment is performed under reduced pressure, the heating time can be shortened. This may be carried out instead of the second heat treatment, or may be carried out before or after the second heat treatment.

[0255] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 14(A)). The interlayer insulating layer 146 can be formed by using a PVD method, a CVD method, or the like. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as tantalum. After formation, the surface can be flattened by methods such as CMP or etching. desirable.

[0256] Next, electrodes are formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. Layer 136a, electrode layer 136b, electrode layer 136c, source electrode layer 142a, drain electrode layer An opening is formed that reaches 142b, and a conductive layer 148 is formed so as to fill the opening. (See FIG. 14(B)). The opening is formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. It is possible. Either wet etching or dry etching can be used. However, from the viewpoint of fine processing, it is preferable to use dry etching. The layer 148 can be formed by a deposition method such as a PVD method or a CVD method. Materials that can be used to form 148 include molybdenum, titanium, chromium, tantalum, and the like. Conductive materials such as zinc, tungsten, aluminum, copper, neodymium, and scandium, Examples of such materials include alloys and compounds (eg, nitrides) of these materials.

[0257] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CVD After forming a thin titanium nitride film by the method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method has an interface The oxide film of the lower electrode (here, electrode layer 136a, electrode layer 136b, electrode layer 136c) is reduced. 6c) a function of reducing contact resistance with the source electrode layer 142a and the drain electrode layer 142b) The titanium nitride formed thereafter also acts as a barrier to inhibit the diffusion of conductive materials. In addition, after forming a barrier film using titanium or titanium nitride, etc., a plating method is used. Alternatively, the copper film may be formed by

[0258] After the conductive layer 148 is formed, the conductive layer 14 is removed by a method such as etching or CMP. 8 is removed to expose the interlayer insulating layer 146, and the electrode layers 150a, 150b, Electrode layers 150c, 150d, and 150e are formed (see FIG. 14(C)). A part of the conductive layer 148 is removed to form the electrode layer 150a, the electrode layer 150b, and the electrode layer 150 c) When forming the electrode layer 150d and the electrode layer 150e, the surfaces are processed to be flat. In this manner, the interlayer insulating layer 146, the electrode layer 150a, the electrode layer 150b, The surfaces of the electrode layers 150c, 150d, and 150e are flattened, so that the following In the process, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, and the like.

[0259] Further, an insulating layer 152 is formed, and the electrode layers 150a, 150b, Openings are formed so as to reach the electrode layers 150c, 150d, and 150e. After forming a conductive layer so as to embed the conductive layer in the A part of the insulating layer 152 is removed to expose the electrode layer 154a, the electrode layer 154b, and the electrode layer 1 54c, an electrode layer 154d is formed (see FIG. 14(D)). Since this is similar to the case of forming the above, details will be omitted.

[0260] When the N-type transistor 164 is fabricated by the above-described method, the oxide semiconductor layer 140 Hydrogen concentration is 5 x 10 19 (atoms / cm 3 ) or less, and N-type transistor 1 The off-state current of 64 is 1×10 at room temperature. -13 [A] or less. Such excellent By applying the N-type transistor 164 having the above characteristics to the logic circuits shown in the first to sixth embodiments, Therefore, it is possible to reduce the standby power consumption of the logic circuit and to suppress malfunction of the logic circuit. It becomes possible.

[0261] <Modification> 15 to 18 show modified examples of the configuration of the N-type transistor 164. 18, the structure of the transistor 160 is similar to that shown in FIG.

[0262] FIG. 15 shows a gate electrode layer 136d under an oxide semiconductor layer 140, and a source electrode layer The drain electrode layer 142a and the drain electrode layer 142b are in contact with each other on the lower surface of the oxide semiconductor layer 140. 1 shows an N-type transistor 164 having such a configuration.

[0263] A major difference between the configuration shown in FIG. 15 and the configuration shown in FIG. 11 is that the source electrode layer 142a and and the position of connection between the drain electrode layer 142b and the oxide semiconductor layer 140. In the configuration shown in FIG. 11, the source electrode layer 1 is formed on the upper surface of the oxide semiconductor layer 140. 15, the oxide layer 42a and the drain electrode layer 142b are in contact with each other. On the lower surface of the semiconductor layer 140, the source electrode layer 142a and the drain electrode layer 142b Due to this difference in contact, the arrangement of other electrode layers, insulating layers, etc. The details of each component are the same as those in FIG.

[0264] Specifically, the N-type transistor 164 shown in FIG. 15 is provided on the interlayer insulating layer 128. a gate electrode layer 136d formed thereon, and a gate insulating layer 138 formed on the gate electrode layer 136d. A source electrode layer 142a and a drain electrode layer 142b are provided on the gate insulating layer 138. b, and the oxide semiconductor in contact with the upper surfaces of the source electrode layer 142a and the drain electrode layer 142b. The N-type transistor 164 has an oxide semiconductor layer 140 on it. A protective insulating layer 144 is provided to cover the insulating film 140.

[0265] FIG. 16 shows an N-type transistor having a gate electrode layer 136d on an oxide semiconductor layer 140. 16A shows the source electrode layer 142a and the drain electrode layer 164. 142b is in contact with the oxide semiconductor layer 140 on the lower surface of the oxide semiconductor layer 140. FIG. 16B shows an example of a structure of a source electrode layer 142a and a drain electrode layer 14 2b is in contact with the oxide semiconductor layer 140 on the upper surface of the oxide semiconductor layer 140. FIG.

[0266] A major difference between the configuration shown in FIG. 11 or FIG. 15 and the configuration shown in FIG. 16 is that the oxide semiconductor layer 1 16(A) and 16(B) are different from each other in that the gate electrode layer 136d is provided on the gate electrode layer 136d. The major difference between the configuration shown in FIG. 16(B) is that the source electrode layer 142a and the drain electrode layer 14 2b contacts the lower surface or the upper surface of the oxide semiconductor layer 140, and Due to these differences, the arrangement of other electrode layers, insulating layers, etc. The details of each component are the same as those in FIG. 11 and the like.

[0267] Specifically, the N-type transistor 164 shown in FIG. 16A is provided on the interlayer insulating layer 128. The source electrode layer 142a and the drain electrode layer 142b are formed by the above-mentioned and an oxide semiconductor layer 140 in contact with the upper surface of the drain electrode layer 142b. A gate insulating layer 138 is provided on the gate insulating layer 140, and an oxide semiconductor layer 1 on the gate insulating layer 138. 40 and a gate electrode layer 136d in a region overlapping with the gate electrode 136a.

[0268] In addition, an N-type transistor 164 shown in FIG. 16(B) is provided on the interlayer insulating layer 128. The oxide semiconductor layer 140 is provided so as to be in contact with the upper surface of the oxide semiconductor layer 140. The source electrode layer 142a and the drain electrode layer 142b, the oxide semiconductor layer 140, and the source A gate insulating layer 138 is provided on the gate electrode layer 142a and the drain electrode layer 142b. A gate electrode layer 13 is provided in a region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138. 6d and.

[0269] In addition, in the configuration shown in FIG. 16, compared with the configuration shown in FIG. 11, components are omitted. In this case, the electrode layer 150a, the electrode layer 154a, etc. may be formed. Of course, in the configuration shown in FIG. It goes without saying that non-essential components can be omitted.

[0270] FIG. 17 shows a case where the size of the element is relatively large, and a The N-type transistor 164 is shown having a gate electrode layer 136d. Since the requirements for flatness and coverage are relatively low, wiring and electrodes can be easily insulated. It is not necessary to form the conductive layer so as to be embedded in the edge layer. For example, the conductive layer may be patterned after it is formed. By performing this process, the gate electrode layer 136d and the like can be formed.

[0271] The major difference between the configuration shown in FIG. 17(A) and the configuration shown in FIG. 17(B) is that the source electrode layer 1 42a and the drain electrode layer 142b are disposed on the lower or upper surface of the oxide semiconductor layer 140. And due to these differences, The arrangement of the electrode layers, insulating layers, etc. is different. This is similar to 11 etc.

[0272] Specifically, the N-type transistor 164 shown in FIG. 17A is provided on the interlayer insulating layer 128. A gate electrode layer 136d is formed on the gate electrode layer 136d. A gate insulating layer 1 is formed on the gate electrode layer 136d. 38, and a source electrode layer 142a and a drain electrode layer 142b provided on the gate insulating layer 138. 142b, and the oxide layer in contact with the upper surfaces of the source electrode layer 142a and the drain electrode layer 142b. and a semiconductor layer 140.

[0273] In addition, an N-type transistor 164 shown in FIG. 17(B) is provided on the interlayer insulating layer 128. a gate electrode layer 136d formed thereon, and a gate insulating layer 138 formed on the gate electrode layer 136d. The oxide semiconductor layer 136d is formed on the gate insulating layer 138 in a region overlapping the gate electrode layer 136d. a source electrode layer provided in contact with the upper surface of the oxide semiconductor layer; The drain electrode layer 142a and the drain electrode layer 142b.

[0274] In addition, the configuration shown in FIG. 17 also has fewer components than the configuration shown in FIG. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0275] FIG. 18 shows a case where the size of the element is relatively large, and a An N-type transistor 164 is shown having a gate electrode layer 136d. The requirements for surface flatness and coverage are relatively low, so wiring, electrodes, etc. It is not necessary to form the conductive layer so as to be embedded in the insulating layer. For example, the conductive layer may be patterned after the formation of the conductive layer. By performing etching, the gate electrode layer 136d and the like can be formed.

[0276] The major difference between the configuration shown in FIG. 18(A) and the configuration shown in FIG. 18(B) is that the source electrode layer 1 42a and the drain electrode layer 142b are disposed on the lower or upper surface of the oxide semiconductor layer 140. And due to these differences, The arrangement of the electrode layers, insulating layers, etc. is different. This is similar to 11 etc.

[0277] Specifically, the N-type transistor 164 shown in FIG. 18A is provided on the interlayer insulating layer 128. The source electrode layer 142a and the drain electrode layer 142b are formed by the above-mentioned The oxide semiconductor layer 140 in contact with the upper surfaces of the source electrode layer 142b and the drain electrode layer 142b, 42a, the drain electrode layer 142b, and the gate insulating film provided on the oxide semiconductor layer 140. the oxide semiconductor layer 140 provided over the gate insulating layer 138 and a gate electrode layer 136d.

[0278] In addition, an N-type transistor 164 shown in FIG. 18(B) is provided on the interlayer insulating layer 128. The oxide semiconductor layer 140 is provided so as to be in contact with the upper surface of the oxide semiconductor layer 140. The source electrode layer 142a and the drain electrode layer 142b are The gate insulating layer 138 is provided on the electrode layer 142b and the oxide semiconductor layer 140. A gate electrode layer 13 is provided in a region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138. 6d and.

[0279] In addition, the configuration shown in FIG. 18 also has fewer components than the configuration shown in FIG. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0280] In this embodiment, an N-type transistor 164 is stacked on a P-type transistor 160. The configuration of the P-type transistor 160 and the N-type transistor 164 has been described. For example, a P-type transistor and an N-type transistor may be arranged on the same plane. In addition, a P-type transistor 160 and an N-type transistor The sensor 162 may be provided so as to overlap the sensor 164.

[0281] The above-mentioned N-type transistor 164 is an N-type By applying this to a transistor, the leakage of electric charge through the thin film transistor is suppressed. As a result, the standby power consumption of the logic circuit can be reduced and malfunction of the logic circuit can be prevented. This makes it possible to suppress the operation.

[0282] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine the contents of the above with parts of the above or with the contents of other embodiments or parts of the above. do.

[0283] (Embodiment 8) In this embodiment, an example of a transistor included in the logic circuit described in any of Embodiments 1 to 6 will be described. Specifically, a thin film transistor having a channel formation region made of an oxide semiconductor will be described. An example of a film transistor will now be described.

[0284] One embodiment of a thin film transistor and a manufacturing method thereof will be described with reference to FIGS. I will explain this in more detail.

[0285] 19(A) and (B) show an example of a planar and cross-sectional structure of a thin film transistor. The thin film transistor 460 shown in (A) and (B) is a thin film transistor with a top gate structure. be.

[0286] FIG. 19(A) is a plan view of a thin film transistor 460 having a top gate structure. 19B) is a cross-sectional view taken along line D1-D2 in FIG. 19A.

[0287] The thin film transistor 460 is formed by forming an insulating layer 457, a source The electrode layer or drain electrode layer 465a (465a1, 465a2), the oxide semiconductor layer 462 , a source or drain electrode layer 465b, a wiring layer 468, a gate insulating layer 452, a gate The source electrode layer 461 (461a, 461b) and the source or drain electrode layer 465 a (465a1, 465a2) are electrically connected to the wiring layer 464 via the wiring layer 468. Although not shown, the source or drain electrode layer 465b is also a gate insulating layer. The layer 452 is electrically connected to the wiring layer through an opening provided therein.

[0288] 20(A) to (E), a thin film transistor 460 is formed on a substrate 450. The process for doing so will be described.

[0289] First, an insulating layer 457 serving as a base film is formed over a substrate 450 having an insulating surface.

[0290] In this embodiment, a silicon oxide layer is formed by a sputtering method as the insulating layer 457. The substrate 450 is transferred to a processing chamber, and a spa containing high-purity oxygen from which hydrogen and moisture have been removed is used. A target gas is introduced, and a silicon target or quartz (preferably synthetic quartz) is used to heat the substrate 4. A silicon oxide layer is formed as an insulating layer 457 on the substrate 50. The sputtering gas is Oxygen or a mixture of oxygen and argon can be used.

[0291] For example, the purity is 6N, quartz (preferably synthetic quartz) is used, the substrate temperature is 108° C., The distance between the substrate and the target (TS distance) was 60 mm, the pressure was 0.4 Pa, and the high frequency voltage was Power source 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = A silicon oxide layer is formed by RF sputtering in a 1:1 atmosphere. The thickness of the layer is 10 The thickness of the silicon target is set to 0 nm. It can be used as a target for depositing a silicon layer.

[0292] In this case, it is preferable to form the insulating layer 457 while removing residual moisture in the processing chamber. This is to prevent the insulating layer 457 from containing hydrogen, hydroxyl, or moisture. The process chamber evacuated using an ion pump contains compounds containing hydrogen atoms, such as water (H2O). Since compounds containing impurities are exhausted, the impurities contained in the insulating layer 457 formed in the processing chamber are The concentration can be reduced.

[0293] The insulating layer 457 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. It is preferable to use high-purity gas in which impurities have been removed to the level of a few ppm or a few ppb. I wish.

[0294] The insulating layer 457 may have a laminated structure, for example, a silicon nitride layer from the substrate 450 side, Nitride insulating layers such as silicon oxynitride layers, aluminum nitride layers, and aluminum oxynitride layers The insulating layer may have a stacked structure of the oxide insulating layer and the oxide insulating layer.

[0295] For example, a silicon oxide layer and a substrate are provided with a space between them that contains high-purity nitrogen from which hydrogen and moisture have been removed. A putter gas is introduced and a silicon nitride layer is formed using a silicon target. In the same manner as for the silicon oxide layer, the silicon nitride layer is formed while removing the residual moisture in the processing chamber. It is preferable to form a film.

[0296] Next, a conductive layer is formed on the insulating layer 457, and the conductive layer is formed by a first photolithography process. A resist mask is formed on the conductive film, and selective etching is performed to form a source electrode layer or a drain electrode layer. After the electrode layers 465a1 and 465a2 are formed, the resist mask is removed (FIG. 20(A) The source and drain electrode layers 465a1 and 465a2 are divided in the cross-sectional view. Although the film is shown as a continuous film, the source electrode layer and the drain electrode The end of the layer is preferably tapered, since this improves the coverage of the gate insulating layer to be laminated thereon. It is.

[0297] The material of the source electrode layer or the drain electrode layer 465a1, 465a2 is Al, Cr , Cu, Ta, Ti, Mo, W, or a material containing the above elements In addition, manganese, magnesium, and the like can be used. A material selected from one or more of aluminum, zirconium, beryllium, and thorium The conductive layer may have a single layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum layer containing silicon, or a titanium layer laminated on an aluminum layer, Two-layer structure: a Ti layer, an aluminum layer on top of the Ti layer, and a T layer on top of that. In addition, titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium) A layer or alloy layer made of a single or multiple combinations of elements selected from Sc (scandium) Alternatively, a nitride layer may be used.

[0298] In this embodiment, the source and drain electrode layers 465a1 and 465a2 are A titanium layer having a thickness of 150 nm is formed by a tarpaulin deposition method.

[0299] Next, the insulating layer 457 and the source and drain electrode layers 465a1 and 465a2 are An oxide semiconductor layer having a thickness of 2 nm to 200 nm is formed on the insulating film.

[0300] Next, the oxide semiconductor layer 462 is processed into an island shape by a second photolithography process. (See FIG. 20B). In this embodiment, an In-Ga-Zn-O based metal oxide target An oxide semiconductor layer is formed by a sputtering method using a material other than SiO 2 .

[0301] The substrate is held in a processing chamber maintained in a reduced pressure state, and hydrogen is introduced into the processing chamber while removing residual moisture therein. A sputtering gas from which moisture has been removed is introduced, and a metal oxide is used as a target to sputter the substrate 450. In order to remove residual moisture in the treatment chamber, an adsorption type vacuum chamber is used. It is preferable to use a pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. It is preferable to use a displacement pump as the exhaust means. A cold trap may be added. The processing chamber is evacuated using a cryopump. For example, compounds containing hydrogen atoms such as water (H2O) (more preferably compounds containing carbon atoms) Since the gases (e.g., gases, etc.) are exhausted, the concentration of impurities contained in the oxide semiconductor layer formed in the treatment chamber increases. The substrate may be heated during the formation of the oxide semiconductor layer.

[0302] The sputtering gas used in forming the oxide semiconductor layer is hydrogen, water, a hydroxyl group, or a hydride. It is possible to use high-purity gas in which impurities such as these have been removed to the level of a few ppm or a few ppb. preferable.

[0303] An example of the deposition conditions is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, Pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, oxygen and argon (oxygen flow rate 15 scc m: Argon flow rate 30sccm) atmosphere is applied. Note that pulse direct current (DC ) power supply reduces the amount of powdery material (also called particles or dust) that is generated during film formation. The oxide semiconductor layer is preferably 5 nm or more and 30 nm or less in thickness. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be appropriately selected depending on the application.

[0304] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer 462 by a thermal etching method.

[0305] In this embodiment, the oxide semiconductor layer 462 is subjected to first heat treatment. The temperature is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the distortion point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment device, and the oxide semiconductor layer is After heat treatment at 450℃ for 1 hour in a nitrogen atmosphere, the specimen was placed in an oxygen-free environment without exposure to air. This first heat treatment prevents water and hydrogen from re-mixing into the oxide semiconductor layer, and obtains an oxide semiconductor layer. The oxide semiconductor layer 462 can be dehydrated or dehydrogenated by this.

[0306] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction from a heating element such as a resistance heating element or the like. The apparatus may be equipped with a device for heating the object to be treated by thermal radiation. For example, the GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment For example, the first heat treatment may be performed at a temperature of 650° C. to 7 The substrate is moved into an inert gas atmosphere heated to a high temperature of 00°C and heated for several minutes. Alternatively, GRTA can be performed by moving the container and releasing it from the inert gas heated to a high temperature. When used, high-temperature heat treatment can be performed in a short period of time.

[0307] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. or rare gases such as helium, neon, argon, etc., with a purity of 6N (99.9999%) or more Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0308] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, In some cases the layer may crystallize and become microcrystalline or polycrystalline.

[0309] In addition, the first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In that case, the substrate may be removed from the heating device after the first heat treatment. Then, the substrate is taken out and subjected to a photolithography process.

[0310] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed by After the film formation, a source electrode and a drain electrode are further laminated on the oxide semiconductor layer, and then a source This may be performed either after forming a gate insulating layer on the electrode and the drain electrode.

[0311] Next, a conductive layer is formed over the insulating layer 457 and the oxide semiconductor layer 462. A resist mask is formed on the conductive layer by a lithography process, and selective etching is performed. After forming the source or drain electrode layer 465b and the wiring layer 468, a resist mask is The source or drain electrode layer 465b and the wiring layer 465c are removed (see FIG. 20C). 468 is a source electrode layer or a drain electrode layer 465a1, 465a2, which is formed using the same material and process. It may be formed as follows.

[0312] In this embodiment, the source or drain electrode layer 465b and the wiring layer 468 are A titanium layer having a thickness of 150 nm is formed by a dipping method. and the source or drain electrode layer 465a1 and 465a2. For the example in which the same titanium layer is used for the source electrode layer 465a1 and the drain electrode layer 46b, The source or drain electrode layer 465b and the source electrode layer 5a2 have a selectivity in etching. Therefore, the source electrode layer or the drain electrode layer 465a1 and 465a2 are not The oxide semiconductor layer 465b is not etched during etching of the drain electrode layer 465b. A wiring layer 468 is formed on the source electrode layer or drain electrode layer 465a2 that is not covered with the dielectric layer 462. The source and drain electrode layers 465a1 and 465a2 are provided. The drain electrode layer 465b is made of a different material having a high selectivity in an etching process. When used, the source or drain electrode layer 465a2 is protected during etching. The wiring layer 468 does not necessarily have to be provided.

[0313] Note that the conductive film is etched such that the oxide semiconductor layer 462 is not removed. The materials and etching conditions are adjusted appropriately.

[0314] In this embodiment, a Ti layer is used as the conductive film, and an In-GaAs layer is used as the oxide semiconductor layer 462. Using a-Zn-O oxide semiconductor, ammonia hydrogen peroxide (NH3H2O) was used as an etchant. A mixture of water and hydrogen peroxide is used.

[0315] Note that in the third photolithography step, the oxide semiconductor layer 462 is only partly etched. In some cases, the source electrode layer is formed by etching, resulting in an oxide semiconductor layer having a groove (a recess). Alternatively, a resist mask for forming the drain electrode layer 465b and the wiring layer 468 is formed by ink jet printing. If the resist mask is formed by the inkjet method, the photomask Since no wiring is used, manufacturing costs can be reduced.

[0316] Next, the insulating layer 457, the oxide semiconductor layer 462, and the source or drain electrode layer 46 The gate electrodes 5a1 and 465a2 are formed on the source or drain electrode layer 465b and the wiring 468. A gate insulating layer 452 is formed.

[0317] The gate insulating layer 452 is formed by a plasma CVD method, a sputtering method, or the like. a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, Alternatively, a single layer or a stacked layer of an aluminum oxide layer can be used. In order to prevent a large amount of hydrogen from being contained in 52, the gate insulating layer is formed by sputtering. It is preferable to form a silicon oxide layer 452 by sputtering. In this case, a silicon target or a quartz target is used as the target, and the sputtering gas is The heating is carried out using oxygen or a mixed gas of oxygen and argon.

[0318] The gate insulating layer 452 is a source or drain electrode layer 465a1, 465a2, A silicon oxide layer and a silicon nitride layer are laminated from the source electrode layer or drain electrode layer 465b side. In this embodiment, the pressure is 0.4 Pa, and the high frequency power supply is 1.5 kW. , oxygen and argon (oxygen flow rate 25sccm:argon flow rate 25sccm=1:1) atmosphere A silicon oxide layer with a thickness of 100 nm is formed by RF sputtering in air.

[0319] Next, a resist mask is formed by a fourth photolithography process, and selectively etched. A part of the gate insulating layer 452 is removed by etching to form an opening 423 that reaches the wiring layer 468. Although not shown, when the opening 423 is formed, the source electrode layer or An opening reaching the drain electrode layer 465b may be formed. An opening for the drain electrode layer 465b is formed after laminating an interlayer insulating layer. In this example, a wiring layer for connecting to a target is formed in an opening.

[0320] Next, a conductive layer is formed on the gate insulating layer 452 and the opening 423, and then a fifth photolithography is performed. A gate electrode layer 461 (461a, 461b) and a wiring layer 464 are formed by a lithography process. The resist mask may be formed by an ink-jet method. When the ink jet method is used, no photomask is used, which reduces manufacturing costs.

[0321] The gate electrode layer 461 (461a, 461b) and the wiring layer 464 are made of molybdenum. Titanium, Chromium, Tantalum, Tungsten, Aluminum, Copper, Neodymium, Scandium It is possible to apply a single layer or a multi-layer of metal materials such as aluminum or alloy materials that have these as the main components. Cut.

[0322] In this embodiment, the gate electrode layer 461 (461a, 461b) and the wiring layer 464 are A titanium layer having a thickness of 150 nm is formed by a sputtering method.

[0323] Then, a second heat treatment (preferably The heating temperature is 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. The second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarizing insulating layer is formed over the thin film transistor 460 .

[0324] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed by maintaining a constant heating temperature, or by heating from room temperature for 1 The temperature is raised to 00°C or higher and lowered to room temperature several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. If the heat treatment is carried out under reduced pressure, the heating time can be shortened.

[0325] Through the above steps, the oxide semiconductor layer 4 is obtained, in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced. A thin film transistor 460 having a layer 62 can be formed (see FIG. 20(E)).

[0326] In addition, a protective insulating layer and a planarization insulating layer for planarization are provided over the thin film transistor 460. Although not shown, a solenoid may be formed on the gate insulating layer 452, the protective insulating layer, and the planarizing insulating layer. An opening is formed so as to reach the source electrode layer or drain electrode layer 465b, and the source electrode layer Alternatively, a wiring layer electrically connected to the drain electrode layer 465b is formed.

[0327] When forming the oxide semiconductor layer as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor layer can be reduced. The oxide semiconductor layer can be stabilized.

[0328] The above-mentioned thin film transistor may be used as a transistor in the logic circuit shown in any one of the first to sixth embodiments. By applying the same to a thin film transistor, the leakage of electric charges through the thin film transistor can be suppressed. As a result, it is possible to reduce the power consumption (standby power) of the logic circuit and prevent errors in the logic circuit. It becomes possible to suppress the operation.

[0329] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine the contents of the above with parts of the above or with the contents of other embodiments or parts of the above. do.

[0330] (Embodiment 9) In this embodiment, an example of a transistor included in the logic circuit described in any of Embodiments 1 to 6 will be described. Specifically, a thin film transistor having a channel formation region made of an oxide semiconductor will be described. An example of a film transistor will now be described.

[0331] One mode of a thin film transistor and a manufacturing method thereof in this embodiment will be described with reference to FIGS. do.

[0332] 21A to 21E show an example of a cross-sectional structure of a thin film transistor. The thin film transistor 390 shown in FIG. 1(E) is a type of bottom gate structure, and is an inverted staggered thin film transistor. Also called a membrane transistor.

[0333] In addition, the thin film transistor 390 will be described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A star can be formed.

[0334] 21(A) to (E), a thin film transistor 390 is fabricated on a substrate 394. The process for doing so will be described.

[0335] First, a conductive layer is formed on a substrate 394 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 391 is formed by a deposition process. The end of the gate electrode layer 391 is A perforated shape is preferable because it improves the coverage of the gate insulating layer to be laminated thereon. The resist mask may be formed by an inkjet method. When the method is used for formation, no photomask is used, and therefore the manufacturing cost can be reduced.

[0336] There is no significant limitation on the substrate that can be used for the substrate 394 having an insulating surface, but at least At the very least, it must have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as a borosilicate glass or an aluminoborosilicate glass substrate can be used.

[0337] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. The above is recommended. For the glass substrate, for example, aluminosilicate glass, Glass materials such as aluminoborosilicate glass and barium borosilicate glass are used. In general, the more barium oxide (BaO) is contained compared to boron oxide, the better the A practical heat-resistant glass can be obtained. For this reason, a glass substrate containing more BaO than B2O3 is used. It is preferable to use

[0338] Instead of the above glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. A substrate made of an insulating material may be used. Alternatively, crystallized glass may be used. In addition, a plastic substrate or the like can also be used as appropriate.

[0339] An insulating layer serving as a base film may be provided between the substrate 394 and the gate electrode layer 391. The function of the silicon nitride layer is to prevent the diffusion of impurity elements from the substrate 394. A silicon layer, a silicon oxide nitride layer, or a silicon oxynitride layer is formed on one or more films. The laminated structure can be formed by the above.

[0340] The gate electrode layer 391 may be formed of any of molybdenum, titanium, chromium, tantalum, and tungsten. Metallic materials such as stainless steel, aluminum, copper, neodymium, scandium, etc., or materials that contain these as their main components A single layer or a multilayer of the alloy material can be applied.

[0341] For example, the gate electrode layer 391 may have a two-layer laminate structure of molybdenum on an aluminum layer. Two-layer structure with a molybdenum layer laminated on a copper layer, two-layer structure with a molybdenum layer laminated on a copper layer, A two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on the titanium nitride layer, and a molybdenum layer and a A two-layer structure in which a tungsten nitride layer and a tungsten layer are laminated, or a tungsten nitride layer and a tungsten layer are laminated. A two-layer structure is preferable. A three-layer structure is preferably a tungsten layer or a tungsten nitride layer. A layer of tin and an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium. It is preferable that the transparent conductive layer has a structure in which a titanium nitride layer or a titanium layer is laminated. The gate electrode layer can also be formed using a conductive layer having a light-transmitting property. Examples of the conductive material include transparent conductive oxides.

[0342] Then, a gate insulating layer 397 is formed over the gate electrode layer 391 .

[0343] The gate insulating layer 397 is formed by using a plasma CVD method, a sputtering method, or the like. a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, Alternatively, a single layer or a stacked layer of an aluminum oxide layer can be used. In order to prevent a large amount of hydrogen from being included in the 97, the gate insulating layer is formed by sputtering. It is preferable to form a silicon oxide layer by sputtering. In this case, a silicon target or a quartz target is used as the target, and the sputtering gas is The heating is carried out using oxygen or a mixed gas of oxygen and argon.

[0344] The gate insulating layer 397 is made up of a silicon nitride layer and a silicon oxide layer from the gate electrode layer 391 side. A laminated structure may also be used. For example, a sputtered thin film may be used as the first gate insulating layer. The silicon nitride layer (SiN y (y>0) A second gate insulating layer having a thickness of 5 nm to 300 nm is formed on the first gate insulating layer. Silicon oxide layer (SiO x (x>0)) is laminated to form a gate insulating layer with a thickness of 100 nm. do.

[0345] In addition, hydrogen, a hydroxyl group, and moisture are preferably contained in the gate insulating layer 397 and the oxide semiconductor layer 393. In order to prevent this from being included, the pre-heating chamber of the sputtering equipment is used as a pre-treatment for film formation. A substrate 394 on which a gate electrode layer 391 is formed, or a substrate on which a gate insulating layer 397 is formed The substrate 394 is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 394 are desorbed and exhausted. The preheating temperature is preferably 100° C. or higher and 400° C. or lower. The temperature is 150°C or higher and 300°C or lower. The exhaust means installed in the preheating chamber is a cryopump. It is preferable to perform the preheating process. However, this preheating process can be omitted. Before the oxide insulating layer 396 is formed, the source electrode layer 395a and the drain electrode layer 395b are The same procedure may be carried out for the substrate 394 formed in step 1.

[0346] Next, an oxide semiconductor layer 3 having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 397. 93 is formed (see FIG. 21(A)).

[0347] Note that before the oxide semiconductor layer 393 was formed by a sputtering method, argon gas was The reverse sputtering is performed by introducing the ions into the gate insulating layer 397 to generate plasma. It is preferable to remove the dust that is in the target. In an argon atmosphere, a voltage is applied to the substrate side using an RF power source to form plasma near the substrate. The surface is modified by forming an argon atmosphere. etc. may also be used.

[0348] The oxide semiconductor layer 393 is formed by a sputtering method. In-Ga-Zn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-G a-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O , Sn-Zn-O, Al-Zn-O, In-O, Sn-O, and Zn-O oxides In this embodiment, the oxide semiconductor layer 393 is made of an In-Ga-Zn-O based metal. The oxide semiconductor layer 3 is formed by a sputtering method using a metal oxide target. 93 is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically The film can be formed by sputtering in an atmosphere of argon and oxygen. In addition, when using a sputtering method, a ter containing 2% to 10% by weight of SiO2 is used. A film may be formed using a get.

[0349] As a target for forming the oxide semiconductor layer 393 by a sputtering method, A metal oxide target mainly composed of lead can be used. Another example of a target is a metal oxide target containing In, Ga, and Zn (composition ratio: As such, In2O3:Ga2O3:ZnO=1:1:1[mol], In:Ga:Zn= 1:1:0.5 [atom]) can be used. In, Ga, and Zn are also included. Metal oxide targets including In:Ga:Zn=1:1:1[atom] or In A target having a composition ratio of Ga:Zn=1:1:2 [atom] can also be used. The filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or more and 96% or less. The metal oxide target with a high filling rate was used, and the oxide film was The solid semiconductor layer becomes a dense layer.

[0350] The substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate is heated to a temperature above room temperature but below 400°C. Then, the remaining moisture in the processing chamber is removed, and the sputtering process in which hydrogen and moisture have been removed is completed. A gas is introduced, and an oxide semiconductor layer 393 is formed on a substrate 394 using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump is used. As an exhaust means, a turbo pump with a cold trap is preferably used. The processing chamber evacuated using a cryopump may be filled with, for example, water (H2O) Compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) are exhausted. Therefore, the concentration of impurities contained in the oxide semiconductor layer formed in the treatment chamber can be reduced. By performing sputtering while removing the moisture remaining in the processing chamber using a cryopump, The substrate temperature when the oxide semiconductor layer 393 is formed can be higher than or equal to room temperature and lower than 400° C. Cut.

[0351] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 P. a. DC power supply 0.5 kW, oxygen (oxygen flow rate 100%) atmosphere In addition, when a pulsed direct current (DC) power supply is used, the powdery material (particulate matter) generated during film formation is reduced. This is preferable because it can reduce the amount of dirt and dust that accumulates on the surface of the oxide semiconductor film and also makes the film thickness uniform. The thickness of the oxide layer is preferably 5 nm to 30 nm. The appropriate thickness varies depending on the material, and an appropriate thickness may be selected depending on the material.

[0352] There are two types of sputtering: RF sputtering, which uses a high-frequency power source as the sputtering power source, and There is a DC sputtering method, and there is also a pulsed DC sputtering method, which applies a bias in a pulsed manner. RF sputtering is mainly used to deposit insulating layers, while DC sputtering is also used. The tarring method is mainly used when forming a metal layer.

[0353] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The TA equipment can deposit layers of different materials in the same chamber, or multiple layers in the same chamber. It is also possible to form a film by discharging two different materials simultaneously.

[0354] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. ECR using a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0355] In addition, as a method for forming a film using a sputtering method, a target material and a sputtering agent are interposed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting with gas components. There is also a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0356] Next, the oxide semiconductor layer is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer. The oxide semiconductor layer 399 is then processed into an island-shaped oxide semiconductor layer 399 (see FIG. 21B). A resist mask for this purpose may be formed by an inkjet method. When the film is formed by the jet method, a photomask is not used, and therefore the manufacturing cost can be reduced.

[0357] Also, when forming a contact hole in the gate insulating layer 397, the process is performed using an oxide semiconductor. This can be done when forming the coating layer 399 .

[0358] Note that the etching of the oxide semiconductor layer 393 here can be performed by dry etching or wet etching. Etching may be used, or both may be used.

[0359] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (C Cl4) etc.) are preferred.

[0360] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur fluoride (S F6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HB r), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing , etc. can be used.

[0361] As a dry etching method, parallel plate type RIE (Reactive Ion Etc. fing method and ICP (Inductively Coupled Plasma) The inductively coupled plasma etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate side, etc. are adjusted appropriately.

[0362] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0363] In addition, the etching solution after wet etching is washed away together with the etched material. The waste liquid of the etching solution containing the removed material is purified, and the material contained therein is The indium contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials such as these, we can make effective use of resources and reduce costs. do.

[0364] In order to etch the desired shape, the etching conditions are adjusted according to the material. Adjust the etching conditions (etching solution, etching time, temperature, etc.) as appropriate.

[0365] Note that reverse sputtering is performed before forming a conductive layer in the next step, and the oxide semiconductor layer 399 and the gate It is preferable to remove resist residues and the like adhering to the surface of the gate insulating layer 397.

[0366] Next, a conductive layer is formed over the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive layer may be formed by sputtering or vacuum deposition. Elements selected from Cr, Cu, Ta, Ti, Mo, and W, or elements containing the above elements The alloy layers may be made of a combination of the above elements. One or more of nesium, zirconium, beryllium, and thorium The metal conductive layer may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum layer containing silicon, a titanium layer on an aluminum layer, A two-layer structure in which a Ti layer is laminated and an aluminum layer is laminated on top of the Ti layer. A three-layer structure is also possible, in which a Ti layer is laminated on top of the Al. i), Tantalum (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), A single or multiple combination of elements selected from Nd (neodymium) and Sc (scandium) Alternatively, a nitrided layer, an alloy layer, or a nitrided layer may be used.

[0367] A resist mask is formed on the conductive layer by a third photolithography process, and selectively etched. After etching to form a source electrode layer 395a and a drain electrode layer 395b, The mask is then removed (see FIG. 21(C)).

[0368] The third photolithography process uses ultraviolet light and KrF for exposure when forming the resist mask. The source electrode layers adjacent to each other on the oxide semiconductor layer 399 are irradiated with a laser beam or an ArF laser beam. The width of the gap between the lower end of the drain electrode layer and the lower end of the thin film transistor to be formed later The channel length L is determined. Note that when performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths of several nm to several tens of nm. et) is used to perform exposure when forming a resist mask in the third photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. The channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. This allows the circuit to operate at higher speeds, and because the off-state current is extremely small, it also reduces power consumption. It is possible.

[0369] Note that the oxide semiconductor layer 399 is not removed when the conductive layer is etched. The materials and etching conditions are adjusted appropriately.

[0370] In this embodiment, a Ti layer is used as the conductive film, and an In-GaAs layer is used as the oxide semiconductor layer 399. Using a-Zn-O oxide semiconductor, ammonia hydrogen peroxide (NH3H2O) was used as an etchant. A mixture of water and hydrogen peroxide is used.

[0371] Note that in the third photolithography step, the oxide semiconductor layer 399 is only partly etched. In some cases, the source electrode layer is formed by etching, resulting in an oxide semiconductor layer having a groove (a recess). A resist mask for forming the drain electrode layer 395a and the drain electrode layer 395b is formed by an inkjet method. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0372] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, Resist formed using a multi-tone mask, an exposure mask that allows light to pass through in multiple intensities The etching process may be performed using a mask. The mask has a shape with multiple film thicknesses, and the shape is further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can be used to produce at least two different patterns. Therefore, the number of exposure masks can be reduced. This also eliminates the need for a corresponding photolithography process, making it possible to simplify the process.

[0373] Plasma treatment with gases such as N2O, N2, or Ar removes exposed oxide. Water adsorbed on the surface of the semiconductor layer may be removed. A plasma treatment may be performed using the gas.

[0374] When the plasma treatment is performed, the oxide semiconductor layer is not exposed to the air and the oxygen is in contact with the oxide semiconductor layer. In this embodiment, an oxide semiconductor layer is formed on the oxide semiconductor insulating layer 396 (see FIG. 21D). In the region where the oxide film 399 does not overlap with the source electrode layer 395a and the drain electrode layer 395b, The oxide semiconductor layer 399 and the oxide insulating layer 396 are formed so as to be in contact with each other.

[0375] In this embodiment, the oxide insulating layer 396 includes an island-shaped oxide semiconductor layer 399, a source The substrate 394 on which the electrode layer 395a and the drain electrode layer 395b have been formed is heated to 100° C. A sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced. A silicon target is used to deposit a defective silicon oxide layer.

[0376] For example, a silicon target with a purity of 6N and doped with boron (resistance value of 0.0 1 Ωcm), the distance between the substrate and the target (TS distance) was 89 mm, and the pressure was 0 .4Pa, DC power supply 6kW, oxygen (oxygen flow rate 100%) atmosphere, pulse D A silicon oxide layer is formed by C sputtering. The film thickness is 300 nm. Instead of a silicon target, quartz (preferably synthetic quartz) is used to form a silicon oxide layer. The sputtering gas can be oxygen or oxygen and The process is carried out using a mixture of argon and argon gas.

[0377] In this case, the oxide insulating layer 396 is formed while removing residual moisture in the treatment chamber. It is preferable that hydrogen, a hydroxyl group, or moisture be contained in the oxide semiconductor layer 399 and the oxide insulating layer 396. This is to ensure that it is not included.

[0378] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The process chamber evacuated using a cryopump may be filled with water (H2O), for example. Since compounds containing elementary atoms are exhausted, the oxide insulating film formed in the processing chamber is The concentration of impurities contained in layer 396 can be reduced.

[0379] Note that as the oxide insulating layer 396, a silicon oxynitride layer or an oxide Alternatively, an aluminum nitride layer, an aluminum oxynitride layer, or the like can be used.

[0380] Further, the oxide insulating layer 396 and the oxide semiconductor layer 399 are heated at 100° C. to 4 Heat treatment may be performed at 00° C. In this embodiment, the oxide insulating layer 396 has many defects. Therefore, hydrogen, moisture, and hydroxide contained in the oxide semiconductor layer 399 are removed by this heat treatment. Impurities such as bases or hydrides are diffused into the oxide insulating layer 396, and the oxide semiconductor layer 399 is The impurities contained in the above can be further reduced.

[0381] The oxide semiconductor layer 3 in which the concentration of hydrogen, moisture, hydroxyl groups, or hydrides is reduced by the above steps is obtained. A thin film transistor 390 having the structure 92 can be formed (see FIG. 21(E)).

[0382] When forming the oxide semiconductor layer as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor layer can be reduced. This can stabilize the oxide semiconductor layer.

[0383] A protective insulating layer may be provided over the oxide insulating layer. In this embodiment, the protective insulating layer 398 is The protective insulating layer 398 is formed on the oxide insulating layer 396. The protective insulating layer 398 may be a silicon nitride layer, a nitride oxide layer, or the like. A silicon oxide layer, an aluminum nitride layer, an aluminum nitride oxide layer, or the like is used.

[0384] The substrate 394 on which the oxide insulating layer 396 has been formed is heated to 100° C. The sputtering gas was heated to 400°C and contained high-purity nitrogen from which hydrogen and moisture had been removed. In this case, the silicon nitride layer is formed using a silicon target. As with the protective insulating layer 396, a protective insulating layer 398 is formed while removing residual moisture in the processing chamber. It is preferred.

[0385] When forming the protective insulating layer 398, the temperature is set to 100° C. to 400° C. during the film formation of the protective insulating layer 398. By heating the substrate 394, hydrogen or moisture contained in the oxide semiconductor layer is oxidized to an oxide insulating layer. In this case, a heat treatment is performed after the formation of the oxide insulating layer 396. This does not have to be done.

[0386] A silicon oxide layer is formed as the oxide insulating layer 396, and a silicon nitride layer is formed as the protective insulating layer 398. When stacking silicon layers, the silicon oxide layer and the silicon nitride layer are placed in the same processing chamber and a common A silicon target can be used for deposition. First, oxygen-containing sputtering gas is introduced. Then, a silicon oxide layer is formed using a silicon target mounted in the processing chamber, and then The sputtering gas was changed to one containing nitrogen, and the same silicon target was used. The silicon oxide layer and the silicon nitride layer are successively formed without exposure to the atmosphere. Therefore, impurities such as hydrogen and moisture are adsorbed on the surface of the silicon oxide layer. In this case, a silicon oxide layer is formed as the oxide insulating layer 396. A silicon nitride layer is then laminated as a protective insulating layer 398, and then the oxide semiconductor layer is Heat treatment (temperature 100°C to 40°C) to diffuse hydrogen or moisture into the oxide insulating layer. 0℃).

[0387] After the protective insulation layer is formed, it is further left in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. The heat treatment may be performed at a constant temperature. Alternatively, the temperature may be increased from room temperature to a heating temperature of 100°C or more and 200°C or less, and then decreased from the heating temperature to room temperature. This heat treatment may be repeated several times to lower the temperature to 100° C. Before the formation, the heating treatment may be performed under reduced pressure. By performing the heating treatment under reduced pressure, the heating time can be shortened. This heat treatment makes it possible to obtain a normally-off thin film transistor. This makes it possible to improve the reliability of the semiconductor device.

[0388] In addition, when an oxide semiconductor layer serving as a channel formation region is formed over a gate insulating layer, By removing residual moisture in the reaction atmosphere, the concentration of hydrogen and hydride in the oxide semiconductor layer can be reduced. can be reduced.

[0389] The above process is applicable to LCD panels, electroluminescent display panels, and electronic ink displays. Used in the manufacture of backplanes (substrates on which thin-film transistors are formed) for display devices, etc. The above process is carried out at a temperature of 400°C or less, so the thickness is 1 mm or less. It can also be applied to manufacturing processes using glass substrates with sides exceeding 1 m. All processes can be carried out at temperatures below 400°C, making it ideal for manufacturing display panels. This means that you don't have to consume a lot of energy to do so.

[0390] The above-mentioned thin film transistor may be used as a transistor in the logic circuit shown in any one of the first to sixth embodiments. By applying the same to a thin film transistor, the leakage of electric charges through the thin film transistor can be suppressed. As a result, it is possible to reduce the standby power consumption of the logic circuit and suppress malfunction of the logic circuit. It will be possible to do this.

[0391] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine the contents of the above with parts of the above or with the contents of other embodiments or parts of the above. do.

[0392] (Embodiment 10) In this embodiment, an example of a transistor included in the logic circuit described in any of Embodiments 1 to 6 will be described. Specifically, a thin film transistor having a channel formation region made of an oxide semiconductor will be described. An example of a film transistor will now be described.

[0393] One mode of a thin film transistor and a manufacturing method thereof in this embodiment will be described with reference to FIGS. do.

[0394] 22A to 22D show an example of a cross-sectional structure of a thin film transistor. The thin film transistor 360 shown in FIG. It is one of the bottom-gate structures used in thin-film transistors and is also called an inverted staggered type.

[0395] In addition, the thin film transistor 360 will be described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A star can also be formed.

[0396] 22(A) to (D), a thin film transistor 360 is fabricated on a substrate 320. The process for doing so will be described.

[0397] First, a conductive layer is formed on a substrate 320 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 361 is formed by a deposition process. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0398] The gate electrode layer 361 may be made of molybdenum, titanium, chromium, tantalum, tungsten, or the like. Metallic materials such as stainless steel, aluminum, copper, neodymium, scandium, etc., or materials that contain these as their main components A single layer or a multilayer of the alloy material can be applied.

[0399] Next, the gate insulating layer 322 is formed on the gate electrode layer 361 .

[0400] In this embodiment, the gate insulating layer 322 is formed to a thickness of 100 nm by plasma CVD. The following silicon oxynitride layers are formed:

[0401] Next, an oxide semiconductor layer having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 322. The oxide semiconductor layer is then processed into an island shape by a second photolithography process. In this embodiment, an In-Ga-Zn-O metal oxide target is used as the oxide semiconductor layer. The film is formed by sputtering.

[0402] In this case, the oxide semiconductor layer can be formed while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor layer.

[0403] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The process chamber evacuated using a cryopump may be filled with water (H2O), for example. Since compounds containing atomic atoms are exhausted, the oxide semiconductor layer formed in the treatment chamber is This can reduce the concentration of impurities.

[0404] The sputtering gas used in forming the oxide semiconductor layer is hydrogen, water, a hydroxyl group, or a hydride. It is possible to use high-purity gas in which impurities such as these have been removed to the level of a few ppm or a few ppb. preferable.

[0405] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment is 400° C. or more and 750° C. or less, preferably 400° C. or more so as to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor is The conductor layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to the air. Therefore, water or hydrogen is prevented from being recontaminated into the oxide semiconductor layer, and the oxide semiconductor layer 332 is obtained. (See Figure 22(A)).

[0406] Then, a plasma treatment is performed using gas such as N2O, N2, or Ar. The Zuma treatment removes adsorbed water and the like attached to the exposed surface of the oxide semiconductor layer. Alternatively, a plasma treatment may be performed using a mixed gas of oxygen and argon.

[0407] Next, an oxide insulating layer is formed over the gate insulating layer 322 and the oxide semiconductor layer 332. Then, a resist mask is formed by a third photolithography process, and selective etching is performed. After etching is performed to form the oxide insulating layer 366, the resist mask is removed.

[0408] In this embodiment, a silicon oxide layer having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 366. The substrate temperature during film formation should be between room temperature and 300° C. In the case of the above, the temperature is set at 100°C. The silicon oxide layer is formed by sputtering using a rare gas (typically Argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) and oxygen mixture The reaction can be carried out in an atmosphere. The target is a silicon oxide target or A silicon target can be used. For example, a silicon target can be used to oxidize oxygen and nitrogen. The silicon oxide layer can be formed by sputtering in a nitrogen atmosphere.

[0409] In this case, the oxide insulating layer 366 is formed while removing residual moisture in the treatment chamber. It is preferable that hydrogen, a hydroxyl group, or moisture be contained in the oxide semiconductor layer 332 and the oxide insulating layer 366. This is to ensure that it is not included.

[0410] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The process chamber evacuated using a cryopump may be filled with water (H2O), for example. Since compounds containing elementary atoms are exhausted, the oxide insulating film formed in the processing chamber is The concentration of impurities contained in layer 366 can be reduced.

[0411] The oxide insulating layer 366 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or hydrogen. By using high-purity gas in which impurities such as chlorine and chlorides have been removed to the level of a few ppm or a few ppb, is preferred.

[0412] Then, a second heat treatment (preferably The heating may be performed at 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The oxide semiconductor layer is heated while a part of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 366. can be.

[0413] In this embodiment, an oxide insulating layer 366 is further provided, and a part of the oxide semiconductor is exposed. The oxide insulating layer 332 is subjected to a heat treatment in a nitrogen or inert gas atmosphere or under reduced pressure. The exposed areas of the oxide semiconductor layer 332 that are not covered by 366 are filled with nitrogen, an inert When heat treatment is performed in a gas atmosphere or under reduced pressure, oxygen becomes deficient, resulting in low resistance, i.e., N-type For example, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0414] The oxide semiconductor layer 332 provided with the oxide insulating layer 366 is subjected to heat treatment in a nitrogen atmosphere. Due to this phenomenon, the exposed region of the oxide semiconductor layer 332 has a low resistance, and the region with a different resistance (FIG. 22 In FIG. 1B, the oxide semiconductor layer 362 has a portion (indicated by a hatched area and a white area).

[0415] Next, a semiconductor layer 362, a gate insulating layer 322, and an oxide insulating layer 366 are formed on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366. After forming the conductive layer, a resist mask is formed by a fourth photolithography process. After selective etching to form the source electrode layer 365a and the drain electrode layer 365b, Then, the resist mask is removed (see FIG. 22(C)).

[0416] The source electrode layer 365a and the drain electrode layer 365b are made of materials such as Al, Cr, Cu, An element selected from Ta, Ti, Mo, and W, or an alloy containing the above elements; The metal conductive layer may be a single-layer structure. Alternatively, it may have a laminated structure of two or more layers.

[0417] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. At the same time as the heat treatment for the oxidation is performed, the oxide semiconductor layer is made to have a low resistance, i.e., to become an N-type oxide semiconductor layer. By forming an oxide insulating layer in contact with the oxide semiconductor layer, a part of the oxide semiconductor layer is selected. As a result, the channel formation region overlapping with the gate electrode layer 361 is At this time, the carrier density is higher than that of the channel formation region 363. The high-resistance source region 364a overlaps the source electrode layer 365a, and at least The high-resistance region 365b overlaps the drain electrode layer 365b and has a higher carrier density than the channel forming region 363. Through the above steps, the thin film transistor 3 is formed in a self-aligned manner. 60 is formed.

[0418] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained at 100° C. or 200° C. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. By performing the heat treatment, the heating time can be shortened. Hydrogen is taken into the oxide insulating layer to obtain a normally-off thin film transistor. This makes it possible to improve the reliability of the semiconductor device.

[0419] Note that the oxide semiconductor layer overlapping with the drain electrode layer 365b (and the source electrode layer 365a) By forming a high-resistance drain region 364b (and a high-resistance source region 364a) in the As a result, the reliability of the thin film transistor can be improved. By forming the drain region 364b, the high resistance drain region 364b is formed from the drain electrode layer. The conductivity of the semiconductor layer 361 can be changed stepwise from the first region 361 to the channel forming region 363. Therefore, a wiring for supplying a high power supply potential VDD to the drain electrode layer 365b is connected. When the transistor is operated continuously, a high electric field is generated between the gate electrode layer 361 and the drain electrode layer 365b. Even if a high voltage is applied, the high-resistance drain region acts as a buffer to prevent localized electric field concentration. It is possible to provide a configuration in which the breakdown voltage of the transistor is improved.

[0420] A protective insulating layer is formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride layer. (See FIG. 22(D)).

[0421] Note that a thin film is further provided on the source electrode layer 365 a, the drain electrode layer 365 b, and the oxide insulating layer 366. An oxide insulating layer may be formed over the insulating film 324 and a protective insulating layer 323 may be stacked over the oxide insulating layer.

[0422] The above-mentioned thin film transistor may be used as a transistor in the logic circuits shown in the first to sixth embodiments. By applying the same to a thin film transistor, the leakage of electric charges through the thin film transistor can be suppressed. As a result, it is possible to reduce the standby power consumption of the logic circuit and suppress malfunction of the logic circuit. It will be possible to do this.

[0423] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine the contents of the above with parts of the above or with the contents of other embodiments or parts of the above. do.

[0424] (Embodiment 11) In this embodiment mode, an example of a semiconductor device equipped with the logic circuit obtained in the above embodiment mode will be described. The logic circuit according to the above embodiment will be described with reference to FIG. The internal components of each semiconductor device are integrated together with external circuits that operate the device and mounted on a circuit board. It will be installed in.

[0425] FIG. 23(A) shows a notebook personal computer having the above-mentioned logic circuit. 2201, a housing 2202, a display unit 2203, a keyboard 2204, etc. It is composed as follows.

[0426] FIG. 23B is a diagram showing a personal digital assistant (PDA) having the above-described logic circuit; The main body 2211 includes a display unit 2213, an external interface 2215, and an operation button 22 14, etc. are provided. Also, a stylus 2212 is provided as an accessory for operation.

[0427] FIG. 23C shows an example of an electronic paper having the above-mentioned logic circuit, an electronic book 22 FIG. 20 is a diagram showing an electronic book 2220. The electronic book 2220 is made up of two cases, a case 2221 and a case 2223. The housing 2221 and the housing 2223 are integrated by a shaft portion 2237. The opening and closing operation can be performed with the shaft portion 2237 as an axis. Therefore, the electronic book 2220 can be used like a paper book.

[0428] A display unit 2225 is incorporated in the housing 2221, and a display unit 2227 is incorporated in the housing 2223. The display unit 2225 and the display unit 2227 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 2225 in FIG. 23C) and An image can be displayed on the display unit (the display unit 2227 in FIG. 23C).

[0429] FIG. 23C shows an example in which an operating unit and the like are provided in the housing 2221. For example, The housing 2221 includes a power source 2231, operation keys 2233, a speaker 2235, etc. The operation keys 2233 can be used to turn pages. The device may be configured to include a keyboard, a pointing device, etc. On the side of the device, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. Furthermore, the electronic book 2220 may be configured to have a function as an electronic dictionary. You may do so.

[0430] The electronic book 2220 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. It is also possible.

[0431] Electronic paper can be applied to any field as long as it displays information. For example, in addition to e-books, posters, in-car advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as credit cards.

[0432] FIG. 23D is a diagram showing a mobile phone having the above-mentioned logic circuit. The device is composed of two housings, housing 2240 and housing 2241. Housing 2241 is , a display panel 2242, a speaker 2243, a microphone 2244, a pointing It is equipped with a device 2246, a camera lens 2247, an external connection terminal 2248, etc. The housing 2240 also includes a solar cell 2249 for charging the mobile phone, an external memory The antenna is built into the housing 2241. do.

[0433] The display panel 2242 has a touch panel function, and in FIG. The multiple operation keys 2245 are shown by dotted lines. A boost circuit is implemented to boost the voltage output by module 2249 to the voltage required by each circuit. In addition to the above configuration, a contactless IC chip, a small recording device, etc. are built in. It is also possible.

[0434] The display direction of the display panel 2242 changes appropriately depending on the usage mode. Since it has a camera lens 2247 on the same surface as the lens 2242, video calls are possible. The speaker 2243 and the microphone 2244 are not limited to voice calls, The housing 2240 and the housing 2241 can be slid together. As shown in Figure 23(D), the folded state can be folded up and carried around. Suitable miniaturization is possible.

[0435] The external connection terminal 2248 can be connected to various cables such as AC adapters and USB cables. The external memory slot 2250 can store data and other information. By inserting a recording medium, it is possible to store and transfer a larger amount of data. In addition, it may be equipped with an infrared communication function, a television receiving function, etc.

[0436] FIG. 23(E) is a diagram showing a digital camera having the above-mentioned logic circuit. The barrel camera is composed of a main body 2261, a display unit (A) 2267, an eyepiece 2263, and an operation switch 2 264, a display unit (B) 2265, a battery 2266, etc.

[0437] FIG. 23(F) is a diagram showing a television device having the above-mentioned logic circuit. In the monitor device 2270, a display unit 2273 is built into a housing 2271. 273 can display images. 2271 is supported by the housing 2271.

[0438] The television device 2270 can be operated using an operation switch provided on the housing 2271 or a separate remote. This can be done by using a remote control operation device 2280. The channel and volume can be controlled by the 2279, and the display 2273 shows In addition, the remote control unit 2280 can be used to control the video. A display unit 2277 for displaying information output from the device 2280 may be provided.

[0439] The television device 2270 is preferably configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting the device to a wired or wireless communication network, It is used to communicate information either directly (i.e., between a sender and a receiver, or between receivers themselves) or in a two-way manner (i.e., between a sender and a receiver, or between receivers themselves). It is possible to do so. EXAMPLES

[0440] In this example, the measured values ​​of the off-state current in the evaluation element (also called TEG) are described below. Reveal.

[0441] In Fig. 24, 200 thin-film transistors with L / W = 3 μm / 50 μm are connected in parallel. Specifically, the initial characteristics of a thin-film transistor with L / W=3μm / 10000μm are shown. FIG. 25(A) shows a plan view thereof, and FIG. 25(B) shows an enlarged top view thereof. The area enclosed by the dotted line in B) is the thin film for one step with L / W=3μm / 50μm and Lov=1.5μm. In order to measure the initial characteristics of the thin-film transistor, the substrate temperature was set to room temperature. The source-drain voltage (hereinafter referred to as drain voltage or Vd) is set to 10 V. The gate-to-source voltage (hereafter referred to as gate voltage or Vg) can be varied from -20V to +20V. The change in the source-drain current (hereinafter referred to as drain current or Id) when the In FIG. 24, Vg was varied from -20V to +5V. The range is shown in .

[0442] As shown in FIG. 24, a thin-film transistor with a channel width W of 10,000 μm has a Vd of 1 V And at 10V, the off-current is 1×10 -13 [A] or less, and measuring instruments (semiconductor Resolution of the parameter analyzer, Agilent 4156C (Agilent) (100fA) or less.

[0443] A method for manufacturing the thin film transistors that were measured will be described.

[0444] First, a silicon nitride layer is formed on a glass substrate as a base film by a CVD method. A silicon oxynitride layer was formed on the silicon oxynitride layer as a gate electrode layer by a sputtering method. A tungsten layer was then formed. The tungsten layer was then selectively etched to form the gate. An electrode layer was formed.

[0445] Next, a 100 nm thick oxide / nitride layer was formed on the gate electrode layer by CVD as a gate insulating layer. A silicon layer was formed.

[0446] Next, an In-Ga-Zn-O oxide semiconductor ternary layer is formed on the gate insulating layer by sputtering. Using a get (molar ratio of In2O3:Ga2O3:ZnO=1:1:2), a thickness of 5 A 0 nm thick oxide semiconductor layer was formed. Here, the oxide semiconductor layer was selectively etched. An island-shaped oxide semiconductor layer was formed.

[0447] Next, the oxide semiconductor layer was subjected to a first heating process in a clean oven under a nitrogen atmosphere at 450° C. for 1 hour. The heat treatment was carried out.

[0448] Next, a titanium layer (thickness 15 mm) was formed on the oxide semiconductor layer as a source electrode layer and a drain electrode layer. A source electrode layer and a drain electrode layer were formed by sputtering. The channel length L of one thin film transistor is 3 μm and the channel width W is 5 0μm, and by connecting 200 pieces in parallel, the effective L / W is 3μm / 10000μm. I made it happen.

[0449] Next, a protective insulating layer was formed by reactive sputtering so as to contact the oxide semiconductor layer. A silicon oxide layer was formed to a thickness of 300 nm. The silicon oxide layer, which is a protective layer, was selectively etched. The gate electrode layer, the source electrode layer, and the drain electrode layer were then etched to form openings. Thereafter, a second heat treatment was carried out in a nitrogen atmosphere at 250° C. for 1 hour.

[0450] Then, before measuring the Vg-Id characteristics, the device was heated at 150° C. for 10 hours.

[0451] Through the above steps, a bottom gate type thin film transistor was fabricated.

[0452] As shown in Figure 24, a thin-film transistor is -13 [A] is the level This is because the hydrogen concentration in the oxide semiconductor layer can be sufficiently reduced in the manufacturing process. The hydrogen concentration in the semiconductor layer is 5×10 19 (atoms / cm 3 ) or less, preferably 5 ×10 18 (atoms / cm 3 ) or less, more preferably 5 × 10 17 (atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer is measured by secondary ion mass spectrometry. (SIMS: Secondary Ion Mass Spectroscopy) cormorant.

[0453] Although an example using an In-Ga-Zn-O-based oxide semiconductor has been shown, the present invention is not particularly limited thereto. Other oxide semiconductor materials, such as In-Sn-Zn-O, Sn-Ga-Zn-O, l-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, In-Sn-O series , Sn-Zn-O, Al-Zn-O, In-O, Sn-O, Zn-O, etc. In addition, AlOx is mixed at 2.5 to 10 wt% as an oxide semiconductor material. In-Al-Zn-O system and In-Zn-O system with 2.5 to 10 wt% SiOx mixed A system can also be used.

[0454] The carrier density of the oxide semiconductor layer measured by a carrier measurement device is 5×10 14 / cm 3Less than 5×10, more preferably 12 / cm 3 More preferably, silicon Intrinsic carrier density 1.45×10 10 / cm 3 is equal to or less than The carrier density of the oxide semiconductor layer can be made as close to zero as possible.

[0455] In addition, the channel length L of the thin film transistor can be set to 10 nm or more and 1000 nm or less. This allows the circuit to operate at higher speeds, and the extremely small off-state current allows for even lower power consumption. It is also possible to reduce power consumption.

[0456] In addition, when the thin film transistor is in an off state, the oxide semiconductor layer can be regarded as an insulator. Design can be done.

[0457] Next, the temperature characteristics of the off-current of the thin film transistor fabricated in this example were evaluated. The temperature characteristics are determined based on the environmental resistance of the final product in which the thin-film transistor is used, as well as the maintenance of its performance. Naturally, the smaller the change, the better, and the greater the degree of freedom in product design. Increase.

[0458] The temperature characteristics are measured using a thermostatic chamber at -30, 0, 25, 40, 60, 80, 100, and 12 The substrate on which the thin film transistor was formed was kept at a constant temperature of 0°C, and the drain voltage The Vg-Id characteristics were obtained by varying the gate voltage from -20V to +20V and the input voltage from 6V.

[0459] Figure 26(A) shows the Vg-Id characteristics measured at each of the above temperatures, which are overlaid. The area of ​​the off-current surrounded by the dotted line is shown in enlargement in FIG. The rightmost curve indicated by the arrow is taken at -30℃, and the leftmost curve is taken at 120℃. The obtained curve is somewhere between these two. The on-current has almost no temperature dependence. As is clear from the enlarged view of Figure 26(B), the off-state current is At all temperatures, except for the 1×10 -12 [A] or lower Even at a high temperature of 120°C, the off-current is 1×1 0 -12 [A] or less is maintained, and the effective channel width W is 10,000 μm Considering this, it can be seen that the off-current is very small.

[0460] Thin film transistors using highly purified oxide semiconductors have little temperature dependence of off-state current. This is because the energy gap of oxide semiconductors is 3 eV or more, and the intrinsic This is due to the extremely small number of carriers. Also, the source and drain regions are degenerate. This is the reason why the temperature dependency does not appear because the transistor is in a state where the Most of the charge is due to carriers injected into the oxide semiconductor from the degenerate source region. Since there is no temperature dependence of the carrier density, the above characteristics (no temperature dependence of off-current) can be explained.

[0461] A logic circuit was constructed using thin-film transistors with extremely low off-state current. In this case, reducing the standby power consumption of the logic circuit or suppressing malfunction of the logic circuit. can be done. [Explanation of symbols]

[0462] 10 Logic Circuits 11 Input terminal 12 Input terminals 13 Output terminal 14 Main logic circuit section 15 Transistor 100 Substrates 102 Protective layer 104 Semiconductor area 106 Element isolation insulating layer 108a Gate insulating layer 108b Insulating layer 110a Gate electrode layer 110b Electrode layer 112 Insulating layer 114a Impurity region 114b Impurity region 116 Channel formation region 118 Sidewall insulating layer 120a High concentration impurity region 120b High concentration impurity region 122 Metal layer 124a Metal compound area 124b Metal compound area 126 Interlayer Insulation Layer 128 Interlayer Insulation Layer 130a Source electrode layer 130b Drain electrode layer 130c electrode layer 132 Insulating Layer 134 Conductive Layer 136a Electrode layer 136b Electrode layer 136c electrode layer 136d Gate electrode layer 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source electrode layer 142b Drain electrode layer 144 Protective Insulation Layer 146 Interlayer Insulation Layer 148 Conductive Layer 150a electrode layer 150b electrode layer 150c electrode layer 150d electrode layer 150e electrode layer 152 Insulating layer 154a Electrode layer 154b Electrode layer 154c electrode layer 154d electrode layer 160 Transistors 164 Transistors 200 Logic Circuits 201 AND Gate 202 Flip-flop 211 Transistor 212 Transistor 213 Transistor 214 Transistor 215 Transistor 216 Transistor 221 Transistor 222 Transistor 223 Transistor 224 Transistor 225 Transistor 231 NAND Gate 232 NAND Gate 233 NAND Gate 234 NAND Gate 241 Transistor 242 Transistor 243 Transistor 244 Transistor 251 Transistor 252 Transistor 253 Transistor 320 Substrate 322 Gate Insulation Layer 323 Protective Insulation Layer 332 Oxide semiconductor layer 360 Thin Film Transistor 361 Gate electrode layer 362 Oxide semiconductor layer 363 Channel Formation Region 364a Source Region 364b Drain region 365a Source electrode layer 365b Drain electrode layer 366 Oxide Insulating Layer 390 Thin-film transistor 391 Gate electrode layer 392 Oxide semiconductor layer 393 Oxide Semiconductor Layer 394 Substrate 395a Source electrode layer 395b Drain electrode layer 396 Oxide Insulating Layer 397 Gate Insulation Layer 398 Protective Insulation Layer 399 Oxide Semiconductor Layer 423 Aperture 450 Substrate 452 Gate insulation layer 457 Insulating Layer 460 Thin Film Transistor 461 Gate electrode layer 461a Gate electrode layer 461b Gate electrode layer 462 Oxide semiconductor layer 464 Wiring layer 465a Source electrode layer or drain electrode layer 465a1 Source electrode layer or drain electrode layer 465a2 Source electrode layer or drain electrode layer 465b Source electrode layer or drain electrode layer 468 Wiring layer 500 Logic Circuit 501 NOR Gate 502 Flip-flop 511 Transistor 512 Transistor 513 Transistor 514 Transistor 521 Transistor 522 Transistor 523 Transistor 600 Logic Circuit 601 Latch 602 Flip-flop 611 Transistor 612 Inverter 613 Inverter 621 Transistor 622 Transistor 631 Transistor 632 Transistor 800 Logic Circuits 801 AND Gate 802 Flip-flop 803 Flip-Flop 804 Flip-Flop 805 Flip-Flops 900 Logic Circuit 901 Flip Flop 902 AND Gate 903 Control Unit 904 Flip-flop 905 Flip-flop 906 Flip-flop 907 Flip-Flops 2201 Main unit 2202 Case 2203 Display section 2204 Keyboard 2211 Main unit 2212 Stylus 2213 Display section 2214 Operation button 2215 External Interface 2220 E-books 2221 Case 2223 Case 2225 Display section 2227 Display section 2231 Power supply 2233 Operation key 2235 Speaker 2237 Shaft 2240 Case 2241 Case 2242 Display Panel 2243 Speaker 2244 Microphone 2245 Operation Key 2246 Pointing Device 2247 Camera Lenses 2248 External connection terminal 2249 Solar Cell 2250 external memory slot 2261 Main unit 2263 Eyepiece 2264 Operation switch 2265 Display section (B) 2266 Battery 2267 Display section (A) 2270 Television Equipment 2271 Case 2273 Display section 2275 Stand 2277 Display section 2279 Operation Key 2280 Remote Controlled Device

Claims

1. a first transistor having silicon in a channel formation region; a second transistor having an oxide semiconductor in a channel formation region, a first conductive layer having a region overlapping with a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with an upper surface of the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer; a third conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having an area underlying the second conductive layer and having the same material as the first conductive layer; the first insulating layer has a region in contact with an upper surface of the fourth conductive layer; The first conductive layer is electrically connected to the second conductive layer.

2. a first transistor having silicon in a channel formation region; a second transistor having an oxide semiconductor in a channel formation region, a first conductive layer having a region overlapping with a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with an upper surface of the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer; a third conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having an area underlying the second conductive layer and having the same material as the first conductive layer; the first insulating layer has a region in contact with an upper surface of the fourth conductive layer; the first conductive layer is electrically connected to the second conductive layer; a second conductive layer overlapping with the third conductive layer in a cross-sectional view taken along a channel length direction of the second transistor;

3. a first transistor having silicon in a channel formation region; a second transistor having an oxide semiconductor in a channel formation region, a first conductive layer having a region overlapping with a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with an upper surface of the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer; a third conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having an area underlying the second conductive layer and having the same material as the first conductive layer; a fifth conductive layer electrically connected to one of the source region and the drain region of the first transistor; the fifth conductive layer has the same material as the second conductive layer; The second insulating layer has a region in contact with an upper surface of the fifth conductive layer.

4. a first transistor having silicon in a channel formation region; a second transistor having an oxide semiconductor in a channel formation region, a first conductive layer having a region overlapping with a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with an upper surface of the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer; a third conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having an area underlying the second conductive layer and having the same material as the first conductive layer; a fifth conductive layer electrically connected to one of the source region and the drain region of the first transistor; the second conductive layer overlaps with the third conductive layer in a cross-sectional view of the second transistor in a channel length direction; the fifth conductive layer has the same material as the second conductive layer; The second insulating layer has a region in contact with an upper surface of the fifth conductive layer.

5. In any one of claims 1 to 4, The second conductive layer has a laminated structure.

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