Semiconductor Device

Abstract

To manufacture an oxide semiconductor suitable for the use in a semiconductor device, and provide a manufacturing method for a semiconductor device using the same, and the semiconductor device.SOLUTION: In a manufacturing method for forming an oxide semiconductor layer by a sputtering method using an oxide semiconductor target containing In, Ga, and Zn, the oxide semiconductor layer contains less Ga than Ga in the target, and the oxide semiconductor layer contains less Zn than Zn in the target. In the oxide semiconductor layer containing In, Ga, and Zn, the content of Zn is less than the content of Ga, the content of Zn is less than the content of In, and an amorphous structure is 90 vol% or less.SELECTED DRAWING: None

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof. [Background technology]

[0002] Field effect transistors are the most widely used semiconductor devices today. The materials used for the type transistors vary depending on the application. In particular, silicon is used Semiconductor materials containing

[0003] The silicon field effect transistors described above have the characteristics required for many applications. For example, single crystal silicon is used for integrated circuits that require high speed operation. This requirement is met. For large-area applications such as display devices, amorphous silicon is used. The use of the .

[0004] As described above, silicon is highly versatile and can be used for a wide range of purposes. There is a trend for semiconductor materials to be more versatile and have higher performance. From the viewpoint of improving the performance of display devices, large-scale switching elements are required to realize high-speed operation. There is a demand for semiconductor materials that can be easily scaled and have performance that exceeds that of amorphous silicon. .

[0005] In this situation, field effect transistors (FETs) using oxide semiconductors have been developed. For example, Patent Document 1 describes a technique for the homologous compound InM O3(ZnO) m (M=In, Fe, Ga, or Al, m=an integer of 1 or more and less than 50) A transparent thin film field effect transistor is disclosed.

[0006] In addition, Patent Document 2 describes an amorphous oxide semiconductor containing In, Ga, and Zn that is an electron carrier. A concentration is 10 18 / cm 3 A field effect transistor using less than In this document, the atomic ratio of the amorphous oxide semiconductor is In:Ga:Zn =1:1:m(m<6).

[0007] Furthermore, Patent Document 3 discloses a field-effect transistor having an active layer made of an amorphous oxide semiconductor containing microcrystals. A transistor is disclosed. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2004-103957 A [Patent Document 2] WO 05 / 088726 [Patent Document 3] JP 2006-165529 A Summary of the Invention [Problem to be solved by the invention]

[0009] In Patent Document 3, the composition in the crystalline state is InGaO3(ZnO). m (m=6 or less In addition, in Example 1 of Patent Document 3, it is disclosed that InGaO3 However, the case of (ZnO)4 is disclosed. Even when they are used, the reality is that sufficient characteristics are not obtained.

[0010] In view of the above problems, an object of the present invention is to provide an oxide semiconductor suitable for use in semiconductor devices. Another object is to provide a semiconductor device using the same. [Means for solving the problem]

[0011] In the disclosed invention, InGaO3(ZnO) m In the amorphous structure represented by (m>0) 2. InGaO3(ZnO) m A semiconductor device is fabricated by incorporating crystal grains represented by (m=1). More specifically, it is as follows:

[0012] One of the disclosed inventions is a method for manufacturing a transistor having an In-Ga-Zn-O-based oxide semiconductor layer. In the semiconductor device used in the formation region, the In-Ga-Zn-O-based oxide semiconductor layer is GaO3(ZnO) m In the amorphous structure represented by (m>0), InGaO3(ZnO) m It is characterized by having a structure containing crystal grains represented by (m=1).

[0013] In the above, the content (atomic %) of Zn in the In-Ga-Zn-O based oxide semiconductor layer is It is preferable that the content is less than the In content (atomic %) and less than the Ga content (atomic %). In addition, the oxide semiconductor layer has a Zn content (atomic %) that is equal to or less than the In content (atomic %) and a Ga content (atomic %) that is equal to or less than the In content (atomic %). It is formed by the sputtering method using a target with a content (atomic percent) of In the above, it is preferable that the crystal grains are formed only of the structure related to m=1. However, in a situation where the structure relating to m=1 occupies 80% or more by volume of the crystal grains, It is possible to obtain certain properties.

[0014] Another aspect of the present invention is to deposit amorphous In on a substrate by sputtering. By forming a -Ga-Zn-O-based oxide semiconductor layer and subjecting the oxide semiconductor layer to a heat treatment, nGaO3(ZnO) m In the amorphous structure represented by (m>0), InGaO3(ZnO) m (m=1) is formed, and the oxide semiconductor layer including the crystal grains is US20100232633A1 - Fabrication of a semiconductor device using a semiconductor layer as a channel forming region of a transistor - Google Patents This is the method.

[0015] In the above, the content of Zn in the In-Ga-Zn-O-based oxide semiconductor layer having an amorphous structure is The content (atomic %) is less than the In content (atomic %) and less than the Ga content (atomic %). It is preferable that the In-Ga-Zn-O oxide having an amorphous structure is formed as follows. The compound semiconductor layer has a Zn content (atomic %) that is equal to or less than the In content (atomic %) and a Ga content (atomic %) that is equal to or less than the In content (atomic %). It is preferable that the film is formed by a sputtering method using a target having a content (atomic %) of 0.1 or less. Moreover, the heat treatment is preferably carried out at a temperature of 350° C. or higher.

[0016] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to display devices, semiconductor circuits, and electronic devices, all of which are included in the category of semiconductor devices. Effect of the Invention

[0017] InGaO3(ZnO) m In the amorphous structure represented by (m>0), InGaO3 (ZnO ) m By including crystal grains represented by (m=1), the electrical characteristics of the oxide semiconductor are improved. In addition, by using the oxide semiconductor, an excellent semiconductor device can be provided. It is possible. [Brief description of the drawings]

[0018] [Figure 1] 1A to 1C illustrate a manufacturing process of an oxide semiconductor layer according to Embodiment 1. [Diagram 2] 11A and 11B are diagrams showing the results of a composition analysis of a non-single crystal semiconductor layer. [Diagram 3] 11A and 11B are diagrams showing the results of a composition analysis of a non-single crystal semiconductor layer. [Figure 4] 1 shows a Bright-field STEM image of an oxide semiconductor layer. [Diagram 5] These are Bright-field-STEM and HAADF-STEM images of the oxide semiconductor layer. [Figure 6] 1 shows an enlarged photograph and a model diagram of the crystal structure. [Figure 7] This is a HAADF-STEM image of an oxide semiconductor layer (target B). [Figure 8] FIG. 1 is a diagram showing the crystal structure of an oxide semiconductor (InGaZnO4). [Figure 9] FIG. 2 is a diagram showing the arrangement of Ga and Zn in a (Ga, Zn)O2 layer. [Figure 10] FIG. 13 is a diagram showing a comparison result of energies relating to the arrangement of elements. [Figure 11] FIG. 13 is a diagram showing the calculation results of the DOS and PDOS of electrons. [Figure 12] FIG. 1 is a distribution diagram of electrons at the bottom of the conduction band. [Figure 13] FIG. 13 is a diagram showing the results of calculation of the geometric optimum of EVO. [Figure 14] FIG. 1 is a diagram showing specific combinations (atomic arrangements) involved in calculations. [Figure 15] FIG. 13 is a diagram showing the energy of each combination. [Figure 16] This is a model diagram of the most likely arrangement. [Figure 17] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to Embodiment 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the described embodiment, and various changes in form and details are possible without departing from the spirit of the invention. It is obvious to those skilled in the art that the configurations according to the different embodiments can be combined as appropriate. In the configuration of the invention described below, the same parts or In the following, the same reference numerals are used for parts having similar functions, and repeated explanations thereof will be omitted.

[0020] (Embodiment 1) In this embodiment, InGaO3(ZnO) m In the amorphous structure represented by (m>0), I nGaO3(ZnO) m The oxide semiconductor layer (In-Ga A method for producing a Zn-O-based oxide semiconductor layer will be described with reference to the drawings.

[0021] First, an In-Ga-Zn-O non-single crystal semiconductor is formed on the surface to be formed (here, on the substrate 100). A conductor layer 102 is formed (see FIG. 1(a)). For example, indium (In), gallium ( The non-metallic compound was fabricated by sputtering using an oxide semiconductor target containing Ga and zinc (Zn). A single crystal semiconductor layer 102 can be formed. The sputtering conditions are, for example, The distance between the target and the oxide semiconductor was set to 30 mm to 500 mm, and the pressure was set to 0.1 Pa to 2.0 Pa. Pa, DC power supply 0.2kW to 5.0kW (when using an 8-inch diameter target) The atmosphere may be an argon atmosphere, an oxygen atmosphere, or a mixture of argon and oxygen. .

[0022] Here, the composition ratio of the oxide semiconductor target is In2O3:Ga2O3:ZnO=1:1. 1, the distance between the substrate 100 and the oxide semiconductor target is 170 mm, and the pressure is 0.4 Pa. The direct current (DC) power supply was 0.5 kW, the argon gas flow rate was 10 sccm, and the oxygen gas flow rate was The non-single crystal semiconductor layer 102 was formed under the condition of 5 sccm.

[0023] The samples prepared by the above method were then analyzed by inductively coupled plasma mass spectrometry. ively Coupled Plasma Mass Spectrometry:I The composition was analyzed using CP-MS. The flow rate of argon gas was 10 sccm, and the acid The composition of the non-single crystal semiconductor layer 102 obtained under the condition of a flow rate of the elemental gas of 5 sccm is InGa 0.94 Zinc 0.40 O 3.31 In addition to the above analysis results, the flow rate of argon gas Analysis of non-single crystal semiconductor layers fabricated under conditions of a flow rate of 40 sccm and an oxygen gas flow rate of 0 sccm. The results are shown in Figure 2.

[0024] In addition, the Rutherford Backscattering Analysis method was used as the analytical method. The results of using RBS analysis Shown in Figure 3.

[0025] 2 and 3, in the non-single crystal semiconductor layer, the composition of Ga and Zn is higher than that of the target. In addition, depending on the preparation conditions and analysis method, The analysis results for the non-single crystal semiconductor layer are different.

[0026] Next, the non-single crystal semiconductor layer is heated to 350° C. to 800° C. (preferably 500° C. to 750° C.) The heat treatment is performed at a temperature of 100° C. for about 10 to 200 minutes. As a result, 10 crystal grains are formed in the amorphous structure. As a result, an oxide semiconductor layer 106 including the oxide semiconductor layer 104 is obtained (see FIG. 1(b)). The electrical characteristics of a thin film transistor fabricated using 6 are as follows: The turn-off ratio is 10 9 More than 10cm of movement 2 / Vs or more, which is favorable. Heat treatment is carried out at 700℃ for 1 hour.

[0027] After the heat treatment, the structure of the oxide semiconductor layer 106 was analyzed. STEM (scanning transmission electron microscope) The images were observed using a vitroscope.

[0028] Figure 4 shows the Bright-field-STEM images of the above sample. 2O3:Ga2O3:ZnO=1:1:1 (In:Ga:Zn=1:1:0.5) Figure 4(b) shows a STEM image of a sample prepared using the target (hereafter referred to as target A). For comparison with the above sample, the target was changed to In2O3:Ga2O3:ZnO=1:1. :2 (In:Ga:Zn=1:1:1) (hereafter, target B) This is a STEM image.

[0029] As shown in FIG. 4, the oxide semiconductor layer 106 formed by the above method has crystal grains 104 in an amorphous structure. It can be seen that the compound has a structure including the following:

[0030] As can be seen from a comparison of Figures 4(a) and 4(b), the Zn content in the target When the Zn content in the target is low, the crystal growth rate is slower than when the Zn content in the target is high. By utilizing this, it is possible to improve the controllability of crystal growth. For example, the Zn content (atomic %) in the non-single crystal semiconductor layer 102 is %) and the Ga content (atomic %), a good oxide semiconductor layer 106 can be obtained. On the other hand, when the crystal growth rate is important, it is possible to form a non-single crystal. This can be achieved by increasing the zinc content in the semiconductor layer 102 .

[0031] Next, we performed STEM image observation of a finer area. The STEM images of the sample are shown in Fig. 5(a) and Fig. 5(b). (b) is the HAADF (high-angle annular dark field). The regular structure can be seen from Fig. 5(a), but the position of each atom cannot be identified. On the other hand, in Fig. 5(b), the crystal orientation is not clear. The positions of the white dots that correspond to the amorphous structure can be clearly seen in the lower right area of ​​Fig. 5(b). It is clear that the structure remains.

[0032] In HAADF-STEM images, contrast proportional to the square of the atomic number is obtained. In Fig. 5(b), the bright points indicate In, The dark spots are Ga or Zn.

[0033] Next, the above crystal structure will be considered with reference to FIG. 6. The right side of Fig. 6 shows the InGaZn O4(InGaO3(ZnO) m (corresponding to m=1 in the figure) viewed from the

[0100] direction This is a model diagram of the structure. By comparing the left and right figures in Figure 6, it is clear that the structure was created using target A. The crystal grains in the sample were found to have the crystal structure of InGaO3(ZnO)1. In the In-Ga-Zn-O oxide semiconductor, In and Ga are electrically conductive. Therefore, in order to maintain good electrical characteristics, the ratio of In and Ga is High-efficiency crystal structure, i.e., InGaO3(ZnO) m Crystal structure where m=1 in The higher the ratio, the more preferable it is.

[0034] Figure 7 shows a HAADF-STEM image of a sample prepared using target B. Bright spots The bright dots are arranged regularly and form a line. The spacing between the lines is about 0.9 nm, about 1.15 nm, and about 1.4 nm. These correspond to the spacing of indium in the crystal structure of m=1, m=2, and m=3. In the sample prepared using target B, multiple combinations of at least m=1 to 3 were formed. It can be said that the crystals are of this structure.

[0035] As mentioned above, in the In-Ga-Zn-O oxide semiconductor, In and Ga are electrically conductive. Therefore, in the situation where the ratio of In and Ga is low (i.e., when m is large), Therefore, by increasing the ratio of the structure related to m=1, It is possible to maintain good electrical properties. Specifically, the crystal structure where m=1 is a crystal It is preferable that the volume of the entire structure is 80% or more, and more preferably 90% or more. do.

[0036] One method to increase the proportion of the crystal structure with m=1 is to use a target with a low Zn content. There is a method for forming the non-single crystal semiconductor layer 102 with a low Zn content by using a Zn-based SiO2 film. For example, the Zn content (atomic %) in the non-single crystal semiconductor layer 102 is In this manner, the non-single crystal semiconductor layer 1 may be formed such that the content of Ga (atomic %) is less than the content of Ga (atomic %). By reducing the Zn content in 02, a crystal structure with good electrical properties can be obtained. can be done.

[0037] The electronic state of In-Ga-Zn-O oxide semiconductors has not been fully elucidated. It is believed that elucidation of the state of oxide semiconductors will lead to an understanding of their electrical properties. In this paper, we present the results of first-principles calculations performed on In-Ga-Zn-O oxide semiconductors. The following calculation results are based on the crystal structure. The same can be understood for a structure in which crystal grains are included in a crystalline structure.

[0038] Figure 8 shows the calculated crystal structure of the In-Ga-Zn-O oxide semiconductor (InGaZnO4). The unit cell of the InGaZnO4 crystal structure is composed of 21 atoms. In this example, to examine the arrangement of Ga, we divided the Ga into a unit (2×2×1) consisting of 84 atoms. The calculation was expanded.

[0039] The calculations were performed using CASTEP, a density functional theory (DFT) based method. This is a first-principles calculation program based on the plane wave pseudopotential method. As a functional, we use GGA (generalized gradient approximation). approximation) and PBE (Perdew-Burke-Ernzer The cut-off energy was chosen as The energy was 500 eV and the k-point was 3 × 3 × 1.

[0040] From Figure 8, the unit cell is composed of two (Ga, Zn)O2 layers and one InO2 layer. For simplicity, we will assume that the unit has a given atomic arrangement. A crystal structure with repeated coordinate lattices was assumed.

[0041] Figure 9 shows the arrangement of Ga and Zn in two (Ga, Zn)O2 layers in a unit cell. In Fig. 9, a structure in which the unit lattice is expanded by 2x2 is shown. The bold lines in the figure indicate The unit cell is shown in FIG. 9(a) and the upper layer and the lower layer. This shows the case where two Ga are placed in each of the lower layers. 9(b) has one Ga in the upper layer and three Ga in the lower layer. This shows the case where

[0042] In the case shown in FIG. 9(a), the arrangement of Ga in each layer is striped. Within the layer, Ga is arranged in parallel lines.

[0043] In addition, when considering the combination of the upper and lower layers, the Ga arrangement is parallel and crossed. The parallel arrangement is the G of the upper layer and the lower layer. A cross arrangement is when the lines of a are parallel to each other, and the upper layer and the lower layer are crossed. This refers to the case where the lines of the Ga of the yars cross. In the case of parallel arrangement, for example, U1+L There are two possible combinations: 1 and U1+L4. On the other hand, in the case of crossed arrangement, Since it is rotationally symmetric, there is only one possible combination, for example U1+L2. In other words, in the case shown in Figure 9(a), there are a total of three combinations. do.

[0044] In the case shown in FIG. 9(b), the combination of the upper layer and the lower layer is, for example, U7 Two possible configurations are possible: U7+L7 and U7+L10. Note that all Ga is in the upper layer or If U11+L is in one of the lower layers, there is only one possible combination. 11: not shown). Therefore, a total of six combinations of Ga arrangements can be considered. .

[0045] Next, the energy comparison results for the six configurations above are shown in Figure 10. The lowest energy of O4 is achieved when two Ga atoms are placed in the upper and lower layers. More specifically, it appears in structures such as U1+L1.

[0046] More detailed calculations were performed on the electronic state of this structure (the structure with the lowest energy). Figure 11 shows the electron density of state (DOS) and The results of the projected density of state (PDOS) calculation are shown below. From FIG. 11, it can be seen that Ga is the most dominant, followed by In.

[0047] Next, from the orbital function Ψ at the bottom of the conduction band, the probability of an electron existing at the bottom of the conduction band |Ψ| 2 Calculate The distribution is shown in Fig. 12. Here, Fig. 12(a) shows the In surface (in the InO2 layer). ) and Fig. 12(b) shows the probability of electrons in the (Ga, Zn)O2 layer. This represents the probability of the existence of an electron. It is interesting to note that the In orbital is separated.

[0048] From Fig. 12(b), the probability of electrons being present is high around Ga, and low around Zn. In addition, the electrical conduction path is not only the In surface, but also the (Ga, Zn This suggests that the InGaZnO4 layer is also It is considered that Ga contributes greatly to the air conduction. The Ga orbitals interact with the In orbitals. It is believed that the (Ga,Zn)O2 layer is also involved in the electrical conduction.

[0049] One of the features of InGaZnO4 is its high tolerance for electrical conductivity. This is believed to be due to the probability of oxygen vacancies (defects). This is because the electrical conductivity varies depending on the amount of element. In order to do so, we calculated the energy required for oxygen vacancy formation.

[0050] In addition, in the calculation based on density functional theory (DFT), the energy level of the oxygen vacancy is For example, LDA (Local Density Approximation) The sity approximation and GGA functions are used to obtain the The gap tends to be smaller than the actual measured value. Since the method is still under debate, we simply use the GGA function without scaling. This will eliminate artificial phenomena and allow us to grasp the true nature of the phenomenon. can be done.

[0051] Energy of oxygen vacancy (E VO ) is defined as follows: E VO =E(A m O n―1 )+E(O)-E(A m O n ) Here, E VOis half the energy of an oxygen molecule, and E(A m O n―1 ) is an oxygen vacancy A has m O n―1 The energy of A is an arbitrary element.

[0052] Figure 13 shows the E VO The geometric optimum value of is calculated as follows. Here, the lattice constants used are those of an ideal crystal. VO is high, i.e. This means that the density of oxygen vacancies is low in the thermal equilibrium state. E of N2O3, ZnO, Ga2O3 VO The following is also shown. In2O3, Zn The crystal structures of GaO and Ga2O3 are bixbyte and wurtzite, respectively. (wurtzite) type and β-Ga type.

[0053] E in InGaZnO VO changes depending on the elements around the oxygen vacancy. Specifically, The following three structural models are considered. Model 1 is a structure in which an oxygen vacancy is connected to one Zn atom and three In model 2, an oxygen vacancy is surrounded by one In atom. In model 3, an oxygen vacancy is surrounded by Ga and three In atoms. , surrounded by two Zn and two Ga atoms. E in GaZnO VO It is found that the number of Ga atoms around the oxygen vacancies increases with the number of Ga atoms around the oxygen vacancies. Also, the E of Ga2O3 VO is the largest, and Ga and O are strongly bonded. It can be said that this is the case.

[0054] When InGaZnO4 is in an amorphous state, in addition to the three models above, a more possible model is There are structures with high E VO is slightly different. By increasing the proportion of Ga in InGaZnO, the density of oxygen vacancies decreases, and As the proportion of Ga in 4 decreases, the density of oxygen vacancies increases.

[0055] In this way, by increasing the proportion of Ga in the non-single crystal semiconductor layer 102, the density of oxygen vacancies is reduced. In other words, the In-Ga-Zn-O oxide with good electrical properties can be used Considering the presence of In that contributes to electrical conduction, the ratio of In is reduced. Since it is not preferable to decrease the amount of Zn in the non-single crystal semiconductor layer 102, the amount of Zn in the non-single crystal semiconductor layer 102 is decreased. For example, it is preferable that the content (atomic %) of Zn in the non-single crystal semiconductor layer 102 is set to In The content (atomic %) of Cu should be less than the content (atomic %) of H and Ga. By reducing the Zn content in the non-single crystal semiconductor layer 102, good electrical characteristics can be obtained. In this way, an oxide semiconductor layer having the above structure can be obtained.

[0056] According to this embodiment, a high-performance oxide semiconductor layer can be provided. The embodiment can be used in appropriate combination with other embodiment modes.

[0057] (Embodiment 2) In this embodiment, the In-Ga-Zn-O based oxide semiconductor layer The results of further investigation into this issue will be explained with reference to the drawings.

[0058] In the first embodiment, the unit cell of the InGaZnO4 crystal structure is composed of two (Ga, Zn) It was shown that the ZnO layer is composed of one InO2 layer and one O2 layer. In this embodiment, the arrangement of Ga and Zn was examined in more detail. As shown in Figure 9, we consider several combinations of the upper and lower layers and The relationship between the arrangement of Ga and Zn in the (Ga, Zn)O2 layer and the energy The calculations and considerations were carried out.

[0059] The specific combinations (atomic arrangements) for which calculations were performed are shown in FIG. selected these combinations based on the number of nearest neighboring atoms of the same kind. For example, Figure 1 In the combination 4(a), Ga and Zn are separated in the upper and lower layers, respectively. By placing the atoms in the same order, the number of nearest neighboring atoms is set to zero. The combination 4(b) is a case where two atoms of the same kind exist at the nearest positions, and is shown in Figure 14(c). ) is the combination where there are 1.5 atoms of the same kind in the nearest positions, as shown in Figure 14(d). The combination is when there is one atom of the same kind at the nearest position. The same as that shown in State 1.

[0060] The calculation results are shown in Figure 15. In Figure 15, the structure with the lowest energy is the origin (energy The energies of each structure are shown as 0 eV.

[0061] The layouts investigated in this embodiment are only a small part of many layouts. From the results, we can see the tendency of Ga and Zn arrangement. This is thought to indicate that as the degree of aggregation decreases, the system becomes more energetically stable. In other words, in the InGaZnO4 crystal structure, Ga and Zn are precipitated as GaO and ZnO. It can be concluded that Ga and Zn are not clustered together, but rather take a mixed arrangement. shows a model diagram of the most likely configuration (corresponding to FIG. 15(d)).

[0062] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0063] (Embodiment 3) In this embodiment, an oxide semiconductor layer formed by the method described in Embodiment 1 or the like is used. An example of a manufacturing process of the semiconductor device will be described with reference to FIG. In this embodiment, detailed description of the same contents as those in the first embodiment will be omitted.

[0064] First, a gate electrode 202 is formed on a substrate 200 having an insulating surface, and then the gate After forming a gate insulating layer 204 on the gate electrode 202, an oxide semiconductor layer 206 and an oxide semiconductor The insulating layer 207 is formed by laminating layers (see FIG. 17(a)).

[0065] The substrate 200 having an insulating surface is, for example, a visible light transmissive substrate used in a liquid crystal display device or the like. The glass substrate may be a non-alkali glass substrate. The alkali-free glass substrate is preferably an aluminosilicate glass plate. Glass materials such as quartz, aluminoborosilicate glass, and barium borosilicate glass are used. In addition, the substrate 200 having an insulating surface may be a resin substrate, a ceramic substrate, a stone substrate, or the like. Insulating substrates made of insulators such as silicon substrates and sapphire substrates, and semiconductor substrates made of semiconductor materials such as silicon A conductive substrate whose surface is covered with an insulating material, or a conductive material made of a conductor such as metal or stainless steel The surface of the substrate can be covered with an insulating material. From the viewpoint of cost efficiency, it is particularly preferable to use a glass substrate. It is preferable that the ion exchange layer 10 has a thickness of 100 nm or less.

[0066] The gate electrode 202 is formed by forming a conductive layer on the entire surface of the substrate 200 and then forming the conductive layer by photolithography. The conductive layer is selectively etched using a resist mask formed by the above process. At this time, the coverage of the gate insulating layer 204 to be formed later is improved, and the step In order to prevent the gate electrode 202 from being cut, the end of the gate electrode 202 is etched to have a tapered shape. It is preferable that the gate electrode 202 is formed of the conductive layer such as a gate wiring. This includes electrodes and wiring that are connected to the substrate.

[0067] The gate electrode 202 is made of a low-resistance conductive material such as aluminum (Al) or copper (Cu). When aluminum is used for wiring and electrodes, Since rubber alone has problems such as low heat resistance and susceptibility to corrosion, it is combined with a heat-resistant conductive material. It is preferable to form them together.

[0068] The heat-resistant conductive material includes titanium (Ti), tantalum (Ta), tungsten ( W), Molybdenum (Mo), Chromium (Cr), Nd (Neodymium), Scandium (Sc) An element selected from the above, or an alloy containing the above elements, or a combination of the above elements The alloys or nitrides containing the above elements can be used. A film made of thermally conductive material and aluminum (or copper) are laminated to form wiring and electrodes. It is possible.

[0069] The gate insulating layer 204 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a nitride oxide film. The insulating film can be formed of a silicon oxide film, an aluminum oxide film, a tantalum oxide film, or the like. These films may be laminated. These films may be formed to a thickness of 20 nm or less by sputtering or the like. For example, the gate insulating layer 204 may be formed to a thickness of 250 nm or less. A silicon oxide film is formed to a thickness of 100 nm by sputtering. 04 only needs to function as a gate insulating layer for the transistor, and the manufacturing method and film thickness are not specified. However, the above numerical ranges should not be construed as being limited thereto.

[0070] Before forming the oxide semiconductor layer 206 on the gate insulating layer 204, the gate insulating layer 20 A plasma treatment may be performed on the surface of the gate insulating layer 4. Dust adhering to the surface of 204 can be removed.

[0071] The above plasma treatment is carried out by injecting an inert gas such as argon (Ar) gas into a vacuum chamber. A bias is applied to the workpiece (here, the substrate 200 on which the gate insulating layer 204 is formed). This can be done by applying a voltage to form a plasma state. There are electrons and Ar positive ions in the electron trap, and the Ar positive ions flow toward the cathode (the substrate 200 side). The accelerated positive ions of Ar collide with the surface of the gate insulating layer 204. As a result, the surface of the gate insulating layer 204 is sputter-etched, and the surface is modified. It is possible to use helium gas instead of argon gas. The atmosphere may be an atmosphere containing oxygen, hydrogen, nitrogen, etc., in addition to the nitrogen atmosphere. The treatment may be carried out in an atmosphere containing chlorine (Cl2) or carbon tetrafluoride (CF4). Plasma processing is sometimes called "reverse sputtering."

[0072] The oxide semiconductor layer 206 can be formed of an In-Ga-Zn-O based non-single crystal semiconductor layer. For example, oxides containing indium (In), gallium (Ga), and zinc (Zn) Sputtering method using a semiconductor target (In2O3:Ga2O3:ZnO=1:1:1) The oxide semiconductor layer 206 is formed by sputtering. The sputtering conditions and the like are the same as those in Embodiment 1. Just refer to it.

[0073] In addition, if a pulsed direct current (DC) power source is used in the above sputtering, dust can be reduced and the film thickness can be increased. In addition, after the above-mentioned plasma treatment, the particles are exposed to the air. By forming the oxide semiconductor layer 206 without forming a gate insulating layer 204, the oxide semiconductor It is possible to prevent dust and moisture from being attached to the interface of the oxide semiconductor layer 206. The film thickness of 06 may be about 5 nm to 500 nm.

[0074] The oxide semiconductor layer 207 is an In-Ga-Zn-O based non-single crystal structure similar to the oxide semiconductor layer 206. For example, the layer may be formed of an oxide semiconductor containing In, Ga, and Zn. The sputtering method uses a target (In2O3:Ga2O3:ZnO=1:1:1) The oxide semiconductor layer 207 can be formed on the oxide semiconductor layer 206. The oxide semiconductor layer 207 can be formed continuously without exposing the oxide semiconductor layer 206 to the air. The sputtering conditions are, for example, a temperature of 20° C. to 100° C. and a pressure of 0.1 Pa to 2 The temperature can be adjusted to 0.0 Pa and the power can be adjusted to 250 W to 3 kW (at 8 inch diameter). It is a good idea to introduce argon gas into the chamber.

[0075] The oxide semiconductor layer 206 and the oxide semiconductor layer 207 are preferably formed under different conditions. For example, the oxide semiconductor layer 206 is formed under the following conditions: Therefore, the ratio of the flow rate of oxygen gas to the flow rate of argon gas is increased. The deposition conditions for the compound semiconductor layer 207 are a rare gas (argon, helium, etc.) atmosphere, or The oxide semiconductor layer 206 was grown under an atmosphere of 10% or less oxygen gas and 90% or more rare gas. The film conditions are an oxygen atmosphere or an atmosphere with a flow rate ratio of oxygen gas to rare gas of 1 or more. In this way, the oxide semiconductor layer 206 has higher electrical conductivity than the oxide semiconductor layer 207. A layer 207 may be formed.

[0076] The oxide semiconductor layer 206 and the oxide semiconductor layer 207 are formed by sputtering. There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, DC sputtering, and pulsed DC A pulsed DC sputtering method in which a bias is applied can be used.

[0077] Also, a multi-target sputtering device capable of mounting multiple targets of different materials may be used. In sputtering equipment, different films can be laminated in the same chamber, or It is also possible to simultaneously sputter multiple types of materials to form a single film. - A method using a magnetron sputtering device equipped with a magnetic field generating mechanism inside (magnetron sputtering method) and ECR sputtering method using plasma generated by microwaves. Also, a chemical reaction between the target material and the sputtering gas components may be performed during the film formation. The reactive sputtering method, which forms a compound from these, and the via method, which applies a voltage to the substrate during film formation, A sputtering method or the like may also be used.

[0078] Note that in this embodiment, when the oxide semiconductor layer 206 and the oxide semiconductor layer 207 are stacked, However, the disclosed invention is not limited to this. A structure in which the semiconductor layer 207 is not provided (a structure in which only the oxide semiconductor layer 206 is formed) may be used. stomach.

[0079] Next, a resist mask 208 is formed over the oxide semiconductor layer 207. 08, the oxide semiconductor layer 206 and the oxide semiconductor layer 207 were selectively etched. An island-shaped oxide semiconductor layer 210 and an island-shaped oxide semiconductor layer 211 are formed (FIG. 17(b) reference).

[0080] For the above etching, it is recommended to use wet etching. For example, ITO07N (Kanto Chemical Co., Ltd.), or by wet etching using a mixture of acetic acid, nitric acid, and phosphoric acid. Then, unnecessary portions of the oxide semiconductor layer 206 and the oxide semiconductor layer 207 are removed to form island-shaped oxide semiconductor layers. The oxide semiconductor layer 210 and the island-shaped oxide semiconductor layer 211 are formed. The resist mask 208 is then removed. The material may be any material that can etch the oxide semiconductor layers 206 and 207. Of course, the above etching may be dry etching. You may use it.

[0081] Next, the conductive layer 212 is formed over the island-shaped oxide semiconductor layer 211 (see FIG. 17(c)).

[0082] The conductive layer 212 is formed by depositing aluminum (Al), copper (Cu) or the like by using a sputtering method or a vacuum deposition method. ), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), Metals containing elements selected from Cr, Nd, and Scandium, Alloys containing the above elements, alloys combining the above elements, or alloys The insulating layer 10 can be formed of a material such as a nitride having the above-mentioned components. After the conductive layer 212 is formed, a heat treatment (for example, at 350° C. to 800° C. (preferably 500° C. to Since the heat treatment is performed at a temperature of 750° C., it is preferable that the conductive layer 212 has a predetermined heat resistance.

[0083] For example, the conductive layer 212 may be formed of a single layer of titanium. 212 may be a laminated structure, for example, a laminated structure of an aluminum film and a titanium film. In addition, a titanium film, an aluminum film containing neodymium (Al-Nd), and a titanium The conductive layer 212 may be a three-layer structure of aluminum containing silicon. A single layer structure of the film may also be used.

[0084] Next, a resist mask 214a, a resist mask 214b, and a resist mask 214c are formed on the conductive layer 212. The conductive layer 212 is selectively etched to form a conductive layer 216a, a conductive The insulating layer 216b and the conductive layer 218 are formed, and the island-shaped oxide semiconductor layer 211 is etched. The semiconductor regions 215a and 215b are formed with high conductivity. A part of the oxide semiconductor layer 210 (a part near the surface) is removed (channel etched) (FIG. 1 7(d)).

[0085] A part of the island-shaped oxide semiconductor layer 210 and a part of the island-shaped oxide semiconductor layer 211 are removed. The recess 220 formed by the above process is between the conductive layer 216a and the conductive layer 216b and between the highly conductive semiconductor layer 216b and the conductive layer 216c. This corresponds to the region between the conductor region 215a and the semiconductor region 215b with high conductivity. The conductive layer 216a functions as one of the source and drain electrodes of the transistor. 216b functions as the other of the source and drain electrodes of the transistor. As shown in Fig. 1D, a part of the oxide semiconductor layer 210 and a part of the island-shaped oxide semiconductor layer 211 are By removing the insulating layer 216a and the insulating layer 216b, a recess 220 is formed. The conductive layer 218 can also electrically connect transistors and the like. It functions as a connecting wire.

[0086] As the above etching, it is preferable to use dry etching. This makes it possible to miniaturize wiring structures, etc., compared to when wet etching is used. In addition, the use of dry etching provides good etching controllability, so that the island-like The removal of the oxide semiconductor layer 210 (the formation of the recesses 220) can be performed with good controllability. Gases that can be used for dry etching include chlorine (Cl2), boron chloride (BCl 3) Chlorine gases such as silicon chloride (SiCl4) and carbon tetrachloride (CCl4) and carbon tetrafluoride Fluorine (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), trifluoromethane (CHF 3) Fluorine gases such as hydrogen bromide (HBr), oxygen (O2), and helium (He) and argon (Ar) are added to the gas. The etching may be wet etching.

[0087] The conductive layer 212 may be made of an island-shaped oxide semiconductor layer 210 or an island-shaped oxide semiconductor layer 211. It is preferable to use a material having a higher etching rate than the conductive layer 211. 12. The island-shaped oxide semiconductor layer 210 and the island-shaped oxide semiconductor layer 211 are etched in one step. In this case, the island-shaped oxide semiconductor layer 210 or the island-shaped oxide semiconductor layer 211 is etched. By making the etching rate of the gate smaller than that of the conductive layer 212, the island-shaped oxide semiconductor This is because excessive etching of layer 210 can be suppressed.

[0088] After the above etching, the resist mask 214a, the resist mask 214b, and the resist The mask 214c is removed.

[0089] Then, the mixture is heated under a predetermined temperature condition (for example, 350°C to 800°C (preferably 500°C to 750°C) When a glass substrate is used as the substrate 200 having an insulating surface, The heat treatment must be performed at a temperature below the distortion point of the glass substrate. The heat treatment may be performed in an air atmosphere or a nitrogen atmosphere. The oxide semiconductor crystal grains grow inside the InGaO3(ZnO) m (m>0) InGaO3(ZnO) in the amorphous structure m (m=1) As a result, a semiconductor layer (In-Ga-Zn-O based oxide semiconductor layer) can be obtained.

[0090] In addition, oxide semiconductors with an amorphous structure can easily be transformed into oxide semiconductors with a crystalline structure by heat or other factors. Therefore, when the ratio of the amorphous structure is high, the reliability of the transistor tends to decrease. From the viewpoint of improving reliability, the amorphous structure is set to 90% by volume or less (preferably 80% by volume or less). The heat treatment is carried out so that the content of the SiO 2 is reduced to 60% by volume or less, more preferably 60% by volume or less.

[0091] The heat treatment time can be appropriately changed depending on the heat treatment temperature. For example, Under these temperature conditions, the time may be about 0.5 to 2 hours. The conditions vary depending on the composition of the intended oxide semiconductor, so it is necessary to determine whether a desired oxide semiconductor layer is obtained. There are no particular limitations as long as the conditions are satisfactory.

[0092] The above heat treatments can be performed in a heating furnace such as a diffusion furnace or a resistance heating furnace, or in a rapid thermal The oxide semiconductor can be heated by using a heating device such as a 1 / 1 annealing device or a microwave heating device. Instead of heat treatment, light (electromagnetic waves) having a wavelength that is absorbed by the conductor may be irradiated. A structure containing crystal grains in an amorphous structure may be realized by irradiation with light (electromagnetic waves). In this case, a laser oscillator capable of emitting short wavelengths or an ultraviolet lamp, etc., can be used as a light source. good.

[0093] Thus, InGaO3(ZnO) m InGa O3(ZnO) m The oxide semiconductor layer including the crystal grain represented by (m=1) is used as the transistor chip. By using it as a channel forming region, a high performance semiconductor device can be provided.

[0094] Here, in order to realize an oxide semiconductor layer having good electrical characteristics, for example, The Zn content (atomic %) in the body is less than the In content (atomic %) and the Ga content (atomic %) is %). By using such a composition, good properties can be obtained. In this way, an oxide semiconductor layer having a large conductivity can be obtained.

[0095] As described above, the Zn content (atomic %) is less than the In content (atomic %) and the Ga content The oxide semiconductor layer having a content (atomic %) of less than 100% was prepared by using a target having a composition close to the intended one. In this case, the insulating layer 11 can be formed by a sputtering method in consideration of Figs. 2 and 3. As a result, the amount of Zn in the formed oxide semiconductor layer decreases compared to the composition of the target. The ratio is larger than that of In and Ga. For example, the content (atomic percent) of Zn is larger than that of In. In order to form an oxide semiconductor layer having a content (atomic %) of less than 100% and a content (atomic %) of Ga less than 100%. The target has an equal Zn content (atomic %) and an equal In or Ga content (atomic %). In other words, the target may be one having a Zn content (atomic %) and an In content ( %) or less and the Ga content (atomic %) or less may be used.

[0096] In this embodiment, the heat treatment is performed after the island-shaped oxide semiconductor layer 210 is formed. The heat treatment is performed at the same time as the oxide semiconductor layer 20. There is no need to be particularly limited as long as it is after the formation of 6. In addition, in the film formation stage, multiple If a structure containing crystal grains (a structure in which multiple crystal grains are dispersed in an amorphous structure) can be obtained, In this case, no heat treatment is required.

[0097] In addition, oxygen radicals are not used for the recesses 220 of the exposed island-shaped oxide semiconductor layer 210. By performing oxygen radical treatment, the island-shaped oxide semiconductor layer 210 is It becomes easy to make the thin film transistor having the channel formation region normally off. In addition, by performing radical treatment, the island-shaped oxide semiconductor layer 210 is etched away. Radical treatment can recover the image. It is preferable to carry out the reaction under an atmosphere of Ar or the like. It is also preferable to add Cl2 or CF4 to the above atmosphere. The radical treatment may be performed in a saturation atmosphere under a bias voltage applied to the substrate 200. It is preferable to do so without

[0098] Next, the gate electrode 202, the island-shaped oxide semiconductor layer 210, and the semiconductor region 215 having high conductivity are a, a thin film transistor including a semiconductor region 215b having high conductivity, a conductive layer 216a, a conductive layer 216b, etc. A protective insulating layer 222 is formed to cover the transistor 250 (see FIG. 17(e)). The protective insulating layer 222 is formed by depositing silicon nitride, silicon oxide, or nitride using a sputtering method or the like. Layers containing materials such as silicon oxide, silicon oxynitride, aluminum oxide, and tantalum oxide It is sufficient to form the following.

[0099] Thereafter, various electrodes and wiring are formed to complete the semiconductor device.

[0100] According to this embodiment mode, a high-performance semiconductor device can be provided. can be used in appropriate combination with other embodiments. [Explanation of symbols]

[0101] 100 Substrates 102 Non-single crystal semiconductor layer 104 Grains 106 Oxide semiconductor layer 200 Substrates 202 Gate electrode 204 Gate insulating layer 206 Oxide semiconductor layer 207 Oxide semiconductor layer 208 Resist Mask 210 Oxide semiconductor layer 211 Oxide semiconductor layer 212 Conductive layer 214a Resist mask 214b Resist mask 214c Resist mask 215a Semiconductor area 215b Semiconductor area 216a conductive layer 216b Conductive layer 218 Conductive Layer 220 Recess 222 Protective insulation layer 250 Thin Film Transistors

Claims

1. A first conductive layer having a region in contact with an insulating surface and functioning as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer, the first insulating layer comprising silicon oxide; a first oxide semiconductor layer having a region in contact with an upper surface of the first insulating layer; a second oxide semiconductor layer having a region in contact with an upper surface of the first oxide semiconductor layer; a second conductive layer having a region in contact with a top surface of the second oxide semiconductor layer, a region in contact with a side surface of the second oxide semiconductor layer, and a region in contact with a side surface of the first oxide semiconductor layer, and functioning as one of a source electrode and a drain electrode of the transistor; the first oxide semiconductor layer contains In, Ga, and Zn; the second oxide semiconductor layer includes In, Ga, and Zn; a content of Zn in the second oxide semiconductor layer is greater than a content of Zn in the first oxide semiconductor layer; the first oxide semiconductor layer has a crystal structure, the second oxide semiconductor layer has a crystal structure, a ratio of the crystal structure in the second oxide semiconductor layer is higher than a ratio of the crystal structure in the first oxide semiconductor layer.

2. A first conductive layer having a region in contact with an insulating surface and functioning as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer, the first insulating layer comprising silicon oxide; a first oxide semiconductor layer having a region in contact with an upper surface of the first insulating layer; a second oxide semiconductor layer having a region in contact with an upper surface of the first oxide semiconductor layer; a second conductive layer having a region in contact with a top surface of the second oxide semiconductor layer, a region in contact with a side surface of the second oxide semiconductor layer, and a region in contact with a side surface of the first oxide semiconductor layer, and functioning as one of a source electrode and a drain electrode of the transistor; the first oxide semiconductor layer contains In, Ga, and Zn; the second oxide semiconductor layer includes In, Ga, and Zn; a content of Zn in the second oxide semiconductor layer is greater than a content of Zn in the first oxide semiconductor layer; the first oxide semiconductor layer has a crystal structure, the second oxide semiconductor layer has a crystal structure, a ratio of the crystal structure in the second oxide semiconductor layer is higher than a ratio of the crystal structure in the first oxide semiconductor layer; a content of Zn in the first oxide semiconductor layer is less than a content of In and less than a content of Ga in the first oxide semiconductor layer.

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