Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device that can obtain predetermined on-resistance and predetermined withstanding voltage stably, and a manufacturing method for the silicon carbide semiconductor device.SOLUTION: A semiconductor wafer in which the n-type impurity concentration of an n-type drift region formed of an n-type epitaxial layer is higher than that of a targeted major carrier concentration (design value) of the n-type drift region is irradiated with a particle beam at any timing after a gate electrode is formed. By this particle beam irradiation, point defects are generated in the n-type drift region at a defect density according to the amount of irradiation with the particle beam. The effective major carrier concentration in the n-type drift region is adjusted to be lower than the n-type impurity concentration in the n-type drift region so as to become close to the target major carrier concentration. After the n-type epitaxial layer to become the n-type drift region is formed, the n-type impurity concentration of the n-type drift region may be measured or the n-type epitaxial layer to become the n-type drift region may be formed at the n-type impurity concentration higher than the design value.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, in a silicon carbide semiconductor device using silicon carbide (SiC) as a semiconductor material, a drift region is formed by epitaxial growth after doping with impurities (dopants) of a predetermined conductivity type. A conventional method for manufacturing a silicon carbide semiconductor device will be described using an example of manufacturing an n-channel vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor with an insulated gate having a three-layer structure of metal-oxide film-semiconductor).

[0003] FIG. 8 is a flowchart showing an outline of a conventional method for manufacturing a silicon carbide semiconductor device. + n-type drain region + A mold starting wafer is prepared. Next, n + On the starting wafer, - The epitaxial layers that will become the p-type drift region and the p-type base region are epitaxially grown in order (step S101). Through the steps up to this point, the main surface on the p-type epitaxial layer side that will become the p-type base region is set as the front surface, and the n + A semiconductor wafer is completed with the main surface on the mold starting wafer side as the back surface.

[0004] Next, n ions are implanted into the active areas in the individual chip regions of the semiconductor wafer. + Type source region and p ++A predetermined diffusion region such as a mold contact region is formed (step S102). Next, a predetermined breakdown voltage structure is formed in an edge termination region surrounding an active region in each chip region of the semiconductor wafer (step S103). Next, a MOS gate (insulated gate having a three-layer structure of metal-oxide-semiconductor) is formed (step S104). Next, an interlayer insulating film is formed on the front surface of the semiconductor wafer (step S105).

[0005] Next, the interlayer insulating film is selectively removed to form n + Type source region and p ++ A contact hole is formed to expose the mold contact region. Next, an ohmic electrode that makes ohmic contact with the semiconductor wafer in the contact hole of the interlayer insulating film is formed (step S106). Next, a front surface electrode and a back surface electrode are formed on both main surfaces of the semiconductor wafer, respectively (steps S107 and S108). Thereafter, the semiconductor wafer is cut (diced) to separate into individual semiconductor chips, thereby completing a conventional silicon carbide semiconductor device.

[0006] In the process of step S101, the epitaxial growth temperature of the epitaxial layer is as high as about 1600° C. - The variation in majority carrier (donor) concentration in the drift region becomes large. For example, - The majority carrier concentration in the type drift region varies from the target majority carrier concentration (design value) by about ±5% within the plane of a semiconductor chip (semiconductor substrate constituting a silicon carbide semiconductor device) and by about ±10% within the plane of a semiconductor wafer.

[0007] Therefore, n - The majority carrier concentration of the drift region varies by about ±15% from the target majority carrier concentration between semiconductor chips diced from the same semiconductor wafer. On the other hand, when silicon (Si) is used as the semiconductor material, the epitaxial growth temperature is lower than when silicon carbide is used as the semiconductor material. For this reason, the n-type drift region formed by epitaxial growth with nitrogen doping is -The variation in majority carrier concentration in the type drift region between semiconductor chips diced from the same semiconductor wafer is small, at about ±7% from the target majority carrier concentration.

[0008] Conventional silicon carbide semiconductor devices include n - The n-type drift region has a lifetime of 1 μsec or less for the minority carrier holes. - In the following Patent Documents 1 and 2, after forming a diffusion region by ion implantation and before forming a gate trench, annealing at a temperature of 1700° C. or higher, irradiation with an electron beam or a positron beam, or helium ion (He + ) irradiation and annealing to obtain n - This shortens the lifetime of minority carriers in the type drift region.

[0009] Conventional semiconductor devices using silicon as a semiconductor material include - Inside the drift region, protons (H + A device has been proposed in which a broad buffer structure is formed by irradiating and annealing the n - By disposing a broad buffer region having a net doping concentration distribution that decreases from the depth position where the net doping concentration is maximum toward each of the two main surfaces of the semiconductor substrate, n - The variation in resistivity of the drift region is reduced.

[0010] Another conventional semiconductor device that uses silicon as a semiconductor material is the n - In the drift region, proton irradiation causes n - An apparatus has been proposed in which hydrogen is introduced into the entire depth direction of the drift region (see, for example, Patent Document 4 below). In Patent Document 4 below, hydrogen is introduced into the entire depth direction of the drift region to increase the hydrogen concentration in the drift region to n - By making it higher than the donor concentration in the drift region, n - By increasing the majority carrier concentration in the drift region,- The resistivity of the drift region is adjusted to achieve high breakdown voltage. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] JP 2019-140242 A [Patent Document 2] JP 2019-080035 A [Patent Document 3] Patent No. 5569532 [Patent Document 4] JP 2007-266233 A Summary of the Invention [Problem to be solved by the invention]

[0012] However, in the above-mentioned conventional method for manufacturing a silicon carbide semiconductor device (see FIG. 8), the n - Although it is possible to reduce the variation in the majority carrier concentration of the epitaxial layer that becomes the drift region, there is a limit to the control of the epitaxial growth temperature. - No mention is made of the effective majority carrier concentration in the drift region.

[0013] n - The variation in majority carrier concentration in the drift region leads to variation in the on-resistance and breakdown voltage of the silicon carbide semiconductor device. - The adverse effects of variations in majority carrier concentration in the drift region become more pronounced. - The thicker the drift region, the greater the n - The adverse effects of variations in majority carrier concentration in the drift region become more pronounced.

[0014] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can stably obtain a predetermined on-resistance and a predetermined withstand voltage. [Means for solving the problem]

[0015] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention is a silicon carbide semiconductor device in which a main current flows through a pn junction between a second conductivity type epitaxial layer and a first conductivity type epitaxial layer, and has the following features: The first conductivity type epitaxial layer is provided on a front surface of a starting substrate made of silicon carbide. The first conductivity type epitaxial layer contains point defects at a defect density corresponding to an irradiation dose of a particle beam, and has an effective majority carrier concentration that is low with respect to a first conductivity type impurity concentration. The second conductivity type epitaxial layer is provided on the first conductivity type epitaxial layer.

[0016] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, an effective majority carrier concentration of the first conductivity type epitaxial layer is greater than or equal to 70% and less than 100% of a first conductivity type impurity concentration in the first conductivity type epitaxial layer.

[0017] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, an effective majority carrier concentration of the first conductivity type epitaxial layer is lower by 10% or less than a first conductivity type impurity concentration of the first conductivity type epitaxial layer.

[0018] In addition, in the silicon carbide semiconductor device according to the present invention, the particle beam is a helium beam, a proton beam or an electron beam.

[0019] In addition, in the silicon carbide semiconductor device according to the present invention, the first conductivity type epitaxial layer and the starting substrate entirely contain the point defects.

[0020] The silicon carbide semiconductor device according to the present invention includes a first conductivity type region, a second conductivity type region, a gate insulating film, a gate electrode, a first electrode, and a second electrode. The first conductivity type region is provided inside the second conductivity type epitaxial layer. The second conductivity type region is a portion of the second conductivity type epitaxial layer excluding the first conductivity type region. The gate insulating film is provided in contact with a region of the second conductivity type region between the first conductivity type region and the first conductivity type epitaxial layer. The gate electrode is provided on the opposite side of the second conductivity type region with the gate insulating film interposed therebetween. The first electrode is electrically connected to the first conductivity type region and the second conductivity type region. The second electrode is provided on a rear surface of the starting substrate.

[0021] Furthermore, in order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features: A first step is performed in which a first conductivity type epitaxial layer is epitaxially grown on a front surface of a starting substrate made of silicon carbide. A second step is performed in which a second conductivity type epitaxial layer is epitaxially grown on the first conductivity type epitaxial layer. A third step is performed in which a first conductivity type region is formed inside the second conductivity type epitaxial layer, and a portion of the second conductivity type epitaxial layer excluding the first conductivity type region is made into a second conductivity type region. A fourth step is performed in which a gate insulating film is formed in contact with a region of the second conductivity type region between the first conductivity type region and the first conductivity type epitaxial layer.

[0022] A fifth step is performed in which a gate electrode is formed on the opposite side of the second conductivity type region with the gate insulating film interposed therebetween. A sixth step is performed in which a first electrode electrically connected to the first conductivity type region and the second conductivity type region is formed. A seventh step is performed in which a second electrode is formed on the rear surface of the starting substrate. After the first step and before the second step, a measuring step is performed in which a first conductivity type impurity concentration of the first conductivity type epitaxial layer is measured. If the first conductivity type impurity concentration of the first conductivity type epitaxial layer measured in the measuring step is higher than a predetermined design value, an adjustment step is performed after the fifth step in which a particle beam is irradiated onto the first conductivity type epitaxial layer to reduce the effective majority carrier concentration of the first conductivity type epitaxial layer relative to the first conductivity type impurity concentration of the first conductivity type epitaxial layer to approach the design value.

[0023] Furthermore, in order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features: A first step is performed in which a first conductivity type epitaxial layer is epitaxially grown on a front surface of a starting substrate made of silicon carbide. A second step is performed in which a second conductivity type epitaxial layer is epitaxially grown on the first conductivity type epitaxial layer. A third step is performed in which a first conductivity type region is formed inside the second conductivity type epitaxial layer, and a portion of the second conductivity type epitaxial layer excluding the first conductivity type region is made into a second conductivity type region. A fourth step is performed in which a gate insulating film is formed in contact with a region of the second conductivity type region between the first conductivity type region and the first conductivity type epitaxial layer.

[0024] A fifth step is performed in which a gate electrode is formed on the opposite side of the second conductivity type region with the gate insulating film interposed therebetween. A sixth step is performed in which a first electrode electrically connected to the first conductivity type region and the second conductivity type region is formed. A seventh step is performed in which a second electrode is formed on the rear surface of the starting substrate. In the first step, the first conductivity type epitaxial layer is epitaxially grown with a first conductivity type impurity concentration higher than a predetermined design value. After the fifth step, an adjustment step is performed in which the first conductivity type epitaxial layer is irradiated with a particle beam to reduce the effective majority carrier concentration of the first conductivity type epitaxial layer relative to the first conductivity type impurity concentration of the first conductivity type epitaxial layer to approach the design value.

[0025] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the adjusting step adjusts an effective majority carrier concentration in the first conductivity type epitaxial layer to be equal to or more than 70% and less than 100% of a first conductivity type impurity concentration in the first conductivity type epitaxial layer.

[0026] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the adjusting step reduces an effective majority carrier concentration in the first conductivity type epitaxial layer by within 10% of a first conductivity type impurity concentration in the first conductivity type epitaxial layer.

[0027] In the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the adjusting step uses helium, protons or an electron beam as the particle beam.

[0028] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the adjusting step includes performing a heat treatment at a temperature of 350° C. or more and 400° C. or less after the particle beam irradiation.

[0029] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the adjusting step performs the heat treatment for not less than 30 minutes and not more than 60 minutes.

[0030] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the method does not include a heating step at a temperature of 400° C. or higher after the heat treatment in the adjusting step. Effect of the Invention

[0031] According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, n - Since the variation in the effective majority carrier concentration in the type drift region can be reduced, a predetermined on-resistance and a predetermined breakdown voltage can be stably obtained. [Brief description of the drawings]

[0032] [Figure 1] 1 is a plan view showing a state where a semiconductor wafer on which a silicon carbide semiconductor device according to an embodiment is manufactured is viewed from the front surface side. [Diagram 2] 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. [Diagram 3] 3 is a cross-sectional view showing a cross-sectional structure of the active region of FIG. 2. [Figure 4] 1 is a flowchart outlining a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Diagram 5] FIG. 13 is a characteristic diagram showing the relationship between the effective majority carrier concentration in the n-type drift region and particle beam irradiation in an experimental example. [Figure 6] FIG. 13 is a characteristic diagram showing the relationship between the effective majority carrier concentration in the n-type drift region and particle beam irradiation in an experimental example. [Figure 7] FIG. 13 is a characteristic diagram showing the relationship between the effective majority carrier concentration in the n-type drift region and particle beam irradiation in an experimental example. [Figure 8] 1 is a flowchart outlining a conventional method for manufacturing a silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with that. In the following description of the embodiments and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted.

[0034] (Embodiment) The structure of the silicon carbide semiconductor device according to the embodiment will be described by taking an n-channel vertical MOSFET with a trench gate structure as an example. FIG. 1 is a plan view showing a state where a semiconductor wafer on which the silicon carbide semiconductor device according to the embodiment is manufactured is viewed from the front surface side. FIG. 2 is a plan view showing a layout of the silicon carbide semiconductor device according to the embodiment as viewed from the front surface side of a semiconductor substrate (semiconductor chip). FIG. 2 shows a state after cutting one chip region 51 of FIG. 1. FIG. 3 is a cross-sectional view showing a cross-sectional structure of the active region of FIG. 2.

[0035] Silicon carbide semiconductor devices 10 according to the embodiment shown in Figures 2 and 3 are fabricated (manufactured) in each chip region 51 (see Figure 1) approximately in the center of a semiconductor wafer 50 using silicon carbide (SiC) as a semiconductor material by a manufacturing method (see Figure 4) for silicon carbide semiconductor device 10 according to an embodiment described later, and are then singulated into semiconductor substrates (semiconductor chips) 30. The chip regions 51 are portions of the semiconductor wafer 50 that are singulated by dicing (cutting) to become semiconductor substrates 30, and a plurality of chip regions 51 are arranged on the semiconductor wafer 50.

[0036] The multiple chip regions 51 of the semiconductor wafer 50 have, for example, a substantially rectangular planar shape, are arranged in a matrix, and are diced by cutting the semiconductor wafer 50 along dicing lines 52 that surround the chip regions 51 in a lattice pattern. All of the semiconductor substrates 30 diced from the same semiconductor wafer 50 have epitaxial layers 32 to 34 (see FIG. 3) that are epitaxially grown and stacked in the same process, and have the same element structure (here, a trench gate structure: see FIG. 3) formed in the same process.

[0037] Specifically, silicon carbide semiconductor device 10 according to the embodiment shown in Figures 2 and 3 is an n-channel vertical MOSFET with a trench gate structure on the front surface side of semiconductor substrate 30 made of silicon carbide in active region 41. Active region 41 is a region through which a main current (drift current) flows when the MOSFET is in an on-state, and multiple unit cells (functional units of an element) of the MOSFET having the same structure are arranged adjacent to each other. Active region 41 is arranged, for example, approximately in the center of semiconductor substrate 30, and is surrounded by edge termination region 42.

[0038] Edge termination region 42 is a region between active region 41 and an edge of semiconductor substrate 30. Edge termination region 42 has a function of maintaining a breakdown voltage by mitigating the electric field on the front surface side of semiconductor substrate 30. A breakdown voltage structure (not shown) such as a field limiting ring (FLR), a junction termination extension (JTE) structure, or a guard ring is disposed in edge termination region 42. The breakdown voltage is the limit voltage at which silicon carbide semiconductor device 10 does not malfunction or break down.

[0039] The semiconductor substrate 30 is made of silicon carbide. + On the front surface of the starting substrate 31, n-type buffer regions 2a, -The epitaxial layers 32 to 34 that become the n-type drift region 2b and the p-type base region (second conductivity type region) 4 are sequentially grown epitaxially. The main surface of the semiconductor substrate 30 on the side of the p-type epitaxial layer (second conductivity type epitaxial layer) 34 is the front surface, and the n-type epitaxial layer 32 is the n-type epitaxial layer (second conductivity type region) 4 on the side of the p-type epitaxial layer (second conductivity type region) 34 is the front surface. + The main surface (n + The back side of the starting substrate 31 is referred to as the back side. + The starting substrate 31 is n + This is a type drain region 1. The epitaxial layers 32 to 34 are epitaxially grown using a general epitaxial apparatus.

[0040] The n-type buffer region 2a is connected to the p-type base region 4 and - Holes (positive holes) generated at the pn junction interface with the n-type drift region 2b recombine in the n-type buffer region 2a to form n + The n-type buffer region 2a has a function of preventing the n-type + The function of this is to suppress the growth of stacking faults in the epitaxial layers 32 to 34 from the n-type starting substrate 31. + On the front surface of the starting substrate 31, - n-type drift region 2b - A first conductivity type epitaxial layer (first conductivity type epitaxial layer) 33 is epitaxially grown.

[0041] n - The drift region 2b is a region for helium (He), protons (H + ) or electron beam or other particle beam irradiation (see step S6 below). - The effective majority carrier (donor) concentration of the n-type drift region 2b is adjusted. - The n-type impurity concentration in the n-type drift region 2b is lower than that in the n-type drift region 2c. - The n-type impurity concentration of the n-type drift region 2b is - It is the concentration of n-type impurities (n-type dopants) doped into the n-type epitaxial layer 33 during epitaxial growth.

[0042] n- The effective majority carrier concentration of the n-type drift region 2b is - This is the concentration of n-type impurities (donors) in an electrically activated state among the n-type impurities (n-type dopants) doped into the n-type epitaxial layer 33 during epitaxial growth. - Since almost all of the n-type impurities doped into the n-type epitaxial layer 33 during epitaxial growth are in an electrically activated state, - The effective majority carrier concentration of the n-type drift region 2b is - The n-type impurity concentration in the n-type drift region 2b is approximately equal to that in the n-type drift region 2c.

[0043] Therefore, when particle beam irradiation is not performed, n - The effective majority carrier concentration of the type drift region 2b varies from the target majority carrier concentration (design value) by about ±5% within the plane of the semiconductor chip (semiconductor substrate 30) and by about ±10% within the plane of the semiconductor wafer 50. - The effective majority carrier concentration in the type drift region 2b varies from the target majority carrier concentration between semiconductor chips separated from the same semiconductor wafer 50 by about ±15%.

[0044] Therefore, in this embodiment, n - Type drift region 2b (n - The n-type epitaxial layer 33) has an n-type impurity concentration of - By irradiating the semiconductor wafer 50 with a particle beam having a higher majority carrier concentration than the target concentration of the n-type drift region 2b, - The effective carrier concentration of the n-type drift region 2b is adjusted to be low. - The drift region 2b contains point defects generated by the particle beam irradiation at a defect density according to the dose of the particle beam. - The n-type impurity concentration in the n-type drift region 2b does not change, but - The effective carrier concentration in the type drift region 2b decreases as the dose of particle beam increases.

[0045] For example, the particle beam irradiation may cause the n - In order to eliminate the variation in the effective carrier concentration of the n-type drift region 2b (about +10% from the target majority carrier concentration), - In this case, the effective carrier concentration of the n-type drift region 2b can be adjusted to be low. - In the n-type drift region 2b, the effective carrier concentration is lower by about 10% or less than the n-type impurity concentration. - Therefore, the variation in the effective majority carrier concentration of the type drift region 2b can be limited to the variation within the surface of the semiconductor chip (approximately +5% from the target majority carrier concentration).

[0046] Specifically, for example, n - 2 × 10 in type drift region 2b 11 / cm 2 When helium is irradiated at a dose of about 100 nm, the n - The effective reduction in majority carrier concentration in the drift region 2b is about 7% within the surface of the semiconductor wafer 50 (see FIG. 5 described later). Therefore, compared to the conventional method (variation of about +15%), the n - In this way, the variation in the effective majority carrier concentration in the type drift region 2b can be set to about +8% (=15%-7%) from the target majority carrier concentration.

[0047] For example, n - 1×10 in type drift region 2b 12 / cm 2 When protons are irradiated at a dose of about n - The effective reduction in majority carrier concentration in the drift region 2b is about 6% within the surface of the semiconductor wafer 50 (see FIG. 6 described later). Therefore, compared to the conventional method (variation of about +15%), the n - In this way, the variation in the effective majority carrier concentration in the type drift region 2b can be set to about +9% (=15%-6%) from the target majority carrier concentration.

[0048] For example, n - When the drift region 2b is irradiated with an electron beam at an absorbed dose of about 300 kGy, the n - The effective reduction in majority carrier concentration in the drift region 2b is about 5% within the surface of the semiconductor wafer 50 (see FIG. 7 described later). Therefore, compared to the conventional method (variation of about +15%), the n - The variation in the effective majority carrier concentration in type drift region 2b can be set to about +10% (=15%-5%) from the target majority carrier concentration.

[0049] The higher the dose of particle beam (helium dose, proton dose, and electron dose), the greater the n - The effective majority carrier concentration of the n-type drift region 2b can be reduced, but - The number of point defects in the n-type drift region 2b increases. - Since the electrical resistance of the n-type drift region 2b becomes high, the on-resistance of the silicon carbide semiconductor device 10 becomes high. - It is preferable that the effective majority carrier concentration in the type drift region 2b is not reduced too much.

[0050] Specifically, n - The effective majority carrier concentration of the n-type drift region 2b is - The n-type impurity concentration in the n-type drift region 2b is preferably, for example, 70% or more and less than 100%. - The variation in the effective majority carrier concentration in the type drift region 2b can be suppressed so that the increase from the target majority carrier concentration is less than +15%, which is smaller than that of the conventional method, and the decrease from the target majority carrier concentration is within approximately -15%, the same as that of the conventional method, while a balance can be achieved between the effect of particle beam irradiation and the suppression of an increase in the on-resistance.

[0051] n -The n-type drift region 2b is provided between the p-type base region 4 and the n-type buffer region 2a in contact with these regions. - The n-type epitaxial layer 33 includes an n-type current diffusion region 3 and first and second p-type + When the mold regions 21 and 22 are provided, n - The n-type drift region 2b is - The n-type epitaxial layer 33 includes the n-type current diffusion region 3 and the first and second p + The portion excluding the n-type regions 21 and 22, and the n-type current diffusion region 3 and the first and second p + The dopant is provided between the n-type regions 21 and 22 and the n-type buffer region 2a so as to be in contact with these regions.

[0052] The p-type base region 4 is a region of the p-type epitaxial layer 34, which will be described later. ++ A p-type source region (first conductivity type region) 5 and ++ The p-type base region 4 is a portion excluding the n-type contact region 6. - The n-type drift region 2b is provided between the n-type drift region 2b. - Between the n-type drift region 2b and the p-type base region 4, an n-type current spreading region 3, which is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers, may be provided in contact with these regions.

[0053] The n-type current diffusion region 3 is n-type, and the ... + The n-type current diffusion region 3 reaches a deep position on the n-type drain region 1 side. - The n-type epitaxial layer 33 is a diffusion region formed by ion implantation. - In the case of an n-type epitaxial layer deposited between the p-type epitaxial layer 33 and the p-type epitaxial layer 34, - Similarly to the n-type drift region 2b, the effective majority carrier concentration of the n-type current diffusion region 3 may be reduced by particle beam irradiation to be lower than the n-type impurity concentration of the n-type current diffusion region 3.

[0054] The trench gate structure includes a p-type base region 4, a n ++ Type source region 5 and p ++ The n-type contact region 6 is composed of a MOS gate including a trench (gate trench) 7, a gate insulating film 8, and a gate electrode 9, which will be described later. ++ Type source region 5 and p ++ The p-type contact region 6 is a diffusion region formed in the p-type epitaxial layer 34 by ion implantation. ++ Type source region 5 and p ++ The p-type contact regions 6 are selectively provided between the front surface of the semiconductor substrate 30 and the p-type base region 4, respectively.

[0055] n ++ Type source region 5 and p ++ The p-type contact region 6 is in contact with the p-type base region 4 and is exposed on the front surface of the semiconductor substrate 30 through a contact hole in the interlayer insulating film 11, which will be described later. The exposure on the front surface of the semiconductor substrate 30 means that the p-type contact region 6 is in contact with an ohmic electrode (first electrode) 13, which will be described later, through the contact hole in the interlayer insulating film 11. ++ The contact region 6 may not be provided. ++ When the contact region 6 is not provided, ++ In place of the p-type contact region 6, the p-type base region 4 is exposed on the front surface of the semiconductor substrate 30.

[0056] p-type base region 4 and n - Between the n-type drift region 2b and the bottom surface of the trench 7, + The first and second p + The first and second mold regions 21 and 22 may be provided. + The type regions 21 and 22 are n - The first and second p-type epitaxial layers 33 and 33a are diffusion regions formed by ion implantation into the n-type epitaxial layer 33 (or into the n-type epitaxial layer constituting the n-type current diffusion region 3). + The mold regions 21 and 22 have the function of reducing the electric field applied to the bottom surface of the trench 7.

[0057] 1st p. + The first p-type region 21 is provided apart from the p-type base region 4 and faces the bottom surface of the trench 7 in the depth direction. + The first region 21 may be electrically connected to the ohmic electrode 13 at a portion not shown. + The mold region 21 may surround the bottom surface of the trench 7 and be exposed to the bottom surface of the trench 7. The exposure to the bottom surface of the trench 7 means that the bottom surface of the trench 7 is in contact with the gate insulating film 8. + The mold region 22 is formed between the adjacent trenches 7 and has a first p + The trench 7 is provided apart from the p-type region 21 and is in contact with the p-type base region 4 .

[0058] Trench 7 is n ++ The n-type current diffusion region 3 (or the n-type current diffusion region 3 if the n-type current diffusion region 3 is not provided) penetrates the p-type source region 5 and the p-type base region 4. - The trench 7 is formed in a first region 100 of the semiconductor substrate 30 and extends to the first drift region 2b (FIG. 2A). A gate electrode 9 is provided inside the trench 7 with a gate insulating film 8 interposed therebetween. An interlayer insulating film 11 is provided on the front surface of the semiconductor substrate 30 and covers the gate electrode 9. A barrier metal (first electrode) 12 for preventing diffusion of metal atoms from the front electrode 14 side to the gate electrode 9 side may be provided over the entire area between the interlayer insulating film 11 and a front electrode (first electrode) 14 described below.

[0059] The ohmic electrode 13 is provided on the front surface of the semiconductor substrate 30 in a contact hole in the interlayer insulating film 11. ++ Type source region 5 and p ++ Type contact region 6(p ++ When the type contact region 6 is not provided, ++ The ohmic electrode 13 is a silicide film that is in ohmic contact with the p-type base region 4 instead of the n-type contact region 6. ++ Type source region 5 and p ++ The gate electrode 13 is electrically connected to the gate contact region 6. The barrier metal 12, the ohmic electrode 13 and the front electrode 14 function as a source electrode.

[0060] The front surface electrode 14 is provided on substantially the entire front surface of the semiconductor substrate 30 in the active region 41 so as to fill the contact hole of the interlayer insulating film 11. The front surface electrode 14 is connected to the p-type base region 4, the n-type ++ Type source region 5 and p ++ The back surface electrode (second electrode) 15 is electrically connected to the back surface (n + The back surface of the starting substrate 31 is provided on the entire surface of the substrate. + The back electrode 15 is electrically connected to the drain region 1. The back electrode 15 functions as a drain electrode.

[0061] Next, a method for manufacturing the silicon carbide semiconductor device 10 according to the embodiment will be described. FIG 4 is a flowchart showing an outline of the method for manufacturing the silicon carbide semiconductor device according to the embodiment. First, n + Prepare a starting wafer (semiconductor wafer). + The starting wafer is n-type after dicing of the semiconductor wafer 50. + Starting substrate 31(n + This is the part that will become the n-type drain region (see Figures 1 to 3). + An n-type epitaxial layer 32 that will become the n-type buffer region 2a is epitaxially grown on the front surface of the starting mold wafer.

[0062] Next, on the n-type epitaxial layer 32, - The n-type drift region 2b is doped with n-type impurities such as nitrogen (N) to achieve the desired majority carrier concentration. - The n-type epitaxial layer 33 is epitaxially grown (step S1: first process). In the process of step S1, - The effective majority carrier concentration of the n-type drift region 2b is - The n-type impurity concentration in the n-type drift region 2b is equal to that in the n-type - The n-type impurity concentration is adjusted to be the same as the target majority carrier concentration of the n-type drift region 2b. - Then, the type epitaxial layer 33 may be formed.

[0063] Next, n - The n-type impurity concentration of the n-type drift region 2b (i.e., n - The n-type impurity concentration of the n-type epitaxial layer 33 is measured (step S2: measuring step). - Since the surface of the n-type epitaxial layer 33 is exposed, - The n-type impurity concentration of the n-type epitaxial layer 33 can be accurately measured. - The n-type impurity concentration of the n-type epitaxial layer 33 may be measured using a common surface analysis method such as surface measurement using secondary ion mass spectrometry (SIMS) in which ions are irradiated and the ions collide with a solid surface at the molecular or atomic level to generate ions that are detected by a mass spectrometer, infrared spectroscopy in which the carrier concentration is measured by analyzing the spectrum shape in the low frequency range, or mercury CV (capacitance-voltage) measurement in which the carrier concentration is measured from the capacitance and voltage.

[0064] In the process of step S2, for example, n - The n-type impurity concentration may be measured in an ineffective region 53 (see FIG. 1) of the n-type epitaxial layer 33, or any one of the multiple chip regions 51 may be used as the region for impurity concentration measurement. The ineffective region 53 is a portion between the outermost chip region 51 of the semiconductor wafer 50 and the edge of the semiconductor wafer 50 that is not used as the semiconductor substrate 30 (see FIG. 2). Alternatively, the n-type impurity concentration may be measured in an ineffective region 53 (see FIG. 1) of the n-type epitaxial layer 33, or any one of the multiple chip regions 51 may be used as the region for impurity concentration measurement. - A sample for impurity measurement may be prepared by epitaxially growing the type epitaxial layer 33 .

[0065] n-type current diffusion region 3 and the first and second p + When forming the mold regions 21 and 22, after the process of step S1 and before the process of step S3 described later, each ion implantation for forming these regions is performed in an arbitrary order. - The n-type epitaxial layer 33 may be subjected to the n-type epitaxial layer 33. - The n-type epitaxial layer 33 is epitaxially grown in a number of stages, and ion implantation is performed each time. -The n-type current diffusion region 3 and the first and second p-type epitaxial layers 33 and 34 extend deep from the interface between the p-type epitaxial layer 34 and the n-type current diffusion region 3. + Mold regions 21 and 22 may be formed.

[0066] Next, n - On the n-type epitaxial layer 33, a p-type epitaxial layer 34 doped with p-type impurities such as aluminum (Al) is epitaxially grown. + Starting wafer (n + On the front surface of the starting substrate 31, an n-type epitaxial layer 32 is formed. - The semiconductor wafer 50 is completed by sequentially stacking the n-type epitaxial layer 33 and the p-type epitaxial layer 34. The main surface of the semiconductor wafer 50 facing the p-type epitaxial layer 34 is the front surface, and the n-type epitaxial layer 34 is the n-type epitaxial layer 33. + The main surface on the mold starting wafer side is the backside.

[0067] Next, a portion of the edge termination region 42 of the p-type epitaxial layer 34 is removed in each chip region 51 of the semiconductor wafer 50 to form an n-type epitaxial layer 34 on the front surface of the semiconductor wafer 50 in the edge termination region 42. - The p-type epitaxial layer 33 is exposed, leaving the p-type epitaxial layer 34 only in the active region 41. Next, n-type ions are implanted into the surface region of the p-type epitaxial layer 34 in the active region 41 of each chip region 51 of the semiconductor wafer 50 by ion implantation. + Type source region 5 and p ++ The mold contact regions 6 are selectively formed respectively.

[0068] removing a portion of edge termination region 42 of p-type epitaxial layer 34; + Type source region 5 and p ++ The order of the steps of forming the p-type contact region 6 and forming the n-type epitaxial layer 34 may be reversed. + Type source region 5 and p ++ The portion excluding the p-type contact region 6 becomes the p-type base region 4 (step S3: second and third steps). Next, the n-type -A predetermined voltage-resistant structure is formed in the surface region of the type epitaxial layer 33 (step S4).

[0069] Next, a MOS gate consisting of a trench 7, a gate insulating film 8, and a gate electrode 9 is formed by a general method (step S5: fourth and fifth steps). - The n-type impurity concentration of the n-type drift region 2b is n - A semiconductor wafer 50 having a higher majority carrier concentration than the target concentration in the type drift region 2b is irradiated with a particle beam (helium, proton or electron beam) from the front or back surface of the semiconductor wafer 50 at a predetermined dose (step S6: adjustment step).

[0070] By particle beam irradiation in step S6, n - By generating point defects in the drift region 2b with a defect density according to the dose of the particle beam, - n-type impurity concentration in the n-type drift region 2b - The effective majority carrier concentration of the n-type drift region 2b is adjusted to be low. The dose of the particle beam is adjusted to be the n - Based on the measured value of the n-type impurity concentration in the n-type drift region 2b, the n - The effective majority carrier concentration threshold of the drift region 2b is n - The concentration is set so as to approach the target majority carrier concentration (design value) of the type drift region 2b.

[0071] n - The effective majority carrier concentration threshold of the n-type drift region 2b is - is the median value of the range of variation of the effective majority carrier concentration of the n-type drift region 2b, - In step S6, after the particle beam irradiation, the semiconductor wafer 50 is heated by annealing (heat treatment) at a temperature of, for example, about 350° C. to 400° C. for about 30 minutes to 60 minutes to obtain a n - The point defects in the n-type drift region 2b are partially restored. -The effective majority carrier concentration threshold of the type drift region 2b may be adjusted.

[0072] By the particle beam irradiation in step S6, n - The entirety of the n-type epitaxial layer 33 and + Starting wafer (n + It is preferable that the whole of the starting substrate 31 is irradiated with the particle beam. - The particle beam may be irradiated to each portion other than the mold drift region 2b. For example, when irradiating the electron beam in step S6, the electron beam passes through the entire semiconductor wafer 50 from the front surface to the back surface (or from the back surface to the front surface) of the semiconductor wafer 50, so that the entire semiconductor wafer 50 is irradiated with the electron beam.

[0073] As described above, by the particle beam irradiation in step S6, n - The n-type impurity concentration in the n-type drift region 2b does not change, but - The effective carrier concentration of the n-type drift region 2b decreases according to the dose of the particle beam. - The effective majority carrier concentration of the drift region 2b can be reduced. - The lower limit of the effective majority carrier concentration of the type drift region 2b is as follows:

[0074] n - The dose of helium irradiation to the drift region 2b is, for example, 1×10 12 / cm 2 It is better to have it at about the following level. - The dose of proton irradiation to the drift region 2b is, for example, 4×10 12 / cm 2 It is better to have it at about the following level. - The absorbed dose of the electron beam irradiation to the drift region 2b is preferably, for example, about 700 kGy or less. By using such a particle beam irradiation dose, the on-resistance of the silicon carbide semiconductor device 10 is maintained while the n - The effective majority carrier concentration of the drift region 2b is set to, for example, 6×1015 / cm 2 It is possible to reduce the

[0075] Next, an interlayer insulating film 11 is formed on the front surface of the semiconductor wafer 50 (step S7). After the process of step S5, but before the process of step S7, a field oxide film may be formed on the front surface of the semiconductor wafer 50 in the edge termination region 42 of each chip region 51. Next, the interlayer insulating film 11 is selectively removed to open contact holes, and n-type semiconductor layers are inserted into the contact holes. + Type source region 5 and p ++ This exposes the mold contact region 6. Next, a barrier metal 12 that covers the entire surface of the interlayer insulating film 11 is formed by a general method.

[0076] Next, in the contact hole of the interlayer insulating film 11, + Type source region 5 and p ++ An ohmic electrode 13 in ohmic contact with the contact region 6 is formed (step S8: sixth step). Next, a front surface electrode 14 and a back surface electrode 15 are formed on both main surfaces of the semiconductor wafer 50 (steps S9, S10: sixth and seventh steps). Thereafter, the semiconductor wafer 50 is cut (diced) into individual semiconductor chips (semiconductor substrates 30), thereby completing the silicon carbide semiconductor device 10 of FIGS. 1 to 3.

[0077] In the manufacturing method of silicon carbide semiconductor device 10 according to the embodiment described above, it is preferable not to perform a heating step of heating semiconductor wafer 50 to a temperature of 400° C. or higher after the processing of step S6 (particle beam irradiation and annealing). The reason is that if semiconductor wafer 50 is heated to a temperature of 400° C. or higher after the processing of step S6, n - The effective majority carrier concentration threshold of the drift region 2b is n - This is because the majority carrier concentration in the type drift region 2b would deviate from the target concentration.

[0078] Specifically, the process of step S5 (formation of MOS gates) involves heating at a temperature of about 1100° C. Therefore, the process of step S6 may be performed at any timing after the process of step S5. The process of step S6 may be performed on a semiconductor chip (semiconductor substrate 30) that has been cut out from the semiconductor wafer 50. In addition, in the process of step S1, n - n-type impurity concentration higher than the target majority carrier concentration of n-type drift region 2b - A type epitaxial layer 33 may be formed.

[0079] In the process of step S1, - n-type impurity concentration higher than the target majority carrier concentration of n-type drift region 2b - By forming the type epitaxial layer 33, all the semiconductor wafers 50 are subjected to the process in step S6. This makes it possible to obtain a higher n-type epitaxial layer 33 than the conventional method (see FIG. 8) not only among semiconductor chips singulated from the same semiconductor wafer 50 but also among all semiconductor chips manufactured under the same manufacturing conditions. - Therefore, the variation in the effective majority carrier concentration in the type drift region 2b can be reduced.

[0080] As described above, according to the embodiment, n - The n-type impurity concentration in the n-type drift region is n - A semiconductor wafer with a higher majority carrier concentration (design value) than the target concentration in the drift region is irradiated with particle beams at some point after the formation of the gate electrode. This particle beam irradiation creates n point defects with a defect density according to the dose of the particle beam. - By generating the n - n for n-type impurity concentration in the n-type drift region - The effective majority carrier concentration in the type drift region is adjusted lower to approach the target majority carrier concentration.

[0081] This allows n - For a semiconductor wafer in which the effective majority carrier concentration in the type drift region varies in an increasing direction from the target majority carrier concentration, -The variation in effective majority carrier concentration in the n-type drift region can be reduced from about +15% in the conventional method (see FIG. 8) to about +5%. - By adjusting the dose of particle beams on the drift region, - The effective majority carrier concentration of the type drift region can be easily adjusted, and a predetermined on-resistance and a predetermined breakdown voltage can be stably obtained.

[0082] (Experimental Example) n after particle irradiation - The effective majority carrier concentration of the n-type drift region 2b was examined. - 4 is a characteristic diagram showing the relationship between the effective majority carrier concentration of the n-type drift region and particle beam irradiation in a MOSFET (hereinafter referred to as an experimental example, see FIG. 3) fabricated according to the method for manufacturing the silicon carbide semiconductor device 10 according to the embodiment described above (see FIG. 4), when helium (He), protons, and an electron beam were irradiated in the process of step S6. - The effective majority carrier concentrations of the n-type drift region 2b are shown in FIGS.

[0083] In Figures 5 to 7, - The n-type drift region 2b - The n-type impurity concentration of the epitaxial layer 33 (corresponding to the measured value in the process of step S2) is shown by a dashed line (reference line: nitrogen concentration 8×10 15 / cm 3 ) and n after the processing in step S6 - The effective majority carrier concentration of the n-type drift region 2b is shown by a solid line. - 5 to 7 represent the dose of helium, the dose of protons, and the absorbed dose of electron beams, respectively.

[0084] n - The effective majority carrier concentration of the p-type drift region 2b is the same as that of the p-type base region 4 and n-type drift region 2b, which are measured by CV (capacitance-voltage) measurement. - The junction capacitance (1 / C2 ) to the reverse voltage (V) applied to the pn junction, the depletion layer is + Calculated using the junction capacitance when the n-type drain region 1 is reached. - 5 to 7, the actual majority carrier concentration in the n-type drift region 2b is shown. + The mold areas 21 and 22 are not provided.

[0085] In any of the examples shown in FIGS. 5 to 7, the n - Since the actual majority carrier concentration in the n-type drift region 2b is decreased, it is considered that the n - It was confirmed that the actual majority carrier concentration of the n-type drift region 2b can be adjusted. - Since the n-type impurity concentration in the n-type drift region 2b does not change even after irradiation with particle beams, the n - n for the n-type impurity concentration in the n-type drift region 2b - It was confirmed that the ratio of the actual majority carrier concentration in the type drift region 2b becomes smaller.

[0086] The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the above-mentioned embodiment, a MOSFET is used as an example. - The present invention is applicable to silicon carbide semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and pin (p-intrinsic-n) diodes that have a type drift region. [Industrial Applicability]

[0087] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and are particularly suitable for MOSFETs. [Explanation of symbols]

[0088] 1n + Type drain region 2a n-type buffer region 2b n - Mold Drift Region 3 n-type current diffusion region 4 p-type base region 5n + Type Source Area 6 p ++ Mold Contact Area 7. Trench 8 Gate insulating film 9 Gate electrode 10 Silicon carbide semiconductor device 11 Interlayer insulating film 12 Barrier metal 13 Ohmic electrode 14 Front electrode 15 Back electrode 21,22 p + type area 30 Semiconductor Substrate 31 n + Starting substrate 32 n-type epitaxial layer 33n - Type epitaxial layer 34 p-type epitaxial layer 41 Active area 42 Edge Termination Area 50 Semiconductor Wafers 51 Chip area of ​​semiconductor wafer 52 Semiconductor wafer dicing line 53 Ineffective Area of ​​Semiconductor Wafer

Claims

1. A starting substrate made of silicon carbide; a first conductivity type epitaxial layer provided on a front surface of the starting substrate; a second conductivity type epitaxial layer provided on the first conductivity type epitaxial layer, wherein a main current flows through a pn junction between the second conductivity type epitaxial layer and the first conductivity type epitaxial layer, the first conductivity type epitaxial layer includes point defects at a defect density corresponding to an irradiation dose of a particle beam, and an effective majority carrier concentration is lower than a first conductivity type impurity concentration; a first conductivity type epitaxial layer having an effective majority carrier concentration that is equal to or greater than 70% and less than 100% of a first conductivity type impurity concentration in the first conductivity type epitaxial layer;

2. A starting substrate made of silicon carbide; a first conductivity type epitaxial layer provided on a front surface of the starting substrate; a second conductivity type epitaxial layer provided on the first conductivity type epitaxial layer, wherein a main current flows through a pn junction between the second conductivity type epitaxial layer and the first conductivity type epitaxial layer, the first conductivity type epitaxial layer includes point defects at a defect density corresponding to an irradiation dose of a particle beam, and an effective majority carrier concentration is lower than a first conductivity type impurity concentration; a first conductivity type epitaxial layer having an effective majority carrier concentration that is within 10% lower than a first conductivity type impurity concentration of the first conductivity type epitaxial layer;

3. A starting substrate made of silicon carbide; a first conductivity type epitaxial layer provided on a front surface of the starting substrate; a second conductivity type epitaxial layer provided on the first conductivity type epitaxial layer, wherein a main current flows through a pn junction between the second conductivity type epitaxial layer and the first conductivity type epitaxial layer, the first conductivity type epitaxial layer includes point defects at a defect density corresponding to an irradiation dose of a particle beam, and an effective majority carrier concentration is lower than a first conductivity type impurity concentration; a first conductivity type epitaxial layer and a starting substrate, the first conductivity type epitaxial layer and the starting substrate each including the point defects;

4. A silicon carbide semiconductor device as described in claim 1, characterized in that the effective majority carrier concentration of the first conductivity type epitaxial layer is within 10% lower than the first conductivity type impurity concentration of the first conductivity type epitaxial layer.

5. A silicon carbide semiconductor device according to claim 1, wherein the particle beam is a helium, proton or electron beam.

6. A silicon carbide semiconductor device as described in claim 1 or 2, characterized in that the point defects are contained throughout the first conductivity type epitaxial layer and the starting substrate.

7. A first conductivity type region provided inside the second conductivity type epitaxial layer; a second conductivity type region which is a portion of the second conductivity type epitaxial layer other than the first conductivity type region; a gate insulating film provided in contact with a region of the second conductivity type region between the first conductivity type region and the first conductivity type epitaxial layer; a gate electrode provided on the opposite side of the second conductivity type region with the gate insulating film interposed therebetween; a first electrode electrically connected to the first conductivity type region and the second conductivity type region; A second electrode provided on the rear surface of the starting substrate; 7. The silicon carbide semiconductor device according to claim 1, further comprising:

8. A first step of epitaxially growing a first conductivity type epitaxial layer on a front surface of a starting substrate made of silicon carbide; a second step of epitaxially growing a second conductivity type epitaxial layer on the first conductivity type epitaxial layer; a third step of forming a first conductivity type region in the second conductivity type epitaxial layer to define a second conductivity type region in the second conductivity type epitaxial layer except for the first conductivity type region; a fourth step of forming a gate insulating film in contact with a region of the second conductivity type region between the first conductivity type region and the first conductivity type epitaxial layer; a fifth step of forming a gate electrode on the opposite side of the second conductivity type region with the gate insulating film interposed therebetween; a sixth step of forming a first electrode electrically connected to the first conductivity type region and the second conductivity type region; a seventh step of forming a second electrode on a rear surface of the starting substrate; Including, performing a measuring step of measuring a first conductivity type impurity concentration of the first conductivity type epitaxial layer after the first step and before the second step; a first conductivity type impurity concentration of the first conductivity type epitaxial layer measured in the measuring step is higher than a predetermined design value, the first conductivity type impurity concentration of the first conductivity type epitaxial layer being irradiated with a particle beam after the fifth step, thereby lowering an effective majority carrier concentration of the first conductivity type epitaxial layer relative to the first conductivity type impurity concentration of the first conductivity type epitaxial layer to approach the design value.

9. A first step of epitaxially growing a first conductivity type epitaxial layer on a front surface of a starting substrate made of silicon carbide; a second step of epitaxially growing a second conductivity type epitaxial layer on the first conductivity type epitaxial layer; a third step of forming a first conductivity type region in the second conductivity type epitaxial layer to define a second conductivity type region in the second conductivity type epitaxial layer except for the first conductivity type region; a fourth step of forming a gate insulating film in contact with a region of the second conductivity type region between the first conductivity type region and the first conductivity type epitaxial layer; a fifth step of forming a gate electrode on the opposite side of the second conductivity type region with the gate insulating film interposed therebetween; a sixth step of forming a first electrode electrically connected to the first conductivity type region and the second conductivity type region; a seventh step of forming a second electrode on a rear surface of the starting substrate; Including, In the first step, the first conductivity type epitaxial layer is epitaxially grown with a first conductivity type impurity concentration higher than a predetermined design value; a first conductivity type epitaxial layer having a first conductivity type impurity concentration in a first conductivity type epitaxial layer and an effective majority carrier concentration in the first conductivity type epitaxial layer, the effective majority carrier concentration being adjusted to approach the design value, the first conductivity type impurity concentration being adjusted by irradiating the first conductivity type epitaxial layer with a particle beam after the fifth step.

10. A method for manufacturing a silicon carbide semiconductor device as described in claim 8 or 9, characterized in that in the adjustment process, the effective majority carrier concentration of the first conductivity type epitaxial layer is set to be 70% or more and less than 100% of the first conductivity type impurity concentration of the first conductivity type epitaxial layer.

11. A method for manufacturing a silicon carbide semiconductor device described in any one of claims 8 to 10, characterized in that in the adjustment process, the effective majority carrier concentration of the first conductivity type epitaxial layer is reduced by within 10% relative to the first conductivity type impurity concentration of the first conductivity type epitaxial layer.

12. A method for manufacturing a silicon carbide semiconductor device as described in any one of claims 8 to 11, characterized in that in the adjustment process, helium, proton or electron beam is used as the particle beam.

13. A method for manufacturing a silicon carbide semiconductor device described in any one of claims 8 to 12, characterized in that in the adjustment process, after irradiation of the particle beam, a heat treatment is performed at a temperature of 350°C or higher and 400°C or lower.

14. A method for manufacturing a silicon carbide semiconductor device as described in claim 13, characterized in that in the adjustment process, the heat treatment is performed for 30 minutes or more and 60 minutes or less.

15. The method for manufacturing a silicon carbide semiconductor device as described in claim 13 or 14, characterized in that it does not include a heating step at a temperature of 400° C. or higher after the heat treatment of the adjustment step.

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