Semiconductor module, semiconductor device, and vehicle

Abstract

A semiconductor module (1) comprises: a laminated substrate (2) having a first circuit board (22) disposed to a top surface of an insulation plate (20); a semiconductor element (3) disposed to a top surface of the first circuit board; a metal wiring board (4) including a first joint portion (40) joined to a top surface of the semiconductor element with a joining material (S) therebetween; and a sealing resin (5) sealing the laminated substrate, the semiconductor element, and the metal wiring board. The first joint portion includes a plate-shaped portion having a top surface and a bottom surface. The metal wiring board comprises: a first rising portion (43) rising upward from one end of the first joint portion; and a second rising portion (44) rising upward from another end of the first joint portion. The first rising portion constitutes a portion of a wiring path along which a main current flows. The second rising portion constitutes a non-wiring path along which the main current does not flow.

Description

[Technical field]

[0001] The present invention relates to a semiconductor module, a semiconductor device, and a vehicle. [Background technology]

[0002] 2. Description of the Related Art Semiconductor modules have substrates on which semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), FWDs (Free Wheeling Diodes), etc. are provided, and are used in inverter devices and the like.

[0003] In this type of semiconductor module, for example, in Patent Documents 1-3, a semiconductor element is disposed on an insulating substrate (which may also be called a laminated substrate), and a metal wiring plate for wiring (which may also be called a terminal connection portion, a lead frame, or an external electrode) is disposed on the upper electrode of the semiconductor element. The metal wiring plate is formed into a predetermined shape, for example, by pressing a metal plate. One end of the metal wiring plate is electrically joined to the upper electrode via a bonding material such as solder. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-079228 A [Patent Document 2] JP 2001-127100 A [Patent Document 3] International Publication No. 2016 / 067414 Summary of the Invention [Problem to be solved by the invention]

[0005] In this type of semiconductor module, the power semiconductor element generates heat as the switching operation proceeds. In the structure in which the metal wiring plate is soldered to the surface of the power semiconductor element as described above, the internal stress caused by temperature change may cause distortion at the joint. Such thermal cycles may cause peeling at the interface between the bonding material such as solder and the sealing resin between the metal wiring plate and the semiconductor element. If this peeling progresses, the thermal deformation of the metal wiring plate increases, and furthermore, the electrode distortion of the semiconductor element increases, which may cause a decrease in the tolerance of the entire device.

[0006] The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a semiconductor module, a semiconductor device, and a vehicle that are capable of suppressing peeling of a metal wiring board. [Means for solving the problem]

[0007] A semiconductor module according to one embodiment of the present invention comprises a laminated substrate having a first circuit board disposed on an upper surface of an insulating plate, a semiconductor element disposed on the upper surface of the first circuit board, a metal wiring board including a first joint portion bonded to the upper surface of the semiconductor element via a bonding material, and a sealing resin that seals the laminated substrate, the semiconductor element, and the metal wiring board, wherein the first joint portion includes a plate-shaped portion having an upper surface and a lower surface, and the metal wiring board has a first rising portion rising upward from one end of the first joint portion and a second rising portion rising upward from the other end of the first joint portion, the first rising portion forming part of a wiring path through which a main current flows, and the second rising portion forming a non-wiring path through which the main current does not flow. Effect of the Invention

[0008] According to the present invention, it is possible to suppress peeling of the metal wiring board. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic diagram showing a semiconductor device according to an embodiment of the present invention as viewed from above; [Diagram 2]2 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line AA. [Diagram 3] 2 is an enlarged view of a metal wiring board according to the present embodiment; FIG. [Figure 4] 4 is a plan view of the metal wiring board shown in FIG. 3 as viewed in the direction of arrow B. [Diagram 5] 4 is a side view of the metal wiring board shown in FIG. 3 as viewed in the direction of arrow C. [Figure 6] FIG. 4 is an enlarged view of the vicinity of part D in FIG. [Figure 7] 4 is a flow diagram showing an example of a method for manufacturing a semiconductor module according to the present embodiment. [Figure 8] 1 is a plan view showing a specific example of a semiconductor module to which a metal wiring board according to an embodiment of the present invention is applied. [Figure 9] 1 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention; [Figure 10] 11A and 11B are schematic diagrams showing modified examples of through-holes formed on the surface of a metal wiring board. [Figure 11] 1A to 1C are schematic diagrams showing variations of metal wiring boards. [Figure 12] 13A and 13B are schematic diagrams showing other variations of the metal wiring board. [Figure 13] 13A and 13B are schematic diagrams showing other variations of the metal wiring board. [Figure 14] 1 is a schematic plan view showing an example of a vehicle to which a semiconductor device of the present invention is applied; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A semiconductor module and a semiconductor device to which the present invention can be applied will be described below. Fig. 1 is a schematic diagram of a semiconductor device according to the present embodiment as viewed from above. Fig. 2 is a cross-sectional view of the semiconductor device shown in Fig. 1 taken along line AA. Fig. 8 is a plan view showing a specific example of a semiconductor module to which the metal wiring board according to the present embodiment is applied. Fig. 9 is an equivalent circuit diagram of the semiconductor device according to the present embodiment.

[0011] In the following figures, the longitudinal direction of the semiconductor module (cooler or metal wiring board) is defined as the X direction, the short side direction of the semiconductor module (cooler or metal wiring board) as the Y direction, and the height direction (thickness direction of the board) as the Z direction. The longitudinal direction of the semiconductor module indicates the direction in which multiple circuit boards are arranged. The illustrated X, Y, and Z axes are mutually orthogonal and form a right-handed system. In some cases, the X direction may be called the left-right direction, the Y direction the front-back direction, and the Z direction the up-down direction. These directions (front-back, left-right, up-down directions) are terms used for convenience of explanation, and the corresponding relationship with each of the XYZ directions may change depending on the mounting posture of the semiconductor module. For example, the heat dissipation surface side (cooler side) of the semiconductor module is called the bottom side, and the opposite side is called the top side. In this specification, plan view means the top or bottom side of the semiconductor module as seen from the Z direction. The aspect ratios and the size relationships between the various members in each drawing are merely schematic diagrams, and therefore do not necessarily match. For the sake of convenience, the size relationships between the components may be exaggerated.

[0012] A semiconductor device 100 according to this embodiment is applied to a power conversion device such as an inverter for an industrial or vehicle-mounted motor. As shown in Fig. 1 and Fig. 2, the semiconductor device 100 is configured by disposing a semiconductor module 1 on the upper surface of a cooler 10. Note that the cooler 10 may have any configuration relative to the semiconductor module 1.

[0013] The cooler 10 dissipates heat from the semiconductor module 1 to the outside and has an overall rectangular parallelepiped shape. Although not shown in the figures, the cooler 10 is configured by providing a plurality of fins on the lower surface side of a base plate and housing these fins in a water jacket. However, the cooler 10 is not limited to this and can be modified as appropriate.

[0014] The semiconductor module 1 is configured by arranging a laminated substrate 2, a semiconductor element 3, a metal wiring board 4, etc. in a case 11.

[0015] The laminated substrate 2 is formed of, for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazing) substrate, or a metal-based substrate. The laminated substrate 2 is formed by laminating an insulating plate 20, a heat sink 21, and a plurality of circuit plates (a first circuit plate 22 and a second circuit plate 23 described later), and is formed into a rectangular shape as a whole in a plan view.

[0016] Specifically, the insulating plate 20 is formed of a plate-like body having an upper surface and a lower surface, and has a rectangular shape in a plan view that is long in the X direction. The insulating plate 20 may be formed of a ceramic material such as aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), aluminum oxide (Al2O3), and zirconium oxide (ZrO2).

[0017] The insulating plate 20 may be formed of, for example, a thermosetting resin such as an epoxy resin or a polyimide resin, or a composite material in which a thermosetting resin is filled with glass or a ceramic material. The insulating plate 20 is preferably flexible and may be formed of, for example, a material containing a thermosetting resin. The insulating plate 20 may be called an insulating layer or an insulating film.

[0018] The heat sink 21 has a predetermined thickness in the Z direction and a rectangular shape in plan view that is long in the Y direction. The heat sink 21 is formed of a metal plate with good thermal conductivity, such as copper or aluminum. The heat sink 21 is disposed on the lower surface of the insulating plate 20. The lower surface of the heat sink 21 is a surface to be attached to the cooler 10 to which the semiconductor module 1 is attached, and also functions as a heat dissipation surface (heat dissipation area) for dissipating heat from the semiconductor module 1. The heat sink 21 is bonded to the upper surface of the cooler 10 via a bonding material S such as solder. The heat sink 21 may be disposed on the upper surface of the cooler 10 via a thermal conductive material such as thermal grease or thermal compound.

[0019] A plurality of circuit boards (first circuit board 22 and second circuit board 23) each have a predetermined thickness and are arranged on the upper surface of insulating plate 20. Each circuit board is formed in the shape of an electrically independent island. For example, each of the two circuit boards has a rectangular shape in a plan view and is arranged side by side in the X direction on insulating plate 20. Specifically, first circuit board 22 is located on the negative side in the X direction, and second circuit board 23 is located on the positive side in the X direction.

[0020] The number of circuit boards is not limited to two as shown in FIG. 1 and can be changed as appropriate. As will be described in detail later, three or more circuit boards may be arranged on the insulating plate 20 as shown in FIG. 8. The shapes and arrangement locations of the circuit boards are also not limited to these and can be changed as appropriate. These circuit boards are formed of metal plates with good thermal conductivity, such as copper or aluminum. The circuit boards may be called circuit layers or circuit patterns.

[0021] The semiconductor element 3 is disposed on the upper surface of the first circuit board 22 via a bonding material S such as solder. The bonding material S may be any material having electrical conductivity, and may be, for example, solder or a sintered metal material. The semiconductor element 3 is formed in a rectangular shape in a plan view using a semiconductor substrate such as silicon (Si).

[0022] In addition, the semiconductor element 3 may be composed of a wide bandgap semiconductor element (which may also be called a wide gap semiconductor element) formed from a wide bandgap semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), diamond, or the like, in addition to the above-mentioned silicon.

[0023] The semiconductor element 3 may be a switching element such as an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (power MOSFET), or a diode such as a free wheeling diode (FWD).

[0024] In this embodiment, the semiconductor element 3 is configured with an RC (Reverse Conducting)-IGBT element that integrates the functions of an IGBT (Insulated Gate Bipolar Transistor) element and an FWD (Free Wheeling Diode) element (see FIG. 9, for example).

[0025] The semiconductor element 3 is not limited to this, and may be configured by combining the above-mentioned switching elements, diodes, etc. For example, an IGBT element and an FWD element may be configured separately. Also, an RB (Reverse Blocking)-IGBT or the like having a sufficient withstand voltage against reverse bias may be used as the semiconductor element 3. Also, the shape, number of semiconductor elements 3, and location thereof may be changed as appropriate. For example, as shown in Figs. 8 and 9, four semiconductor elements 3 may be provided and the semiconductor elements 3 may be connected two by two to form an upper arm and a lower arm.

[0026] The semiconductor element 3 thus configured has an upper surface and a lower surface on the XY plane, and electrodes (not shown) are formed on each surface. For example, a main electrode and a gate electrode are formed on the upper surface of the semiconductor element 3, and a main electrode is also formed on the lower surface of the semiconductor element 3.

[0027] For example, when the semiconductor element 3 is a MOSFET element, the main electrode on the upper surface side may be called a source electrode, and the main electrode on the lower surface side may be called a drain electrode. When the semiconductor element 3 is an IGBT element, the main electrode on the upper surface side may be called an emitter electrode, and the main electrode on the lower surface side may be called a collector electrode. Regardless of the type of element, the gate electrode may be called a gate electrode as it is. An auxiliary electrode may be provided on the upper surface of the semiconductor element 3 in addition to the main electrode. For example, the auxiliary electrode may be an auxiliary source electrode or an auxiliary emitter electrode that is electrically connected to the main electrode on the upper surface side and serves as a reference potential for the gate potential. The auxiliary electrode may be a temperature sense electrode that is electrically connected to a temperature sense unit described later and measures the temperature of the semiconductor element. Such electrodes (main electrode, gate electrode, and auxiliary electrode) formed on the upper surface of the semiconductor element 3 may be collectively called upper surface electrodes, and the electrodes formed on the lower surface of the semiconductor element 3 may be called lower surface electrodes. Among the upper surface electrodes, the gate electrode and the auxiliary electrode may be called control electrodes.

[0028] In this embodiment, the main electrode is an electrode through which a main current flows, and the gate electrode is an electrode for controlling a gate for turning on and off the main current. Details of the upper surface electrode of the semiconductor element 3 will be described later.

[0029] Furthermore, the semiconductor element 3 in this embodiment may be a so-called vertical switching element in which functional elements such as transistors are formed in the thickness direction of a semiconductor substrate, or may be a horizontal switching element in which these functional elements are formed in the planar direction.

[0030] The upper surface (main electrode) of the semiconductor element 3 and the upper surface of the second circuit board 23 are electrically connected by the metal wiring board 4. The metal wiring board 4 constitutes a main current wiring member, and functions as a part of the path of the main current flowing inside the semiconductor module 1 (main current path).

[0031] The metal wiring board 4 is formed of a plate-like body having an upper surface and a lower surface. The thickness of the metal wiring board 4 may be 0.1 mm or more and 2.5 mm or less. The metal wiring board 4 is formed of a metal such as copper, a copper alloy, an aluminum alloy, an iron alloy, etc. The metal wiring board 4 is formed into a predetermined shape, for example, by press working. Note that the shape of the metal wiring board 4 shown below is merely an example and can be changed as appropriate. The metal wiring board 4 may also be called a lead frame.

[0032] The metal wiring board 4 according to this embodiment is an elongated body extending in the X direction in a plan view, and has a crank shape having a bent portion bent multiple times in a side view. Specifically, the metal wiring board 4 includes a first joint portion 40, a second joint portion 41, and a connecting portion 42. The first joint portion 40 is connected to the upper surface of the semiconductor element 3 via a bonding material S. The second joint portion 41 is connected to the upper surface of the second circuit board 23 via a bonding material S. The connecting portion 42 connects the first joint portion 40 and the second joint portion 41.

[0033] The first bonding portion 40 is formed in a rectangular shape smaller than the outer shape (or the upper electrode) of the semiconductor element 3 in a plan view. The first bonding portion 40 has upper and lower surfaces on the XY plane and includes a plate-like portion having a thickness in the Z direction. The first bonding portion 40 is disposed opposite the upper electrode of the semiconductor element 3 in the Z direction and is bonded to it via a bonding material S.

[0034] Although details will be described later, a plurality of bosses 40a protruding toward the semiconductor element 3 are formed on the lower surface of the first bonding portion 40. In addition, recesses 40b are formed on the upper surface of the first bonding portion 40 at locations directly above the bosses 40a.

[0035] At one end (the end on the positive side in the X direction) of the first joint portion 40, a first rising portion 43 is formed, which is bent at a substantially right angle and rises upward. The first rising portion 43 has a flat surface in the YZ plane and includes a plate-like portion having a thickness in the X direction. At the upper end of the first rising portion 43, a connecting portion 42 is formed, which is bent at a substantially right angle and extends in the X direction. That is, the upper end of the first rising portion 43 is connected to one end (the left end) of the connecting portion 42.

[0036] Further, at the other end (the end on the negative side in the X direction) of the first joint 40, a second rising portion 44 is formed, which is bent at a substantially right angle to the first joint 40 and rises upward. The second rising portion 44 has a flat surface in the YZ plane and includes a plate-like portion having a thickness in the X direction. Although details will be described later, the upper end of the second rising portion 44 is located higher than the first rising portion 43. Furthermore, the first rising portion 43 and the second rising portion 44 are formed on opposite sides of the rectangular first joint 40. The first rising portion 43 and the second rising portion 44 are disposed so as to face each other in the X direction.

[0037] The second joint portion 41 is formed in a rectangular shape smaller than the outer shape of the second circuit board 23 in a plan view. The second joint portion 41 has an upper surface and a lower surface on the XY plane and includes a plate-like portion having a thickness in the Z direction. The second joint portion 41 is disposed opposite the second circuit board 23 in the Z direction and is joined via a bonding material S.

[0038] Although details will be described later, a plurality of bosses 41a protruding toward the second circuit board 23 are formed on the lower surface of the second joint portion 41. In addition, recesses 41b are formed on the upper surface of the second joint portion 41 at locations directly above the bosses 41a.

[0039] A third rising portion 45 is formed at one end (the end on the negative side in the X direction) of the second joint portion 41, bending at a substantially right angle to the second joint portion 41 and rising upward. The third rising portion 45 has a flat surface in the YZ plane and includes a plate-like portion having a thickness in the X direction. A connecting portion 42 is formed at the upper end of the third rising portion 45, bending at a substantially right angle and extending toward the negative side in the X direction. That is, the other end (right end) of the connecting portion 42 is connected to the upper end of the third rising portion 45.

[0040] The connecting portion 42 has an upper surface and a lower surface on the XY plane, and includes a plate-like portion having a thickness in the Z direction. As described above, one end of the connecting portion 42 (the end on the negative side in the X direction) is connected to the first rising portion 43, and the other end of the connecting portion 42 (the end on the positive side in the X direction) is connected to the second rising portion 44. In other words, the connecting portion 42 connects the upper end of the first rising portion 43 and the upper end of the third rising portion 45.

[0041] Moreover, the length of the first rising portion 43 in the Z direction is shorter than that of the third rising portion 45 by the thickness of the semiconductor element 3. That is, the first bonding portion 40 and the second bonding portion 41 are provided at positions with different heights. More specifically, the first bonding portion 40 is provided at a higher position than the second bonding portion 41.

[0042] The width in the Y direction of the metal wiring board 4 thus configured is uniform from the first joint 40 to the second joint 41. The thickness of the metal wiring board 4 is uniform from the first joint 40 to the second joint 41. The first joint 40, the second joint 41, and the connecting portion 42 are arranged in a line along the X direction in a plan view. The width in the Y direction of the metal wiring board 4 does not need to be uniform from the first joint 40 to the second joint 41, and may have different widths as shown in FIG. 8. The thickness of the metal wiring board 4 does not need to be uniform from the first joint 40 to the second joint 41, and each bent portion may be partially thin. The first joint 40, the second joint 41, and the connecting portion 42 do not need to be arranged in a line, and may be arranged so as to be diagonally shifted from each other as shown in FIG. 8.

[0043] The shape, number, arrangement location, etc. of the metal wiring boards 4 described above are merely examples, and can be changed as appropriate without being limited thereto. As will be described in detail later, a plurality of (for example, four) metal wiring boards 4 may be arranged for one semiconductor module, as shown in Fig. 8. In this embodiment, the semiconductor element 3, the metal wiring boards 4, and main terminals, etc., described later, may form an inverter circuit, for example, as shown in Fig. 9.

[0044] The laminated substrate 2, the semiconductor element 3, and the metal wiring board 4 are surrounded by a case 11. The case 11 has a cylindrical or frame shape that is rectangular in plan view, and is made of, for example, a synthetic resin. The case 11 may be made of a thermosetting resin material such as epoxy resin or silicone rubber. The lower end of the case 11 is bonded to the upper surface of the cooler 10 via an adhesive (not shown), and the upper end extends to a position sufficiently higher than the upper surface of the metal wiring board 4. In this way, the case 11 surrounds the laminated substrate 2, the semiconductor element 3, and the metal wiring board 4, and defines a space that accommodates the laminated substrate 2, the semiconductor element 3, and the metal wiring board 4.

[0045] The internal space defined by the case 11 is filled with sealing resin 5. The sealing resin 5 may be filled so that the upper surface reaches the upper end of the case 11. This seals the laminated substrate 2, the semiconductor element 3, and the metal wiring board 4. The metal wiring board 4 is entirely covered with the sealing resin 5.

[0046] The sealing resin 5 may be made of, for example, a thermosetting resin. The sealing resin 5 preferably contains at least one of epoxy, silicone, urethane, polyimide, polyamide, and polyamideimide. For example, an epoxy resin mixed with a filler is suitable for the sealing resin 5 in terms of insulation, heat resistance, and heat dissipation.

[0047] As shown in a specific example in FIG. 8, the case 11 may be provided with a plurality of main terminals 60 for main current and a plurality of control terminals 64 for control. The main terminals 60 are formed of a plate-like elongated body. The main terminals 60 are embedded in the side walls of the case 11, one end of the main terminals 60 extending inward from the side walls of the case 11, and the other end of the main terminals 60 extending outward from the side walls of the case 11. One end of the main terminals 60 is electrically connected to a predetermined main electrode of the semiconductor element 3. In FIG. 8, two main terminals 60 constituting an N terminal and a P terminal are arranged side by side in the X direction on the side walls of the case 11 located on the negative side in the Y direction. Also, a main terminal 60 constituting an M terminal is arranged on the side walls of the case 11 located on the positive side in the Y direction.

[0048] As described above, in this embodiment, the semiconductor element 3, the metal wiring board 4, the main terminals 60, etc. form an inverter circuit as shown in Fig. 9, for example. These main terminals 60 (N terminal, P terminal, M terminal) correspond to IN(N) (which may be called a low potential side input terminal or a negative terminal), IN(P) (which may be called a high potential side input terminal or a positive terminal), and OUT(M) (which may be called an output terminal or an intermediate terminal) in Fig. 9, respectively.

[0049] Moreover, the control terminal 61 is formed of a long plate-like body. The control terminal 61 is embedded in a side wall of the case 11 located on the positive side in the Y direction. One end of the control terminal 61 extends from the side wall of the case 11 to the inside, and the other end of the control terminal 61 extends from the side wall of the case 11 to the outside. One end of the control terminal 61 is electrically connected to a predetermined control electrode of the semiconductor element 3 via a wiring member such as a bonding wire.

[0050] The main terminals 60 and the control terminals 61 are made of a metal such as copper, a copper alloy, an aluminum alloy, an iron alloy, etc., and have a predetermined electrical conductivity and a predetermined mechanical strength. The shapes, numbers, locations, etc. of the main terminals 60 and the control terminals 61 are not limited to these and can be changed as appropriate.

[0051] When a semiconductor module is subjected to a power cycle test and operated until it fails, most of the failures are due to electrode failures of the semiconductor elements. The following events, for example, can be considered as factors that can cause early failure of a semiconductor module.

[0052] Thermal stress causes peeling at the interface between the bonding material and the sealing resin between the semiconductor element and the metal wiring board. The peeling progresses along the interface between the metal wiring board and the sealing resin. If the thermal deformation of the metal wiring board increases due to the progression of the peeling, the electrode distortion increases, and the resistance decreases. Therefore, in order to improve the resistance of the semiconductor module, it is necessary to suppress peeling at the interfaces between the metal wiring board, the bonding material, and the sealing resin.

[0053] In view of this, the present inventors have arrived at the present invention in order to suppress peeling of the metal wiring board.The structure of the semiconductor module according to the present embodiment, in particular the detailed structure of the metal wiring board, will be described below.

[0054] Fig. 3 is an enlarged view of a metal wiring board according to this embodiment. Fig. 4 is a plan view of the metal wiring board shown in Fig. 3 as viewed in the direction of arrow B. In particular, Fig. 4A is a detailed view of the surface of the metal wiring board, and Fig. 4B is a see-through view of the configuration of the surface of a semiconductor element with the details of the surface omitted. Fig. 5 is a side view of the metal wiring board shown in Fig. 3 as viewed in the direction of arrow C. Fig. 6 is an enlarged view of the periphery of part D in Fig. 3.

[0055] 3 to 6, the first joint portion 40 of the metal wiring board 4 is recessed from the upper surface side to form a recess 40b, and a boss 40a protrudes from the lower surface side. In addition, a plurality of recesses 40c smaller than the recess 40b are formed on the upper surface of the first joint portion 40. The boss 40a and the recesses 40b, 40c are formed by press working.

[0056] Moreover, the bosses 40a are disposed in positions close to the four corners of the rectangular first joint portion 40 in a plan view. In this manner, by forming a plurality of bosses 40a, the first joint portion 40 does not tilt with respect to the upper surface of the semiconductor element 3 in the bonding process of the metal wiring board 4. Therefore, the posture of the metal wiring board 4 (first joint portion 40) can be stabilized.

[0057] Furthermore, by providing the boss 40a on the lower surface of the metal wiring board 4, a gap at least the height of the boss 40a can be secured between the first bonding portion 40 and the semiconductor element 3. By filling the gap with the bonding material S, the thickness of the bonding material S can be secured.

[0058] In addition, the upper surface of the first bonding portion 40 is roughened by forming a plurality of recesses 40c. As a result, the surface area of ​​the upper surface of the first bonding portion 40 is increased, and it is possible to improve the adhesion (anchor effect) between the upper surface of the first bonding portion 40 and the sealing resin. Therefore, it is possible to suppress the progress of peeling of the upper surface of the metal wiring board 4 caused by thermal stress above the semiconductor element 3.

[0059] In addition, a boss 41a protruding toward the second circuit board 23 is also formed on the back surface side of the second joint portion 41. This makes it possible to secure a gap at least the height of the boss 41a between the second joint portion 41 and the second circuit board 23. By filling the gap with the joint material S, it is possible to ensure the thickness of the joint material S.

[0060] As shown in FIG. 4A, in this embodiment, a total of four bosses 40a are provided, two in the X direction and two in the Y direction. The four bosses 40a are arranged along the outer periphery of the first joint portion 40 at positions corresponding to the four corners of the first joint portion 40. The bosses 40a have, for example, a cylindrical shape. In addition, a recess 40b is formed on the upper surface of the first joint portion 40 at a position directly above the boss 40a. The recess 40b may have a shape complementary to the boss 40a, and may have, for example, a cylindrical shape with the same diameter as the boss 40a.

[0061] Two bosses 41a are provided on the lower surface of the second joint portion 41 side by side in the Y direction. The shape of the bosses 41a may be the same as or different from that of the boss 40a described above. A recess 41b is formed on the upper surface of the second joint portion 41 at a location directly above the boss 41a. The recess 41b may have a shape complementary to the boss 41a, and may have, for example, a cylindrical shape with the same diameter as the boss 41a. The recess 41b may have the same shape and size as the recess 40b.

[0062] The shapes, arrangements, and numbers of the bosses 40a, 41a, the recesses 40b, 41b, and the recesses 40c described above are not limited to those described above and can be changed as appropriate. For example, the bosses 40a, 41a are not limited to a cylindrical shape, and may be a prismatic shape, a truncated cone shape tapering downward, or a hemispherical shape.

[0063] Moreover, the recess 40c is smaller than the recess 40b in plan view. For example, the recess 40c may have a polygonal shape (including a triangle, a rectangle, a pentagon, etc.) in plan view. The recess 40c may be square in plan view. The length D2 of one side of the square recess 40c may be, for example, 50 μm or more and 600 μm or less, and is preferably 80 μm or more and 300 μm or less.

[0064] Moreover, the recess 40c may have a quadrangular pyramid shape. The depth of the recess 40c may be 25% to 150% of the length D2 of one side of the recess 40c, and is preferably 50% to 110%. This shape allows the press die to have a simple shape. For example, the depth of the recess 40c may be smaller than the depth of the recess 40b. The depth of the recess 40c may be 30% to 90% of the depth of the recess 40b, and is preferably 50% to 75%.

[0065] The plurality of recesses 40c thus formed may be arranged in a lattice pattern at a predetermined pitch P, for example, in the X and Y directions. The predetermined pitch may be, for example, 50 μm or more and 900 μm or less, and preferably 100 μm or more and 600 μm or less. The plurality of recesses 40c may be formed on the upper surface of the second bonding portion 41, or may be formed only in the first bonding portion 40.

[0066] Moreover, it is preferable that the lower surface of the first bonding portion 40 is a flat surface except for the boss 40a. In other words, it is preferable that the lower surface of the first bonding portion 40 does not have a recess 40c formed thereon. For example, it is preferable that the surface roughness of the lower surface of the first bonding portion 40 is smaller than the surface roughness of the upper surface of the first bonding portion 40. By having a flat lower surface of the first bonding portion 40, voids and sink marks are less likely to occur in the bonding material S.

[0067] More specifically, the surface roughness of the upper surface and the lower surface of the first joint portion 40 in the present embodiment was compared by the interface development area ratio (Sdr). Here, the interface development area ratio is a value measured in accordance with ISO25178. In addition, the following are exemplified as the measurement environments for each parameter. The measurement region is preferably a range in which at least one pitch of the recess 40c is included. However, it is not limited to this measurement environment, and values measured in an equivalent measurement environment can also be used. [Examples of measurement environment] Measuring instrument: VK-X1100 manufactured by Keyence Corporation Controller unit: VK-X1000 manufactured by Keyence Corporation Objective lens: Apo × 20 times Cutoff: Gaussian S filter: None L filter: None F-operation: None

[0068] For example, on the lower surface of the first joint portion 40, the interface development area ratio is 0 < Sdr < 0.2, and more preferably 0.02 < Sdr < 0.15. If the lower surface of the first joint portion 40 is too rough, the wettability of the solder deteriorates, and voids and sink marks are likely to occur. On the other hand, on the upper surface of the first joint portion 40, 0.10 ≤ Sdr < 1.0, and more preferably 0.2 ≤ Sdr < 1.0. If the interface development area ratio on the upper surface of the first joint portion 40 is too small, there is a risk that peeling cannot be sufficiently suppressed. Also, if the interface development area ratio is too large, warping and undulation may occur during processing, resulting in deformation.

[0069] In addition, the area of the recess 40c in plan view may be 0.5% or more and 75% or less of the area of the boss 40a or the recess 40b, and preferably 1.0% or more and 25% or less. By setting it within this range, it is possible to effectively increase the surface area of the upper surface of the first joint portion 40.

[0070] Moreover, the metal wiring board 4 according to this embodiment is provided with a second rising portion 44 rising upward at the tip of the first bonding portion 40. The second rising portion 44 makes it possible to equalize the elongation of the base end side (the end on the positive side of the X-direction) and the tip side (the end on the negative side of the X-direction) of the first bonding portion 40. This is because the surface area in the vicinity of the tip of the first bonding portion 40 is increased by the second rising portion 44, so that it is possible to sufficiently secure the contact area with the sealing resin 5 as with the base end. As a result, it is possible to suppress the deformation amount of the first bonding portion 40 as a whole due to thermal stress, and it is possible to improve the effect of suppressing peeling at the interface.

[0071] Moreover, the main current flows between the semiconductor element 3 and the second circuit board 23 via a part of the metal wiring board 4. The first joint portion 40 and the first rising portion 43 are located on the wiring path between the semiconductor element 3 and the second circuit board 23. Therefore, the first rising portion 43 constitutes a part of the wiring path through which the main current flows. On the other hand, the second rising portion 44 is not located on the wiring path between the semiconductor element 3 and another semiconductor element, a terminal, or a circuit board (for example, the second circuit board 23). Therefore, almost no main current flows in the second rising portion 44. Here, a portion through which the main current does not flow is referred to as a non-wiring path. The second rising portion 44 constitutes a non-wiring path.

[0072] The first rising portion 43 and the second rising portion 44 are disposed opposite to each other, and the upper end of the second rising portion 44 is located higher than the first rising portion 43. This makes it possible to secure a larger surface area on the tip side of the first bonding portion 40 and more effectively suppress misalignment of the interface.

[0073] In addition, a plurality of recesses 44a are formed on the inner side of the second rising portion. A plurality of recesses 43a may also be formed on the inner side of the first rising portion 43. The recesses 44a, 43a may be configured with the same shape, number, and density as the recess 40c described above. In this way, by roughening the inner sides of the second rising portion 44 and the first rising portion 43, the surface area of ​​these inner sides is increased, and it is possible to improve the adhesion (anchor effect) with the sealing resin. Therefore, it is possible to effectively suppress the peeling progress of the metal wiring board 4 caused by thermal stress above the semiconductor element 3.

[0074] 3 to 6, the second rising portion 44 has a through-hole 44b penetrating in the thickness direction (X direction). As shown in FIG. 5, the through-hole 44b is formed, for example, as a circular hole. A plurality of the through-holes 44b (five in FIG. 5) are formed, for example, lined up in the Y direction. As shown in FIG. 6, the through-hole 44b is filled with the sealing resin 5. This improves the adhesion between the second rising portion 44 and the sealing resin 5, and in particular makes it possible to effectively suppress deformation of the second rising portion 44 in the Z direction. The shape and number of the through-holes 44b can be changed as appropriate.

[0075] 4B, a main electrode 3a and a plurality of control electrodes 3b are disposed on the upper surface of the semiconductor element 3 according to this embodiment. The main electrode 3a is formed in a rectangular shape in a plan view having an area covering most of the upper surface of the semiconductor element 3. Specifically, the main electrode 3a has an area larger than that of the first bonding portion 40 in a plan view. The plurality of (e.g., five) control electrodes 3b are disposed side by side along one side of the semiconductor element 3 on the negative side in the X direction.

[0076] Furthermore, a temperature sensing section 30a for detecting the temperature of the semiconductor element 3 may be provided on the upper surface of the semiconductor element 3. The temperature sensing section 30a has an elongated shape in a predetermined direction (e.g., the X direction) in a plan view at the center of the upper surface of the semiconductor element 3 (main electrode 3a). An output sense wiring 30b is electrically connected to the temperature sensing section 30a. The sense wiring 30b may be called a runner.

[0077] The sense wiring 30b extends linearly from the center of the upper surface of the semiconductor element 3 toward the outer edge of the semiconductor element 3 (one side on the negative side in the X direction). As described above, one end of the sense wiring 30b is electrically connected to the temperature sensing unit 30. The other end of the sense wiring 30b is electrically connected to a predetermined control electrode 3b. More specifically, the other end of the sense wiring 30b is connected to the control electrode 3b located in the center among the five control electrodes 3b. In this case, the predetermined control electrode 3b connected to the sense wiring 30b may be called a temperature sense electrode.

[0078] Moreover, the sense wiring 30b and the second rising portion 44 are provided at a position where they overlap (intersect) in a plan view. Since the joint portion between the sense wiring 30b and the first joint portion 40 is a region that is relatively prone to peeling, by positioning the second rising portion 44 directly above the sense wiring 30b, it is possible to increase the joint strength. Therefore, it is possible to prevent peeling at that portion in advance.

[0079] Next, a method for manufacturing the metal wiring board 4 configured as above will be described. Fig. 7 is a flow diagram showing an example of a method for manufacturing the semiconductor module (metal wiring board) according to this embodiment.

[0080] As shown in FIG. 7, the method for manufacturing semiconductor module 1 according to the present embodiment preferably includes the following steps ST101-ST105 in the process of manufacturing metal wiring board 4.

[0081] In step ST101, a roughening process is first performed. In this process, a plurality of recesses 40c are formed on the upper surface of the first joint portion 40, a plurality of recesses 43a are formed on the inner surface of the first rising portion 43, and a plurality of recesses 44a are formed on the inner surface of the second rising portion 44. Here, a metal plate that is the material of the metal wiring board 4 is prepared. Then, the lower surface of the metal plate that corresponds to the lower surface of the metal wiring board 4 is arranged so as to contact a lower mold having a flat surface. Note that, at this stage, the upper surface of the first joint portion 40, the inner surface of the first rising portion 43, and the inner surface of the second rising portion 44 are on the same plane. Then, an upper mold having a predetermined convex shape is pressed against the upper surface of the metal plate that corresponds to the upper surface of the metal wiring board 4. In this way, a plurality of recesses 40c, 43a, and 44a are formed in a predetermined region of the upper surface of the metal plate. In addition, the lower surface of the metal plate becomes flat. Furthermore, the roughening process may be performed by excluding the region that corresponds to the recess 40b.

[0082] In step ST102, a punching process is performed. In this step, the metal plate is punched into a predetermined shape. The predetermined shape may be an external shape in which a plurality of metal wiring plates 4 are partially connected by a connection bar (not shown). At this time, the through-holes 43b and 44b may be punched out using a predetermined mold shape.

[0083] In step ST103, a bending process is performed. In this process, predetermined portions of the metal wiring board 4 are bent to form a crank shape. As a result, the first joint portion 40, the second joint portion 41, the connecting portion 42, the first rising portion 43, the second rising portion 44, and the third rising portion 45 are formed in the metal wiring board 4.

[0084] In step ST104, a boss forming process is performed. In this process, a recess 40b is formed on the upper surface and a boss 40a is formed on the lower surface at a predetermined location (e.g., first joint 40) of the metal wiring board 4. For example, the lower surface of the metal wiring board 4 is placed in contact with a lower mold in which a recess corresponding to the boss 40a is formed. Then, an upper mold in which a convex shape corresponding to the recess 40b is formed is pressed against the upper surface of the metal wiring board 4. In this way, a plurality of recesses 40b are formed on the upper surface of the metal wiring board 4, and a plurality of bosses 40a are formed on the lower surface of the metal wiring board 4. The same applies to the bosses 41a and the recesses 41b.

[0085] In step ST105, a connection bar cutting process is performed. In this process, the connection bars of the metal wiring boards 4 connected together by the connection bars are cut to separate the metal wiring boards 4 into individual metal wiring boards 4. This process may also be performed by pressing using two dies, one above and one below.

[0086] The above steps ST101-105 are all realized by press processing. Therefore, it is possible to realize boss formation and surface roughening with a cheaper configuration than when laser processing or chemicals are used. Note that each step is merely an example, and the order of each step can be changed as appropriate within the scope of not causing any contradiction. In addition, other steps such as plating and rust prevention treatment may be included.

[0087] As described above, according to this embodiment, the bonding strength between the semiconductor element and the metal wiring board can be improved.

[0088] Next, modified examples will be described with reference to Fig. 10 to Fig. 13. Fig. 10 is a schematic diagram showing a modified example of a through-hole formed on the surface of a metal wiring board. Figs. 11A-11C are schematic diagrams showing variations of the metal wiring board. Figs. 12A-12B and Figs. 13A-13B are schematic diagrams showing other variations of the metal wiring board. In the following modified examples, the previously mentioned configurations are indicated by the same names and the same symbols, and the description will be omitted as appropriate.

[0089] In the above embodiment, as shown in FIG. 5, the through-hole 44b is formed as a circular through-hole, but the present invention is not limited to this configuration. For example, the configuration shown in FIG. 10 may be used. In FIG. 10, the through-hole 44b is formed in the center of the second rising portion 44 in the Y direction. In addition, notches are formed at both ends of the second rising portion 44 as other through-holes 44c. The notches extend from the edges of the second rising portion 44 in the Y direction toward the center in the Y direction. By filling the sealing resin 5 in such through-holes 44b and 44c, the anchor effect of the second rising portion 44 in the Z direction can be enhanced. In addition, the through-holes 44b and 44c can also be applied to the first rising portion 43.

[0090] In the above embodiment, the sense wiring 30b formed on the upper surface of the semiconductor element 3 and the second rising portion 44 are arranged to overlap each other in a plan view, but the present invention is not limited to this configuration. For example, the configurations shown in Figs. 11 and 12 are also possible. In Figs. 11 and 12, the first rising portion 43 and the second rising portion 44 are formed on opposite sides of the rectangular first joint portion 40.

[0091] 11A and 11B, the first rising portion 43 and the second rising portion 44 are arranged to face each other with the sense wiring 30b therebetween. That is, in Figures 11A and 11B, the sense wiring 30b and the first rising portion 43 and the second rising portion 44 may be arranged so as not to overlap each other in a plan view.

[0092] 11A, the first rising portion 43 and the second rising portion 44 may be disposed so as to face each other in front with the temperature sensing portion 30a in between. That is, the first rising portion 43 and the second rising portion 44 may be disposed in line symmetry with respect to the temperature sensing portion 30a.

[0093] 11B, the first rising portion 43 and the second rising portion 44 may be disposed so as to be diagonally opposed to each other with the temperature sensing portion 30a therebetween. That is, the first rising portion 43 and the second rising portion 44 may be disposed point-symmetrically with respect to the temperature sensing portion 30a.

[0094] 11C, one first rising portion 43 may be provided, while two second rising portions 44 may be arranged in opposing portions. In this case, the sense wiring 30b may be located between the two second rising portions 44. Even in this case, the sense wiring 30b and the second rising portion 44 do not overlap in a planar view. The total width of the two second rising portions 44 may be the same as or larger than the width of the first rising portion 43.

[0095] 12A , the width of the second rising portion 44 may be greater than the width of the first rising portion 43. The width of the second rising portion 44 may be the same as the width of the first joint portion 40, or the width of the first rising portion 43 may be smaller than the width of the first joint portion 40.

[0096] 12B, a notch 46 may be formed at the base end of the first rising portion 43 and the base end of the second rising portion 44. That is, the notch 46 is formed at the end of the first joint portion 40 to which the lower end of the first rising portion 43 is connected. Similarly, the notch 46 is formed at the end of the first joint portion 40 to which the lower end of the second rising portion 44 is connected.

[0097] The two notches 46 may be disposed so as to face each other diagonally with the temperature sensing portion 30a in between. That is, the two notches 46 may be disposed point symmetrically with respect to the temperature sensing portion 30a. With these configurations, the stress on the first bonding portion 40 caused by each rising portion (the first rising portion 43 and the second rising portion 44) can be alleviated, and the first bonding portion 40 can be made less likely to peel off from the upper surface of the semiconductor element 3.

[0098] In the above embodiment, the second rising portion 44 rises at a right angle to the first joint portion 40, but the present invention is not limited to this configuration. The second rising portion 44 may be inclined with respect to the first joint portion 40. For example, the second rising portion 44 may rise (or be bent) to form an acute angle or an obtuse angle with respect to the first joint portion 40.

[0099] Specifically, as shown in Figures 13A and 13B, the angle between the first joint 40 and the first rising portion 43 is represented as θ1, and the angle between the first joint 40 and the second rising portion 44 is represented as θ2. In this case, it is preferable that θ2<θ1. In this case, the upper end of the second rising portion 44 may be located lower than the first rising portion 43. In addition, it is preferable that the length L1 of the first rising portion 43 (the difference in height between the first joint 40 and the connecting portion 42) is longer than the length L2 of the second rising portion 44.

[0100] According to this configuration, when the width of the first rising portion 43 and the width of the second rising portion 44 are the same, it is possible to make the surface area of ​​the second rising portion 44 larger than that of the first rising portion 43. This makes it possible to make the contact area of ​​the second rising portion 44 with the sealing resin 5 larger than that of the first rising portion 43, and to further enhance the anchor effect. In other words, it is preferable that the surface area of ​​the second rising portion 44 is larger than the surface area of ​​the first rising portion 43.

[0101] In the above embodiment, the multiple recesses 40c are arranged in a lattice pattern with equal pitches in a plan view, but the present invention is not limited to this configuration. For example, the multiple recesses 40c may be arranged in a staggered pattern. Here, the staggered pattern refers to a pattern in which a row of recesses 40c is formed by multiple recesses 40c arranged in a predetermined direction (for example, the X direction), and the row of recesses 40c is shifted by half a pitch (1 / 2P) from the row of adjacent recesses 40c. In the staggered pattern, the rows of multiple recesses 40c are alternately arranged with a half pitch shift. The fluctuating arrangement of the recesses 40c may be applied to the recesses 43a and the recesses 44a.

[0102] A vehicle to which the present invention is applied will be described with reference to Fig. 14. Fig. 14 is a schematic plan view showing an example of a vehicle to which the semiconductor device of the present invention is applied. Vehicle 101 shown in Fig. 14 is, for example, a four-wheeled vehicle equipped with four wheels 102. Vehicle 101 may be, for example, an electric vehicle in which the wheels are driven by a motor or the like, or a hybrid vehicle that uses power from an internal combustion engine in addition to a motor.

[0103] The vehicle 101 includes a drive unit 103 that applies power to the wheels 102, and a control device 104 that controls the drive unit 103. The drive unit 103 may be composed of at least one of an engine, a motor, and a hybrid of an engine and a motor, for example.

[0104] The control device 104 performs control (for example, power control) of the above-mentioned drive unit 103. The control device 104 includes the above-mentioned semiconductor device 100. The semiconductor device 100 may be configured to perform power control for the drive unit 103.

[0105] Furthermore, in the above embodiment, the number and locations of the semiconductor elements 3 are not limited to the above configuration and can be changed as appropriate.

[0106] In addition, in the above embodiment, the number and layout of the circuit boards are not limited to the above configuration, and can be changed as appropriate.

[0107] In the above embodiment, the laminated substrate 2 and the semiconductor element 3 are configured to be rectangular or square in plan view, but are not limited to this configuration. These configurations may be formed into polygonal shapes other than those described above.

[0108] Furthermore, although the present embodiment and modifications have been described, other embodiments may be combinations of the above-described embodiments and modifications in whole or in part.

[0109] In addition, the present embodiment is not limited to the above-mentioned embodiment and modification, and may be modified, substituted, or altered in various ways without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological progress or a different derived technology, it may be implemented using that method. Therefore, the claims cover all embodiments that may be included in the scope of the technical idea.

[0110] The features of the above embodiment are summarized below. The semiconductor module according to the above embodiment includes a laminated substrate having a first circuit board disposed on an upper surface of an insulating plate, a semiconductor element disposed on the upper surface of the first circuit board, a metal wiring board including a first joint portion bonded to the upper surface of the semiconductor element via a bonding material, and a sealing resin that seals the laminated substrate, the semiconductor element, and the metal wiring board, wherein the first joint portion includes a plate-shaped portion having an upper surface and a lower surface, and the metal wiring board has a first rising portion rising upward from one end of the first joint portion and a second rising portion rising upward from the other end of the first joint portion, the first rising portion forming part of a wiring path through which a main current flows, and the second rising portion forming a non-wiring path through which the main current does not flow.

[0111] In the semiconductor module according to the above embodiment, the first rising portion and the second rising portion are disposed opposite to each other.

[0112] In the semiconductor module according to the above embodiment, the second rising portion has a larger surface area than the first rising portion.

[0113] In the semiconductor module according to the above embodiment, the upper end of the second rising portion is located higher than the first rising portion.

[0114] In the semiconductor module according to the above embodiment, the width of the second rising portion is equal to or greater than that of the first rising portion in a plan view.

[0115] In the semiconductor module according to the above embodiment, the first rising portion and / or the second rising portion rises at a right angle to the first joint portion.

[0116] Furthermore, in the semiconductor module of the above embodiment, the second raised portion is inclined with respect to the first joint portion, and the angle formed between the first joint portion and the second raised portion is smaller than the angle formed between the first joint portion and the first raised portion.

[0117] In the semiconductor module according to the above embodiment, the upper end of the second rising portion is located lower than the first rising portion.

[0118] In the semiconductor module according to the above embodiment, a plurality of recesses are formed on the inner side surface of the second rising portion.

[0119] In the semiconductor module according to the above embodiment, the recesses are also formed on the upper surface of the first joint portion and on the inner side surface of the first rising portion.

[0120] In the semiconductor module according to the above embodiment, the second rising portion has a through portion penetrating in a thickness direction, and the sealing resin is filled in the through portion.

[0121] In the semiconductor module according to the above embodiment, the through portion is formed by a hole or a notch.

[0122] Furthermore, in the semiconductor module according to the above embodiment, a second circuit board independent of the first circuit board is formed on the upper surface of the insulating plate, and the metal wiring board further has a second bonding portion bonded to the upper surface of the second circuit board via a bonding material, a third rising portion rising upward from one end of the second bonding portion, and a connecting portion connecting an upper end of the third rising portion to an upper end of the first rising portion.

[0123] Furthermore, in the semiconductor module according to the above embodiment, the semiconductor element has a temperature sensing portion arranged on its upper surface and a sense wiring electrically connected to the temperature sensing portion, the sense wiring extends from the temperature sensing portion on the upper surface of the semiconductor element toward the outer edge of the semiconductor element, and the sense wiring and the first rising portion and / or the second rising portion are arranged in a position where they overlap in a planar view.

[0124] Furthermore, in the semiconductor module according to the above embodiment, the semiconductor element has a temperature sensing portion arranged on its upper surface and a sense wiring electrically connected to the temperature sensing portion, the sense wiring extends from the temperature sensing portion on the upper surface of the semiconductor element toward the outer edge of the semiconductor element, and the sense wiring and the first rising portion and / or the second rising portion are arranged in positions that do not overlap in a planar view.

[0125] In addition, in the semiconductor module of the above embodiment, a boss protruding toward the semiconductor element is formed on the lower surface of the first joint, and another recess larger than the recess is formed on the upper surface of the first joint at a location directly above the boss.

[0126] A semiconductor device according to the above embodiment includes the above semiconductor module and a cooler disposed on the lower surface of the laminated substrate.

[0127] Furthermore, the vehicle according to the above embodiment includes the above semiconductor module or semiconductor device. [Industrial Applicability]

[0128] As described above, the present invention has the effect of improving the bonding strength between a semiconductor element and a metal wiring board while ensuring the thickness of the bonding material, and is particularly useful for industrial or electrical semiconductor modules, semiconductor devices, and vehicles.

[0129] This application is based on Japanese Patent Application No. 2021-210859, filed on December 24, 2021, the contents of which are incorporated herein in their entirety. [Explanation of symbols]

[0130] 1: Semiconductor module 2:Laminated substrate 3: Semiconductor elements 3a: Main electrode 3b: Control electrode (temperature sense electrode) 4:Metal wiring board 5: Sealing resin 10:Cooler 11: Case 20: Insulating plate 21: Heat sink 22: 1st circuit board 23: 2nd circuit board 30a: Temperature sensor section 30b: Sense wiring 40: 1st joint 40a: Boss 40b: Recess 40c: Recess 41:Second joint 41a: Boss 41b: recess 42:Connection part 43: First rising section 43a: Recess 43b: Penetration part 44: Second rising section 44a: Recess 44b: Penetration part 44c: Penetration part 45: Third rising section 46: Notch 60: Main terminal 61: Control terminal 64: Control terminal 100: Semiconductor device 101: Vehicle 102 :Wheel 103: Drive unit 104: Control device S: Bonding material

Claims

1. a laminated substrate having a first circuit board disposed on an upper surface of an insulating plate; a semiconductor device disposed on an upper surface of the first circuit board; a metal wiring board including a first bonding portion bonded to an upper surface of the semiconductor element via a bonding material; a sealing resin that seals the laminated substrate, the semiconductor element, and the metal wiring board; The first joint portion includes a plate-like portion having an upper surface and a lower surface, The metal wiring board is a first rising portion rising upward from one end of the first joint portion; A second rising portion rising upward from the other end of the first joint portion, The first rising portion constitutes a part of a wiring path through which a main current flows, the second rising portion constitutes a non-wiring path through which the main current does not flow, A semiconductor module, wherein a surface area of ​​the second raised portion is larger than a surface area of ​​the first raised portion.

2. The semiconductor module according to claim 1 , wherein the first raised portion and the second raised portion are disposed opposite each other.

3. The semiconductor module according to claim 1 , wherein an upper end of the second rising portion is located higher than an upper end of the first rising portion.

4. 4. The semiconductor module according to claim 1, wherein a width of the second rising portion is equal to or greater than a width of the first rising portion in a plan view.

5. 4. The semiconductor module according to claim 1, wherein the first rising portion and / or the second rising portion rises at a right angle to the first joint portion.

6. 3. The semiconductor module according to claim 1, wherein the second raised portion is inclined relative to the first joint portion, and an angle between the first joint portion and the second raised portion is smaller than an angle between the first joint portion and the first raised portion.

7. The semiconductor module according to claim 6 , wherein an upper end of the second rising portion is located lower than the first rising portion.

8. The semiconductor module according to claim 1 , wherein a plurality of recesses are formed on an inner surface of the second rising portion.

9. The semiconductor module according to claim 8 , wherein the recesses are also formed on an upper surface of the first joint portion and on an inner side surface of the first rising portion.

10. a laminated substrate having a first circuit board disposed on an upper surface of an insulating plate; a semiconductor device disposed on an upper surface of the first circuit board; a metal wiring board including a first bonding portion bonded to an upper surface of the semiconductor element via a bonding material; a sealing resin that seals the laminated substrate, the semiconductor element, and the metal wiring board; The first joint portion includes a plate-like portion having an upper surface and a lower surface, The metal wiring board is a first rising portion rising upward from one end of the first joint portion; A second rising portion rising upward from the other end of the first joint portion, The first rising portion constitutes a part of a wiring path through which a main current flows, the second rising portion constitutes a non-wiring path through which the main current does not flow, The second rising portion has a through-portion penetrating in a thickness direction, The sealing resin is filled in the through portion.

11. The semiconductor module according to claim 10 , wherein the through portion is formed by a hole or a notch.

12. a second circuit board independent of the first circuit board is formed on an upper surface of the insulating plate; The metal wiring board is a second bonding portion bonded to an upper surface of the second circuit board via a bonding material; a third rising portion rising upward from one end of the second joint portion; 4. The semiconductor module according to claim 1, further comprising a connecting portion connecting an upper end of the first rising portion and an upper end of the third rising portion.

13. a laminated substrate having a first circuit board disposed on an upper surface of an insulating plate; a semiconductor device disposed on an upper surface of the first circuit board; a metal wiring board including a first bonding portion bonded to an upper surface of the semiconductor element via a bonding material; a sealing resin that seals the laminated substrate, the semiconductor element, and the metal wiring board; The first joint portion includes a plate-like portion having an upper surface and a lower surface, The metal wiring board is a first rising portion rising upward from one end of the first joint portion; A second rising portion rising upward from the other end of the first joint portion, The first rising portion constitutes a part of a wiring path through which a main current flows, the second rising portion constitutes a non-wiring path through which the main current does not flow, The semiconductor device is A temperature sensor disposed on the upper surface; a sense wiring electrically connected to the temperature sensing unit, the sense wiring extends from the temperature sensing portion to an outer edge of the semiconductor element on a top surface of the semiconductor element, the sense wiring and the first rising portion or the second rising portion are provided at a position where they overlap in a plan view, A semiconductor module, wherein a surface area of ​​the second raised portion is larger than a surface area of ​​the first raised portion.

14. a laminated substrate having a first circuit board disposed on an upper surface of an insulating plate; a semiconductor device disposed on an upper surface of the first circuit board; a metal wiring board including a first bonding portion bonded to an upper surface of the semiconductor element via a bonding material; a sealing resin that seals the laminated substrate, the semiconductor element, and the metal wiring board; The first joint portion includes a plate-like portion having an upper surface and a lower surface, The metal wiring board is a first rising portion rising upward from one end of the first joint portion; A second rising portion rising upward from the other end of the first joint portion, The first rising portion constitutes a part of a wiring path through which a main current flows, the second rising portion constitutes a non-wiring path through which the main current does not flow, The semiconductor device is A temperature sensor disposed on the upper surface; a sense wiring electrically connected to the temperature sensing unit, the sense wiring extends from the temperature sensing portion to an outer edge of the semiconductor element on a top surface of the semiconductor element, the sense wiring and the first rising portion and / or the second rising portion are provided at positions where they do not overlap with each other in a plan view, A semiconductor module, wherein a surface area of ​​the second raised portion is larger than a surface area of ​​the first raised portion.

15. a boss protruding toward the semiconductor element is formed on a lower surface of the first joint portion; 9. The semiconductor module according to claim 8, wherein another recess larger than the recess is formed on the upper surface of the first joint portion at a location directly above the boss.

16. A semiconductor module according to any one of claims 1 to 3, a cooler disposed on a lower surface of the laminated substrate.

17. A vehicle comprising the semiconductor module according to any one of claims 1 to 3 or the semiconductor device according to claim 16.

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