Power component, semiconductor module and vehicle

Abstract

The invention discloses a power assembly, a semiconductor module and a vehicle, and belongs to the technical field of power semiconductors. The power assembly comprises a chip layer and a wiring layer, and a power chip is arranged in the chip layer; the wiring layer is provided with a control electrode and a conduction circuit; the wiring layer and the chip layer are sequentially stacked in the first direction, and the conduction circuit is connected between the power chip and the control electrode. By embedding the power chip into the semiconductor structure, the design space of an internal circuit of the semiconductor structure is large, the flexibility is high, on one hand, the optimization of the module performance is facilitated, on the other hand, the number of connecting terminals and binding wires can be reduced, an inverter, a charger and a DC / DC unit can be integrated, the size of the module is effectively reduced, and the power density is improved.

Description

Technical Field

[0001] This application belongs to the technical field of power semiconductors, and particularly relates to a power component, a semiconductor module, and a vehicle. Background Art

[0002] The high-voltage system of a vehicle mainly includes an inverter module, an OBC (On-Board Charger) module, and a DC / DC module. In related technologies, there are problems such as large volume and low power density in the layout of these three components. The power density of the high-voltage system still needs to be further improved. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems existing in the prior art. For this purpose, this application provides a power component, a semiconductor module, and a vehicle, in which the power chips of the inverter, the charger, and the DC / DC unit are embedded in a semiconductor structure, reducing the volume of the module and increasing the power density.

[0004] In a first aspect, this application provides a power component, which includes: A chip layer, in which power chips are provided. A wiring layer, which is provided with control electrodes and conduction lines. The wiring layer and the chip layer are stacked in a first direction, and the conduction lines are connected between the power chips and the control electrodes.

[0005] According to an embodiment of this application, control electrodes are provided on the surface of the wiring layer away from the chip layer, and conduction lines are provided inside the wiring layer.

[0006] According to an embodiment of this application, the chip layer includes: A frame layer, which is provided with a lead frame, and the power chips are connected to the lead frame.

[0007] According to an embodiment of this application, the power chips include multiple groups of chip sets, the number of lead frames is multiple, and each chip set is connected to each lead frame in a one-to-one correspondence.

[0008] According to an embodiment of this application, the frame layer includes: A laminate, which is provided with empty slots, the lead frames are arranged in the empty slots, and the laminate is made of an insulating material.

[0009] According to an embodiment of this application, the chip layer further includes a thermistor, the thermistor is connected to the lead frame and is arranged close to the power chips; On the surface of the wiring layer away from the chip layer, a detection electrode is further provided, and a detection line is further provided inside the wiring layer, and the detection line is connected between the thermistor and the detection electrode.

[0010] According to an embodiment of this application, the wiring layer includes: An insulating layer, the insulating layer and the chip layer are stacked in sequence in the first direction, and the insulating layer covers the power chip; The control electrode is disposed on the surface of the insulating layer away from the chip layer and is connected to the power chip through a conduction line.

[0011] According to an embodiment of the present application, the insulating layer is provided with a via hole in the first direction, and at least a part of the conduction line is disposed in the via hole.

[0012] According to an embodiment of the present application, the control electrode includes a power electrode, the conduction line includes a power connection layer, and the power connection layer is connected between the power electrode and the power chip.

[0013] According to an embodiment of the present application, the control electrode includes a power electrode, and the insulating layer includes: A first insulating layer, a power connection layer is provided on the surface of the first insulating layer away from the chip layer; A third insulating layer, the third insulating layer covers the power connection layer, and a power electrode is provided on the surface of the third insulating layer away from the first insulating layer.

[0014] According to an embodiment of the present application, the conduction line includes a power line, the first insulating layer and the third insulating layer are provided with via holes in the first direction, and the power line is disposed in the via holes.

[0015] According to an embodiment of the present application, the control electrode includes a signal electrode, the conduction line includes a signal connection layer, and the signal connection layer is connected between the signal electrode and the power chip.

[0016] According to an embodiment of the present application, the control electrode includes a signal electrode, and the insulating layer includes: A second insulating layer, a signal connection layer is provided on the surface of the second insulating layer away from the chip layer; A third insulating layer, the third insulating layer covers the signal connection layer, and the signal electrode is provided on the surface of the third insulating layer away from the second insulating layer.

[0017] According to an embodiment of the present application, the conduction line includes a signal line, the second insulating layer and the third insulating layer are provided with via holes in the first direction, and the signal line is disposed in the via holes.

[0018] According to an embodiment of the present application, the control electrode includes a signal electrode, the conduction line includes a signal connection layer, and the insulating layer includes: A second insulating layer, a signal connection layer is provided on the surface of the second insulating layer away from the chip layer, and the signal connection layer is connected between the power electrode and the power chip; The third insulating layer, the second insulating layer and the first insulating layer are stacked in sequence in the first direction.

[0019] According to an embodiment of the present application, the conduction line includes a power line and a signal line; The first insulating layer is provided with a via hole in the first direction, and the power line is disposed in the via hole; The second insulating layer is provided with a via hole in the first direction, and the signal line is disposed in the via hole.

[0020] According to an embodiment of the present application, the first insulating layer and / or the second insulating layer includes multiple layers.

[0021] According to an embodiment of the present application, the power component further includes: A substrate disposed on a side of the chip layer away from the wiring layer.

[0022] According to an embodiment of the present application, the power component further includes: A third insulating layer disposed between the chip layer and the substrate.

[0023] According to an embodiment of the present application, the substrate, the third insulating layer, the laminate, the chip layer, and the wiring layer are laminated and fused.

[0024] According to an embodiment of the present application, the substrate is an aluminum-based copper clad laminate, and the second insulating layer includes a prepreg material having adhesive properties.

[0025] According to an embodiment of the present application, the power chip includes an upper bridge chip and a lower bridge chip, the control electrode includes a first power electrode, the conduction line includes a first power connection layer and a first power line, and the first power connection layer is connected to the first power pin of the upper bridge chip, the first power pin of the lower bridge chip, and the first power electrode through the first power line.

[0026] According to an embodiment of the present application, the control electrode further includes a second power electrode, the conduction line further includes a second power connection layer and a second power line, the second power connection layer is arranged on the same layer as the first power connection layer and is insulated and isolated, and the second power connection layer is connected to the second power pin of the lower bridge chip and the second power electrode through the second power line.

[0027] According to an embodiment of the present application, the control electrode includes a third power electrode, the conduction line includes a third power line, and the third power line is connected between the second power pin of the upper bridge chip and the third power electrode.

[0028] According to an embodiment of the present application, the number of upper bridge chips and the number of lower bridge chips are both multiple, the first power pins of each upper bridge chip and the first power pins of each lower bridge chip are connected to the same first power connection layer, and the second power pins of each lower bridge chip are connected to the same second power connection layer.

[0029] According to an embodiment of the present application, the orthographic projection of each upper-bridge chip on the substrate is within the orthographic projection range of the first power connection layer on the substrate, and the orthographic projection of each lower-bridge chip on the substrate is within the orthographic projection range of the second power connection layer on the substrate.

[0030] According to an embodiment of the present application, the control electrode includes a first signal electrode and a second signal electrode, the conduction line includes a first signal connection layer, a second signal connection layer, a first signal line, and a second signal line. The first signal connection layer is connected to the signal pins and the first signal electrode of each upper-bridge chip through the first signal line, and the second signal connection layer is connected to the signal pins and the second signal electrode of each lower-bridge chip through the second signal line.

[0031] According to an embodiment of the present application, both the upper-bridge chip and the lower-bridge chip include a plurality of signal pins, the first signal connection layer and the second signal connection layer both include a plurality of sub-signal connection layers, and each sub-signal connection layer is connected to each signal pin of each upper-bridge chip or each lower-bridge chip.

[0032] According to an embodiment of the present application, the number of both the upper-bridge chips and the lower-bridge chips is multiple. The sub-signal connection layer includes a main connection line and a plurality of branch connection lines. The main connection line is connected to the signal electrode through the signal line. The first end of the branch connection line is perpendicularly connected to the main connection line, and the second end of the branch connection line is connected to the signal pin of the upper-bridge chip or the lower-bridge chip through the signal line, and the lengths of the branch connection lines are the same.

[0033] In a second aspect, the present application provides a semiconductor module, which includes a bottom plate and the power component as described above, and the power component is arranged on the bottom plate.

[0034] According to an embodiment of the present application, the power component includes at least one of a first power component, a second power component, and a third power component. The power chips in the first power component are used to construct an inverter, the power chips in the second power component are used to construct a charger, and the power chips in the third power component are used to construct a DC / DC unit.

[0035] According to an embodiment of the present application, the second power component and the third power component are integrally prepared.

[0036] According to an embodiment of the present application, each power component is welded to the first side of the bottom plate, and a heat dissipation structure is provided on the second side of the bottom plate opposite to the first side.

[0037] According to an embodiment of the present application, the multiple power components include at least two first power components. At least one first power component is used to construct the main drive inverter of the vehicle motor, and at least one first power component is used to construct the inverter of the vehicle-mounted compressor.

[0038] In a third aspect, the present application provides a vehicle, which includes the semiconductor module described above.

[0039] For the power component, semiconductor module and vehicle according to the present application, the power component can integrate an inverter, a charger and a DC / DC unit, embed the power chip into the semiconductor structure, and the design space of the internal circuit of the semiconductor structure is large and flexible. On the one hand, it is beneficial to optimize the module performance, and on the other hand, it can also reduce the connection terminals and bonding wires, effectively reduce the volume of the module, and improve the power density.

[0040] Some of the additional aspects and advantages of the present application will be given in the following description, some will become obvious from the following description, or will be understood through the practice of the present application. Description of the Drawings

[0041] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, where: Figure 1 is a cross-sectional schematic diagram of the power component provided by an embodiment of the present application; Figure 2 is an external structure schematic diagram of the main drive inverter power component provided by an embodiment of the present application; Figure 3 is a chip layout schematic diagram of the main drive inverter power component provided by an embodiment of the present application; Figure 4 is a wiring structure schematic diagram of the main drive inverter power component provided by an embodiment of the present application; Figure 5 is a simplified cross-sectional structure schematic diagram of the main drive inverter power component provided by an embodiment of the present application; Figure 6 is a wiring schematic diagram of the power connection layer of the main drive inverter power component provided by an embodiment of the present application; Figure 7 is one of the signal connection layer wiring schematic diagrams of the main drive inverter power component provided by an embodiment of the present application; Figure 8 is another signal connection layer wiring schematic diagram of the main drive inverter power component provided by an embodiment of the present application; Figure 9 is a surface electrode layer wiring schematic diagram of the main drive inverter power component provided by an embodiment of the present application; Figure 10 is an external structure schematic diagram of the on-vehicle charger and DC / DC power component provided by an embodiment of the present application; Figure 11 is a simplified cross-sectional structure schematic diagram of the on-vehicle charger and DC / DC power component provided by an embodiment of the present application; Figure 12It is a schematic external structure diagram of the in-vehicle compressor assembly provided by an embodiment of the present application; Figure 13 It is a simplified cross-sectional structure diagram of the in-vehicle compressor assembly provided by an embodiment of the present application; Figure 14 It is a schematic structure diagram of the semiconductor module provided by an embodiment of the present application. Detailed implementation manners

[0042] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the drawings. In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Wherever the same or similar reference numerals are used throughout, they denote the same or similar elements or elements having the same or similar functions. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation of the present application.

[0043] It should be understood that when an element or layer is referred to as "on...", "adjacent to...", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on...", "directly adjacent to...", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part. And when discussing the second element, component, region, layer or part, it does not necessarily mean that there is a first element, component, region, layer or part in the present disclosure.

[0044] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0045] In related technologies, the integration of in-vehicle power modules mostly involves simply arranging the inverter circuit components, in-vehicle charger circuit components, and DC / DC circuit components in a planar manner and then encapsulating them as a whole in the same packaging shell, but this still occupies a relatively large space. In addition, the in-vehicle compressor inverter is not integrated, leaving room for further improvement in power density.

[0046] This application proposes a power component, a semiconductor module, and a vehicle. The power component integrates an inverter, a charger, and a DC / DC unit. The power chips are embedded in the semiconductor structure. The internal wiring design space of the semiconductor structure is large and flexible. On the one hand, it is beneficial to optimize the module performance. By adjusting the connection method and shape area of the circuit, the switching delay of the chipset can be reduced, and the overcurrent capacity of the module can be improved. On the other hand, the connection terminals and bonding wires can be reduced, effectively reducing the volume of the module and increasing the power density. In addition, the in-vehicle compressor inverter can also be integrated, with a small volume change, further increasing the power density.

[0047] Referring to Figure 1 , Figure 1 FIG. shows a cross-sectional structure of a power component. An embodiment of this application proposes a power component. In this embodiment, the power component includes a chip layer 110 and a wiring layer 120. The chip layer 110 is provided with power chips 111. The wiring layer 120 is provided with control electrodes 130 and conduction lines 140. The wiring layer 120 and the chip layer 110 are stacked in sequence in the first direction, and the conduction lines 140 are connected between the power chips 111 and the control electrodes 130.

[0048] As shown in Figure 1 , the first direction is the X direction, that is, the direction from top to bottom. The wiring layer 120 and the chip layer 110 are stacked up and down. The conduction lines 140 and the control electrodes 130 in the wiring layer 120 realize the signal input and power input / output of the power chips 111.

[0049] As an example, the control electrodes 130 may include power electrodes and signal electrodes. The conduction lines 140 include power lines and signal lines. The power lines are connected between the power pins of the power chips and the power electrodes, and the signal lines are connected between the signal pins of the power chips and the signal electrodes.

[0050] The power chip can be an Insulated Gate Bipolar Transistor (IGBT) or a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Taking the power chip as a MOSFET as an example, its power pins are the source and drain, and the signal pin is the gate. Some MOSFETs also have a Kelvin source, which can also be used as a signal pin.

[0051] At least one power chip is encapsulated in the power component, and the specific number can be determined according to the circuit topology to be constructed. For example, the power component can be encapsulated with an inverter circuit, which can be a half-bridge or a full-bridge. Each arm of the bridge can include one, four, or eight power chips. The power component can also be encapsulated with a three-phase full-bridge inverter circuit, which includes three inverter circuits. An insulation isolation can be provided around the power chip in the chip layer 110 to play a protective role.

[0052] In some embodiments, the control electrode 130 is disposed on the surface of the wiring layer 120 away from the chip layer 110, and the conduction line 140 is disposed in the wiring layer 120.

[0053] The power line and the signal line are used to construct the power loop and the signal loop of the power chip. By connecting to the power electrode and the signal electrode on the surface, the power input / output and the signal input / output of the power component are realized. Among them, when there are multiple power chips in the power component, the power line can also be connected between the power pins of each power chip to achieve power distribution, and the signal line can also be connected between the signal pins of each power chip to achieve signal distribution.

[0054] The specific paths of the power loop and the signal loop can be determined according to the circuit topology to be constructed. For example, the power component can be encapsulated with a half-bridge or a full-bridge inverter circuit, and the power loop and the signal loop need to be realized according to the power connection relationship and the signal connection relationship of each arm in the half-bridge or the full-bridge.

[0055] As an example, the source of the MOSFET in the upper arm is connected to the source of the MOSFET in the lower arm through the power loop, and the drain of the MOSFET in the upper arm is connected to the drain of the MOSFET in the lower arm through the power loop to the power electrode. When there are multiple MOSFETs in one arm, the gates of the multiple MOSFETs in this arm can be connected to each other through the signal loop and connected to the signal electrode.

[0056] In some embodiments, the wiring layer 120 includes an insulating layer, which is stacked with the chip layer 110 in a first direction in sequence, and the insulating layer covers the power chip 111; the control electrode 130 is disposed on the surface of the insulating layer away from the chip layer 110 and is connected to the power chip 111 through a conduction line 140.

[0057] By covering the power chip 111, the insulating layer can play an isolation and protection role for the power chip 111. The conduction line 140 can pass through or bypass the insulating layer to be connected between the control electrodes 130, realizing the input and output of signals and power.

[0058] In some embodiments, the insulating layer is provided with vias in the first direction, and at least part of the conduction line 140 is disposed in the vias.

[0059] Part of the conduction line 140 can extend in the via to both sides of the insulating layer to penetrate the insulating layer to achieve connection on both sides. Directly penetrating the insulating layer for connection can shorten the line length and simplify the line. The control electrode 130 can be located above the insulating layer, and the power chip 111 is located below the insulating layer. Part of the conduction line 140 passes through the via to be connected between the control electrode 130 and the power chip 111.

[0060] In some embodiments, the control electrode 130 includes a power electrode, and the conduction line 140 includes a power connection layer, and the power connection layer is connected between the power electrode and the power chip 111.

[0061] The power electrode is used for the power input and output of the power chip 111. If the power chip 111 is a MOS transistor, the power electrode can be used as the source and drain. The power connection layer can be used to collect the power of multiple power chips 111 to make the power distribution uniform among the power chips 111.

[0062] In some embodiments, the control electrode 130 includes a power electrode, the insulating layer includes a first insulating layer and a third insulating layer, a power connection layer is provided on the surface of the first insulating layer away from the chip layer, the third insulating layer covers the power connection layer, and a power electrode is provided on the surface of the third insulating layer away from the first insulating layer.

[0063] The first insulating layer is used to isolate the power connection layer and the power chip 111, playing a protective role. The third insulating layer is used to isolate the power connection layer and the power electrode, playing a protective role.

[0064] In some embodiments, the conduction line 140 includes a power line, the first insulating layer and the third insulating layer are provided with vias in the first direction, and the power line is disposed in the vias.

[0065] The power line is used to achieve power connection in the first direction. The power line extends within the vias of the first insulating layer to connect the power chip 111 and the power connection layer on both sides of the first insulating layer. By directly passing through the first insulating layer for connection, the length of the power line can be shortened and the circuit can be simplified.

[0066] In some embodiments, the control electrode 130 includes a signal electrode, and the conduction line 140 includes a signal connection layer, and the signal connection layer is connected between the signal electrode and the power chip 111.

[0067] The signal electrode is used for signal input of the power chip 111 to achieve control of the power chip 111. If the power chip 111 is a MOS transistor, the signal electrode can be used as the gate. The signal connection layer can be used to collect the signals of multiple power chips 111 to synchronize the signals between the power chips 111.

[0068] In some embodiments, the control electrode 130 includes a signal electrode, the insulating layer includes a second insulating layer and a third insulating layer, a signal connection layer is provided on the surface of the second insulating layer away from the chip layer, the third insulating layer covers the signal connection layer, and a signal electrode is provided on the surface of the third insulating layer away from the second insulating layer.

[0069] The first insulating layer is used to isolate the signal connection layer and the power chip 111, playing a protective role. The third insulating layer is used to isolate the signal connection layer and the signal electrode, playing a protective role.

[0070] In some embodiments, the conduction line 140 includes a signal line, the second insulating layer and the third insulating layer are provided with vias in the first direction, and the signal line is also provided in the vias.

[0071] The signal line is used to achieve signal connection in the first direction. The signal line extends within the vias of the second insulating layer to connect the power chip 111 and the signal connection layer on both sides of the second insulating layer. By directly passing through the second insulating layer for connection, the length of the signal line can be shortened and the circuit can be simplified.

[0072] In some embodiments, the control electrode 130 includes a power electrode and a signal electrode, the conduction line 140 includes a power connection layer and a signal connection layer, the insulating layer includes a first insulating layer and a second insulating layer, a power connection layer is provided on the surface of the first insulating layer away from the chip layer, the power connection layer is connected between the power electrode and the power chip 111, a signal connection layer is provided on the surface of the second insulating layer away from the chip layer, the signal connection layer is connected between the power electrode and the power chip 111, and the third insulating layer, the second insulating layer and the first insulating layer are stacked in sequence in the first direction.

[0073] The power chip 111 is a MOS transistor. The power electrodes can serve as the source and drain, and the signal electrode can serve as the gate. The power connection layer can be used to aggregate the power of multiple power chips 111, and the signal connection layer can be used to aggregate the signals of multiple power chips 111, thereby enabling uniform power distribution and signal synchronization among the power chips 111.

[0074] In some embodiments, the conduction line 140 includes a signal line and a power line. The first insulating layer is provided with vias in the first direction, and the power line is disposed in the vias; the second insulating layer is provided with vias in the first direction, and the signal line is disposed in the vias.

[0075] The power line is used to achieve power connection in the first direction, and the power line extends in the vias of the first insulating layer. The signal line is used to achieve signal connection in the first direction, and the signal line extends in the vias of the second insulating layer. By directly passing through the first insulating layer and the second insulating layer for connection, the lengths of the power line and the signal line can be shortened, and the circuit can be simplified.

[0076] In the above embodiments, the first insulating layer and / or the second insulating layer includes multiple layers.

[0077] Arranging multiple layers of the first insulating layer and / or the second insulating layer can improve the isolation effect, and at the same time can also adapt to the design of different conduction lines 140. For example, the power connection layer and the signal connection layer can also be arranged in multiple layers, and the first insulating layer or the second insulating layer can be provided between adjacent two-layer connection layers (power connection layer or signal connection layer).

[0078] In some embodiments, the power component further includes a substrate, and the substrate is disposed on the side of the chip layer 110 away from the wiring layer 120.

[0079] The substrate such as Figure 1 the first substrate 1 in is used to carry the power component, facilitating the preparation and installation of the power component.

[0080] In some embodiments, the power component further includes a third insulating layer, and the third insulating layer is disposed between the chip layer 110 and the substrate.

[0081] An insulating layer can also be provided between the first substrate 1 and the chip layer 110. The third insulating layer can provide secondary isolation and protection for the chip layer 110. In addition, the third insulating layer can also improve the connection reliability between the chip layer 110 and the first substrate 1.

[0082] In this embodiment, different circuit topologies can be formed by configuring power chips, power circuits, and signal circuits in the power component, thereby constructing different devices. For example, a power component with a three-phase full-bridge inverter circuit topology can be used as an inverter, or a power component with a DC / DC circuit topology can be used as a DC / DC unit. Or during application, different devices can be constructed by connecting to external devices to achieve corresponding functions. For example, multiple AC-DC conversion circuits are formed inside the power component. When the power electrodes are connected to the primary and secondary sides of an external transformer, it can be used as a charger, or when connected to the primary and secondary sides of an external transformer, it can also be used as an isolated DC / DC unit.

[0083] Referring to Figure 2 , Figure 2 FIG. shows the external structure of a main drive inverter power component 100. The main electrodes are led out from the upper surface of the main drive inverter power component 100. The power electrodes include a high-voltage DC positive electrode 101, a high-voltage DC negative electrode 102, and a high-voltage AC electrode 103. The signal electrodes include a first control electrode 104 and a second control electrode 105.

[0084] A three-phase full-bridge inverter circuit is formed inside the main drive inverter power component 100, and the power chips corresponding to each phase bridge arm are arranged along the length direction. The high-voltage DC positive electrode 101 and the high-voltage DC negative electrode 102 are arranged close to one long side, the high-voltage AC electrode 103 is arranged close to the other long side, and the first control electrode 104 and the second control electrode 105 are located at the middle positions between the two long sides. The DC electrodes and the AC electrodes are separated as much as possible to reduce coupling interference and improve electromagnetic compatibility.

[0085] Referring to Figure 3 , Figure 4 and Figure 5 , Figure 3 FIG. shows the chip layout of a main drive inverter power component 100, Figure 4 FIG. shows the wiring structure of a main drive inverter power component 100, Figure 5 FIG. shows the simplified cross-sectional structure of a main drive inverter power component 100. In some embodiments, the chip layer includes a frame layer 3 and an insulating layer 5. The frame layer 3 is provided with a lead frame, and the power chip is connected to the side of the lead frame away from the first substrate 1; the insulating layer 5 is provided on the side of the frame layer 3 away from the first substrate 1 and covers the power chip.

[0086] As an example, the power chips in the main drive inverter power module 100 are configured into a full-bridge inverter circuit. Each arm of the bridge includes eight power chips. As a chip group 4, it can be connected to the lead frame through silver sintering. The lead frame is used to support the power chips, achieve electrical connection and provide a heat dissipation path. It is surrounded by an insulating material to achieve isolation. The thickness of the insulating material can be the same as that of the lead frame to keep the upper surface flush.

[0087] In some embodiments, the power chips include multiple groups of chip groups 4, and the number of lead frames is multiple. Each chip group is connected to each lead frame in a one-to-one correspondence.

[0088] The lead frame can be used to extend the pins of the power chips. The power loop and / or signal loop can be connected to the power chips through the lead frame. Thus, the power chips connected by one lead frame are preferably configured to have the same function. For example, the power chips in the main drive inverter power module 100 are divided into multiple chip groups 4 according to the arms where they are located, and each arm is connected by a separate lead frame.

[0089] In some embodiments, the chip layer 110 further includes a thermistor 34. The thermistor 34 is connected to the lead frame and is arranged close to the power chips. On the surface of the wiring layer 120 away from the chip layer 110, a detection electrode is further provided. A detection line is also provided in the wiring layer 120, and the detection line is connected between the thermistor 34 and the detection electrode.

[0090] The thermistor 34 and the lead frame can be connected by a thermally conductive insulating adhesive to detect the junction temperature of the power chips. The detection electrode is used to connect to the control unit, and the detection signal of the thermistor 34 is led out through the detection line and transmitted to the control unit through the detection electrode.

[0091] In some embodiments, the frame layer 3 includes a first laminate 31. The first laminate 31 is provided with an empty slot, and the lead frame is arranged in the empty slot. The frame layer 3 and the upper and lower layers can be fused into a whole through three-layer pressing, so that the preparation process is simple.

[0092] As Figure 4 shown, the wiring layer 120 includes a first connection layer 7, a second connection layer 10, and a third connection layer 13. Between each connection layer, the power chips, and the electrode layer, they are isolated by an insulating layer 8, an insulating layer 11, and an insulating layer 14. Through holes are provided in the insulating layer and filled with a conductive material to form a first via layer 6, a second via layer 9, a third via layer 12, and a fourth via layer 15. Among them, the conductive material in each connection layer and via can be copper or silver, etc. The following will be described in detail in combination with Figure 5 for a detailed description.

[0093] Taking a half-bridge module as an example, the first layer of pressing plate 31 is provided with two empty slots in the area corresponding to the half-bridge module, and a first lead frame 32 and a second lead frame 33 are respectively embedded therein. The thicknesses of the two lead frames are the same as that of the first layer of pressing plate 31. The chipset 4 includes two groups, one group is the first upper-bridge chip 41, and the other group is the first lower-bridge chip 42. The first upper-bridge chip 41 is connected to the first lead frame 32, and the first lower-bridge chip 42 is connected to the second lead frame 33. The sides of the first upper-bridge chip 41 and the first lower-bridge chip 42 away from the lead frames are covered by an insulating layer 5 to achieve insulation and protection.

[0094] In some embodiments, an insulating layer 2 is provided between the first substrate 1 and the first layer of pressing plate 31, and the first substrate 1, the insulating layer 2, the first layer of pressing plate 31, the power chips and the insulating layer 5 are fused together after lamination. By laminating on one side, the substrate and chip layer 110 are fused into a whole, so that the preparation process is simple.

[0095] In some embodiments, the first substrate 1 is an aluminum-based copper clad laminate, and the insulating layer 2 includes a prepreg material with bonding properties. Using an aluminum plate for the first substrate 1 is not prone to cracking during lamination, and the quality is more reliable. The prepreg material can be, for example, FR4 (Flame Retardant Type 4) or BT (Bismaleimide-Triazine). The thicknesses of the first substrate 1 and the insulating layer 2 can be adjusted according to actual application and preparation process requirements.

[0096] In some embodiments, the power electrode includes a first power electrode, and the power line includes a first power connection layer 71 and a first power line. The first power connection layer 71 is connected to the first power pin of the first upper-bridge chip 41, the first power pin of the first lower-bridge chip 42 and the first power electrode through the first power line respectively.

[0097] The first connection layer 7 is used to achieve power connection, and it includes a first power connection layer 71. The first via layer 6 includes a first via 61 and a second via 62, and the fourth via layer 15 includes a tenth via 153. Connection lines are provided in the first via 61, the second via 62 and the tenth via 153 to form a first power line to achieve the power connection of the first power connection layer 71.

[0098] As an example, the first power pin can be the source electrode, and the first power electrode can be the high-voltage AC electrode 103. The first power connection layer 71 is connected to the source electrode of the first upper-bridge chip 41 through the first via 61, the first power connection layer 71 is connected to the source electrode of the first lower-bridge chip 42 through the second via 62, and the first power connection layer 71 is connected to the high-voltage AC electrode 103 through the tenth via 153 to conduct the main current.

[0099] When the first lower bridge chip 42 is connected to the lead frame, the first power connection layer 71 is connected to the lead frame through the second via 62 to achieve the source connection with the first lower bridge chip 42. Of course, the first power connection layer 71 can also be connected to the lead frame through the first via 61 to achieve the source connection with the first upper bridge chip 41.

[0100] It can be understood that when the number of the first upper bridge chips 41 and the number of the first lower bridge chips 42 are both multiple, the first power pins of each first upper bridge chip 41 and the first power pins of each first lower bridge chip 42 are connected to the same first power connection layer 71. In addition to realizing the power connection between the sources of the first upper bridge chips 41 and the sources of the first lower bridge chips 42, the first power connection layer 71 can also realize the power connection between the sources of each first upper bridge chip 41 and between the sources of each first lower bridge chip 42, so as to collect the currents of these pins in the first power connection layer 71 and then lead them out to the high-voltage AC electrode 103.

[0101] In some embodiments, the power electrode further includes a second power electrode, and the power line further includes a second power connection layer 72 and a second power line. The second power connection layer 72 is arranged on the same layer as the first power connection layer 71 and is insulated and isolated. The second power connection layer 72 is connected to the second power pins and the second power electrode of the first lower bridge chip 42 through the second power line respectively.

[0102] The first connection layer 7 further includes a second power connection layer 72, the first via layer 6 further includes a third via 63, and the fourth via layer 15 includes a ninth via 152. Connection lines are provided in the third via 63 and the ninth via 152 to form a second power line to achieve the power connection of the second power connection layer 72. The second power pin can be a drain, and the second power electrode can be the high-voltage DC negative electrode 102. The second power connection layer 72 is connected to the drain of the first lower bridge chip 42 through the third via 63 and is connected to the high-voltage DC negative electrode 102 through the ninth via 152.

[0103] When the number of the first lower bridge chips 42 is multiple, the second power pins of each first lower bridge chip 42 are connected to the same second power connection layer 72. The second power connection layer 72 can realize the power connection between the drains of each first lower bridge chip 42, so as to collect the currents of these pins in the second power connection layer 72 and then lead them out to the high-voltage DC negative electrode 102.

[0104] In some embodiments, the power electrode further includes a third power electrode, and the power line includes a third power line, and the third power line is connected between the second power pin of the first upper bridge chip 41 and the third power electrode.

[0105] The fourth via layer 15 further includes an eighth via 151, inside which a connection line is provided to form a third power line, realizing the power connection of the first upper bridge chip 41. The second power pin may be a drain, and the third power electrode is the high-voltage DC positive electrode 101. The drain of the first upper bridge chip 41 is connected to the high-voltage DC positive electrode 101 through the eighth via 151. In summary, the power lines are exemplarily arranged to lead out the power pins of the power chips to the power electrodes.

[0106] In some embodiments, the orthographic projection of each first upper bridge chip 41 on the first substrate 1 is within the orthographic projection range of the first power connection layer 71 on the first substrate 1, and the orthographic projection of each first lower bridge chip 42 on the first substrate 1 is within the orthographic projection range of the second power connection layer 72 on the first substrate 1.

[0107] Refer to Figure 6 , Figure 6 shows a wiring structure of the power connection layer of a main drive inverter power module 100. As Figure 6 shown, the first power connection layer 71 and the second power connection layer 72 may adopt a large-area copper layer structure, which is beneficial to increasing the cross-sectional area of overcurrent, improving the overcurrent capacity of the module, and reducing the stray inductance.

[0108] It should be noted that since the first power connection layer 71 and the second power connection layer 72 respectively cover the first upper bridge chip 41 and the first lower bridge chip 42, in order to facilitate the arrangement of the remaining power lines and signal lines, the first power connection layer 71 and the second power connection layer 72 may respectively expose some pins (such as the drain and gate) of the first upper bridge chip 41 and the first lower bridge chip 42.

[0109] In some embodiments, the signal electrodes include a first signal electrode and a second signal electrode, the signal lines include a first signal connection layer, a second signal connection layer, a first signal line, and a second signal line. The first signal connection layer is connected to the signal pins and the first signal electrode of each first upper bridge chip 41 through the first signal line, and the second signal connection layer is connected to the signal pins and the second signal electrode of each first lower bridge chip 42 through the second signal line.

[0110] When the number of the first upper bridge chips 41 and the number of the first lower bridge chips 42 are both multiple, the signals of the signal pins of each first upper bridge chip 41 converge on the first signal connection layer, and the signals of the signal pins of each first lower bridge chip 42 converge on the second signal connection layer to achieve common control. Among them, the signal pins of the power chips may be gates.

[0111] In some embodiments, both the first upper-bridge chip 41 and the first lower-bridge chip 42 include a plurality of signal pins. Both the first signal connection layer and the second signal connection layer include a plurality of sub-signal connection layers, and each sub-signal connection layer is connected to each signal pin of each first upper-bridge chip 41 or each first lower-bridge chip 42.

[0112] As an example, the signal pins of the first upper-bridge chip 41 and the first lower-bridge chip 42 both include a gate and a Kelvin source. Since the signals of different signal pins need to be isolated, both the first signal connection layer and the second signal connection layer include two sub-signal connection layers.

[0113] Continuing to refer to Figure 5 , both the second connection layer 10 and the third connection layer 13 are used for arranging signal lines. The second connection layer 10 is used to connect the gates of the power chips and includes a first sub-signal connection layer 107 and a second sub-signal connection layer 108. The third connection layer 13 is used to connect the Kelvin sources of the power chips and includes a third sub-signal connection layer 131 and a fourth sub-signal connection layer 132. The first sub-signal connection layer 107 and the third sub-signal connection layer 131 serve as the first signal connection layer for leading out the signal pins of the first upper-bridge chip 41, and the second sub-signal connection layer 108 and the fourth sub-signal connection layer 132 serve as the second signal connection layer for leading out the signal pins of the first lower-bridge chip 42.

[0114] The second via layer 9 includes a fourth via 91 and a fifth via 92. The lower surface of the second connection layer 10 is connected to the upper surface of the insulating layer 8. The gate in the first upper-bridge chip 41 is electrically connected to the first sub-signal connection layer 107 through the fourth via 91, and the gate in the first lower-bridge chip 42 is electrically connected to the second sub-signal connection layer 108 through the fifth via 92. The third via layer 12 includes a sixth via 121 and a seventh via 122. The lower surface of the third connection layer 13 is in contact with the upper surface of the insulating layer 11. The Kelvin source in the first upper-bridge chip 41 is electrically connected to the third sub-signal connection layer 131 through the sixth via 121, and the Kelvin source in the first lower-bridge chip 42 is electrically connected to the fourth sub-signal connection layer 132 through the seventh via 122.

[0115] Referring to Figure 7 and Figure 8 , Figure 7 shows one of the signal connection layer wirings of a main drive inverter power module 100, Figure 8 shows another signal connection layer wiring of a main drive inverter power module 100. It should be noted that Figure 5 To more clearly show the relationship between the lines in the power module between the upper and lower layers, the actual positions are simplified. The specific shapes of the second connection layer 10 and the third connection layer 13 are as shown in combination with Figure 7 and Figure 8 .

[0116] In some embodiments, the sub-signal connection layer includes a main connection line and a plurality of branch connection lines. The main connection line is connected to the signal electrode through a connection hole. The first end of the branch connection line is perpendicularly connected to the main connection line, and the second end of the branch connection line is connected to the signal pin of the upper bridge chip or the lower bridge chip through a connection hole. The lengths of the branch connection lines are the same.

[0117] From Figure 7 and Figure 8 it can be seen that the main connection line is used to collect signals, and the branch connection lines are connected to each power chip to achieve specific signal distribution. The branch connection lines are perpendicularly connected to the main connection line, which can shorten the length of the branch connection lines; and since the lengths of the branch connection lines are the same, it is possible to make the current paths to each chip as short and the same as possible, which is beneficial to reducing the switching delay of the chip group.

[0118] In some embodiments, in the stacking direction of the power component, the portions of the sub-signal connection layers corresponding to the first upper bridge chip 41 or the first lower bridge chip 42 partially overlap and are arranged parallel to each other.

[0119] From Figure 7 and Figure 8 it can be seen that the middle portions of the first sub-signal connection layer 107 and the third sub-signal connection layer 131 overlap, and the middle portions of the second sub-signal connection layer 108 and the fourth sub-signal connection layer 132 overlap. Due to the effect of partial overlap and being parallel to each other, signal interference and stray inductance can be reduced.

[0120] Continuing to refer to Figure 5 , the fourth via layer 15 is mainly used to connect the internal lines of the power component to the electrodes on the surface. The power electrodes are as described above. The signal electrodes include a first control electrode 104, a second control electrode 105, and a detection electrode 106. The first control electrode 104 includes a first control source electrode 104a and a first control gate electrode 104b. The second control electrode includes a second control source electrode 105a and a second control gate electrode 105b. The detection electrode 106 of the thermistor includes a detection resistor positive electrode 106a and a detection resistor negative electrode 106b. The fourth via layer 15 further includes an eleventh via 154a, a twelfth via 154b, a thirteenth via 155a, a fourteenth via 155b, a fifteenth via 156a, and a sixteenth via 156b. Among them, connection lines are provided in the fourth via 91, the sixth via 121, the eleventh via 154a, and the twelfth via 154b to form a first signal line to realize the signal connection of the first upper bridge chip 41. Connection lines are provided in the fifth via 92, the seventh via 122, the thirteenth via 155a, and the fourteenth via 155b to form a second signal line to realize the signal connection of the first lower bridge chip 42.

[0121] Referring to Figure 9 , Figure 9Shows the surface electrode layer wiring of a main drive inverter power component 100. The lower surface of each electrode contacts the upper surface of the insulating layer 14. The high-voltage DC positive electrode 101 is electrically connected to the first lead frame 32 through the eighth hole 151, the high-voltage DC negative electrode 102 is electrically connected to the second power connection layer 72 through the ninth hole 152, the high-voltage AC electrode 103 is electrically connected to the first power connection layer 71 through the tenth hole 153, the first control source electrode 104a is electrically connected to the third sub-signal connection layer 131 through the eleventh hole 154a, the first control gate electrode 104b is electrically connected to the first sub-signal connection layer 107 through the twelfth hole 154b, the second control source electrode 105a is electrically connected to the fourth sub-signal connection layer 132 through the thirteenth hole 155a, and the second control gate electrode 105b is electrically connected to the second sub-signal connection layer 108 through the fourteenth hole 155b. The positive electrode 106a of the detection resistor is connected to the positive electrode of the thermistor through the fifteenth hole 156a, and the negative electrode 106b of the detection resistor is connected to the negative electrode of the thermistor through the sixteenth hole 156b.

[0122] Refer to Figure 10 , Figure 10 Shows the external structure of a vehicle-mounted charger and a DC / DC power component 200. In some embodiments, the power chips in the second power component construct a power factor correction unit, a resonant primary unit 201, and a resonant secondary unit 203, and the power chips in the third power component construct a DC primary unit 204 and a DC secondary unit 205; in the first direction, the resonant secondary unit 203 is located on the first side of the DC secondary unit 205, the resonant primary unit 201 is located on the side of the resonant secondary unit 203 away from the DC secondary unit 205, the DC primary unit 204 is located on the first side of the DC secondary unit 205, and the power factor correction unit is located on the side of the DC primary unit 204 away from the DC secondary unit 205; in the second direction, the DC primary unit 204 is located on the second side of the resonant secondary unit 203, the power factor correction unit is located on the second side of the resonant primary unit 201, and the first direction is perpendicular to the second direction.

[0123] The power factor correction unit may include a PFC fast tube 206 and a PFC slow tube 202, and a first signal low-voltage electrode 207 and a first high-voltage electrode 208 may be provided on the surface of the power component.

[0124] Refer to Figure 11 , Figure 11Shows a simplified cross-sectional structure of an on-vehicle charger and a DC / DC power component 200. The second laminate 211 has a plurality of empty slots, and the third lead frame 215 is embedded in the plurality of empty slots of the second laminate 211. The thickness of the third lead frame 215 is the same as the thickness of the second laminate 211. The second laminate 211 and the third lead frame 215 are connected to the second substrate 209 through the sixth insulating layer 210. The second substrate 209 can be an aluminum-based copper clad laminate, and the sixth insulating layer 210 includes a prepreg material with bonding properties. The second substrate 209 made of an aluminum plate is not prone to cracks during lamination, and the quality is more reliable. The prepreg material can be, for example, FR4 or BT. The thicknesses of the second substrate 209 and the sixth insulating layer 210 can be adjusted according to actual application and manufacturing process requirements. The third lead frame 215 is provided with a second upper bridge chip 217 and a second lower bridge chip 219, and a seventh insulating layer 212 is provided above the chips. The second substrate 209, the sixth insulating layer 210, the second upper bridge chip 217, the second lower bridge chip 219, and the seventh insulating layer 212 are fused into an integral body through one-time lamination. In this way, the manufacturing process is simple, the aluminum plate is not prone to cracks during lamination, and the quality is more reliable.

[0125] The surface of the on-vehicle charger and the DC / DC power component 200 is provided with power electrodes and signal electrodes, forming a first electrode layer 225. The drain of the second upper bridge chip 217 passes through the seventh insulating layer 212 and the eighth insulating layer 213 through the seventeenth hole 223 and is connected to the power electrode of the first electrode layer 225. The source is connected to the third power connection layer 224 through the eighteenth hole 220 passing through the seventh insulating layer 212, and is connected to the drain of the second lower bridge chip 219 and the power electrode of the first electrode layer 225 through the nineteenth hole 218 and the twentieth hole 227 respectively by passing through the seventh insulating layer 212 and the eighth insulating layer 213. The gate and the Kelvin source of the second upper bridge chip 217 are respectively connected to the signal electrodes of the first electrode layer 225 through the twenty-first hole 221 and the twenty-second hole 222 by passing through the seventh insulating layer 212 and the eighth insulating layer 213. The source of the second lower bridge chip 219 passes through the seventh insulating layer 212 and the eighth insulating layer 213 through the twenty-third hole 226 and is connected to the power electrode of the first electrode layer 225. The gate and the Kelvin source of the second lower bridge chip 219 are respectively connected to the signal electrodes of the first electrode layer 225 through the twenty-fourth hole 214 and the twenty-fifth hole 216 by passing through the seventh insulating layer 212 and the eighth insulating layer 213.

[0126] Referring to Figure 12 and Figure 13 , Figure 12 shows an external structure of an on-vehicle compressor assembly 300. Figure 13A simplified cross-sectional structure of a vehicle-mounted compressor assembly 300 is shown. A second high-voltage electrode 301 and a second signal low-voltage electrode 302 are provided on the surface of the vehicle-mounted compressor assembly 300. The third laminate 305 has a plurality of empty slots, and the fourth lead frame 309 is embedded in the plurality of empty slots of the third laminate 305. The thickness of the fourth lead frame 309 is the same as that of the third laminate 305. The third laminate 305 and the fourth lead frame 309 are connected to the third substrate 303 through the ninth insulating layer 304. The third substrate 303 can be an aluminum-based copper-clad laminate, and the ninth insulating layer 304 includes a prepreg material with adhesive properties. The third substrate 303 is made of an aluminum plate and is not prone to cracks during lamination, and the quality is more reliable. The prepreg material can be, for example, FR4 or BT. The thicknesses of the third substrate 303 and the ninth insulating layer 304 can be adjusted according to actual application and manufacturing process requirements. A third upper-bridge chip 313 and a third lower-bridge chip 311 are provided on the fourth lead frame 309, and a tenth insulating layer 306 is provided above the chips. The third substrate 303, the ninth insulating layer 304, the third upper-bridge chip 313, the third lower-bridge chip 311, and the tenth insulating layer 306 are fused into an integral body through one-time lamination. In this way, the manufacturing process is simple, the aluminum plate is not prone to cracks during lamination, and the quality is more reliable.

[0127] The second high-voltage electrode 301 and the second signal low-voltage electrode 302 on the surface of the vehicle-mounted compressor assembly 300 can serve as the second electrode layer 319, where the second high-voltage electrode 301 is a power electrode and the second signal low-voltage electrode 302 is a signal electrode. The drain of the third upper-bridge chip 313 passes through the tenth insulating layer 306 and the eleventh insulating layer 307 through the twenty-sixth hole 317 and is electrically connected to the power electrode of the second electrode layer 319. The source passes through the tenth insulating layer 306 through the twenty-seventh hole 314 and is connected to the fourth power connection layer 318, and is connected to the drain of the third lower-bridge chip 311 and the power electrode of the second electrode layer 319 through the twenty-eighth hole 312 and the twenty-ninth hole 321 respectively through the tenth insulating layer 306 and the eleventh insulating layer 307. The gate and the Kelvin source of the third upper-bridge chip 313 pass through the tenth insulating layer 306 and the eleventh insulating layer 307 through the thirtieth hole 315 and the thirty-first hole 316 and are electrically connected to the signal electrode of the second electrode layer 319. The source of the third lower-bridge chip 311 passes through the tenth insulating layer 306 and the eleventh insulating layer 307 through the thirty-second hole 320 and is electrically connected to the second electrode layer 319. The gate and the Kelvin source of the third lower-bridge chip 311 pass through the tenth insulating layer 306 and the eleventh insulating layer 307 through the thirty-third hole 308 and the thirty-fourth hole 310 and are electrically connected to the signal electrode of the second electrode layer 319.

[0128] Refer to Figure 14 , Figure 14The structure of a semiconductor module is shown. An embodiment of the present application also proposes a semiconductor module. In this embodiment, the semiconductor module includes a bottom plate 400 and the power components as described above, and the power components are arranged on the bottom plate 400.

[0129] For the specific structure and principle of the power components, reference may be made to the foregoing embodiments, which have corresponding technical effects and will not be elaborated herein.

[0130] In some embodiments, the power components include at least one of a first power component, a second power component, and a third power component. The power chips in the first power component are used to construct an inverter, the power chips in the second power component are used to construct a charger, and the power chips in the third power component are used to construct a DC / DC unit.

[0131] As an example, multiple power components can be respectively configured as a main drive inverter power component 100, an on-vehicle charger, a DC / DC power component 200, and an on-vehicle compressor component 300. The main drive inverter power component 100, the on-vehicle charger, the DC / DC power component 200, and the on-vehicle compressor component 300 are fixed on the bottom plate 400.

[0132] The main drive inverter power component 100, the on-vehicle charger, the DC / DC power component 200, and the on-vehicle compressor component 300 can be welded to the first side of the bottom plate 400, and a heat dissipation structure is provided on the second side of the bottom plate 400 opposite to the first side.

[0133] In this embodiment, the power components can be welded to the bottom plate 400 by solder after being manufactured to ensure connection stability. In addition, the power components and the bottom plate 400 can also be connected in other ways, such as bonding. Welding on the same side leaves space for the second side, facilitating the setting of the heat dissipation structure and improving the reliability of the power components.

[0134] The heat dissipation structure can be heat dissipation teeth integrated with the bottom plate 400. The material of the bottom plate 400 can be copper or aluminum, which has high thermal conductivity and improves the heat dissipation effect. Of course, the heat dissipation structure can also be of other types, such as air cooling or liquid cooling.

[0135] In some embodiments, the multiple power components include at least two first power components. At least one first power component is used to construct a main drive inverter for a vehicle motor, and at least one first power component is used to construct an inverter for an on-vehicle compressor. The power components integrate the main drive inverter for the vehicle motor and the inverter for the on-vehicle compressor, effectively reducing the volume of the module and increasing the power density.

[0136] As an example, the power chips, power circuits, and signal circuits within the first power component are configured as a three-phase full-bridge inverter circuit. When the DC side of one first power component is connected to the DC bus of the vehicle high-voltage system and its AC side is connected to the vehicle motor, it can serve as the main drive inverter for the vehicle motor. When the DC side of another first power component is connected to the DC bus and its AC side is connected to the compressor of the vehicle air-conditioning system, it can serve as the main drive inverter for the vehicle motor.

[0137] In some embodiments, the second power component and the third power component are integrally fabricated. The second power component and the third power component can be different regions within a semiconductor structure as a whole. Thus, the connection line between the second power component and the third power component can be directly implemented within the wiring layer 120, reducing connection terminals and wire bonding and improving power density.

[0138] During the fabrication process, when forming the chip layer 110 on a first substrate 1, power chips that meet the requirements of the charger and the DC / DC unit are configured simultaneously. Subsequently, when the wiring layer 120 forms the corresponding power lines and signal lines, the charger and the DC / DC unit can be integrated into a semiconductor structure. The power connection relationship between the charger and the DC / DC unit is achieved through the power circuit within the wiring layer 120.

[0139] An embodiment of the present application also provides a vehicle, which includes the power component according to the foregoing. The specific structure and principle of the power component can be referred to the foregoing embodiments, and it also has corresponding technical effects, which will not be elaborated herein.

[0140] In this article, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also other elements not explicitly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or device comprising that element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in a reverse order according to the functions involved. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0141] Although embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A power component, characterized in that: include: A chip layer, wherein the chip layer is provided with a power chip; A wiring layer, wherein the wiring layer is provided with control electrodes and conducting lines; The wiring layer and the chip layer are stacked in sequence in a first direction, and the conductive line is connected between the power chip and the control electrode.

2. The power component according to claim 1, characterized in that: The control electrode is arranged on a surface of the wiring layer away from the chip layer, and the conducting line is arranged in the wiring layer.

3. The power assembly according to claim 1, characterized in that: The chip layer comprises: The frame layer is provided with a lead frame, and the power chip is connected to the lead frame.

4. The power component according to claim 3, characterized in that: The power chip includes a plurality of chip groups, the number of the lead frames is multiple, and each of the chip groups is connected to each of the lead frames in a one-to-one correspondence.

5. The power assembly according to claim 3, characterized in that: The framework layer includes: The laminate is provided with an empty slot, the lead frame is arranged in the empty slot, and the laminate is made of insulating material.

6. The power assembly according to claim 3, characterized in that: The chip layer also includes: a thermistor connected to the lead frame and arranged close to the power chip; A detection electrode is also provided on a surface of the wiring layer on one side away from the chip layer. A detection circuit is also provided in the wiring layer. The detection circuit is connected between the thermistor and the detection electrode.

7. The power assembly according to claim 1, characterized in that: The wiring layer comprises: an insulating layer, wherein the insulating layer and the chip layer are sequentially stacked in the first direction, and the insulating layer covers the power chip; The control electrode is disposed on a surface of the insulating layer away from the chip layer, and is connected to the power chip through the conductive line.

8. The power assembly according to claim 7, characterized in that: The insulating layer is provided with a via hole in a first direction, and at least a portion of the conducting line is disposed in the via hole.

9. The power assembly according to claim 7, characterized in that: The control electrode includes a power electrode, the conductive line includes a power connection layer, and the power connection layer is connected between the power electrode and the power chip.

10. The power assembly according to claim 9, characterized in that: The control electrode includes a power electrode, and the insulating layer includes: a first insulating layer, wherein the power connection layer is disposed on a surface of the first insulating layer away from the chip layer; A third insulating layer covers the power connection layer, and the power electrode is disposed on a surface of the third insulating layer away from the first insulating layer.

11. The power assembly according to claim 10, characterized in that: The conducting circuit includes a power circuit, the first insulating layer and the third insulating layer are provided with via holes in a first direction, and the power circuit is arranged in the via holes.

12. The power assembly according to claim 7, characterized in that: The control electrode includes a signal electrode, the conductive line includes a signal connection layer, and the signal connection layer is connected between the signal electrode and the power chip.

13. The power assembly according to claim 12, characterized in that: The control electrode includes a signal electrode, and the insulating layer includes: a second insulating layer, wherein the signal connection layer is disposed on a surface of the second insulating layer away from the chip layer; A third insulating layer covers the signal connection layer, and the signal electrode is disposed on a surface of the third insulating layer away from the second insulating layer.

14. The power assembly according to claim 13, characterized in that: The conducting circuit includes a signal circuit, the second insulating layer and the third insulating layer are provided with via holes in a first direction, and the signal circuit is arranged in the via holes.

15. The power assembly according to claim 11, characterized in that: The control electrode includes a signal electrode, the conductive line includes a signal connection layer, and the insulating layer includes: a second insulating layer, wherein the signal connection layer is disposed on a surface of the second insulating layer away from the chip layer, and the signal connection layer is connected between the power electrode and the power chip; The third insulating layer, the second insulating layer, and the first insulating layer are sequentially stacked in a first direction.

16. The power assembly according to claim 15, characterized in that: The conducting circuit includes a power circuit and a signal circuit; The first insulating layer is provided with a via hole in a first direction, and the power circuit is arranged in the via hole; The second insulating layer is provided with a via hole in the first direction, and the signal line is arranged in the via hole.

17. The power assembly according to claim 15, characterized in that: The first insulating layer and / or the second insulating layer may include multiple layers.

18. The power component according to any one of claims 1 to 17, characterized in that: Also includes: A substrate is arranged on a side of the chip layer away from the wiring layer.

19. The power assembly according to claim 18, characterized in that: Also includes: A third insulating layer is disposed between the chip layer and the substrate.

20. The power assembly according to claim 19, characterized in that: The substrate, the third insulating layer, the chip layer, and the wiring layer are laminated and fused.

21. The power component according to any one of claims 1 to 16, characterized in that: The power chip includes an upper bridge chip and a lower bridge chip, the control electrode includes a first power electrode, the conduction circuit includes a first power connection layer and a first power circuit, and the first power connection layer is respectively connected to the first power pin of the upper bridge chip, the first power pin of the lower bridge chip and the first power electrode through the first power circuit.

22. The power assembly according to claim 21, characterized in that: The control electrode also includes a second power electrode, and the conduction circuit also includes a second power connection layer and a second power circuit, the second power connection layer is insulated and isolated from the first power connection layer, and the second power connection layer is respectively connected to the second power pin of the lower bridge chip and the second power electrode through the second power circuit.

23. The power assembly according to claim 22, characterized in that: The control electrode includes a third power electrode, the conduction line includes a third power line, and the third power line is connected between the second power pin of the upper bridge chip and the third power electrode.

24. The power assembly according to claim 23, characterized in that: The number of the upper bridge chips and the number of the lower bridge chips are both multiple, the first power pin of each upper bridge chip and the first power pin of each lower bridge chip are connected to the same first power connection layer, and the second power pin of each lower bridge chip is connected to the same second power connection layer.

25. The power assembly according to claim 24, characterized in that: A substrate is provided on the side of the chip layer away from the wiring layer, the orthographic projection of each upper bridge chip on the substrate is located within the orthographic projection range of the first power connection layer on the substrate, and the orthographic projection of each lower bridge chip on the substrate is located within the orthographic projection range of the second power connection layer on the substrate.

26. The power assembly according to claim 21, characterized in that: The control electrode includes a first signal electrode and a second signal electrode, and the conductive line includes a first signal connection layer, a second signal connection layer, a first signal line, and a second signal line. The first signal connection layer is respectively connected to the signal pins of each upper bridge chip and the first signal electrode through the first signal line, and the second signal connection layer is respectively connected to the signal pins of each lower bridge chip and the second signal electrode through the second signal line.

27. The power assembly according to claim 26, characterized in that: The upper bridge chip and the lower bridge chip each include a plurality of signal pins, the first signal connection layer and the second signal connection layer each include a plurality of sub-signal connection layers, and each sub-signal connection layer is connected to each signal pin of each upper bridge chip or each lower bridge chip.

28. The power assembly according to claim 27, characterized in that: The number of the upper bridge chips and the number of the lower bridge chips are both multiple, and the sub-signal connection layer includes a main connection line and multiple branch connection lines, the main connection line is connected to the signal electrode through a signal line, the first end of the branch connection line is vertically connected to the main connection line, and the second end of the branch connection line is connected to the corresponding signal pin of the upper bridge chip or the lower bridge chip through the signal line, and the lengths of the branch connection lines are the same.

29. A semiconductor module, characterized in that: include: Base plate; The power component as described in any one of claims 1-28, wherein the power component is arranged on the base plate.

30. The semiconductor module according to claim 29, characterized in that The power component includes at least one of a first power component, a second power component and a third power component. The power chip in the first power component is used to construct an inverter, the power chip in the second power component is used to construct a charger, and the power chip in the third power component is used to construct a DC / DC unit.

31. The semiconductor module according to claim 30, characterized in that The second power component and the third power component are manufactured integrally.

32. The semiconductor module according to any one of claims 29 to 31, characterized in that The power component is welded to a first side of the base plate, and a heat dissipation structure is disposed on a second side of the base plate opposite to the first side.

33. The semiconductor module according to any one of claims 29 to 31, characterized in that The power component includes at least two first power components, at least one of which is used to construct a vehicle motor main drive inverter, and at least one of which is used to construct a vehicle compressor inverter.

34. A vehicle, characterized in that: The vehicle comprises a semiconductor module according to any one of claims 29-33.

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