Power Amplifiers

Abstract

A power amplifier according to the present disclosure includes a transistor, a main line connected to a drain of the transistor, a branch line that branches from the main line and is connected to a drain pad, and a drain bias circuit provided on the branch line. The drain bias circuit includes a first shunt capacitor connected to the branch line, and a second shunt capacitor connected to the branch line between the first shunt capacitor and the drain pad. The first shunt capacitor is capacitive at an operating frequency of the transistor, the second shunt capacitor is inductive at the operating frequency, and the first shunt capacitor and the second shunt capacitor resonate at the operating frequency.

Description

[Technical field]

[0001] The present disclosure relates to power amplifiers. [Background technology]

[0002] Patent Document 1 discloses a power amplifier having multiple amplifying elements. A tournament circuit having multiple transmission lines arranged in a tournament configuration is connected to the multiple amplifying elements. Multiple difference frequency short circuits are shunt-connected to multiple nodes of the tournament circuit. Each of the multiple difference frequency short circuits has an inductor and a capacitor connected in series. The resonant frequency of the multiple difference frequency short circuits decreases as they are farther away from the multiple amplifying elements. Difference frequency short circuits having the same resonant frequency are connected to multiple nodes at the same stage among the multiple nodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 202532 Summary of the Invention [Problem to be solved by the invention]

[0004] As the capacity of information communication increases, radio frequency modules used in small earth stations for satellite communication are shifting to the Ka band, which can use a wider bandwidth than the Ku band. In the Ku band, an internally matched field effect transistor (FET) is generally used for the final stage amplifier of the radio frequency module transmission circuit. However, it is difficult to apply the internally matched FET to the Ka band.

[0005] In the Ku-band internally matched FET, the matching circuit is generally formed using wires connecting the semiconductor transistor chip and the circuit board. On the other hand, the Ka-band requires shorter wires than the Ku-band. The short wires suitable for the Ka-band generally cannot physically connect the chip and the board. Even if they could be connected, the wire length is so short in the Ka-band that manufacturing tolerances cannot be ignored. This makes the RF characteristics sensitive to manufacturing variations in the wire length, and there is a risk of a significant drop in manufacturing yield.

[0006] For this reason, the final stage amplifier for Ka-band uses, for example, a monolithic microwave integrated circuit (MMIC), in which no wires are used in the matching circuit, and all circuit patterns are formed on a semiconductor chip.

[0007] Furthermore, in order to further expand transmission capacity, there is an increasing need for multi-carrier communications in the Ku band. In response to this, there are cases where internally matched FETs used in high-frequency module transmission circuits are also required to have specifications compatible with multi-carriers. Specifications compatible with multi-carriers are low distortion characteristics over a wide detuning range. The type of distortion that is problematic for semiconductor amplifiers for satellite communications is generally third-order intermodulation distortion IMD3 (3rd Intermodulation Distortion), which occurs when two main signals are input. In general, the ratio of IMD3 to the main signal is considered to be -25 dBc or less.

[0008] Here, the difference in frequency between the two main signals is called the detuning frequency Δf. The detuning width specification for Ku-band single-carrier communication is Δf=1-10MHz, but for multi-carrier communication, for example, Δf=1-375MHz, and a wider detuning width is required. The maximum value of Δf is 1 / 2 the bandwidth of the used band of 13.75-14.5GHz, that is, (14.5GHz-13.75GHz) / 2=375MHz. This need for multi-carrier is also spreading to Ka-band. Since the used band of Ka-band is 27.5-30GHz, the maximum detuning width is Δf=(30GHz-27.5GHz) / 2=1250MHz. In other words, a detuning width of three times or more of Δf in Ku-band is required.

[0009] The impedance at Δf seen from the transistor to the output side has a strong correlation with IMD3 at Δf. Therefore, in order to reduce IMD3, it is effective to sufficiently reduce the impedance at Δf seen from the transistor to the output side.

[0010] In Patent Document 1, a wire and a line are connected to the main line of the output side circuit. A capacitor with a capacity that shorts Δf is connected to the tip of the circuit composed of the wire and the line. This provides LC resonance, reduces the impedance at Δf, and reduces IMD3 at Δf. By providing multiple difference frequency short circuits by such LC resonance, a wide detuning can be achieved. However, if a wire is stretched on the main line in a Ka-band MMIC, it is expected that the variation of the wire cannot be ignored for the wavelength of the Ka band. For this reason, the RF characteristics become sensitive to the variation of the wire length, and there is a risk of a significant decrease in yield.

[0011] Another method of shorting the difference frequency is to connect a capacitor for shorting the difference frequency to the main line via a drain bias circuit. In this case, multiple types of capacitors can be used, but only one type of wire can be used as an inductor. As a result, there is only one resonance point, and wide detuning characteristics cannot be obtained.

[0012] In order to provide many resonance points due to inductance, it is possible to provide a quarter-wavelength short stub as an inductance on the MMIC chip. However, even for Ka-band, the quarter-wavelength line is large compared to the chip size. Therefore, providing multiple short stubs increases the chip size, which leads to problems such as increased manufacturing costs.

[0013] An object of the present disclosure is to provide a power amplifier that can be miniaturized. [Means for solving the problem]

[0014] A power amplifier according to the present disclosure includes a transistor, a main line connected to a drain of the transistor, a branch line branching from the main line and connected to a drain pad, and a drain bias circuit provided on the branch line, the drain bias circuit having a first shunt capacitor connected to the branch line and a second shunt capacitor connected to the branch line between the first shunt capacitor and the drain pad, the first shunt capacitor being capacitive at an operating frequency of the transistor and the second shunt capacitor being inductive at the operating frequency, and the first shunt capacitor and the second shunt capacitor resonating at the operating frequency. Each of the first shunt capacitor and the second shunt capacitor has a base electrode connected to a ground wiring and an upper electrode provided on the base electrode, and the upper electrode of the first shunt capacitor and the upper electrode of the second shunt capacitor are connected by an air bridge. do. Effect of the Invention

[0015] In the power amplifier according to the present disclosure, the first shunt capacitor and the second shunt capacitor resonate with each other, which eliminates the need to use a short stub in the drain bias circuit and allows the power amplifier to be miniaturized. [Brief description of the drawings]

[0016] [Figure 1] 1 is a block diagram of a power amplifier according to a first embodiment. [Diagram 2] 2 is a diagram showing a configuration of an output side circuit of the final stage of the power amplifier according to the first embodiment. FIG. [Diagram 3] FIG. 2 is a diagram showing a configuration of a capacitor circuit according to the first embodiment. [Figure 4] FIG. 2 is a diagram showing a layout of a capacitor circuit according to the first embodiment. [Diagram 5] 2 is an equivalent circuit diagram of a capacitor circuit according to the first embodiment. FIG. [Figure 6] FIG. 1 is a diagram illustrating an ideal capacitor. [Figure 7] FIG. 2 is a diagram showing the impedance of an ideal capacitor. [Figure 8] 4 is an equivalent circuit diagram of a first shunt capacitor according to the first embodiment. FIG. [Figure 9] FIG. 4 is a diagram illustrating the impedance of a first shunt capacitor in the first embodiment. [Figure 10] 4 is an equivalent circuit diagram of a second shunt capacitor according to the first embodiment. FIG. [Figure 11] FIG. 4 is a diagram illustrating the impedance of a second shunt capacitor in the first embodiment. [Figure 12] 4 is an equivalent circuit diagram of a second shunt capacitor and an air bridge according to the first embodiment. FIG. [Figure 13] FIG. 4 is a diagram illustrating impedance of a second shunt capacitor and an air bridge according to the first embodiment. [Figure 14] 2 is an equivalent circuit diagram of a capacitor circuit according to the first embodiment. FIG. [Figure 15] FIG. 4 is a diagram illustrating the impedance of a capacitor circuit according to the first embodiment. [Figure 16] FIG. 13 is a diagram showing a configuration of an output side circuit of the final stage of a power amplifier according to a modification of the first embodiment. [Figure 17] FIG. 13 is a diagram showing a configuration of an output side circuit of the final stage of a power amplifier according to a comparative example. [Figure 18] FIG. 1 is an equivalent circuit diagram of a MIM capacitor. [Figure 19] FIG. 1 is a diagram showing a layout of an MIM capacitor. [Figure 20] FIG. 20 is a diagram showing a layout of an MIM capacitor having the same area as the MIM capacitor shown in FIG. 19. [Figure 21]FIG. 20 is a diagram showing the impedance of the MIM capacitor shown in FIG. [Figure 22] FIG. 21 is a diagram showing the impedance of the MIM capacitor shown in FIG. 20. [Figure 23] FIG. 13 is a diagram showing the C2 / C1 dependency of the impedance of a capacitor circuit. [Figure 24] FIG. 13 is a diagram showing the layout of a capacitor circuit when C2 / C1=15. [Diagram 25] FIG. 13 is a diagram showing the layout of a capacitor circuit when C2 / C1=6. [Figure 26] FIG. 13 is a diagram showing a layout of a capacitor circuit according to a comparative example. [Figure 27] 4 is a cross-sectional view showing a state in which an air bridge is connected to a first shunt capacitor in accordance with the first embodiment. FIG. [Figure 28] 4 is a diagram showing a state in which a chip capacitor is provided in the power amplifier according to the first embodiment. FIG. [Figure 29] FIG. 11 is a diagram showing a layout of a capacitor circuit according to a second embodiment. [Diagram 30] FIG. 13 is a diagram showing a layout of a capacitor circuit according to a comparative example. [Diagram 31] FIG. 11 is a diagram illustrating the impedance of a capacitor circuit according to the second embodiment. [Diagram 32] FIG. 11 is a diagram illustrating the impedance of a capacitor circuit according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] A power amplifier according to each embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0018] Embodiment 1 1 is a block diagram of a power amplifier 100 according to a first embodiment. The power amplifier 100 has three power amplification stages. The number of power amplification stages is not limited to three. An input matching circuit 12 is connected between an input terminal 10 and a first-stage transistor 21. Inter-stage matching circuits 13 and 14 are connected between the first-stage transistor 21 and the second-stage transistor 22, and between the second-stage transistor 22 and a final-stage transistor 23, respectively. An output matching circuit 16 is connected between the final-stage transistor 23 and an output terminal 18. A gate bias circuit 25 and a drain bias circuit 26 are provided in each stage.

[0019] The operating frequency of the power amplifier 100 is the Ka band. The power amplifier 100 is composed of, for example, one Ka band MMIC chip. For example, GaN-based transistors, which are optimal for high-output amplifiers, are used as the transistors 21, 22, and 23. However, this is not limiting, and GaAs-based, InP-based, or other transistors may also be used. The substrate of the MMIC is formed of, for example, SiC. The substrate material may be different.

[0020] FIG. 2 is a diagram showing a configuration of an output side circuit of the final stage of the power amplifier 100 according to the first embodiment. The first stage, second stage, and final stage input side circuits are not shown. The MMIC chip 50 includes transistors 23a and 23b as the transistor 23. The gates of the transistors 23a and 23b are connected in parallel to an input terminal 51 via a capacitor. One end of the main lines 16a and 16b is connected to the drains of the transistors 23a and 23b. One end of a main line 16c is connected to the other end of the main lines 16a and 16b. An output terminal 52 is connected to the other end of the main line 16c via a coupling capacitor 16d. The output matching circuit 16 is composed of the main lines 16a, 16b, and 16c that transmit an RF output signal, and the coupling capacitor 16d.

[0021] Next, the configuration of the drain bias circuit 26 in the final stage will be described. The drain bias circuit 26 in the final stage is a capacitor circuit 30. The drain bias circuits 26 in the first and second stages may have the same configuration as that of the final stage, or may have different configurations. Branch lines 17a and 17b branch out from the main lines 16a and 16b, respectively. The branch lines 17a and 17b are connected to drain pads 54a and 54b, respectively. The drain pads 54a and 54b are also called DC pads. Capacitor circuits 30a and 30b are provided on the branch lines 17a and 17b, respectively, as the capacitor circuit 30.

[0022] 3 is a diagram showing a configuration of a capacitor circuit 30 according to the first embodiment. In the following, the capacitor circuit 30a will be described as an example, but the capacitor circuit 30b has a similar configuration. The capacitor circuit 30 has a terminal 31 connected to the main line 16a and a terminal 32 connected to the drain pad 54a. The capacitor circuit 30 has a first shunt capacitor 34 connected to the branch line 17a, and a second shunt capacitor 35 connected to the branch line 17a between the first shunt capacitor 34 and the drain pad 54a.

[0023] 4 is a diagram showing a layout of the capacitor circuit 30 according to the first embodiment. The first shunt capacitor 34 and the second shunt capacitor 35 are, for example, MIM (Metal-Insulator-Metal) capacitors. The first shunt capacitor 34 has a base electrode 34a connected to a ground wiring and an upper electrode 34b provided on the base electrode 34a. Similarly, the second shunt capacitor 35 has a base electrode 35a and an upper electrode 35b provided on the base electrode 35a. In each MIM capacitor, an MIM insulating film (not shown) is provided between the upper electrode and the base electrode.

[0024] The upper electrode 34b of the first shunt capacitor 34 is connected to the main line 16a via the air bridge 33. The lower electrode 34a of the first shunt capacitor 34 is connected to a via hole 37, which is a grounding wiring, via a via hole wiring 36. The upper electrode 34b is connected to an upper electrode 35b of the second shunt capacitor 35 via the air bridge 33. The lower electrode 35a of the second shunt capacitor 35 is connected to a via hole 39, which is a grounding wiring, via a via hole wiring 38. The upper electrode 35b is connected to a drain pad 54a via the air bridge 33. The via holes 37 and 39 are connected to a ground provided on the back surface of the substrate. A DC bias is supplied to the transistor 23a connected to the main line 16a via the drain pad 54a, the air bridge 33, and the upper electrodes 35b and 34b.

[0025] The via holes 37, 39 are formed, for example, by etching from the rear surface of the substrate. The via hole wirings 36, 38 serve as etching stoppers. For convenience, the via holes 37, 39 are shown in Fig. 4. In reality, the via holes 37, 39 are not visible because the via hole wirings 36, 38 are above the via holes 37, 39.

[0026] 5 is an equivalent circuit diagram of the capacitor circuit 30 according to the first embodiment. The capacitances of the first shunt capacitor 34 and the second shunt capacitor 35 are C1 and C2, respectively. The MIM capacitor has parasitic inductance. Here, the parasitic inductances of the upper electrodes 34b and 35b are Lmima1 and Lmima2, the parasitic inductances of the lower electrodes 34a and 35a are Lmimb1 and Lmimb2, and the parasitic inductance of the air bridge 33 is Lab. In addition, the inductance of the connection line between the first shunt capacitor 34 and the second shunt capacitor 35 is L12, and the parasitic inductance of the via hole is Lvh.

[0027] FIG. 6 is a diagram for explaining an ideal capacitor. An ideal capacitor has no parasitic components. One end of the ideal capacitor is connected to a terminal 81 via a phase adjustment line 82. The other end of the ideal capacitor is grounded. FIG. 7 is a diagram showing the impedance of an ideal capacitor. In FIG. 7, markers are attached to 1 GHz, 5 GHz, 14 GHz, and 30 GHz as examples of L, C, Ku, and Ka bands, respectively. With the electrical length of the phase adjustment line 82 set to 0°, the impedance of the ideal capacitor seen from the terminal 81 is capacitive at 1 GHz, 5 GHz, and 14 GHz. On the other hand, at 30 GHz, which is the Ka band, the impedance is capacitive but close to inductive. Note that the upper half of the Smith chart is inductive, and the lower half is capacitive.

[0028] In FIG. 7, in order to make the impedance at 14 GHz inductive, the electrical length of the phase adjustment line 82 needs to be 20°. In this case, assuming a microstrip line with a substrate thickness of 50 μm and a characteristic impedance of 50 Ω in a SiC substrate generally used in GaN systems, a line of about 480 μm is required. On the other hand, in order to make the impedance at 30 GHz, which is the Ka band, inductive, the electrical length of the phase adjustment line 82 needs to be about 10°. Similarly, assuming a microstrip line with a substrate thickness of 50 μm and a characteristic impedance of 50 Ω in a SiC substrate, this corresponds to a line of about 120 μm. In this way, the physical length required to obtain inductivity in the Ka band is 1 / 4 compared to the Ku band.

[0029] An actual MIM capacitor and a via hole have a parasitic inductance. In this embodiment, this parasitic inductance is utilized to make the second shunt capacitor 35 inductive. The intrinsic capacitance of the MIM capacitor is Cint, the parasitic inductance of the MIM capacitor and the via hole is Lext, the phase of the intrinsic capacitance is φCint, and the phase of the parasitic inductance is φLext. In this case, an inductive capacitor is obtained by Lext satisfying φLext>180°+φCint (equation (1)).

[0030] 8 to 15 show the equivalent circuit and impedance of the MIM capacitor alone or the capacitor circuit 30. In the Smith charts shown in Figs. 9, 11, 13, and 15, the impedance of the MIM capacitor or the capacitor circuit 30 as viewed from the terminal 31 is shown. In Figs. 9, 11, 13, and 15, a marker is placed at 29 GHz. The other end of the MIM capacitor is connected to the ground on the back side of the substrate via a via hole. Here, for convenience, the parasitic inductances of the MIM capacitor and the via hole are collectively referred to as Lext1 and Lext2. The frequency is 29 GHz, C1=0.63 pF, C2=3.8 pF, Lext1=15 pH, Lext2=23 pH, and L12=18 pH.

[0031] Fig. 8 is an equivalent circuit diagram of the first shunt capacitor 34 according to embodiment 1. Fig. 9 is a diagram showing the impedance of the first shunt capacitor 34 according to embodiment 1. The first shunt capacitor 34 is a small-sized MIM capacitor that is capacitive including a parasitic inductance.

[0032] FIG. 10 is an equivalent circuit diagram of the second shunt capacitor 35 according to the first embodiment. FIG. 11 is a diagram showing the impedance of the second shunt capacitor 35 according to the first embodiment. FIG. 12 is an equivalent circuit diagram of the second shunt capacitor 35 and the air bridge 33 according to the first embodiment. FIG. 13 is a diagram showing the impedance of the second shunt capacitor 35 and the air bridge 33 according to the first embodiment. In FIG. 12, the inductance of the air bridge 33 is indicated as L12. The second shunt capacitor 35 is a large-sized MIM capacitor so that it satisfies equation (1) including the parasitic inductance and is inductive.

[0033] FIG. 14 is an equivalent circuit diagram of the capacitor circuit 30 according to the first embodiment. FIG. 15 is a diagram showing the impedance of the capacitor circuit 30 according to the first embodiment. When the capacitive first shunt capacitor 34 and the inductive second shunt capacitor 35 are connected by an air bridge 33, LC parallel resonance occurs. At this time, the capacitor circuit 30 has a high impedance as shown in FIG. 15. Since the impedance is high, the effect of the capacitor circuit 30 on the characteristics of the main circuit can be suppressed.

[0034] In the capacitor circuit 30 of this embodiment, the first shunt capacitor 34 is capacitive at the operating frequency of the transistor 23a, and the second shunt capacitor 35 is inductive at the operating frequency of the transistor 23a. The first shunt capacitor 34 and the second shunt capacitor 35 resonate at the operating frequency of the transistor 23a. A difference frequency short circuit can be configured by connecting a capacitor for short-circuiting the difference frequency to this capacitor circuit 30 via the drain pad 54a. In this embodiment, it is not necessary to add a 1 / 4 wavelength short stub as a drain bias circuit. This makes it possible to miniaturize the power amplifier 100. Also, the chip cost can be reduced.

[0035] 16 is a diagram showing a configuration of an output side circuit of the final stage of the power amplifier 100 according to a modification of the first embodiment. The MMIC chip 250 differs from the MMIC chip 50 in that it further includes capacitor circuits 30c, 30d and drain pads 54c, 54d. A plurality of branch lines branch off from the main lines 16a, 16c, and a plurality of capacitor circuits 30a, 30c are provided on the branch lines. The configurations of the capacitor circuits 30c, 30d are similar to those of the capacitor circuits 30a, 30b.

[0036] The drain pads 54a, 54c are connected to the upper electrodes of chip capacitors 65a, 65c provided outside the chip via wires 62. The chip capacitors 65a, 65c have an upper and lower electrode structure. The lower electrodes of the chip capacitors 65a, 65c are connected to the ground. The chip capacitors 65a, 65c are each a capacitor for shorting a difference frequency. Furthermore, the upper electrodes of the chip capacitors 65a, 65c are connected to a pad 64 provided on the external chip substrate 60 via wires 62. A DC bias is supplied from the pad 64 to the drain of the transistor 23a.

[0037] The chip capacitor 65a, the wire 62, the drain pad 54a, and the capacitor circuit 30a constitute a difference frequency short circuit 70a. Similarly, the chip capacitor 65c, the wire 62, the drain pad 54c, and the capacitor circuit 30c constitute a difference frequency short circuit 70c. Although not shown, the configurations of the chip capacitors and off-chip substrate connected to the capacitor circuits 30b and 30d are similar to the configurations of the chip capacitors 65a and 65c and the off-chip substrate 60.

[0038] In this way, in this embodiment, since the difference frequency short circuits 70a and 70c can be made smaller, multiple difference frequency short circuits 70a and 70c can be provided. Therefore, it is possible to provide resonance points equal to the number of difference frequency short circuits 70a and 70b, enabling a wide range of detuning. In FIG. 16, two difference frequency short circuits 70a and 70b are provided in one transistor 23a, but the number of difference frequency short circuits may be one or more.

[0039] Although the wire 62 is used in FIG. 16, the main signal is short-circuited by the capacitor circuit 30, so that the wire 62 does not affect the main signal.

[0040] FIG. 17 is a diagram showing the configuration of the output side circuit of the final stage of the power amplifier according to the comparative example. The MMIC chip 850 according to the comparative example includes a drain bias circuit 826. The drain bias circuit 826 is connected to chip capacitors C11 and C12 provided on an external chip substrate 860 via a drain pad 54a and a wire L. The chip capacitors C11 and C12 are capacitors for short-circuiting the difference frequency. In the comparative example, multiple types of chip capacitors C11 and C12 can be used. However, only one type of wire L can be used as an inductor. Therefore, only L(C11+C12) resonance is obtained, and wide detuning characteristics cannot be obtained. In contrast, in the present embodiment, multiple small difference frequency short-circuit circuits 70a and 70c are provided, thereby enabling wide detuning.

[0041] Next, we will explain MIM capacitors that are prone to inductivity and MIM capacitors that are not prone to inductivity. Figure 18 is an equivalent circuit diagram of an MIM capacitor. The equivalent circuit of an MIM capacitor is represented by an intrinsic capacitance Cint and distributed constant lines 83a and 83b as parasitic inductance. The intrinsic capacitance Cint is a parallel plate capacitance. Therefore, the intrinsic capacitance Cint is determined by the thickness of the insulating film, the relative dielectric constant of the insulating film, and the electrode size. The distributed constant lines 83a and 83b, which are parasitic components, have the same width as the capacitor width and a length that is half the length of the capacitor, to obtain the parasitic inductance Lext.

[0042] When the capacitance value of the MIM capacitor is large, for example 3.8 pF, the capacitor size is large and the parasitic inductance is also large. In this case, inductivity is obtained when the MIM capacitor is a square with one side of 153 μm. Here, the thickness of the insulating film of the MIM capacitor is 350 nm, and the relative dielectric constant is 6.4. In addition, for the distributed constant lines 83a and 83b, the substrate material is SiC, the substrate thickness is 50 μm, and the wiring thickness is 2 μm. In this way, if the capacitance value is large, it is easy to obtain inductivity. However, if the capacitance value is small, it is difficult to obtain inductivity.

[0043] In order to make a capacitor with a small capacitance value inductive, it is effective to use a layout in which the shape from the input end of the MIM capacitor to the via hole is long and narrow so as to increase the L component of the distributed constant lines 83a, 83b. Fig. 19 is a diagram showing the layout of MIM capacitor Ca. Fig. 20 is a diagram showing the layout of MIM capacitor Cb, which has the same area as MIM capacitor Ca shown in Fig. 19. MIM capacitor Ca is square in plan view, and MIM capacitor Cb is rectangular in plan view. The areas of MIM capacitors Ca and Cb are both approximately 2100 μm 2 The capacitance values ​​of both are small, at 0.34 pF.

[0044] The input end is the end of the upper electrode of the MIM capacitors Ca, Cb that overlaps with the air bridge 33. The distance from the input end to the via holes 37a, 37b is Da=85 μm for the MIM capacitor Ca, and Db=120 μm for the MIM capacitor Cb. In the MIM capacitor Cb, Db is made longer to increase the parasitic inductance.

[0045] FIG. 21 is a diagram showing the impedance of the MIM capacitor Ca shown in FIG. 19. FIG. 22 is a diagram showing the impedance of the MIM capacitor Cb shown in FIG. 20. The MIM capacitors Ca and Cb have the same capacitance and area, but in the Ka band, the square MIM capacitor Ca is capacitive, and the elongated MIM capacitor Cb is inductive. In the Ku band, the MIM capacitors Ca and Cb do not exhibit inductivity due to parasitic inductance alone, and both are capacitive. In this way, in this embodiment, the upper electrode 35b of the second shunt capacitor 35 is rectangular in a plan view, so that the second shunt capacitor 35 can be set to be inductive while suppressing the area.

[0046] The via holes 37a and 37b also have parasitic inductance. Therefore, the inductance of the via holes 37a and 37b can also be used to make the MIM capacitor inductive. In this way, the parasitic inductance of the MIM capacitor and the parasitic inductance of the via holes are set to satisfy equation (1). This allows the shunt capacitor to obtain inductivity in the millimeter wave bands of Ka band and above.

[0047] Next, consider the capacitance ratio C2 / C1 between the first shunt capacitor 34 and the second shunt capacitor 35. FIG. 23 is a diagram showing the C2 / C1 dependency of the impedance of the capacitor circuit 30. Here, C1 is set to 0.625 pF. In FIG. 23, a high impedance of 100 Ω or more is obtained when C2 / C1=5 to 8. Furthermore, the impedance has a peak when C2 / C1=6. The position of this peak depends on the value of C1. For example, when C1=0.28 pF, the peak occurs when C2 / C1=15.

[0048] Next, consider the layout of the capacitor circuit. FIG. 24 is a diagram showing the layout of the capacitor circuit 30 when C2 / C1=15. Here, C1=0.28 pF. For miniaturization, only one via hole 37 is provided and is shared by the first shunt capacitor 34 and the second shunt capacitor 35. The first shunt capacitor 34 and the second shunt capacitor 35 are connected to adjacent sides of the rectangular via hole wiring 36. An arrow 86 indicates the path of the millimeter wave. When C2 / C1=15, the size of the second shunt capacitor 35 is too large, so a part of the region 87 of the capacitance C2 does not appear as a capacitance in the millimeter wave band. To make the entire capacitance C2 appear as a capacitance, a via hole needs to be added. In this case, in addition to the size of the second shunt capacitor 35 being large, the number of via holes also increases. Therefore, there is a risk of the layout size becoming large.

[0049] For comparison, FIG. 25 shows the layout of the capacitor circuit 30 when C2 / C1=6. The layout is arranged to aim for miniaturization, similar to the case of C2 / C1=15. Here, the initial value of the first shunt capacitor is 0.625 pF, but since the size is larger than the first shunt capacitor in FIG. 24 and the parasitic inductance is larger, C1 can be made smaller than the initial value to 0.38 pF. As shown in FIG. 25, in the example of C2 / C1=6, the area of ​​the second shunt capacitor is small and the expected area appears as capacitance. Therefore, a small layout size can be realized. Note that, in the case of C2 / C1=15, if the pattern shape of the second shunt capacitor 35 is L-shaped, the part that appears as capacitance increases. However, in this case, the layout size is also larger than the case of C2 / C1=6. In the Ka band, if at least C2 / C1≦8, the chip size can be suppressed from increasing.

[0050] It is also possible to increase C1 to shift the peak position in Figure 23 to a lower C2 / C1 position. However, C2 / C1 ≧ 1. In general, the lower the capacitance of the capacitor, the closer it is to the transistor, which will provide more stable operation. When unwanted oscillation occurs, the higher the frequency of the unwanted wave, the easier it is to couple with other circuits. For this reason, the higher the frequency, the better it is to short-circuit the unwanted wave at a location closer to the transistor. The condition for a capacitor to short-circuit the unwanted wave is impedance Z = 1 / (2πfC) ≒ 0. The higher the frequency of the unwanted wave, the smaller the capacitor for short-circuiting. For this reason, it is preferable that the capacitor with the lower capacitance is closer to the transistor, and it is preferable that C2 / C1 ≧ 1.

[0051] From the above, it is preferable that 1≦C2 / C1≦8. In other words, it is preferable that the area of ​​the upper electrode b of the second shunt capacitor is 1 to 8 times the area of ​​the upper electrode b of the first shunt capacitor .

[0052] Furthermore, if C1 is too small, C2 / C1 will become large, and the layout may become large. Specifically, if C1 is smaller than 0.3 pF, C2 / C1 will become large, and the layout will become large. Furthermore, if C1 is larger than 0.7 pF, the first shunt capacitor 34, which should be capacitive, will become inductive in the millimeter wave band due to parasitic inductance. For these reasons, it is preferable that the capacitance of the first shunt capacitor 34 be 0.3 to 0.7 pF.

[0053] The vertical width of the capacitor circuit 30 shown in Fig. 25 is 200 µm. Fig. 26 is a diagram showing the layout of a capacitor circuit 830 according to a comparative example. In the capacitor circuit 830, the same function as in this embodiment is realized using a ¼ wavelength short stub 829, an MIM capacitor, and a via hole 37. The vertical width of the capacitor circuit 830 according to the comparative example is about 1300 µm. It can be seen that the capacitor circuit 30 of this embodiment can be significantly miniaturized compared to the comparative example.

[0054] In this embodiment, the wiring connected to the upper electrode 34b of the first shunt capacitor 34 or the upper electrode 35b of the second shunt capacitor 35 includes an air bridge 33. FIG. 27 is a cross-sectional view showing a state in which the air bridge 33 is connected to the first shunt capacitor 34 according to the first embodiment. The base electrode 34a is larger than the upper electrode 34b. For example, if the upper electrode 34b is extended and used as a wiring without using the air bridge 33, the overlapping area between the upper electrode 34b and the base electrode 34a increases more than the original area S1, and the parasitic capacitance may increase. On the other hand, if the air bridge 33 is used, a space S2 is provided between the air bridge 33 and the MIM insulating film 34c. Therefore, an unnecessary increase in parasitic capacitance can be suppressed.

[0055] In addition, the via hole wiring 36 is used to connect the base electrode 34a and the ground wiring, which minimizes the distance from the base electrode 34a to the back electrode, thereby suppressing unnecessary parasitic inductance.

[0056] FIG. 28 is a diagram showing a state where a chip capacitor 65a is provided in the power amplifier 100 according to the first embodiment. In the power amplifier 100, the semiconductor substrate 20, which is the substrate of the MMIC chip 50, the chip capacitors 65a and 65c, and the chip off-chip substrate 60 are mounted on the package base 101. The base 101 is at ground potential. The chip off-chip substrate 60 is formed from an insulator. In the chip capacitors 65a and 65c, a lower electrode m1, an insulator I1, and an upper electrode m2 are laminated. The lower electrode m1 is connected to the base 101. The chip capacitors 65a and 65c are connected to GND simply by being mounted on the base 101. Therefore, the structure of the power amplifier 100 can be simplified and assembly can be facilitated. The chip capacitors 65a and 65c may be replaced with a bale-shaped capacitor or the like.

[0057] The structure, layout, and values ​​of each part of the power amplifier 100 shown so far are merely examples and are not limited to the above. The capacitance and shape of the shunt capacitor are also not limited to those described above. At the operating frequency, the first shunt capacitor 34 is capacitive, the second shunt capacitor 35 is inductive, and the first shunt capacitor and the second shunt capacitor only need to resonate. This embodiment can also be applied to a frequency converter using a difference frequency short circuit or a switch using a drain bias circuit.

[0058] The above-mentioned modifications can be appropriately applied to the power amplifiers according to the following embodiments. Note that the power amplifiers according to the following embodiments have many points in common with the first embodiment, so the following description will focus on the differences from the first embodiment.

[0059] Embodiment 2 29 is a diagram showing a layout of a capacitor circuit 330 according to embodiment 2. A first shunt capacitor 34 and a second shunt capacitor 35 are provided on via holes 37 and 39. The other configurations are similar to those of embodiment 1.

[0060] 30 is a diagram showing a layout of a capacitor circuit 930 according to a comparative example. In the comparative example, the first shunt capacitor 34 and the second shunt capacitor 35 do not overlap with the via hole 37. In the capacitor circuit 930, the first shunt capacitor 34 and the second shunt capacitor 35 share the via hole 37 in order to reduce the size.

[0061] In both the capacitor circuits 330 and 930, C1=0.40 pF and C2=1.2 pF. In the capacitor circuit 330, the via holes 37 and 39 are located directly below the first shunt capacitor 34 and the second shunt capacitor 35, so that the first shunt capacitor 34 and the second shunt capacitor 35 can also serve as wiring for the via holes. Therefore, the layout area can be reduced by about 28% compared to the comparative example.

[0062] Fig. 31 is a diagram showing the impedance of the capacitor circuit 330 according to the second embodiment. Fig. 32 is a diagram showing the impedance of the capacitor circuit 930 according to the comparative example. Impedances obtained by electromagnetic field analysis are shown in Figs. 31 and 32. The capacitor circuit 330 can achieve impedance equivalent to that of the capacitor circuit 930, despite its small size.

[0063] As a modification of this embodiment, one of the first shunt capacitor 34 or the second shunt capacitor 35 may be provided above a via hole.

[0064] The technical features described in each embodiment may be used in appropriate combination. [Explanation of symbols]

[0065] 10 input terminal, 12 input matching circuit, 13 interstage matching circuit, 16 output matching circuit, 16a, 16b, 16c main line, 16d coupling capacitor, 17a branch line, 18 output terminal, 20 semiconductor substrate, 21, 22, 23, 23a, 23b transistor, 25 gate bias circuit, 26 drain bias circuit, 30, 30a, 30b, 30c capacitor circuit, 31, 32 terminal, 33 air bridge, 34 first shunt capacitor, 34a base electrode, 34b top electrode, 34c MIM insulating film, 35 second shunt capacitor, 35a base electrode, 35b top electrode, 36 via hole wiring, 37, 37a via hole, 38 via hole wiring, 39 via hole, 50 MMIC chip, 51 input terminal, 52 output terminal, 54a, 54c Drain pad, 60 Substrate outside chip, 62 Wire, 64 Pad, 65a, 65c Chip capacitor, 70a, 70c Difference frequency short circuit, 81 Terminal, 82 Phase adjustment line, 83a, 83b Distributed constant line, 100 Power amplifier, 101 Base, 250 MMIC chip, 330 Capacitor circuit, 826 Drain bias circuit, 829 Wavelength short stub, 830 Capacitor circuit, 850 MMIC chip, 860 Substrate outside chip, 930 Capacitor circuit, C11, C12 Chip capacitor, Ca, Cb MIM capacitor, I1 Insulator, L Wire, m1 Lower electrode, m2 Upper electrode

Claims

1. A transistor; a main line connected to the drain of the transistor; a branch line branching off from the main line and connected to a drain pad; a drain bias circuit provided on the branch line; Equipped with The drain bias circuit includes: a first shunt capacitor connected to the branch line; a second shunt capacitor connected to the branch line between the first shunt capacitor and the drain pad; having the first shunt capacitor is capacitive at an operating frequency of the transistor; the second shunt capacitor is inductive at the operating frequency; At the operating frequency, the first shunt capacitor and the second shunt capacitor resonate; each of the first shunt capacitor and the second shunt capacitor has a base electrode connected to a ground wiring and an upper electrode provided on the base electrode; a top electrode of the first shunt capacitor and a top electrode of the second shunt capacitor are connected by an air bridge.

2. 2. The power amplifier according to claim 1, wherein an area of ​​the upper electrode of the second shunt capacitor is 1 to 8 times an area of ​​the upper electrode of the first shunt capacitor.

3. 3. The power amplifier according to claim 1, wherein the upper electrode of the second shunt capacitor is rectangular in plan view.

4. 4. The power amplifier according to claim 1, wherein the first shunt capacitor or the second shunt capacitor is provided on a via hole that is a ground wiring.

5. 5. The power amplifier according to claim 1, wherein the capacitance of the first shunt capacitor is 0.3 to 0.7 pF.

6. 6. The power amplifier according to claim 1, wherein the operating frequency is a Ka band.

7. A plurality of the branch lines branch off from the main line, 7. The power amplifier according to claim 1, wherein a plurality of the drain bias circuits are provided on a plurality of the branch lines.

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