Executing small memory address width program code in a large memory address width address space

Abstract

A method and system are provided for executing a small memory address width program within a large memory address width address space. The method includes dividing a small memory address width program executable code into a set of portions, reserving a first virtual storage area in a portion of the address space accessed with the small memory address width addresses, and reserving a set of second virtual storage areas in a portion of the address space accessed with the large memory address width addresses to accommodate the program executable code. The method provides a relocation mechanism that relocates processor threads by converting from addresses in the reserved first virtual storage area to one of the reserved second virtual storage areas that accommodates the executable code using a relocation factor.

Description

[Technical field]

[0001] The present invention relates to computer addressing modes, and more particularly to executing smaller memory-address width programs within a larger memory-address width address space. [Background technology]

[0002] The addressing mode (AMODE) is used to identify the number of bits a program uses for storage addresses. AMODE-31 programs use 31-bit storage addresses and accommodate them using 4-byte fields and 4-byte registers. AMODE-64 programs use 64-bit storage addresses and accommodate them using 8-byte fields and 8-byte registers.

[0003] Residence Mode (RMODE) is used to describe where the program itself should reside in memory. RMODE-31 programs must reside in storage accessible using 31-bit addresses, i.e., within the first 2GB of address space, also known as "below the bar". RMODE-64 programs must reside in storage accessible using 64-bit addresses, i.e., somewhere within the address space of a 64-bit architecture. RMODE-64 programs can, and preferably do, reside in storage above the first 2GB, also known as "above the bar".

[0004] Modern computer architectures typically support 64-bit virtual storage addresses, while older versions of the same architecture typically supported smaller addresses such as 8-bit, 16-bit, 24-bit, 31-bit, or 32-bit. 64-bit architectures are designed to run AMODE-64 programs, but often can also run programs from older versions of the architecture. Techniques that make this possible include emulation, and bimodal or trimodal operation. Other useful techniques that can be applied to this include thunking, which is used to provide interoperability between software modules that cannot call routines from each other, where code is inserted into the calling process (and sometimes into the return process).

[0005] Bimodal operation allows a program to run in two addressing modes. Application servers use this feature extensively, allowing users to continue to run applications developed over decades on modern processors. Also, for a variety of reasons, users continue to develop new AMODE-31 programs. Installations may have a large and growing amount of "below the bar" storage occupied by RMODE-31 programs. Users of such installations may wish to "free up" the below the bar storage by RMODE-31 programs in order to make more storage available for data, or to load more programs into the address space, or both.

[0006] This issue also applies to other cases where you need to run an application program that is built for a smaller memory address width than the runtime can support. Summary of the Invention

[0007] According to one aspect of the invention, there is provided a computer-implemented method for executing a small memory address width program within a large memory address width address space, the method including dividing a small memory address width program executable code into a set of portions, reserving a first virtual storage area in a portion of the address space accessed using the small memory address width addresses, reserving a set of second virtual storage areas in the portion of the address space accessed using the large memory address width addresses to accommodate the program executable code, and providing a relocation factor for a processor thread to convert from an address of the reserved first virtual storage area to one of the reserved second virtual storage areas that accommodates the executable code.

[0008] According to another aspect of the invention, there is provided a computer program product for executing a small memory address width program in a large memory address width address space, where at runtime of the program the method includes receiving an access request for executable code of the program on a processor thread, looking up a reserved first storage area for the processor thread in a portion of the address space accessed using the small memory address width addresses, looking up a relocation factor for the processor thread to obtain a relocation factor, and using the relocation factor to translate from an address of the reserved first storage area to one of a set of second virtual storage areas in the portion of the address space accessed using the large memory address width addresses corresponding to the program executable code, where the reserved second storage area accommodates the code to be executed in the reserved first storage area.

[0009] According to another aspect of the invention, there is provided a computer system for executing a small memory address width program within a large memory address width address space, the computer system including a processor, a memory configured to provide computer program instructions to the processor for performing functions of the component, and an address reservation component including a partitioning component for partitioning the small memory address width program executable code into a set of portions, a first storage area reservation component for reserving a first virtual storage area in a portion of the address space accessed with the small memory address width addresses, a second storage area reservation component for reserving a set of second virtual storage areas in a portion of the address space accessed with the large memory address width addresses to accommodate the program executable code, and a relocation factor providing component for providing a relocation factor for a processor thread to translate from an address in the reserved first virtual storage area to one of the reserved second virtual storage areas that accommodates the executable code.

[0010] The system can further include a runtime placement component including an access request receiving component for receiving an access request for the program executable code on the processor thread, a first storage area lookup component for looking up a relocation area register for the processor thread to identify a reserved first storage area, a relocation factor lookup component for looking up a relocation factor register for the processor thread to obtain a relocation factor, and an address translation component for using the relocation factor to translate from an address of the reserved first storage area to one of the reserved second storage areas that accommodates the code executing in the reserved first storage area.

[0011] According to another aspect of the invention, there is provided a computer program product for executing a small memory address width program within a large memory address width address space, the computer program product including a computer readable storage medium having program instructions embodied therein that are executable by a processor to cause the processor to divide small memory address width program executable code into a set of portions; reserving a first virtual storage area in a portion of the address space accessed with the small memory address width addresses; reserving a set of second virtual storage areas in a portion of the address space accessed with the large memory address width addresses to accommodate the program executable code; and providing a relocation factor for a processor thread to translate from addresses of the reserved first virtual storage areas to one of the reserved second virtual storage areas that accommodates the executable code.

[0012] According to another aspect of the invention, there is provided a computer program product for executing a small memory address width program in a large memory address width address space, the computer program product including a computer readable storage medium having program instructions embodied thereon that are executable by a processor to cause the processor to perform a method including receiving a request for access to executable code of the program on a processor thread; looking up a reserved first storage area for the processor thread in a portion of the address space accessed using the small memory address width addresses; looking up a relocation factor for the processor thread to obtain the relocation factor; and using the relocation factor to translate from an address of the reserved first storage area to one of a set of second virtual storage areas in the portion of the address space accessed using the large memory address width addresses corresponding to the program executable code, the reserved second storage area accommodating the code to be executed in the reserved first storage area.

[0013] The computer readable storage medium may be a non-transitory computer readable storage medium and the computer readable program code may be executable by a processing circuit. [Brief description of the drawings]

[0014] The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of this specification. The invention, both as to organization and method of operation, together with its objects, features, and advantages, may best be understood by reference to the following detailed description read in conjunction with the accompanying drawings.

[0015] Preferred embodiments of the invention will now be described, by way of example only, with reference to the following drawings:

[0016] [Figure 1] FIG. 2 is a flow diagram of an exemplary embodiment of a method according to the present invention. [Diagram 2] FIG. 2 is a flow diagram of an exemplary embodiment of one aspect of a method in accordance with the present invention. [Diagram 3] FIG. 4 is a flow diagram of an exemplary embodiment of another aspect of the method according to the present invention. [Figure 4] FIG. 2 is a schematic diagram for explaining the method according to the present invention. [Diagram 5] FIG. 1 is a block diagram of an exemplary embodiment of a system in accordance with the present invention. [Figure 6] FIG. 1 is a block diagram of one embodiment of a computer system or cloud server on which the present invention can be implemented.

[0017] It will be understood that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous features. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The described method and system allows small memory address width programs to reside outside of the small memory address width addressable portion of the address space and execute in a small memory address width addressing mode, thereby allowing small memory address width programs to execute on a large memory address width architecture while freeing up space in the small memory address width portion of the address space to utilize the larger available space in the large memory address width portion of the address space.

[0019] The terms "smaller memory-address width" and "larger memory-address width" addresses are used to describe any suitable combination of smaller and larger memory-address width addresses. In the described example, the smaller memory-address width addresses are 31-bit addresses and the larger memory-address width addresses are 64-bit addresses.

[0020] In the described method, for any one program, while it is executing, there are two virtual storage regions within the same address space: a first located in a portion of the address space where a small width of addresses is sufficient, and a second one of a set of regions located in a larger portion of the address space where a larger width of addresses is required. A relocation mechanism is provided that allows threads to use addresses in the first region to access executable code located in the second region.

[0021] Referring to FIG. 1, a flow diagram 100 illustrates an exemplary embodiment of the described method.

[0022] An application program of executable code with a small memory address width is divided into a set of parts (101). This division takes into account the links between parts to ensure that one part does not contain pointers to other parts. A single executable object of a statically linked program functions as one part because the object contains no pointers that point into other such objects. This insight simplifies the process of dividing up the application code. Furthermore, the division may contain multiple objects within the same part, and an existing object may be split into two objects, provided that the code of one object does not statically link to the code of the other object.

[0023] A first virtual storage area accessed by the small memory address width addresses is reserved (102) with a size at least sufficient to accommodate the largest of the set of code portions. A second set of storage areas that must be accessed by the large memory address width addresses is reserved (103). Each of the set of second storage areas may be the same size as the first area. Alternatively, the second storage areas may be allocated such that each matches the size of the application portion that each will accommodate.

[0024] The method provides (104) a relocation area register for the processor thread to identify a reserved first storage area, and provides (105) a relocation factor register having a relocation factor for the processor thread to access a set of second storage areas based on a translation of an address in the first storage area.

[0025] The software must provide these values ​​to the hardware, which keeps them available for its own use. The term "register" is used as a general term for memory locations used in this manner. One exemplary implementation may use fields in the Dispatched Unit Control Table (DUCT) of the z / Architecture (z / Architecture is a trademark of International Business Machines Corporation), which may also be described as registers.

[0026] At runtime, a method of executing an application program includes using a relocation mechanism to look up a relocation area register associated with a processor thread to identify an address in the reserved first storage area. The relocation mechanism also looks up a relocation factor register for the processor thread to provide a translation of the address in the first storage area to enable access to one of the set of second storage areas. This enables the thread to access executable code in one of the set of second storage areas using a small memory address width address. Different relocation factors are provided for different threads and for the same thread at different times to use the same first storage area to access different sets of second storage areas obtaining different executable code.

[0027] Taking 31-bit addressing mode (AMODE-31) and 64-bit addressing mode (64-AMODE) as an example, the method can access AMODE-31 executable code in above-the-bar virtual storage using below-the-bar virtual storage addresses. This allows the executable code to refer to itself (e.g., when branching or accessing constants) using 31-bit addresses. The executable code can still access data and other programs in below-the-bar storage using 31-bit addresses. In this way, executable code can run in AMODE-31 (RMODE-31) even though it resides in above-the-bar storage.

[0028] When a 31-bit address is used to access above-the-bar virtual storage that contains executable code, the relocation mechanism calculates a 64-bit address by adding a 64-bit displacement or relocation factor associated with the thread to the 31-bit address, the addition process being transparent to the executing code.

[0029] Different relocation factors can be used to allow different threads (or the same thread at different times) to access different above-the-bar storage that contains different executable code. In this way, the same range of below-the-bar virtual addresses can be used for different pieces of executable AMODE-31 code that reside in different ranges of above-the-bar virtual addresses.

[0030] Referring to Figure 2, a flow diagram 200 illustrates a more detailed exemplary embodiment of the described method. In this exemplary embodiment, the small memory address width addresses are 31-bit addresses and the first virtual storage space is "below-the-bar", i.e., in the first 2GB of address space, and the large memory address width addresses are 64-bit addresses and the second virtual storage space is "above-the-bar". The method described in connection with Figure 2 can be used for other pairs of small and large memory address width addresses.

[0031] The method divides the entirety of the application program executable code in 31-bit addressing mode into several parts 201. The details of this division to accommodate the links between the programs are described further below.

[0032] The method reserves 202 a below-the-bar storage region at least large enough to accommodate the largest of these portions. The method identifies 203 the reserved region in the below-the-bar storage using a relocation region register associated with the processor thread. For example, the relocation region register may contain an address and length of the region, or a start address and end address of the region. The relocation region register may be provided in much the same manner that an instruction address register is associated with a processor thread.

[0033] The method reserves (204) a set of regions of above-the-bar storage, each region being the same size as the reserved region of below-the-bar storage. The number of regions in the set of regions is at least equal to the number of portions obtained by partitioning the executable code. The method calculates (205) a relocation factor for each of the set of reserved above-the-bar regions, such that adding the relocation factor to an address at a displacement in the below-the-bar region results in an address at the same displacement in the above-the-bar region.

[0034] The method also associates the calculated relocation factors with processor threads (206) using relocation factor registers in much the same way that instruction address registers are associated with processor threads.

[0035] The method uses 207 the relocation mechanism to access the above-the-bar storage with relocation from a below-the-bar address in the below-the-bar storage.

[0036] 3, a flow diagram 300 illustrates an exemplary embodiment of a method for accessing instructions or data stored using the described storage methods. A relocation mechanism can perform the described access methods.

[0037] For any one program, while it is executing, there exist two virtual storage regions within the same address space: a first storage region located in a portion of the address space where a small address width is sufficient, and a second storage region is one of a set of regions located in a larger portion of the address space where a larger address width is required. A relocation mechanism is provided that allows threads to use addresses in the first storage region to access executable code located in the second storage region.

[0038] An access request is received (301) using a small memory address width addressing mode in a processor thread, and a lookup is performed (302) against a relocation region register for the processor thread to identify an access to storage within a first storage region of an address space where the small address width is sufficient.

[0039] The method looks up 303 a relocation factor register to obtain a relocation factor associated with the processor thread. The obtained relocation factor is applied 304 to an address of the small memory address width, and the resulting address is used 305 to access storage in the second storage region requiring an address of the larger width. The method is used for both instruction accesses and data accesses.

[0040] 4, a schematic diagram 400 illustrates the described method. An application program 410 is divided into n portions 411, with the largest portion 412 having size x. A divide 425 is provided in the virtual address space 420 between a small memory address width address space 423 and a remaining address space 424. When the small memory address width addresses are 31-bit addresses, the divide 425 is a "bar" in 2 GB.

[0041] A first region A 421 of size x is reserved in the small memory address width address space 423, and a set of n regions (regions B, C, ... M) 422 of size x are reserved in the remaining address space 424. A relocation region register 430 is provided to identify 431 the reserved region A 421 as being for the processor thread, and a relocation factor register 440 is provided to provide a relocation factor 441 for the processor thread to convert the first region address to one of the set of regions 422 in the remaining address space 424.

[0042] The described method allows a portion of an application's code to reside in one of the reserved areas of above-the-bar storage and run in AMODE-31. Any code executing in that processor thread accesses all storage within the above-the-bar area using 31-bit addresses in the reserved below-the-bar storage area. References to storage outside the above-the-bar area, such as calls to services provided by the runtime or operating system or references to data owned by the runtime or operating system, are not affected by the relocation process. The application's code, and any runtime code that the application calls, behaves in the same way as if the application code resided within the below-the-bar area.

[0043] The method uses the described capabilities to reduce the below-the-bar storage required for AMODE-31 application code. To accomplish this, the runtime uses different above-the-bar storage areas for different parts of the application code, but relocates the same range of below-the-bar addresses from the reserved below-the-bar area to these different above-the-bar storage areas.

[0044] The runtime ensures that there is a correct relocation factor in the relocation factor register for the processor thread that is using the application code within that portion. Because the relocation factor register is a hardware component, the runtime will call an operating system service to set its contents.

[0045] Divide your application code into parts The above embodiment does not allow one small memory address width application code portion to access storage in a different small memory address width application code portion. In other words, if one application program accesses the storage of another application program, both programs must reside in the same portion. The following discussion of aspects of dividing application code into portions addresses that.

[0046] When one application program calls another, it typically uses one of the following linking mechanisms for the entry and return point addresses:

[0047] The first mechanism provides static linking: the calling program "knows" the storage address of the called program's entry point. It branches to that address, passing the return address (within itself) as an argument. The called program returns by branching to its return address. It uses a linker or similar mechanism to use static libraries to combine a set of interlinked programs into a single executable object, which in the z / Architecture (z / Architecture is a trademark of International Business Machines Corporation), is sometimes called a load module. This means that statically linked calls and returns necessarily access storage that is in the same load module.

[0048] In the described method, the application code is divided into portions, each of which contains a single executable statically linked program object within one portion, i.e., a load module exists within one portion when the code is divided.

[0049] The second mechanism allows for dynamic linking, where the calling program does not know the storage address of the called program. In some cases, the runtime does not load the called program into memory until the call is issued. The calling program invokes the runtime service, passing a name or other token that identifies the entry point of the target program, and passing the return address, if applicable. The runtime service calls the target program after loading it into memory. This is dynamic linking, which allows interlinked programs to exist in different executable objects.

[0050] In the described method, dynamic linking calls and returns are handled by the runtime, which can consequently modify the relocation factor register as necessary, allowing different load modules to exist in different parts.

[0051] When one piece of code dynamically links to another, it is necessary to replace the relocation values ​​used in the linked piece of code with the values ​​required by the new piece of code, because the two pieces of code each sequentially use the same "first area", but different "second areas". Because the dynamic linking mechanism uses code that is not part of the application, that code is in a position to change values ​​in the relocation registers during the linking process.

[0052] A variation on dynamic linking involves the program that loads an application load module building a table containing the entry point addresses. Application programs in other load modules can load the required entry point addresses from the table and branch directly to the target program (somewhat similar to a static link call). The program that builds the table in this way can also be modified so that the table stores the address of a "glue" program rather than the address of the target entry point itself. The glue program can then invoke conventional dynamic linking, allowing the load module containing the target entry point to be located in a separate part of the program.

[0053] A calling program usually passes data to a called program as arguments, and the called program receives the arguments as parameters. Typically, arguments are either the address of the data (call by reference) or the value of the data (call by value).

[0054] In the case of a call by reference, the data itself may be within the calling program's part - if so, the calling program must either be in the same part as the called program or be excluded from the relocation process entirely.

[0055] In either case, the data may be an address: if it is the address of storage within the calling program's portion, then the calling program must either be in the same portion as the called program, or be excluded from the relocation process entirely.

[0056] Alternatively, the by-referenced data can be copied to dynamic storage and the call can be modified to pass the address of that dynamic storage instead. This can be accomplished by having the compiler generate different call logic, or by including "thunk" code statically or created by a linkage service at runtime.

[0057] If an application program is reentrant, the data within the program remains constant.

[0058] In summary, since direct references from one program to another are generally mediated by a linker (or similar) and are constrained within a load module, a load module is a natural choice for a part.

[0059] Links between different load modules do not necessarily prevent the load modules from being in separate parts; if they do, the called program and the calling program can be in the same part.

[0060] In some cases, if the target is widely used, it may be possible to include multiple copies of the target program in multiple parts, or to exclude the target from the relocation process entirely and treat it as a traditional RMODE small memory address width program.

[0061] 5, there is shown a computing system 500 including at least one processor 501 that is a hardware module or circuit for performing the functionality of the described components, which may be software units running on at least one processor. Multiple processors running parallel processor threads may be provided to allow parallel processing of some or all of the functionality of the components.

[0062] The memory 502 can be configured to provide computer instructions to at least one processor 501 to execute the functions of the component. A virtual storage space 520 is provided for accessing the stored executable code 503, along with associated relocation area registers 530 and relocation factor registers 540.

[0063] The computer system 500 includes an address reservation component 550 for providing the code address translation described herein, providing address relocation that allows small memory address width programs to reside outside of the small memory address width addressable portion of the large memory address width address space and execute in a small memory address width addressing mode.

[0064] The computer system 500 also includes a runtime relocation component 560 for providing address relocation during runtime to small memory address width programs executing in the small memory address width addressing mode while residing outside the small memory address width addressable portion.

[0065] Because relocation factor register 540 is a hardware component, runtime relocation component 560 can call operating system services to set its contents. The operating system can restrict which programs can set the relocation factor register, and a typical way to do this is to only allow operating system code to issue instructions to set the value. Thus, other code may need to invoke operating system services that set the required values ​​on its behalf.

[0066] The address reservation component 550 can include a partitioning component 551 for partitioning a small memory address width application program executable code into a set of portions. The partitioning component 551 can include a link handling component 552 for handling linking requirements upon partitioning, including providing a single executable object for statically linked programs in one portion.

[0067] The address reservation component 550 may include a first storage area reservation component 553 for reserving a first virtual storage area in a portion of an address space accessed using a small memory address width address, and a second storage area reservation component 554 for reserving a second set of storage areas in a portion of the address space accessed using a large memory address width address to accommodate program executable code.

[0068] The address reservation component 550 may include a relocation factor calculation component 557 for calculating a relocation factor for each processor thread of the set of second storage areas based on an address of the first storage area, such that adding the relocation factor to an address at a displacement in the first storage area results in an address at the same displacement in the second storage area.

[0069] The address reservation component 550 may include a relocation area providing component 555 for providing the relocation area register 530 to enable the processor thread to identify a reserved first storage area, and a relocation factor providing component 556 for providing a relocation factor register 540 having a relocation factor for the processor thread to access a set of second storage areas based on a translation of an address in the first storage area.

[0070] The runtime relocation component 560 may include an access request receive component 561 for receiving an access request for executable code of an application program on a processor thread. The runtime relocation component 560 may include a first storage area lookup component 563 for looking up the relocation area register 530 for the processor thread to identify the reserved first storage area, and a relocation factor lookup component 564 for looking up the relocation factor register 540 for the processor thread to obtain a relocation factor.

[0071] The runtime relocation component 560 may include a relocation mechanism 565 having an address translation component 566 for translating using the relocation factor from an address in the reserved first storage area to a set of second storage areas to access executable code in the set of second storage areas.

[0072] The runtime relocation component 560 may include a dynamic linking component 567 for modifying the relocation factor registers during runtime to accommodate dynamic linking calls and returns.

[0073] 6 illustrates a block diagram of components of a computing system 500 in accordance with an embodiment of the present invention. It should be understood that FIG. 6 is only intended to provide an illustration of one implementation and is not intended to imply any limitation with respect to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made.

[0074] The computing system may include one or more processors 602, one or more computer-readable RAMs 604, one or more computer-readable ROMs 606, one or more computer-readable storage media 608, device drivers 612, read / write drives or interfaces 614, and network adapters or interfaces 616, all interconnected over a communications fabric 618. The communications fabric 618 may be implemented with any architecture designed to pass data and / or control information between processors (such as microprocessors, communications and network processors), system memory, peripheral devices, and any other hardware components in the system.

[0075] One or more operating systems 610 and application programs 611, such as executable code address reservation component 550 and executable code runtime relocation component 560, are stored on one or more of the computer readable storage media 608 for execution by one or more of the processors 602 via one or more of the respective RAMs 604 (which typically include cache memory). In the illustrated embodiment, each of the computer readable storage media 608 may be a magnetic disk storage device of an internal hard drive, a CD-ROM, a DVD, a memory stick, a magnetic tape, a magnetic disk, an optical disk, a semiconductor storage device, such as a RAM, a ROM, an EPROM, a flash memory, etc., or any other computer readable storage medium capable of storing computer programs and digital information, in accordance with an embodiment of the present invention.

[0076] The computing system may also include a R / W drive or interface 614 for reading from and writing to one or more portable computer readable storage media 626. Application programs 611 on the computing system may be stored on one or more portable computer readable storage media 626 and read via the respective R / W drive or interface 614 and loaded into the respective computer readable storage media 608.

[0077] The computing system may also include a network adapter or interface 616, such as a TCP / IP adapter card or wireless communication adapter. Application programs 611 on the computing system may be downloaded to the computing device from an external computer or external storage device via a network (e.g., the Internet, a local area network or other wide area network or wireless network) and the network adapter or interface 616. From the network adapter or interface 616, the programs may be loaded into the computer readable storage medium 608. The network may include copper wire, fiber optic, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0078] The computing system may also include a display screen 620, a keyboard or keypad 622, and a computer mouse or touchpad 624. The device drivers 612 interface to the display screen 620 for imaging, to the keyboard or keypad 622, to the computer mouse or touchpad 624, or to the display screen 620 for alphanumeric character entry and pressure sensing of user selections, or combinations thereof. The device drivers 612, the R / W drive or interface 614, and the network adapter or interface 616 may include hardware and software stored in the computer readable storage medium 608 or in the ROM 606, or both.

[0079] The present invention may be a system, method, or computer program product, or combination thereof, at any possible level of technical detail integration. The computer program product may include a computer readable storage medium having computer readable program instructions for causing a processor to perform aspects of the present invention.

[0080] A computer readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanical coding devices such as punch cards or raised groove structures having instructions recorded thereon, and any suitable combination of the above. Computer-readable storage medium, as used herein, should not be construed as a transitory signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

[0081] The computer readable program instructions described herein may be downloaded from a computer readable storage medium into each computing / processing device or may be downloaded to an external computer or storage device, for example, via the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and transfers the computer readable program instructions to a computer readable storage medium in the respective computing / processing device for storage.

[0082] The computer readable program instructions for carrying out the operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine language instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object oriented programming languages ​​such as Smalltalk or C++, and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or a connection to an external computer may be made (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions by utilizing state information of the computer readable program instructions to individualize the electronic circuitry to perform aspects of the invention.

[0083] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0084] These computer readable program instructions may be provided to a computer processor or other programmable data processing apparatus to produce a machine such that the instructions executed by the computer processor or other programmable data processing apparatus create means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions may also be stored in a computer readable storage medium capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer readable medium having instructions stored therein includes an article of manufacture including instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0085] The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to generate a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus or other device implement the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0086] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or part of instructions, including one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may be performed in a different order than that noted in the figures. For example, two blocks shown in succession may in fact be accomplished in one step, may be performed simultaneously, may be performed substantially simultaneously, or the blocks may sometimes be performed in reverse order, in a partially or fully overlapped manner in time, depending on the functions involved. It should also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or may be performed by a combination of dedicated hardware and computer instructions.

[0087] The computer program product of the present invention includes one or more computer readable hardware storage devices having computer readable program code stored thereon, which is executable by one or more processors to perform the methods of the present invention.

[0088] The computer system of the present invention includes one or more processors, one or more memories, and one or more computer-readable hardware storage devices that contain program code executable by the one or more processors via the one or more memories to perform the methods of the present invention.

[0089] The description of various embodiments of the present invention is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements over the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0090] Improvements and modifications can be made to the foregoing without departing from the scope of the present invention.

Claims

1. A method for executing a small memory address width program in a large memory address width address space by a computer, comprising: Dividing a small memory address width program executable code into a set of portions; reserving a first virtual storage area in a portion of an address space accessed using small memory address width addresses; reserving a second set of virtual storage areas in a portion of the address space accessed using large memory address width addresses to accommodate the program executable code; providing a relocation factor for a processor thread to translate from an address in the first reserved virtual storage area to an address in one of the second reserved virtual storage areas containing the executable code; The method includes:

2. providing a relocation area register to enable the processor thread to identify the reserved first virtual storage area; providing a relocation factor register having the relocation factor for the processor thread; The method of claim 1 , comprising:

3. 2. The method of claim 1, wherein reserving the first virtual storage area comprises reserving an area large enough to accommodate the largest of the set of portions of the program executable code, and wherein different relocation factors are provided for different threads and for the same thread at different times to access different sets of second virtual storage areas using the same first virtual storage area to obtain different executable code.

4. 2. The method of claim 1, wherein the relocation factor adds a displacement to a small memory address width address in the first virtual storage area to calculate a large memory address width address in one of the second virtual storage areas.

5. 2. The method of claim 1, further comprising: calculating a relocation factor for a processor thread for each of the set of second virtual storage areas based on the address of the first virtual storage area, wherein adding the relocation factor to an address at a displacement in the first virtual storage area results in an address at the same displacement in the second virtual storage area.

6. 2. The method of claim 1, wherein dividing the small memory address width program executable code into a set of portions comprises providing a single object of executable statically linked program in one portion.

7. 2. The method of claim 1, wherein dividing the small memory address width program executable code into a set of portions includes providing the calling program within the same portion as the called program.

8. 2. The method of claim 1, wherein the small memory address width address is one of the group of an 8-bit address, a 16-bit address, a 24-bit address, a 31-bit address, or a 32-bit address, and the large memory address width address is a 32-bit address or a 64-bit address.

9. 2. The method of claim 1, wherein the smaller memory address width addresses are 31-bit addresses and the larger memory address width addresses are 64-bit addresses, the first virtual storage area is within a first 2 GB of address space, and the second set of virtual storage areas is beyond the first 2 GB of address space.

10. A computer program for executing a small memory address width program in a large memory address width address space, the computer program comprising: receiving a request for access to executable code of the small memory address width program on a processor thread; looking up a reserved first virtual storage area for the processor thread in a portion of an address space accessed using a small memory address width address; looking up a relocation factor for the processor thread to obtain a relocation factor; using the relocation factor to translate from an address in the reserved first virtual storage area to an address in one of a set of second virtual storage areas in a portion of an address space accessed using large memory address width addresses corresponding to the executable code, the reserved second virtual storage area accommodating code executing in the reserved first virtual storage area; A computer program for causing a computer to carry out a method comprising:

11. looking up the reserved first virtual storage area includes looking up a relocation area register for the processor thread; 11. The computer program product of claim 10, wherein looking up a relocation factor comprises looking up a relocation factor register of the processor thread to obtain a relocation factor for the processor thread.

12. 11. The computer program product of claim 10, wherein converting using a relocation factor comprises adding a displacement to a small memory address width address in the first virtual storage area to calculate a large memory address width address in one of the second virtual storage areas.

13. 11. The computer program product of claim 10, further comprising modifying the relocation factor register during run-time to accommodate dynamic link calls and returns.

14. 1. A computer system for executing small memory address width programs in a large memory address width address space, comprising: a processor and a memory configured to provide computer program instructions to the processor to perform the functions of the component; Address Reservation Component and the address reservation component comprising: a partitioning component for partitioning the small memory address width program executable code into a set of portions; a first storage area reservation component for reserving a first virtual storage area in a portion of an address space accessed using small memory address width addresses; a second storage area reservation component for reserving a second set of virtual storage areas in a portion of the address space accessed using large memory address width addresses to accommodate program executable code; a relocation factor providing component for providing a relocation factor for a processor thread to translate from an address in a reserved first virtual storage area to an address in one of the reserved second virtual storage areas that accommodates the executable code; 1. A computer system comprising:

15. the address reservation component: a relocation area providing component for providing a relocation area register to enable a processor thread to identify the reserved first virtual storage area; the relocation factor providing component providing a relocation factor register having a relocation factor for the processor thread; 15. The computer system of claim 14.

16. the address reservation component:

15. The computer system of claim 14, further comprising a relocation factor calculation component for calculating a relocation factor for a processor thread for each of the set of second virtual storage areas based on an address of the first virtual storage area, wherein adding the relocation factor to an address at a displacement in the first virtual storage area results in an address at the same displacement in the second virtual storage area.

17. 15. The computer system of claim 14, wherein the splitting component includes a link handling component for handling linking requirements upon splitting to provide a single object of an executable statically linked program in one portion.

18. The method further includes the step of: an access request receiving component for receiving an access request for executable code of a program on a processor thread; a first storage area lookup component for looking up the relocation area register for the processor thread to identify a reserved first virtual storage area; a relocation factor lookup component for looking up a relocation factor register for a processor thread to obtain a relocation factor; an address translation component for translating, using the relocation factor, from an address in the first reserved virtual storage area to an address in one of the second reserved virtual storage areas that accommodates code executing in the first reserved virtual storage area; 16. The computer system of claim 15, comprising:

19. 20. The computer system of claim 18, wherein the runtime relocation component includes a dynamic linking component for modifying relocation factor registers during runtime to accommodate dynamic linking calls and returns.

20. 20. The computer system of claim 18, wherein the runtime relocation component calls an operating system service to set the relocation factor register.

21. A computer-readable storage medium storing a computer program according to any one of claims 10 to 13.

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