Plastic package cavity structure and method for fabricating same

Abstract

To provide a plastic packaged cavity structure which has high accuracy, can be reduced in packaging volume, and has high packaging efficiency, and a manufacturing method thereof.SOLUTION: A plastic packaged cavity structure includes: an embedded packaging frame having a first cavity and a first via pillar 102 reach penetrating an insulation layer along a height direction; a chipset provided within the first cavity, and having first and second chips 210, 220; a first circuit layer 500 provided on an upper surface of the embedded packaging frame; a first medium layer 700 provided on the first circuit layer; a second circuit layer 800 on the first medium layer; a through via hole 103 penetrating the first medium layer and the insulation layer; a second cavity 340 on a lower surface of the embedded packaging frame; a support pillar wall 310 in the second cavity; and a plastic packaging layer 300 formed along the outside of the support pillar wall. The second cavity communicates with the through via hole.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present application relates to the technical field of electronic component packaging, and in particular to a plastic package cavity structure and method for making the same. [Background technology]

[0002] MEMS (Micro-Electro-Mechanical System) sensors are widely used in the fields of medicine, automobiles, communications and computers, and MEMS sensors include MEMS microphones, MEMS barometers, MEMS thermometers and hygrometers, MEMS gas sensors, etc. The packaging structure mainly includes a packaging substrate, a MEMS sensing chip, an ASIC (Application Specific Integrated Circuit) chip, a protective casing and a passage for realizing the environmental detection of the MEMS sensing chip, and since electronic products are currently showing a trend of miniaturization and thinning, there is a demand for miniaturization and high-density integration of the MEMS sensing packaging structure.

[0003] The conventional packaging of MEMS sensors and ASIC chips mainly involves mounting the MEMS sensing chip and ASIC chip on a packaging substrate, and using methods such as wire bonding to realize electrical connection between the MEMS sensing chip, ASIC chip and the packaging substrate, and then mounting a protective casing to protect the packaged components, and pre-setting a through via hole in the substrate or protective casing to realize interaction between the MEMS sensing chip and the external environment. Therefore, the conventional plastic package cavity structure has the following problems: The packaging volume is large, which cannot meet the development needs of miniaturization and thinning of semiconductor packaging; Each sensor unit needs to be provided with a protective cover, so the processing efficiency is low and the cost is high; The method of providing a protective cover has poor processing precision and cannot meet the development needs of high-density packaging. Summary of the Invention [Problem to be solved by the invention]

[0004] In view of this, the objective of the present application is to propose a plastic package cavity structure and a method for fabricating the same. [Means for solving the problem]

[0005] In view of the above objectives, the present application provides a method for fabricating a plastic package cavity structure, comprising the following steps: (a) providing an embedded packaging frame, the embedded packaging frame including a first cavity and a first via pillar each penetrating an insulating layer along a height direction; (b) embedding a chip set in a bottom portion of the first cavity, the chip set including a first chip and a second chip that are stacked, and bonding the back surfaces of the first chip and the second chip to each other so that the terminal surfaces of both chips face each other back to back; (c) forming a packaging layer in a gap between the chip set and the first cavity, the packaging layer having a blind via exposing a terminal of the second chip; (d) forming a first circuit layer and a second via pillar on the upper surface of the embedded packaging frame, the first circuit layer being conductively connected to a terminal of the second chip; (e) laminating a first medium layer on the top surface of the first circuit layer and aligning a top surface of the first medium layer with a top surface of the second via pillar; (f) forming a second circuit layer on a top surface of the first medium layer and a third circuit layer on a bottom surface of the embedded packaging frame, forming a support pillar wall in the third circuit layer surrounding the first cavity; (g) forming a through via hole penetrating the first medium layer and the insulating layer in this order along a height direction, the through via hole being surrounded by the support pillar wall; (h) forming a plastic package layer below the embedded packaging frame and along an outer side of the support pillar wall, forming a second cavity between the plastic package layer and the embedded packaging frame;

[0006] An embodiment of the present application also provides a plastic package cavity structure, including: an embedded packaging frame having a first cavity and a first via pillar respectively penetrating an insulating layer along a height direction; a chipset provided in the first cavity; a first circuit layer provided on an upper surface of the embedded packaging frame; a first medium layer provided on the first circuit layer; a second circuit layer provided on the first medium layer; a through via hole penetrating the first medium layer and the insulating layer; a third circuit layer on a lower surface of the embedded packaging frame; a support pillar wall on the third circuit layer; and a plastic package layer formed along an outer side of the support pillar wall; A second cavity communicating with the through via hole is formed between the plastic package layer and the lower surface of the embedded packaging frame, and the chip set includes a first chip and a second chip stacked back to back. Effect of the Invention

[0007] As can be seen from the above description, the plastic package cavity structure provided by the embodiments of the present application stacks a chip set consisting of a first chip and a second chip arranged in a stacked manner, embeds it inside a packaging substrate, and packages it, thereby achieving electrical connection with the packaging substrate through blind vias in the packaging layer, and by processing copper pillar walls on the upper part (i.e., the lower surface) of the embedded packaging substrate, a second cavity can be formed after packaging, and sensing of the external environment is achieved through the second cavity and the through via holes, thereby achieving high-density integrated packaging, and has advantages such as high precision, small packaging volume, and high packaging efficiency. [Brief description of the drawings]

[0008] In order to more clearly describe the technical solutions in the present application or related art, the following briefly introduces the drawings used in the description of the embodiments or related art. Needless to say, the drawings described below are only the embodiments of the present application, and those skilled in the art can obtain other drawings from these drawings without novel work. [Figure 1] FIG. 1 shows a structural schematic diagram of the main packaging methods of MEMS sensors and ASIC chips in the prior art. [Diagram 2] FIG. 2 shows a cross-sectional view of a plastic package cavity structure provided by an embodiment of the present application. [Figure 3a] 3A-3C are schematic cross-sectional views of intermediate structures in steps of a manufacturing method of a plastic package cavity structure according to an embodiment of the present application. [Figure 3b] 3b shows schematic cross-sectional views of intermediate structures in each step of a manufacturing method of a plastic package cavity structure according to an embodiment of the present application. [Figure 3c] 3C shows schematic cross-sectional views of intermediate structures in each step of a manufacturing method of a plastic package cavity structure according to an embodiment of the present application. [Figure 3d] 3D shows schematic cross-sectional views of intermediate structures in each step of a manufacturing method of a plastic package cavity structure according to an embodiment of the present application. [Figure 3e] 3E shows schematic cross-sectional views of intermediate structures in each step of a manufacturing method of a plastic package cavity structure according to an embodiment of the present application. [Figure 3f] 3f shows schematic cross-sectional views of intermediate structures in each step of a manufacturing method of a plastic package cavity structure according to an embodiment of the present application. [Figure 3g] 3g shows schematic cross-sectional views of intermediate structures in each step of a manufacturing method of a plastic package cavity structure according to an embodiment of the present application. [Figure 3h] 3H shows schematic cross-sectional views of intermediate structures in each step of a manufacturing method of a plastic package cavity structure according to an embodiment of the present application. [Figure 3i]3i shows schematic cross-sectional views of intermediate structures in each step of a manufacturing method of a plastic package cavity structure according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the present application will be described in more detail using specific embodiments and with reference to drawings, so that the objectives, technical solutions and advantages of the present application will be more apparent.

[0010] Unless otherwise defined, technical or scientific terms used in the embodiments of the present application have the common meanings understood by those skilled in the art. The terms "first", "second" and similar terms used in the embodiments of the present application do not denote any order, quantity or importance, but are used to distinguish different components. The term "comprises" or similar terms means that the element or object appearing before the term covers the elements or objects listed after the term and their equivalents, but does not exclude other elements or objects. The term "connected" or similar terms is not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are used to express only relative positional relationships, and if the absolute position of the object being described is changed, the relative positional relationships may change accordingly.

[0011] FIG. 1 shows a structural schematic diagram of the main packaging methods of MEMS sensors and ASIC chips in the prior art.

[0012] As shown in FIG. 1, in some major packaging methods for MEMS sensors and ASIC chips, multiple units are formed by electrically connecting the MEMS sensing chip and ASIC chip to the packaging substrate by bonding wires, and a protective cover is provided for each unit to protect them and form a cavity, thereby achieving packaging.

[0013] That is, in the conventional packaging method for MEMS sensors and ASIC chips, a protective cover must be provided for each unit, which results in problems such as low processing efficiency and high costs. In addition, the method of providing a protective cover has problems such as poor processing precision and cannot meet the needs of developing high-density packaging. In addition, the packaging volume is large, which cannot meet the needs of developing smaller and thinner semiconductor packaging.

[0014] In view of this, the embodiments of the present application provide a method for fabricating a plastic package cavity structure, and a plastic package cavity can be formed after packaging by processing a copper pillar wall on the upper part of an embedded packaging substrate. The conventional plastic package cavity structure requires a protective cover for each unit, which results in low processing efficiency, high cost, poor processing accuracy, and inability to meet the development needs of high-density packaging, and the packaging volume is large, which cannot meet the development needs of miniaturization and thinning of semiconductor packaging. This can solve the problems to some extent.

[0015] FIG. 2 shows a cross-sectional view of a plastic package cavity structure provided by an embodiment of the present application.

[0016] 2, the plastic package cavity structure provided by the embodiment of the present application may include an embedded packaging frame, a chip set embedded in the embedded packaging frame, and a plastic package layer 300 surrounding the lower surface of the embedded packaging frame. The chip set includes a first chip 210 and a second chip 220 stacked together, and terminals of the first chip 210 and the second chip 220 are back-to-back.

[0017] The plastic package cavity structure includes a first cavity and a first via pillar 102 that respectively penetrate the insulating layer of the embedded packaging frame along the height direction. The chipset is disposed in the first cavity, and further includes a packaging layer 400 disposed in a gap between the chipset and the first cavity, a first circuit layer 500 and a second via pillar 600 disposed on the upper surface of the embedded packaging frame, a first medium layer 700 and a second circuit layer 800 disposed on the first circuit layer 500, and further includes a through via hole 103 that penetrates the first medium layer 700 and the insulating layer of the embedded packaging frame in this order.

[0018] The embedded packaging frame further includes a third circuit layer provided on the lower surface of the embedded packaging frame and a support pillar wall 310 provided around the lower surface of the embedded packaging frame, and the third circuit layer may include a functional circuit layer 910 and a circuit wall 920, and the support pillar wall 310 may be provided correspondingly on the circuit wall 920. That is, the support pillar wall is provided on the third circuit layer. A passive element 250 is provided on the lower surface of the third circuit layer, and a plastic package layer 300 is provided on the lower surface of the embedded packaging frame and on the outside of the third circuit layer and the support pillar wall 310, that is, the plastic package layer 300 is formed along the outside of the support pillar wall. A second cavity 340 communicating with the through via hole 103 is provided between the plastic package layer 300 and the lower surface of the embedded packaging frame.

[0019] It should be understood that multiple chipsets may be provided, and can be specifically determined according to actual needs. Correspondingly, multiple first cavities may be provided, and each is used to embed multiple chipsets. The second cavity 340 formed between the plastic package layer 300 and the lower surface of the packaging substrate can cover all the chipsets, thereby realizing the formation of a high-density integrated packaging.

[0020] The plastic package cavity structure provided by the embodiment of the present application stacks a chip set consisting of a first chip 210 and a second chip 220 arranged in a stacked manner, embeds it inside a packaging substrate, and packages it, thereby achieving electrical connection with the packaging substrate through blind vias in the packaging layer 400, and forming a plastic package cavity after packaging by processing a copper pillar wall on the upper part (i.e., the lower surface) of the embedded packaging substrate, thereby achieving high-density integrated packaging, with advantages such as high precision, compact packaging volume, and high packaging efficiency.

[0021] In some embodiments, the embedded packaging frame is a polymer frame. The frame may be made of a polymer used as a polymer sheet or a glass fiber reinforced polymer used as a prepreg. It may comprise one or more layers.

[0022] The via pillar (e.g., the first via pillar 102 or the second via pillar 600) referred to in this embodiment may include at least one copper pillar with a through via hole as an IO channel, thereby realizing conduction between layers, and the sizes and / or shapes of the multiple via pillars may be the same or different. The via pillar may be a solid copper pillar or a hollow pillar with copper plating on the surface, and preferably the via pillar includes multiple copper pillars with a through via hole as an IO channel, and the ends of the via pillar may be aligned with the packaging layer.

[0023] In the chip set, the first chip 210 may be a sensing chip (e.g., a MEMS sensing chip) having a plurality of terminals 211 and one sensing component 212. And the terminal surface of the first chip 210 is mounted on the bottom of the first cavity. The surface of the sensing component 212 is exposed, that is, the surface of the sensing component is not covered by the third circuit layer. That is, the surface of the sensing component of the first chip is exposed to the second cavity and communicates with the outside through the through via hole. Thus, the sensing chip can detect an external environmental load through the second cavity 340 and the through via hole 103, and then output an electrical signal to the second chip 220.

[0024] The second chip 220 and the first chip 210 may be connected by a viscous material 230. The size (e.g., length) of the second chip 220 may be smaller than that of the first chip 210 and the viscous material 230, and the size of the viscous material 230 may be the same as that of the first chip 210. The viscosity of the viscous material 230 may exceed the viscosity of the packaging layer 400, thereby avoiding damage to the chip when the packaging layer 400 is pressed against the viscous material 230 because it is too hard. The second chip 220 may be an ASIC chip, which can amplify the electrical signal output by the MEMS chip and modulate it into a predetermined standard output signal.

[0025] In some embodiments, the device further includes a second medium layer 350 disposed between the plastic package layer 300 and the third circuit layer and the support pillar wall 310. That is, a second medium layer is further included between the plastic package layer 300 and the second cavity. The second medium layer 350 may be a conformal coating film. The conformal coating film may be a polytetrafluoroethylene (PTFE) film or a polyimide (PI) film, etc. In this way, the plastic package layer 300 can be conformally coated better by the conformal coating film, and stress can be efficiently released.

[0026] In some embodiments, the support pillar wall 310 may be a copper support pillar wall, which can provide support and heat dissipation. When a surface of an embedded packaging frame is taken as a reference plane, the orthogonal projection of the support pillar wall 310 on the reference plane partially overlaps with the orthogonal projection of the circuit wall 920 on the reference plane.

[0027] In some embodiments, a second metal seed layer may be provided between the embedded packaging frame and the first circuit layer 500, and a first metal seed layer may be further provided between the embedded packaging frame and the third circuit layer, thereby improving the stability and reliability of the electrical continuity and connection between the first via pillar 102 and the first circuit layer 500, and improving the stability and reliability of the electrical continuity and connection between the first via pillar 102 and the third circuit layer.

[0028] In some embodiments, a third metal seed layer may be further provided between the first medium layer 700 and the second circuit layer 800. This can improve the stability and reliability of the electrical continuity and connection between the second via pillar 600 and the first circuit layer 500 and the second circuit layer 800.

[0029] Referring to FIGS. 3a to 3i, schematic cross-sectional views of intermediate structures in each step of a method for fabricating a plastic package cavity structure according to an embodiment of the present application are shown.

[0030] The manufacturing method includes the following steps: Step (a) is to prepare an embedded packaging frame 100, which includes a first cavity 101 and a first via pillar 102 respectively penetrating the embedded packaging frame along a height direction, as shown in Fig. 3a.

[0031] In general, multiple first cavities 101 may be provided for later chipset implementation, and the size of the multiple first cavities 101 may be the same or different, which is determined by the shape and size of the chipset to be embedded, and is not limited here. The embedded packaging frame 100 may be made of a polymer used as a polymer sheet or a glass fiber reinforced polymer used as a prepreg. It may have one or multiple layers.

[0032] In general, the embedded packaging frame 100 can be manufactured by pattern plating or panel plating using Zhuhai Yueya's through via hole pillar technology, followed by selective etching to manufacture through via holes as via pillars, and then laminated using dielectric materials such as polymer films or prepregs composed of woven glass fiber bundles in a polymer matrix to improve stability. In one embodiment, the dielectric material is Hitachi 705G. In another embodiment, MGC832 NXA NSFLCA is used. In another embodiment, Sumitomo GT-K can be used. In another embodiment, Sumitomo LAZ-4785 series films are used. In another embodiment, Sumitomo LAZ-6785 series are used. Alternative materials include Taiyo's HBI and Zaristo-125 or Ajinomoto's ABF GX material series.

[0033] There are many advantages to using through via hole pillars to manufacture via pillars rather than drill and fill technology. Through via hole pillar technology can manufacture all through via holes at the same time, whereas drill and fill technology requires drilling holes separately, so through via hole pillar technology is faster. Also, all drilled through via holes are cylindrical, but through via hole pillars can be of any shape. In practice, all drilled and filled through via holes have the same size (within tolerance range), but through via hole pillars can have different shapes and sizes. And, to increase strength, the polymer matrix is ​​preferably fiber reinforced, typically using braided glass fiber bundles for reinforcement. After the prepreg containing fibers in the polymer is coated on the upright through via hole pillars and cured, the through via hole pillars are characterized by having smooth vertical sides. However, when drilling holes in composite materials, the drill and fill through via holes are typically inclined and typically have rough surfaces, which induce stray inductance and lead to noise.

[0034] Typically, the first via pillars 102 have a width in the range of 25-500 μm. If cylindrical, as is required for drill-and-fill and is typical for via pillars, each via pillar may have a diameter of 25-500 μm.

[0035] Then, as shown in FIG. 3b, a chipset is embedded in the bottom of the first cavity 101--step (b).

[0036] Generally, embedding a chipset in the bottom of the first cavity 101 in step (b) includes: (b 1 2.) Apply an adhesive layer 240 to the lower surface of the embedded packaging frame 100. Generally, the adhesive layer 240 can be a single-sided adhesive tape, which is generally a commercially available thermally decomposable or ultraviolet radiation decomposable transparent film, and the adhesive layer 240 can temporarily support and fix the chipset.

[0037] (b 2 ) The terminal surface of the second chip 220 of the chipset is attached to the adhesive layer 240 exposed in the first cavity 101, thereby mounting the chipset on the bottom of the first cavity 101. The chipset includes a first chip 210 and a second chip 220 that are stacked, the terminal surfaces of the first chip 210 and the second chip 220 are back-to-back, and the terminal surface of the first chip 210 is mounted on the bottom of the first cavity. In general, the height of the chipset may be smaller than the height of the first cavity, so that the packaging layer 400 can be formed on the chipset by a later process, and the chipset can withstand a load applied to the chipset when other layered structures are manufactured on the surface of the embedded packaging frame, thereby avoiding damage to the chipset. In general, the rear surfaces of the first chip 210 and the second chip 220 may be adhered with a viscous material 230.

[0038] Then, forming a packaging layer 400 in the gap between the chipset and the first cavity 101--step (c), as shown in Figure 3d. In general, this step may include: (c 1 3c, a packaging layer 400 is formed in the gap between the chipset and the first cavity 101 and on the upper surface of the embedded packaging frame 100. In general, the packaging layer 400 may be selected from a pure resin.

[0039] (c 2) The packaging layer 400 is thinned to expose the upper surfaces of the first via pillars 102 of the embedded packaging frame 100 and the upper surface of the embedded packaging frame 100, and the upper surface of the packaging layer 400 is aligned with the upper surfaces of the first via pillars 102 and the upper surface of the embedded packaging frame 100. This allows the upper surface of the embedded packaging frame 100 to have good flatness, which avoids the difficulty of build-up conduction caused by unevenness of components and is useful for later fabrication of the first circuit layer 500, etc. on the upper surface of the embedded packaging frame 100. Generally, the packaging material can be thinned by methods such as grinding or plasma etching.

[0040] (c 3 2) A window is made in the terminal 221 of the second chip 220, and a blind via 410 is formed in the packaging layer 400. In general, the blind via 410 is connected to the terminal 221 of the second chip 220, which serves for electrical connection between the second chip 220 and the first circuit layer 500 to be fabricated later. This allows the electrical connection between the chipset and the packaging substrate to have a high degree of integration and stability. In general, a window is made in the terminal 221 of the second chip 220 by laser drilling, etc., and the blind via 410 is formed.

[0041] Then, as shown in Fig. 3e, a first circuit layer 500 and a second via pillar 600 are formed on the upper surface of the embedded packaging frame 100--step (d). Generally, step (d) includes: (d 1 ) A second metal seed layer is formed on the upper surface of the embedded packaging frame 100 and on the bottom and sidewall of the blind via 410, and generally, the second metal seed layer is formed by a sputtering process. The material of the second metal seed layer is not specifically limited and can be determined according to actual needs, and generally may be titanium or copper.

[0042] (d 2) applying a third photoresist layer to the second metal seed layer and exposing and developing the third photoresist layer to form a third feature pattern; (d 3 ) Electroplating is performed on the third feature pattern to form a first circuit layer 500. In general, the first circuit layer 500 is connected to a terminal surface of the second chip 220, (d 4 ) removing the third photoresist layer, applying a fourth photoresist layer to the second metal seed layer, and exposing and developing the fourth photoresist layer to form a fourth feature pattern; (d 5 ) forming second via pillars 600 by electroplating in the fourth feature pattern, and generally, the second via pillars 600 may be provided corresponding to the first via pillars 102; (d 6 ) removing the third and fourth photoresist layers and etching the exposed second metal seed layer;

[0043] Next, a first medium layer 700 is laminated on top of the first circuit layer 500 - step (e), as shown in Figure 3f. Generally, step (e) includes: A first medium material is laminated on the top surface of the first circuit layer 500. In general, the height of the first medium material exceeds the height of the second via pillar 600. This helps to align the end face of the second via pillar 600 with the first medium layer 700 in preparation for the fabrication of a hierarchical structure later by thinning the exposed second via pillar 600.

[0044] The first medium material is thinned to expose the top surface (end surface) of the second via pillar 600, forming a first medium layer 700 whose top surface is flush with the top surface of the via pillar. In general, the first medium material can be thinned by methods such as grinding or plasma etching.

[0045] 3g, a second circuit layer 800 is formed on the upper surface of the first medium layer 700, and a third circuit layer and a support pillar wall 310 are formed on the lower surface of the embedded packaging frame to surround the embedded packaging frame--step (f). In general, forming the second circuit layer 800 on the upper surface of the first medium layer 700 in step (f) includes: (f 1 ) A third metal seed layer is formed on the upper surface of the first medium layer 700. Generally, the third metal seed layer is formed by a sputtering process. The material of the third metal seed layer is not specifically limited and can be determined according to actual needs. Generally, it can be titanium or copper. (f 2 ) applying a fifth photoresist layer to the third metal seed layer and exposing and developing the fifth photoresist layer to form a fifth feature pattern; (f 3 ) forming a second circuit layer 800 by electroplating in the fifth feature pattern, the second circuit layer 800 being connected to the first circuit layer 500 by the second via pillar 600; (f 4 ) stripping the fifth photoresist layer and etching the exposed third metal seed layer.

[0046] Generally, in step (f), forming a third circuit layer on the lower surface of the embedded packaging frame and a support pillar wall 310 surrounding the embedded packaging frame includes: (f 5 ) removing the adhesive layer 240 applied to the bottom surface of the embedded packaging frame; (f 6 ) A first metal seed layer is formed on the lower surface of the embedded packaging frame, and the first metal seed layer is generally formed by a sputtering process. The material of the first metal seed layer is not specifically limited and can be determined according to actual needs, and generally can be titanium or copper; (f 7) applying a first photoresist layer to the first metal seed layer and exposing and developing the first photoresist layer to form a first feature pattern; (f 8 ) Electroplating is performed on the first feature pattern to form a third circuit layer, which may include a functional circuit layer 910 and a circuit wall 920, and a support pillar wall 310 may be correspondingly provided on the circuit wall 920, such that the surface of the sensing component 212 of the first chip 210 is exposed, i.e., the surface of the sensing component is not covered by the third circuit layer.

[0047] (f 9 ) removing the first photoresist layer, applying a second photoresist layer to the first metal seed layer, and exposing and developing the second photoresist layer to form a second feature pattern; (f 10 3h, electroplating is performed on the second feature pattern to form support pillar wall 310. In general, the support pillar wall 310 may be a copper support pillar wall 310, which can provide support and heat dissipation. When a surface of the embedded packaging frame is taken as a reference plane, the orthogonal projection of the support pillar wall 310 on the reference plane partially overlaps with the orthogonal projection of the circuit wall 920 on the reference plane.

[0048] (f 11 ) stripping the second photoresist layer and etching the exposed first metal seed layer.

[0049] Next, as shown in Fig. 3i, a through via hole 103 is formed in the height direction through the first medium layer 700 and the embedded packaging frame in this order to form a first packaging structure having the chipset and a second packaging structure not having the chipset - step (g). In general, the through via hole 103 can be formed by a method such as drilling using a machine, and the through via hole 103 and the first chip 210 (i.e., the sensing chip) can detect an external environmental load and then output an electrical signal to the second chip 220.

[0050] 2, a passive component 250 is mounted on the underside of the second packaging structure, and a plastic package layer 300 is formed on the underside of the embedded packaging frame and on the outside of the circuit wall 920 and the support pillar wall 310 - step (h). In general, the passive component 250 may be mounted on the underside of the functional circuit layer 910 in the third circuit layer.

[0051] Generally, forming a plastic package layer 300 on the underside of the embedded packaging frame and outside the circuit wall 920 and the support pillar wall 310 includes: A second medium layer 350 is laminated on the lower surface of the embedded packaging frame and on the outside of the circuit wall 920 and the support pillar wall 310 to form a second cavity 340 for accommodating the passive element 250. Thus, the first chip 210 (i.e., MEMS sensing chip) in the chipset can sense an external environmental load through the second cavity 340 and the through via hole 103, and then output an electrical signal to the second chip 220 (i.e., ASIC chip). The ASIC chip amplifies the electrical signal output by the MEMS chip and modulates it to a predetermined standard output signal. In general, the second medium layer 350 may be a conformal coating film. The use of the conformal coating film can play a role of protection and isolation. In addition, the plastic package layer 300 has high transparency and smoothness, and has heat resistance, weather resistance, antistatic performance, etc.

[0052] A plastic package layer 300 is laminated onto the surface of the second medium layer 350 .

[0053] The plastic package cavity structure and its manufacturing method provided by the embodiment of the present application realizes high-density integrated packaging by stacking the MEMS sensing chip and the ASIC chip, embedding them inside the packaging substrate, and packaging them. By processing the copper pillar wall on the upper part of the embedded packaging substrate, a plastic package cavity can be formed after packaging, and the sensing part of the MEMS sensing chip is exposed, and sensing of the external environment is realized by the plastic package cavity structure and the hole penetrating the substrate. This solves the technical problems of the prior art, such as low efficiency, high cost, poor accuracy, and inability to reduce the packaging volume. It has the following advantages: High-density integrated packaging of the MEMS sensing chip and the ASIC chip can be realized, the processing efficiency is improved and the cost is reduced by the panel level processing of the plastic package cavity structure, and the plastic package cavity is formed by providing the copper pillar wall and compressing the conformal coating film and packaging, which has higher processing accuracy than the cavity formed by the protective cover, and can meet the needs of high-density integrated packaging.

[0054] Those skilled in the art will understand that the discussion of any of the above embodiments is merely illustrative, and does not imply that the scope of the present disclosure (including claims) is limited to these examples. Under the spirit of the present disclosure, the technical features of the above embodiments or different embodiments may be combined with each other, steps may be performed in any order, and there may be many other variations of different aspects of the above embodiments of the present disclosure, which are not provided in the detailed description for the sake of simplicity.

[0055] While the present disclosure has been described using specific embodiments thereof, it is understood that many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the above description.

[0056] The embodiments of the present disclosure are intended to include all such replacements, amendments, and modifications that fall within the broad scope of the claims. Therefore, any omissions, amendments, equivalent replacements, improvements, etc. that fall within the spirit and principles of the embodiments of the present disclosure are intended to be included in the scope of the claims of the present disclosure. [Explanation of symbols]

[0057] 100 embedded packaging frame, 101 first cavity, 102 first via pillar, 103 through via hole, 210 first chip, 211 terminal, 212 sensing component, 220 second chip, 221 terminal, 230 viscous material, 240 adhesive layer, 250 passive element, 300 plastic package layer, 310 support pillar wall, 340 second cavity, 350 second medium layer, 400 packaging layer, 410 blind via, 500 first circuit layer, 600 second via pillar, 700 first medium layer, 800 second circuit layer, 910 functional circuit layer, 920 circuit wall

Claims

1. A method for fabricating a plastic package cavity structure, comprising: (a) providing an embedded packaging frame, the embedded packaging frame including a first cavity and a first via pillar extending along a height direction, the first cavity and the first via pillar each extending through an insulating layer; (b) embedding a chip set in a bottom portion of the first cavity, the chip set including a first chip and a second chip stacked on top of each other, and bonding back surfaces of the first chip and the second chip together such that terminal surfaces of the first chip and the second chip are back-to-back with each other; (c) forming a packaging layer in a gap between the chip set and the first cavity, the packaging layer including blind vias exposing terminals of the second chip; (d) forming a first circuit layer and a second via pillar on the upper surface of the embedded packaging frame, the first circuit layer being conductively connected to a terminal of the second chip; (e) laminating a first media layer on a top surface of the first circuit layer, aligning a top surface of the first media layer with a top surface of the second via pillar; (f) forming a second circuit layer on a top surface of the first medium layer, forming a third circuit layer on a bottom surface of the embedded packaging frame, and forming a support pillar wall in the third circuit layer surrounding the first cavity; (g) forming a through via hole penetrating the first medium layer and the insulating layer in this order along a height direction, the through via hole being surrounded by the support pillar wall; (h) forming a plastic package layer below the embedded packaging frame along the outside of the support pillar wall, and forming a second cavity between the plastic package layer and the embedded packaging frame.

2. Step (h) is applying a second media layer beneath the embedded packaging frame and along an exterior of the support pillar walls to form the second cavity; 2. The method for making a plastic package cavity structure according to claim 1, further comprising: laminating the plastic package layer to the second medium layer.

3. 3. The method for manufacturing a plastic package cavity structure according to claim 2, wherein the second medium layer is a conformal coating film.

4. 2. The method for manufacturing a plastic package cavity structure as described in claim 1, wherein the first chip is a sensor chip, and a surface of a sensing component of the first chip is exposed to the second cavity and communicates with the outside by the through via hole.

5. 2. The method for fabricating a plastic package cavity structure as claimed in claim 1, wherein the third circuit layer includes a functional circuit layer and a circuit wall, and the support pillar wall is formed on the circuit wall by electroplating.

6. 2. The method for fabricating a plastic package cavity structure as claimed in claim 1, wherein the support pillar wall is a copper pillar wall.

7. Step (f) forming a first metal seed layer on a bottom surface of the embedded packaging frame; applying a first photoresist layer to the first metal seed layer and exposing and developing the first photoresist layer to form a first feature pattern; forming a third circuit layer by electroplating in the first feature pattern; removing the first photoresist layer, applying a second photoresist layer to the first metal seed layer, and exposing and developing the second photoresist layer to form a second feature pattern; electroplating in the second feature to form a support pillar wall; 2. The method of claim 1, further comprising: removing the second photoresist layer and etching the exposed first metal seed layer.

8. Step (b) applying an adhesive layer to a lower surface of the embedded packaging frame; 2. The method for manufacturing a plastic package cavity structure as described in claim 1, further comprising: attaching a terminal surface of the first chip to an exposed adhesive layer in the first cavity; and further attaching a back surface of the second chip to a back surface of the first chip, thereby mounting the chip set to the bottom of the first cavity.

9. Step (c) forming a packaging layer in a gap between the chipset and the first cavity and on a top surface of the embedded packaging frame; thinning the packaging layer to expose via pillars of the embedded packaging frame; 2. The method for fabricating a plastic package cavity structure as claimed in claim 1, further comprising: creating a window in the packaging layer to form a blind via exposing a terminal of the second chip.

10. A plastic package cavity structure, comprising: the embedded packaging frame includes a first cavity and a first via pillar that respectively penetrate an insulating layer along a height direction; a chipset provided in the first cavity; a first circuit layer provided on an upper surface of the embedded packaging frame; a first medium layer provided on the first circuit layer; a second circuit layer provided on the first medium layer; a through via hole that penetrates the first medium layer and the insulating layer; a third circuit layer on a lower surface of the embedded packaging frame; a support pillar wall on the third circuit layer; and a plastic package layer formed along an outer side of the support pillar wall; a second cavity communicating with the through via hole is formed between the plastic package layer and the lower surface of the embedded packaging frame, and the chip set includes a first chip and a second chip stacked back to back.

11. 11. The plastic package cavity structure of claim 10, wherein the first chip is a sensing chip, a surface of a sensing part of the first chip is exposed to the second cavity and communicates with the outside through the through via hole.

12. 11. The plastic package cavity structure of claim 10, further comprising a second medium layer between the plastic package layer and the second cavity.

13. The plastic package cavity structure according to claim 12 , wherein the second medium layer is a conformal coating film.

14. 11. The plastic package cavity structure of claim 10, wherein the first chip is selected from a MEMS sensor chip, and the second chip is selected from an ASIC chip.

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