Packaging substrate and method for manufacturing same

Abstract

To provide a packaging substrate and a method for manufacturing the same useful for meeting the needs for high integration, multi-functionality, and ultra-miniaturization in electronic products.SOLUTION: A packaging substrate includes a first dielectric layer 101, a first circuit layer 102 provided on the first dielectric layer 101 and including a dam 103, a second dielectric layer 104 provided on the first dielectric layer 101 and covering the first circuit layer 102, a component 105 embedded in the second dielectric layer 104 and surrounded by the dam 103, and a third dielectric layer 106 provided on the second dielectric layer 104 and covering the component 105. By providing the dam 103, the dam 103 can be used to effectively avoid the problem of misalignment of the component 105 in the process of being embedded in the second dielectric layer 104, and to ensure good bonding between the dielectric layers by eliminating the step of baking to roughen the surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to the field of semiconductor technology, and in particular to a packaging substrate and a method for fabricating the same. [Background technology]

[0002] With the continuous development of the electronics industry, the trend of electronic products is to increase the functionality and miniaturization. In the packaging substrate field, embedding components inside the substrate helps to meet the needs of high integration, multi-function and miniaturization in electronic products. Summary of the Invention [Problem to be solved by the invention]

[0003] In view of this, the object of the present disclosure is to propose a packaging substrate and a manufacturing method. [Means for solving the problem]

[0004] In view of the above objectives, in a first aspect, the present disclosure provides a packaging substrate, the packaging substrate comprising: a first dielectric layer; a first circuit layer provided on the first dielectric layer, the first circuit layer including a dam; a second dielectric layer provided on the first dielectric layer and covering the first circuit layer; a component embedded in the second dielectric layer and surrounded by the dam; and a third dielectric layer disposed on the second dielectric layer and covering the component.

[0005] In some embodiments, the dam has a height of 5 to 50 μm.

[0006] In some embodiments, the shape of the dam conforms to the shape of the part.

[0007] In some embodiments, the distance of the periphery of the component to the dam is between 5 and 500 μm; and / or The component is embedded in the dam to a depth of 1 μm or more.

[0008] In some embodiments, the dam includes at least one opening.

[0009] In some embodiments, the thickness of the second dielectric layer between the first dielectric layer and the component is between 3 and 30 μm.

[0010] In some embodiments, the first dielectric layer includes a cavity, the cavity being located within the dam.

[0011] In some embodiments, the depth of the cavity is 60 μm or less.

[0012] In some embodiments, the second dielectric layer and the third dielectric layer are single-layer or multi-layer structures.

[0013] In a second aspect, the present disclosure provides a method for fabricating a packaging substrate, the method specifically comprising: a) providing a substrate, the substrate including a first dielectric layer and a first circuit layer disposed thereon, the first circuit layer including a dam; b) forming a second dielectric layer on the first dielectric layer and the first circuit layer; c) mounting components on the second dielectric layer at locations corresponding to the dams; d) heating the second dielectric layer to restore its flow and applying pressure to the component to embed it in the second dielectric layer surrounded by the dam along a direction perpendicular to the substrate; e) forming a third dielectric layer on the second dielectric layer overlying the component.

[0014] In some embodiments, the dam has a height of 5 to 50 μm.

[0015] In some embodiments, the method further comprises: This involves controlling the embedding depth of the component by adjusting the temperature, pressure and pressing time.

[0016] In some embodiments, the component is embedded in the dam to a depth of 1 μm or more.

[0017] In some embodiments, the distance of the periphery of the component to the dam is between 5 and 500 μm; and / or The thickness of the second dielectric layer between the first dielectric layer and the component is 3 to 30 μm.

[0018] In some embodiments, the method further comprises: Forming a cavity in the first dielectric layer, the cavity being located within the dam.

[0019] In some embodiments, the depth of the cavity is 60 μm or less. [Effects of the Invention]

[0020] As can be seen from the above description, the packaging substrate and manufacturing method provided by the present disclosure can effectively avoid the problem of component misalignment during the process of embedding in the second dielectric layer by using the dam, and can also omit the baking and roughening step to ensure good bonding strength between the dielectric layers. [Brief explanation of the drawings]

[0021] In order to more clearly explain the technical solutions in the present disclosure or related art, the following briefly introduces drawings used in the description of the embodiments or related art. Needless to say, the drawings described below are merely embodiments of the present disclosure, and those skilled in the art can obtain other drawings from these drawings without performing any novel work. In the drawings, the thickness and shape of some layers and regions may be exaggerated for better understanding and ease of explanation. [Figure 1] FIG. 1 is a schematic cross-sectional view of a packaging substrate provided according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view of a partial structure of the packaging substrate of FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of another packaging substrate provided by an embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic diagram of a component subjected to force on a packaging substrate provided by an embodiment of the present disclosure. [Figure 5(a)] FIG. 5(a) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a packaging substrate according to an embodiment of the present disclosure. [Figure 5(b)] FIG. 5(b) is a schematic cross-sectional view of an intermediate structure in each step of the method for fabricating a packaging substrate according to an embodiment of the present disclosure. [Figure 5(c)] FIG. 5(c) is a schematic cross-sectional view of an intermediate structure in each step of the method for fabricating a packaging substrate according to an embodiment of the present disclosure. [Figure 5(d)] FIG. 5(d) is a schematic cross-sectional view of an intermediate structure in each step of the method for fabricating a packaging substrate according to an embodiment of the present disclosure. [Figure 5(e)] FIG. 5(e) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a packaging substrate according to an embodiment of the present disclosure. [Figure 5(f)] FIG. 5(f) is a schematic cross-sectional view of an intermediate structure in each step of the method for fabricating a packaging substrate according to an embodiment of the present disclosure. [Figure 6(a)] FIG. 6(a) is a schematic cross-sectional view of an intermediate structure at each step of another method for fabricating a packaging substrate according to an embodiment of the present disclosure. [Figure 6(b)] FIG. 6(b) is a schematic cross-sectional view of an intermediate structure at each step of another method for fabricating a packaging substrate according to an embodiment of the present disclosure. [Figure 6(c)] FIG. 6(c) is a schematic cross-sectional view of an intermediate structure at each step of another method for fabricating a packaging substrate according to an embodiment of the present disclosure. [Figure 6(d)] FIG. 6(d) is a schematic cross-sectional view of an intermediate structure at each step of another method for fabricating a packaging substrate according to an embodiment of the present disclosure. [Figure 6(e)]FIG. 6(e) is a schematic cross-sectional view of an intermediate structure at each step of another method for fabricating a packaging substrate according to an embodiment of the present disclosure. [Figure 6(f)] FIG. 6(f) is a schematic cross-sectional view of an intermediate structure at each step of another method for fabricating a packaging substrate according to an embodiment of the present disclosure. [Figure 6(g)] FIG. 6(g) is a schematic cross-sectional view of an intermediate structure at each step of another method for fabricating a packaging substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, the present disclosure will be described in more detail using specific embodiments and with reference to drawings so that the objectives, technical solutions and advantages of the present disclosure will be more apparent.

[0023] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure have common meanings understood by those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The term "comprises" or similar terms means that the elements or objects listed after the term cover the elements or objects listed after the term and their equivalents, but do not exclude other elements or objects. Terms such as "top," "bottom," "left," and "right" are used to express only relative positional relationships, and if the absolute position of the object being described changes, the relative positional relationships may change accordingly.

[0024] When terms such as "above," "upper," "under," or "beside" are used to describe the relative position of two parts, one or more parts may be located between the two parts, unless these terms are used in conjunction with the terms "immediately adjacent" or "directly."

[0025] When an element or layer is referred to as being "on" another element or layer, the other layer or element may be directly on top of or interposed between the other element.

[0026] In conventional cavityless molding techniques, components are generally mounted on the surface of a resin, which is then baked to harden, and the resin medium further encapsulates the components, and finally electrical conduction between layers is achieved.

[0027] To avoid component misalignment caused by resin flow under heat and pressure during the subsequent resin encapsulation process, a nitrogen bake step is required after component mounting to fix the components to the resin surface. Because the resin surface has already hardened after baking, further surface roughening is generally required to avoid poor bonding strength between the two resin layers in preparation for the subsequent resin encapsulation. However, this results in an excessively thick resin encapsulation layer, which is unfavorable for creating interlayer via holes and reducing the overall thickness of the board.

[0028] In view of this, as a first aspect, an embodiment of the present disclosure provides a packaging substrate and provides a dam, which effectively avoids the problem of component misalignment during the process of embedding in the second dielectric layer, eliminates the baking and roughening step, and helps ensure good bonding strength between the dielectric layers.

[0029] As shown in Figures 1 to 3, the packaging substrate includes a first dielectric layer 101, a first circuit layer 102 provided on the first dielectric layer 101, the first circuit layer including a dam 103 (see Figure 2), a second dielectric layer 104 provided on the first dielectric layer 101 and covering the first circuit layer 102, a component 105 embedded in the dam 103, the bottom of the component 105 contacting the second dielectric layer 104, and a third dielectric layer 106 provided on the second dielectric layer 104 and covering the component 105.

[0030] 4, the use of dam 103 instead of baking in nitrogen is due to the following: on the one hand, dam 103 serves to stop the flow of the second dielectric layer, and on the other hand, when component 105 tries to slide due to the force F1 not being balanced by the flow of the compressed dielectric layer, it receives a reaction force F2 from the "dam," thereby embedding component 105 in second dielectric layer 104 and ensuring no misalignment occurs during the process of compressing third dielectric layer 106. Furthermore, since there is no need for baking or an additional step of roughening the surface of the dielectric layer, the manufacturing process is simplified and the total thickness of the substrate is reduced.

[0031] In some embodiments, the first dielectric layer 101 may be a dielectric layer on the surface of a mounting plate or substrate, and the material may be selected from, for example, liquid crystal polymer, BT (bismaleimide triazine) resin, prepreg, ABF (Ajinomoto Build-up) film, epoxy resin, polyimide resin, etc., and the present disclosure is not limited thereto.

[0032] In some embodiments, the height of the dam 103 is 5 to 50 μm, for example, 5 μm, 10 μm, 15 μm, 26 μm, 32 μm, 38 μm, 45 μm, or 50 μm. If the height of the dam 103 is less than 5 μm, the effect of preventing misalignment cannot be guaranteed. However, since the dam 103 and the first circuit layer 102 are fabricated simultaneously, if the height of the dam 103 exceeds 50 μm, the fabrication cost becomes high and unnecessary. Here, the first circuit layer 102 may be formed by electroplating, and the material may be copper.

[0033] The component 105 may be an active element, such as a transistor, an IC chip, a logic circuit element, or a power amplifier, or may be a passive element, such as a capacitor, an inductor, a resistor, or a combination thereof, although the present disclosure is not limited in this respect.

[0034] This allows the shape of the dam 103 to match the shape of the part 105, for example round, square, etc.

[0035] Furthermore, the dam 103 may be a completely closed structure (see FIG. 2) or may include at least one opening (not shown). Those skilled in the art can specifically adjust the structure of the dam 103 as needed to meet actual needs.

[0036] In some embodiments, the depth to which the component 105 is embedded in the dam 103 is 1 μm or more, for example, 1 μm, 1.5 μm, 2 μm.

[0037] In some embodiments, the distance d of the periphery of the part 105 to the dam 103 is between 5 and 500 μm (see FIG. 2), for example, 5 μm, 50 μm, 100 μm, 180 μm, 220 μm, 250 μm, 296 μm, 388 μm, 420 μm, 460 μm, 500 μm.

[0038] In some embodiments, the thickness of the second dielectric layer 104 between the first dielectric layer 101 and the component 105 is between 3 and 30 μm, for example, 3 μm, 7 μm, 10 μm, 15 μm, 20 μm, 22 μm, 30 μm.

[0039] 6(b), the first dielectric layer 101 includes a cavity 109, which is located within the dam 103. By providing the cavity 109, the depth of the dam 103 can be increased, allowing the component 105 to be embedded deeper; on the one hand, the component 105 is protected from the larger area of ​​the "dam" during a subsequent compression process, preventing the component 105 from flowing with the dielectric layer material and shifting its position; on the other hand, the increased embedded depth of the component 105 reduces the height of the component 105 and ultimately the thickness of the substrate.

[0040] Optionally, the depth of the cavity 109 is 60 μm or less, for example, 2 μm, 10 μm, 16 μm, 24 μm, 28 μm, 30 μm, 37 μm, 45 μm, 52 μm, 60 μm.

[0041] In some embodiments, the second dielectric layer 104 and the third dielectric layer 106 may have a single-layer or multi-layer structure, and the second dielectric layer 104 and the third dielectric layer 106 may be made of the same insulating material or different materials, such as resin material, BT (bismaleimide triazine) resin, prepreg, ABF (Ajinomoto Build-up) film, epoxy resin, polyimide resin, etc., and the types are not specifically limited.

[0042] Whether or not there is a boundary line between the second dielectric layer 104 and the third dielectric layer 106 is determined by the chemical properties of the resin material, and generally, if the materials are the same, there is no interface. However, this does not necessarily mean that if the materials are different, there will be an interface, and the present disclosure does not place any restrictions on the interface.

[0043] Illustratively, FIG. 1 shows a structural schematic diagram when there is an interface between the second dielectric layer 104 and the third dielectric layer 106, and FIG. 3 shows a structural schematic diagram when there is no interface between the second dielectric layer 104 and the third dielectric layer 106.

[0044] 5(f), the packaging substrate further includes a via pillar 107 and a second circuit layer 108. The second circuit layer 108 is located on the third dielectric layer 106, and the via pillar 107 is used to connect the first circuit layer 102 and the second circuit layer 108.

[0045] Here, the present disclosure does not strictly limit the thickness of the third dielectric layer 106, as long as the component 105 is enclosed therein.

[0046] As a second aspect, the present disclosure also provides a method for manufacturing a packaging substrate. Referring to FIGS. 5(a) to 5(f), the manufacturing method includes the following steps: As shown in FIG. 5(a), step (a) provides a substrate 100. Here, the substrate 100 is a semi-finished substrate, such as a printed circuit board. The type of semi-finished substrate can be selected according to needs. In the following process, only semi-finished substrates are shown and described, but the manufacturing method is not limited to being suitable only for semi-finished substrates. Optionally, the semi-finished substrate can be manufactured by a tenting process, an MSAP process, or a SAP process, and is not specifically limited.

[0047] Furthermore, the substrate 100 includes a first dielectric layer 101 and a first circuit layer 102 located thereon, and the first circuit layer 102 includes a dam 103 (see dotted box A in FIG. 5(a)). Optionally, the height of the dam 103 is 5 to 50 μm.

[0048] Next, as shown in Figure 5(b), a second dielectric layer 104 is formed on the first dielectric layer 101 and the first circuit layer 102 - step (b). Here, the surface of the second dielectric layer 104 becomes viscous at room temperature or when heated, allowing components to adhere thereto.

[0049] For example, the second dielectric layer 104 may be formed by applying a liquid resin, or by pressing a medium material having a conformal coating function in a dry film form, and the method is not specifically limited here.

[0050] 5(c), the components 105 are mounted on the second dielectric layer 104 at positions corresponding to the dams 103 - step (c). In some embodiments, the components 105 may be attached to the second dielectric layer 104 using a chip mounter. Whether or not to heat the second dielectric layer 104 during attachment can be determined depending on the viscosity of the second dielectric layer 104. For example, if the viscosity is low, the components may be heated, or a chip mounter with a heating function may be used to heat the semi-finished substrate before attaching the components 105.

[0051] 5(d), the second dielectric layer 104 is heated to restore its flow, and pressure F3 is applied to the component 105 to embed it in the second dielectric layer 104 surrounded by the dam 103 along a direction perpendicular to the substrate 100 - step (d). In one embodiment, as the component 105 presses the second dielectric layer 104, the second dielectric layer 104 becomes adhesive and creeps up on the side surface of the component 105, and different pressure application parameters result in different heights to which the adhesive creeps up, and the present disclosure is not limited thereto.

[0052] The embedding depth of the component 105 can be controlled by adjusting the temperature, pressure, and pressing time. The parameters of the temperature, pressure, and pressing time can be specifically adjusted according to the actual situation, and are not limited here.

[0053] Optionally, the component 105 is embedded into the dam 103 to a depth of 1 μm or more. Optionally, the distance between the periphery of the component 105 and the dam 103 is 5 to 500 μm. Optionally, the thickness of the second dielectric layer 104 between the first dielectric layer 101 and the component 105 is 3 to 30 μm.

[0054] 5(e), a third dielectric layer 106 is formed on the second dielectric layer 104 to cover the components 105 - step (e). The method for forming the third dielectric layer 106 is similar to that for the second dielectric layer 104, and therefore, the description thereof will be omitted here.

[0055] The third dielectric layer 106 and the second dielectric layer 104 may be made of the same insulating material or different materials, such as resin material, BT (bismaleimide triazine) resin, prepreg, ABF (Ajinomoto Build-up) film, epoxy resin, polyimide resin, etc., and the type is not specifically limited.

[0056] Next, as shown in Fig. 5(f), an interlayer conductive blind via is fabricated to form a second circuit layer 108 and a via pillar 107 - step (f). Here, the conductive blind via may be formed by laser drilling, and the second circuit layer 108 and the via pillar 107 may be formed by electroplating. The present disclosure does not specifically limit this.

[0057] The present disclosure also provides another method for fabricating a packaging substrate, the fabrication method of which is almost the same as the steps of the above method, and therefore will be briefly described here as follows: Referring to Figures 6(a) to 6(g), the fabrication method includes the following steps: As shown in Figure 6(a), a substrate 100 is provided - step (a).

[0058] Next, as shown in FIG. 6(b), a cavity 109 is formed in the first dielectric layer 101, and the cavity 109 is located in the dam 103—step (b). Here, the cavity 109 is formed in the first dielectric layer 101 by thinning the resin dielectric layer in the “dam” using methods such as plasma, sandblasting, depth-controlled mechanical milling, laser ablation, etching, etc., to obtain a “dam” that is deeper in the vertical direction. The present disclosure does not limit the processing method for forming the “cavity.”

[0059] Optionally, the depth of the cavity is 60 μm or less. By providing the cavity 109, the depth of the dam 103 can be increased, and the component 105 can be embedded deeper, which on the one hand protects the component 105 from the larger area of ​​the “dam” in the subsequent compression process, preventing the component 105 from flowing along with the dielectric layer material and shifting its position, and on the other hand, since the embedded depth of the component 105 is increased, the height of the component 105 is reduced, and ultimately the thickness of the substrate is also reduced.

[0060] Subsequently, as shown in FIG. 6(c), a second dielectric layer 104 is formed on the first dielectric layer 101 and the first circuit layer 102 - step (c).

[0061] Next, as shown in FIG. 6(d), components 105 are mounted on the second dielectric layer 104 at corresponding positions of the dam 103 - step (d).

[0062] Next, as shown in FIG. 6(e), the second dielectric layer 104 is heated to restore its flow, and pressure F3 is applied to the component 105 to embed it into the dam 103 along a direction perpendicular to the substrate 100 - step (e).

[0063] Next, as shown in FIG. 6(f), a third dielectric layer 106 is formed on the second dielectric layer 104 to cover the component 105 - step (f).

[0064] Subsequently, as shown in FIG. 6(g), an interlayer conductive blind via is fabricated to form a second circuit layer 108 and a via pillar 107 - step (g).

[0065] Those skilled in the art will understand that the discussion of any of the above embodiments is merely illustrative and does not imply that the scope of the present disclosure (including the claims) is limited to these examples. Within the spirit of the present disclosure, the technical features of the above embodiments or different embodiments can be combined with each other, steps can be performed in any order, and there can be many other variations of different aspects of the above embodiments of the present disclosure, which are not provided in the detailed description for the sake of simplicity.

[0066] The embodiments of the present disclosure are intended to include all such replacements, amendments, and variations that fall within the broad scope of the claims, and therefore, any omissions, amendments, equivalent replacements, improvements, etc. that fall within the spirit and principles of the embodiments of the present disclosure are intended to be included within the scope of the claims of the present disclosure. [Explanation of symbols]

[0067] 100 substrate, 101 first dielectric layer, 102 first circuit layer, 103 dam, 104 second dielectric layer, 105 component, 106 third dielectric layer, 107 via pillar, 108 second circuit layer, 109 cavity, F1 force, F2 reaction force, F3 pressure, d distance

Claims

1. 1. A packaging substrate, comprising: A first dielectric layer; a first circuit layer disposed on the first dielectric layer, the first circuit layer including a dam; a second dielectric layer disposed on the first dielectric layer and covering the first circuit layer; a component embedded in the second dielectric layer and surrounded by the dam; a third dielectric layer disposed on the second dielectric layer and covering the component; A packaging substrate, wherein the first dielectric layer includes a cavity, the cavity being located within the dam.

2. 2. The packaging substrate according to claim 1, wherein the height of the dam is 5 to 50 μm.

3. The packaging substrate according to claim 1 , wherein the shape of the dam is adapted to the shape of the component.

4. the distance of the periphery of the part to the dam is between 5 and 500 μm; and / or 2. The packaging substrate according to claim 1, wherein the component is embedded in the dam to a depth of 1 [mu]m or more.

5. The packaging substrate of claim 1 , wherein the dam includes at least one opening.

6. 2. The packaging substrate according to claim 1, wherein the thickness of the second dielectric layer between the first dielectric layer and the component is 3 to 30 μm.

7. The packaging substrate according to claim 1 , wherein the cavity has a depth of 60 μm or less.

8. The packaging substrate according to claim 1 , wherein the second dielectric layer and the third dielectric layer have a single-layer or multi-layer structure.

9. A method for making a packaging substrate, comprising the steps of: in particular, a) providing a substrate, the substrate including a first dielectric layer and a first circuit layer disposed thereon, the first circuit layer including a dam; b) forming a second dielectric layer on the first dielectric layer and the first circuit layer; c) mounting components on the second dielectric layer at locations corresponding to the dams; d) heating the second dielectric layer to restore its flow and applying pressure to the component to embed it in the second dielectric layer surrounded by the dam along a direction perpendicular to the substrate; e) forming a third dielectric layer on said second dielectric layer overlying said component.

10. 10. The method according to claim 9, wherein the height of the dam is 5 to 50 μm.

11. The method comprises:

10. The method of claim 9, further comprising controlling the embedding depth of the component by adjusting temperature, pressure and pressing time.

12. 10. The method according to claim 9, wherein the component is embedded in the dam to a depth of 1 [mu]m or more.

13. the distance of the periphery of the part to the dam is between 5 and 500 μm; and / or 10. The method of claim 9, wherein the thickness of the second dielectric layer between the first dielectric layer and the component is 3 to 30 μm.

14. The method comprises:

10. The method of claim 9, further comprising forming a cavity in said first dielectric layer, said cavity being located within said dam.

15. 15. The method of claim 14, wherein the cavity has a depth of 60 [mu]m or less.

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