Silicon substrate with ESD protection elements

Abstract

ESD protection devices are embedded in a silicon substrate, suitable for example as a carrier for an ASIC, and are separated by one or more vias that pass through the silicon substrate. Electrical connections to the ESD protection devices are made through rewiring that is routed between the ESD protection devices and the vias.

Description

[Technical Field]

[0001] The present invention relates to a silicon substrate having an ESD protection element. [Background technology]

[0002] In electronic SIP ("System in a Package") modules, or for example in MEMS microphones or other modules suitable for mobile applications, application specific integrated circuits ("ASICs") are used. These integrated circuits are usually protected by on-chip ESD protection structures (overvoltage protection structures). In the present application, on-chip ESD protection structures are understood to mean ESD protection structures that are a direct part of the integrated circuit chip, which may usually be mounted on a substrate. An example of such an on-chip ESD protection structure is shown in FIG. 7 and represents prior art to the present invention. As shown in FIG. 7, an ASIC 50 can be arranged on a substrate 1', which itself is arranged on a circuit board 52. The on-chip ESD protection structure (2') can occupy more than one-third of the available chip or board area. This contradicts the requirement that current and future applications must be increasingly miniaturized in their lateral dimensions.

[0003] To date, no concept is known in which an ESD protection structure is clearly separated from other structures and can be flexibly integrated into a substrate in terms of its size. Conventional systems in which the ESD structure is within the substrate are significantly limited in their applicability and have various drawbacks that are overcome by the present invention, as described below.

[0004] Patent document 1 describes a diode structure as ESD protection in a via that passes through a silicon substrate ("through silicon via") The diode is obtained by appropriate doping of the silicon substrate in the immediate vicinity of the via.

[0005] However, this direct coupling does not allow more complex ESD protection structures, which may also include, for example, transistors or thyristors, to be implemented within the substrate.

[0006] Patent Document 2 describes a further configuration of an ESD protection element disposed in an interposer on a printed circuit board (PCB). It describes that the ESD protection element can be connected through a via inside the interposer.

[0007] Patent document 3 shows a simple ESD protection structure for silicon solar cells, which is based on a simple diode system and can be connected to vias in the substrate through a structure similar to a redistribution line.

[0008] US Pat. No. 5,649,399 describes that an ESD protection structure, which in this case may also include a transistor and a simple diode, can be implemented close to an interface in a silicon substrate.

[0009] When vias are implemented in a silicon substrate, the sidewalls of the openings created in the silicon substrate are usually passivated. Patent document 5 describes the possibility that such passivation can be created.

[0010] Patent document 6 discloses only very generally that overvoltage protection structures (ESD protection structures) can be integrated into ceramic substrates, in particular varistor substrates.

[0011] US Pat. No. 6,299,499 discloses a laminate structure with integrated ESD protection.

[0012] Patent Document 8 discloses an integrated circuit having a thyristor as an ESD protection element.

[0013] US Pat. No. 5,699,499 discloses a light emitting device in which a feedthrough and a pn diode can be implemented. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] U.S. Patent No. 8,164,113 [Patent Document 2] U.S. Patent No. 9,412,708 [Patent Document 3] US Patent Application Publication No. 2015 / 0048497 [Patent Document 4] US Patent Application Publication No. 2008 / 0296697 [Patent Document 5] US Patent Application Publication No. 2020 / 0161244 [Patent Document 6] German Patent Application Publication No. 102018118016 [Patent Document 7] US Patent Application Publication No. 2011 / 0079912 [Patent Document 8] International Publication No. 2017 / 091155 [Patent Document 9] US Patent Application Publication No. 2013 / 0240922 Summary of the Invention

[0015] According to a first aspect of the present invention, a silicon substrate is provided. An integrated circuit is disposed on a first surface of the silicon substrate. The substrate further includes a first via and an ESD protection element. In this case, preferably, the first via penetrates the silicon substrate from the first surface to the second surface, where the second surface is opposite the first surface. Furthermore, the ESD protection element is integrated into the silicon substrate. That is, the ESD protection element is embedded in the silicon substrate, i.e., completely within the volume of the substrate. Furthermore, the ESD protection element is spatially separated from the first via. The separation is preferably along the direction in which the silicon substrate extends, i.e., a direction parallel to the first surface, for example. Furthermore, the ESD protection element is connected to the via by a first rewiring. Furthermore, the ESD protection element includes at least one selected from the group consisting of a suppressor diode, a transistor, and a thyristor.

[0016] The silicon substrate can be any type of substrate made of silicon, such as amorphous silicon or polycrystalline silicon, but preferably the silicon substrate is a wafer, such as a monocrystalline silicon wafer.

[0017] This design according to the first aspect of the present invention makes it possible to provide off-chip ESD structures that can be custom-fitted to integrated circuit elements, such as application specific integrated circuits (ASICs). In this case, these integrated circuit elements are preferably located on or above the first surface of a silicon substrate. In contrast to on-chip ESD structures, the off-chip ESD structures are not located on the chip to be protected itself, but are embedded separately in the silicon substrate. This allows for a reduction in chip size, as required according to the present invention, since the ESD protection in an off-chip design does not need to be part of the chip.

[0018] In particular, the ESD protection element can be ESD protection at a system level (system-level ESD protection), or the ESD protection element can ensure ESD protection at a system level, meaning that all integrated circuits are protected together, not just a single circuit or part of a circuit. System-level ESD protection can be, for example, input signal-to-output signal protection, i.e., ESD protection that systematically protects all electronic components or integrated circuits attached between input signal conductors and output signal conductors against overvoltages.

[0019] In addition to the system-level ESD protection provided by the ESD protection elements, further ESD protection structures may be implemented in the application-specific integrated circuit. These further ESD protection structures may here, for example, be on-chip protection structures. Here, it is advantageous, and the present invention makes it possible, to provide a customized coordination between the ESD protection elements and the further ESD protection structures in the application-specific integrated circuit. Therefore, a further aspect of the present invention is to enable a customized coordination between the off-chip ESD protection elements and the on-chip protection elements according to the present invention.

[0020] The separation of the ESD protection elements from vias and connection through rewiring is highly advantageous because it can affect both the impedance of the ESD protection structure and the onset time of the ESD protection elements, and therefore can be customized and tailored for each application.

[0021] In a further aspect, the ESD protection element can further comprise an EMI protection structure (electromagnetic interference protection structure). In this case, it is advantageous to implement the EMI protection directly together with the ESD protection. Especially for high-frequency data conductors, both the ESD protection requirements and the resulting capacitance and inductance or parasitic capacitance can be customized and adjusted in parallel.

[0022] In that case, the EMI protection structure is formed by a coil structure, a thin film resistor and / or a capacitance, i.e. either a coil structure, a thin film resistor or a capacitance, or any combination of such components may be used.

[0023] The selection of these components is customized for each application.

[0024] According to a further aspect, the silicon substrate may include an ESD protection element constructed from structures embedded within the silicon substrate, including a combination of thyristor and diode structures, where the diode structure may be a semiconductor structure with diode functionality, where the diode structure is not part of the thyristor structure.

[0025] While the combination of thyristor and diode structures is already common in on-chip ESD protection devices, in accordance with the present invention these components can be embedded in or integrated into the silicon substrate, thereby providing off-chip ESD protection.

[0026] Preferably, a passivation layer is also formed on the first surface of the silicon substrate, and it is further advantageous that the ESD protection element is in direct contact with the first surface on which the passivation layer is located, i.e., the ESD protection element is preferably in direct contact with the passivation layer on this first surface.

[0027] According to a further embodiment, the silicon substrate can include at least one additional redistribution line. In this case, the additional redistribution line can electrically connect the first via to a UBM (Under-Bump-Metallisierung) contact pad. For example, in such a case, the redistribution line can extend within the aforementioned passivation layer. Preferably, the UBM contact pad is then arranged on or within the surface of the passivation layer in a manner suitable for contacting additional electronic components, for example via solder bumps. In this case, it is particularly preferred that the additional redistribution line (7) can include adaptive elements. These adaptive elements include capacitance, inductance, or delay elements. They can thus contribute to matching the impedance of the integrated ESD protection element to additional electronic components, such as ASICs, connected to the UBM contact pads connected in this way. Furthermore, the onset time can be adapted during an ESD event.

[0028] This optional additional rewiring is preferably different from the first rewiring.

[0029] According to a further aspect, the silicon substrate additionally includes a second via penetrating the silicon substrate from the first surface to the second surface. Furthermore, in the silicon substrate, the ESD protection element is spatially separated from the second via as well as from the first via. Furthermore, the ESD protection element, in this case, is connected to the second via via a second redistribution line. The connection of the ESD protection element, the first and second vias, and the first and second redistribution lines described herein is referred to herein and hereinafter as an ESD circuit.

[0030] For example, the ESD circuit can be symmetrical, i.e., the ESD protection elements can be symmetrically located between two redistribution lines and vias, and the first and second redistribution lines or the first and second vias can be very similar or identical to each other.

[0031] According to a further aspect, a silicon substrate is provided comprising a plurality of the above-described ESD circuits, wherein the plurality of ESD circuits are formed adjacent to one another within a common silicon substrate, i.e., a plurality of ESD protection elements connected to first and second vias by first and second redistribution lines, respectively, can be included within the silicon substrate.

[0032] According to a further aspect, the silicon substrate described above can be used for a MEMS microphone (Micromechanical System Microphone), i.e., a MEMS microphone can be built on the silicon substrate as described above.

[0033] According to a further aspect of the present invention, a method for fabricating an ESD protection device in a silicon substrate as previously described is presented.

[0034] In this case, first, an embedded structure of an ESD protection element is fabricated in a silicon substrate using a CMOS ("Complementary Metal-Oxide-Semiconductor") process. The embedded structure of the ESD protection element includes at least one selected from the group consisting of a suppressor diode, a transistor, and a thyristor. After the ESD protection element structure is formed, a first contact pad is created on one of the surfaces of the silicon substrate.

[0035] Subsequently, an opening for the via between the first surface and the second surface of the silicon substrate is created in the silicon substrate. The opening can be created by laser or deep reactive ion etching (DRIE). The opening is formed so as to be spatially separated from the buried structure of the ESD protection device, in particular, such that the separation is oriented in the extension direction of the silicon substrate.

[0036] The inner walls of the openings are then passivated. The openings are then filled with a first metal to create vias. Furthermore, redistribution lines made of a second metal are created between the vias of the ESD protection device and the integrated circuit, i.e., the redistribution lines electrically connect the vias to the ESD protection device.

[0037] The method described herein can be used to fabricate an ESD protection device as described above or a substrate as described above.

[0038] This means that in a later step in the manufacturing method, an integrated circuit, such as an ASIC, can be created or placed on the first surface of the silicon substrate.

[0039] These integrated circuits can for example be part of the MEMS microphone, such as the control electronics, according to the example above.

[0040] According to a further aspect of the method for fabricating an ESD protection device in a silicon substrate, the first metal can be copper (Cu), in which case the via can be formed by filling the opening with an electrical process.

[0041] Furthermore, the redistribution lines can be made of aluminum (Al) or Cu.

[0042] Furthermore, the inner walls of the openings can be passivated before forming the vias, i.e., before filling with the first metal, for example, by atomic layer deposition (ALD process) or by a plasma etching process (sequential dry etching and passivation). This passivation by the plasma etching process can be performed during the DRIE etching. Thus, the plasma etching process can be part of the DRIE process.

[0043] According to a further aspect of the method, in a further step, a passivation may also be produced on the first surface and on the second surface, preferably before an integrated circuit, such as an ASIC, is produced on or above the first surface.

[0044] The passivation provided here corresponds to the passivation described above for the substrate: it can for example comprise or consist of a silicon oxide, preferably a polymer-based passivation layer.

[0045] In or on the corresponding passivation layer, UBM contact pads are implemented, which can contact elements of the integrated circuit above the first surface. In the case of thinner passivation layers, the UBM contact pads can extend through the passivation layer in the thickness direction, thus enabling direct electrical contact with the vias. However, the UBM contact pads can also indirectly contact the vias. In the case of thicker passivation layers, additional rewiring to the UBM contact pads can be fabricated, as described above, that is indirectly connected to the vias.

[0046] In the following, the present invention will be described in detail based on exemplary embodiments. These exemplary embodiments are illustrated in the following drawings, which are not to scale. Therefore, dimensions and relative and absolute sizes cannot be read from the drawings. The present invention is also not limited to the following description. [Brief explanation of the drawings]

[0047] [Figure 1] 1 shows a first embodiment of a silicon substrate in a schematic cross-sectional view. [Figure 2] 2 shows a second embodiment of a silicon substrate in a schematic cross-sectional view. [Figure 3] 2 shows a third embodiment of a silicon substrate in a schematic cross-sectional view. [Figure 4] 1 shows a fourth embodiment of a silicon substrate in a schematic cross-sectional view. [Figure 5] 1 shows a MEMS microphone in a schematic cross-sectional view. [Figure 6] 1 shows a schematic cross-sectional view of an ASIC on a substrate according to the invention on a circuit board. [Figure 7] 1 shows a schematic cross-sectional view of an ASIC on a substrate according to the prior art prior to the present invention on a circuit board. DETAILED DESCRIPTION OF THE INVENTION

[0048] In FIG. 1 a first embodiment of a silicon substrate 1 according to the invention is shown in a schematic cross section.

[0049] Here, the silicon substrate 1 is a silicon wafer. However, in principle, any other substrate made of silicon is suitable as the silicon substrate 1. The silicon substrate 1 has a first surface 11 and an opposite second surface 12. Preferably, the second surface 12 is oriented parallel to the first surface 11. Here, the extension direction of the silicon substrate 1 is parallel to the first surface 11.

[0050] An ESD protection element 2 is embedded in the silicon substrate 1. In this embodiment, the ESD protection element 2 is in direct contact with the first surface 11 of the silicon substrate 1. Furthermore, the ESD protection element 2 is completely embedded within the silicon substrate.

[0051] The ESD protection element 2 is separated from the first via 3. That is, the ESD protection element 2 and the first via 3 have a distance that is typically greater than 0 in the direction in which the silicon substrate 1 extends, that is, they are spatially separated or separated from each other.

[0052] The specific structure of the ESD protection element 2 also depends on the intended application and can be customized accordingly. In particular, a low clamping voltage should be achieved. The embedded structure of the ESD protection element 2 is at least one TVS diode (suppressor diode) embedded in a silicon substrate. Additionally or alternatively, a transistor or thyristor can be used. For many applications, an integrated circuit consisting of a combination of a thyristor and a diode structure is preferred as the embedded structure of the ESD protection element 2. Depending on the application, the extension of the ESD protection element 2 in the extension plane can be 50 μm × 50 μm to 300 μm × 300 μm, and the shape here can be rectangular, but is not limited to this. The substrate can also be circular in the extension plane. The size depends on the voltage of the ESD events that need to be protected against. For normal ESD protection against voltage peaks of 8 kV to 30 kV, the extension of the ESD protection element 2 in the extension direction is preferably 100 μm×100 μm to 200 μm×200 μm, and again the shape is not limited.

[0053] Furthermore, the ESD protection element 2 may also be provided with an electromagnetic interference protection structure (EMI protection structure). As such, coil structures, thin film resistors and / or capacitances may contribute. However, in particular, capacitances are already inherently introduced by the embedded structure of the ESD protection element. These must therefore be adapted to the application. This plays an important role, especially in the case of high-frequency data conductors.

[0054] The first via 3 is a TSV (Through Silicon Via) and extends between the first surface 11 and the second surface 12. Preferably, the first via 3 is made of a conductive metal (first metal) such as copper.

[0055] As shown in FIG. 1 , the first via 3 can be conical, e.g., thicker on the side of the first surface 11 and thinner on the side of the second surface 12. Alternatively, the conical shape can extend in the opposite direction, i.e., thinner on the side of the first surface 11 and thicker on the side of the second surface 12. Furthermore, the thickness can be approximately uniform. Essentially, the shape can depend on the manufacturing method used, as will be explained below. For example, a conical shape according to FIG. 1 can be achieved by a laser from the side of the first surface. An inverse conical shape can be achieved by a laser from the side of the second surface. If a DRIE process is used, the resulting shape for the first via 3 can be approximately cylindrical, but can have, for example, a depression typical of DRIE.

[0056] The interface between the conductive metals of the first via 3 is preferably passivated, i.e., electrically isolated, with an insulating layer 30. The insulating layer 30 is typically formed along the entire interface between the first via 3 and the silicon substrate 1.

[0057] The electrical or electronic connection between the ESD protection element 2 and the first via 3 is made through the first redistribution line 4, which can extend, for example, along the first surface 11. In this case, the first redistribution line 4 can be slightly embedded in the first surface 3 or can extend above it. The first redistribution line 4 can be made of any conductive metal (second metal), such as, for example, aluminum or copper.

[0058] In combination with the above-mentioned distance between the ESD protection element 2 and the first via 3, the impedance of the circuit and the response time of the ESD protection can be affected via the first redistribution line 4.

[0059] On the first surface 11 and on the second surface 12, respectively, there is arranged a first passivation 5 or a second passivation 5', i.e., an electrically insulating and substantially inert layer, which can basically be made of any material that fulfills these conditions. In this example, it consists of a polymer passivation layer.

[0060] Furthermore, UBM contact pads 6 and 6' are attached to the first surface 11 and the second surface 12. They are arranged directly above and below the first vias 3 and may, for example, consist of the same material as the first vias 3 or the first redistribution lines 4. However, the UBM contact pads 6 and 6' may also consist of or contain the following metals: aluminum, titanium, copper, nickel, palladium, silver, gold, or tin. For example, one of these metals may form the main volume of the UBM contact pad 6 or 6', while one or more of the other metals may form the surface of the UBM contact pad 6 or 6' as a thin layer. The contact pads 6 and 6' extend through the upper passivation layer 5 or the lower passivation layer 5', respectively. They serve as contact surfaces for attaching an integrated circuit above the first surface, for example, via soldering, or for ensuring external contact, for example, for input signals. That is, in an application, if integrated circuits, such as ASICs, are located directly on or above the silicon substrate, these can be electrically connected to the UBM contact surfaces 6 and therefore to the rewiring 3 via solder bumps.

[0061] The first via 3 and its connected UBM contact pads 6 and 6' may form signal conductors of an attached electronic component, such as an ASIC.

[0062] The ground may optionally be contributed by another second UBM contact pad 62 attached to the silicon substrate, which may be manufactured similarly to the UBM contact pad 6 and connected to the ground line in any way.

[0063] The component can be manufactured by essentially any suitable method. Preferably, the following method is used: A silicon substrate 1 is prepared on a carrier foil. The embedded structure of the ESD protection element 2, including the EMI protection structure, can be introduced into the silicon substrate by a CMOS process. Next, a passivation layer 5 can be generated on the first surface 11 along with the first redistribution line 7. Subsequently, a UBM contact pad 6 and a second UBM contact pad 62, for example made of Cu, are generated on the first surface 11 of the silicon substrate 1 by a photolithography process. Subsequently, an opening for the first via 3 between the first surface 11 and the second surface 12 of the silicon substrate 1 is generated by a laser or DRIE. If irradiated from the second surface side, the first via 3 can have a conical shape, inverse to that shown in FIG. 1 . The inner wall of the opening is passivated by either an ALD process or a plasma etching process, thereby generating an insulating layer 30 for the first redistribution line 3. The plasma etching process can be part of the DRIE process. The openings are then filled with a first metal, i.e., the metal of the vias 3, by an electrical process. The silicon substrate is then thinly polished from the side of the second surface, after which a second passivation layer 5' can be applied. Furthermore, with the aid of photolithographic structuring, UBM contact pads 6' are formed on the second surface 12, which can also be provided with a gold or nickel layer by electrochemical deposition. The silicon substrate 1 can then be cut to the correct shape and size, for example, using a plasma sawing process. The silicon substrate thus treated can then be peeled off from the carrier foil.

[0064] FIG. 2 shows a second embodiment of a silicon substrate 1 in a schematic cross-sectional view.

[0065] The silicon substrate 1 corresponds substantially to the silicon substrate 1 described in relation to Fig. 1. The manufacturing method can be similar. Although not explicitly shown, it is preferable that an insulating layer for the first via 3 is formed.

[0066] 1, the silicon substrate 1 of the second embodiment has a second via 31, which is preferably manufactured in the same manner as the first via 3. This second via 31 also has contact pads 61 and 61' arranged on the first surface 11 or the second surface 12, similar to the contact pads 6 and 6' of the first via 3. In particular, the contact pad 61 of the second via 31 can be replaced by the contact pad 62 shown in FIG.

[0067] The ESD protection element 2 is separated from the second via 31 as well as from the first via 3 .

[0068] The second via 31 is connected to the ESD protection element 2 via a second redistribution line 41. The second redistribution line 41 is preferably fabricated corresponding to the first redistribution line 4.

[0069] In one application, preferably either the first via 3 or the second via 31 is a signal conductor, for example for an input or output signal. The other via is preferably grounded. In that way, the signal conductor can be protected from this grounded via via an ESD protection element.

[0070] The combination of the ESD protection element 2, the first via 3, the first redistribution line 4, the second via 31 and the second redistribution line 41 is defined as an ESD circuit.

[0071] The silicon substrate 1 shown in FIG. 2 is suitable as an intermediate component, also called an interposer, on the surface of which for example an ASIC can be arranged.

[0072] 3 shows a third embodiment of the silicon substrate 1 in a schematic cross-sectional view. The third embodiment of the silicon substrate 1 includes two ESD circuits, as defined for FIG. 2, which are integrated into a common silicon substrate 1. The structures may therefore largely correspond. However, fundamentally, in particular the two ESD protection elements 2 may differ, since they protect different electronic components with different ESD protection requirements.

[0073] However, in such a design, ESD protection of individual components can also be provided by one of the two ESD protection elements 2, and ESD protection at the system level can be provided by the other ESD protection element 2.

[0074] Similarly, it is possible to mount any number of ESD protection elements 2 on one substrate, that is, to integrate a large number of ESD circuits on one substrate.

[0075] 4 shows a fourth embodiment of the silicon substrate 1. In this case, all the structures inside the silicon substrate 1 correspond to those of the first embodiment of the module, as shown in FIG.

[0076] However, unlike the first module shown in FIG. 3, in the second module additional redistribution lines 7 or 7' are embedded in the first passivation layer 5 or the second passivation layer 5'.

[0077] Additional redistribution lines 7 in the first passivation layer 5 connect each one of the two second vias 31 to a UBM contact pad 61 on the outer (top) surface of the first passivation layer 5 .

[0078] One or both of the additional rewirings 7, in particular the grounded additional rewiring 7, may include adaptive elements. These may include capacitances, inductances or delay elements, i.e., for example, coils or capacitors may be part of the additional rewirings 7. The delay is determined in particular by the length of the additional rewirings 7. In other words, a delay element may be an element that increases the line length of the additional rewirings 7 and thus can delay a possible ESD pulse.

[0079] In the second passivation layer 5' on the underside of the substrate, an additional rewiring 7' connects one of the second vias 31 to a UBM contact pad 61' that is located directly on the other second via 31, similar to the UBM contact pad in the previous example.

[0080] A further redistribution line 7' in the second passivation layer 5' connects one of the first vias 3 to a further UBM contact pad 6'.

[0081] As in the previous example, for example, either the first or second via can be grounded, while the other of the two can form or be connected to a signal conductor, respectively.

[0082] FIG. 5 shows a MEMS microphone 100 as a possible application of the present invention.

[0083] The MEMS microphone 100 comprises a substrate 101. The substrate 101 can correspond to the silicon substrate 1, as described with reference to Figures 1 to 5 shown above, or the silicon substrate 1 is part of the substrate 101. That is, in the area marked here as silicon substrate 1, for example, one or more ESD circuits are present, as described with reference to Figure 2, for example.

[0084] One or more ESD protection elements included in the ESD circuit protect components and / or ensure ESD protection at a system level for the ASIC 102 of the MEMS microphone 100 located on or above the substrate 101.

[0085] The ASIC 102 may be electronically connected to UBM contact pads (not shown) or vias connected thereto, for example, via solder bumps, as described in the previous examples.

[0086] Further components of the MEMS microphone include, for example, a sound aperture 103 in the substrate 101, a membrane 104, a back plate (electrostatic capacitor plate) 105, and a rear chamber 106 that forms the back volume of the MEMS microphone.

[0087] Preferably, a wrapping 107 made of a polymer film is applied over the component. The wrapping 107 is different from the passivation layer described with reference to Figure 1. The MEMS component may be closed by, for example, a metal cover 108.

[0088] A further application of the substrate 1 according to the invention is shown in FIG.

[0089] FIG. 6 shows a printed circuit board (PCB) 52 having a number of electronic components 53 disposed thereon.

[0090] Furthermore, a silicon substrate 1 according to the present invention, here functioning as an interposer, is mounted on the circuit board 52. The silicon substrate 1 may correspond to that of Figure 3 as shown, but may alternatively correspond to other embodiments described herein.

[0091] In particular, a plurality of ESD protection elements 2 are integrated into a silicon substrate 1 .

[0092] On top of the silicon substrate 1 an ASIC 50 is mounted, which for example has its own additional ESD protection structures 51. These are preferably individual protection structures for one or more components of the ASIC.

[0093] In that way, one of the ESD protection devices 1 can provide ESD protection at the system level in a compatible manner.

[0094] Connections between the various components may be made by solder bumps 32 mounted on the UBM contact pads.

[0095] FIG. 7 shows an ESD protection arrangement on a circuit board 52 according to the prior art prior to the present invention.

[0096] The ESD protection element 2' not according to the invention is now arranged in an on-board configuration on the substrate 1' not according to the invention, and therefore requires additional space in addition to the structure to be protected (ASIC 50).

[0097] This reduces the number of components on the circuit board, i.e., the integration density, as becomes clear from a comparison with the illustration of the present invention in Figure 6. In other words, the present invention allows for a higher integration density. [Explanation of symbols]

[0098] 1. Silicon substrate 1' Substrate not according to the present invention 2 ESD protection devices 2' On-board ESD protection device not according to the present invention 3 First via 4. First Rewiring 5 First passivation layer 5' Second passivation layer 6,6' UBM contact pad of first via 7,7' Additional rewiring 11 First Surface 12 Second Surface 30 First rewiring insulating layer 31 Second Via 32 solder bumps 41 Second Rewiring 50 ASIC 51 ESD protection structure for ASIC 52 Circuit Board 61,61' UBM contact pad for second via 62 Second UBM Contact Pad 100 MEMS microphones 101 MEMS microphone board 102 MEMS microphone ASIC 103 Sound Aperture 104 Membrane 105 Back Plate 106 Rear Chamber 107 Wrapping 108 Metal Cover

Claims

1. A silicon substrate (1) comprising: an integrated circuit on a first surface (11); a second surface (12) opposite the first surface (11); a first via (3); and an ESD protection element (2); The ESD protection element (2) is completely integrated into the silicon substrate; The ESD protection element (2) is spatially separated from the first via (3); The ESD protection element (2) is connected to the via by a first rewiring (4), The ESD protection element (2) includes at least one component selected from the group including a suppressor diode, a transistor, and a thyristor; The ESD protection element (2) further comprises an EMI protection structure, the EMI protection structure being embedded in the silicon substrate together with the ESD protection element.

2. The silicon substrate (1) of claim 1, wherein the ESD protection element (2) ensures ESD protection at a system level.

3. The silicon substrate (1) according to claim 1 or 2, wherein the ESD protection element ensures input-signal to output-signal protection at a system level for multiple electronic components or integrated circuits.

4. 4. The silicon substrate (1) according to claim 2 or 3, wherein some electronic components or integrated circuits have, in addition to the ESD protection at the system level, individual ESD protection arranged in the respective on-chip structures.

5. The silicon substrate (1) according to any one of the preceding claims, wherein the EMI protection structure is formed by a coil structure, a thin film resistor and / or a capacitance.

6. The silicon substrate (1) according to any one of claims 1 to 5, wherein the ESD protection element (2) has an embedded structure consisting of a combination of a thyristor and a diode structure which is not part of the thyristor.

7. 7. The silicon substrate (1) according to claim 1, wherein the ESD protection element (2) is in contact with a first passivation layer (5) formed on the first surface (11) of the silicon substrate (1).

8. At least one additional rewiring (7), The additional redistribution lines (7) electrically connect the first vias (3) to UBM contact pads (61); The additional rewiring (7) includes adaptive elements; The silicon substrate (1) according to any one of the preceding claims, wherein the adaptive element comprises a capacitance, an inductance or a delay element.

9. a second via (31) extending through the silicon substrate from the first surface (11) to the second surface (12); The ESD protection element (2) is spatially separated from the second via (31); The ESD protection element (2) is connected to the second via (31) through a second rewiring (41); The silicon substrate (1) of any one of claims 1 to 8, wherein the ESD protection element (2), the first via (31), the first redistribution line (4), the second via (31) and the second redistribution line (41) thus coupled together form an ESD circuit.

10. The silicon substrate (1) according to claim 9, comprising a plurality of ESD circuits.

11. The silicon substrate (1) according to any one of the preceding claims, wherein the first via is insulated from the silicon substrate by an insulating layer (30).

12. The silicon substrate (1) according to claim 3 or 4, wherein the electronic component or integrated circuit comprises a MEMS microphone.

13. A method for manufacturing an ESD protection device (2) in a silicon substrate (1), comprising the steps of: The embedded structure of the ESD protection element (2) in the silicon substrate (1) is manufactured by a CMOS process, and the embedded structure of the ESD protection element (2) includes an EMI protection structure; The embedded structure of the ESD protection element (2) comprises at least one selected from the group consisting of a suppressor diode, a transistor, and a thyristor; A first UBM contact pad (6, 61) is produced on a first surface (11) of the silicon substrate (1); openings for vias (3, 31) between the first surface (11) and the second surface (12) of the silicon substrate (1) are created by laser or deep reactive ion etching, The opening is spatially separated from the buried structure of the ESD protection element (2); the inner wall of the opening is passivated; a via (3, 31) is created by filling the passivated opening with a first metal; A redistribution line (4, 41) made of a second metal is generated between the via (3, 31) and the buried structure of the ESD protection device (2).

14. the first metal is Cu; said vias (3, 31) being produced by filling said openings by an electrical process; The method for manufacturing an ESD protection device (2) in a silicon substrate (1) according to claim 13, wherein the second metal is Cu or Al.

15. 15. The method for manufacturing an ESD protection element (2) in a silicon substrate (1) according to claim 13 or 14, wherein a passivation layer (5, 5') is produced on the first surface (11) and on the second surface (12).

16. A silicon substrate (1) comprising: an integrated circuit on a first surface (11); a second surface (12) opposite the first surface (11); a first via (3); and an ESD protection element (2), The ESD protection element (2) is completely integrated into the silicon substrate; The ESD protection element (2) is spatially separated from the first via (3); The ESD protection element (2) is connected to the via by a first rewiring (4), The ESD protection element (2) includes at least one component selected from the group including a suppressor diode, a transistor, and a thyristor; The ESD protection device (2) is a silicon substrate (1) that ensures ESD protection at a system level.

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