Semiconductor package, electronic device, and method for manufacturing semiconductor package

Abstract

An objective of the present invention is to add a circuit to a semiconductor package while minimizing an increase in the size of the semiconductor package.　The semiconductor package comprises a transparent member, an embedding resin, an embedded circuit, and a solid-state image capture element. In this semiconductor package, the embedding resin is formed around the periphery of the transparent member. Furthermore, in this semiconductor package, the embedded circuit is embedded in the embedding resin. Moreover, in this semiconductor package, the solid-state image capture element photoelectrically converts light passing through the transparent member and generates image data.

Description

[Technical field]

[0001] The present technology relates to a semiconductor package, and more particularly to a semiconductor package that generates image data, an electronic device, and a method for manufacturing the semiconductor package. [Background technology]

[0002] Conventionally, semiconductor packages have been used in which a semiconductor integrated circuit is mounted on a substrate and sealed for the purpose of making the semiconductor integrated circuit easier to handle, etc. For example, a semiconductor package has been proposed in which an image sensor is mounted inside a frame material as a semiconductor integrated circuit, and the top of the frame material is covered with glass to seal the package (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5885690 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above-mentioned conventional technology, it is difficult to add a circuit without changing the size of the semiconductor package. If a SiP (System in Package) technology is used, which connects multiple semiconductor chips and houses them in one package, a circuit can be added, but the size of the semiconductor package increases. For example, in the SiP, a side-by-side method in which an additional semiconductor chip is arranged next to a semiconductor chip increases the area of ​​the semiconductor package. In addition, in the SiP, a stack method in which multiple semiconductor chips are stacked increases the thickness of the semiconductor package. Thus, in the above-mentioned conventional technology, there is a problem that it is not possible to add a circuit while suppressing an increase in the size of the semiconductor package.

[0005] The present technology has been developed in view of the above circumstances, and aims to add circuits to a semiconductor package provided with a solid-state imaging element while suppressing an increase in the size of the semiconductor package. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a semiconductor package including a transparent member, an embedding resin formed around the transparent member, an embedded circuit embedded in the embedding resin, and a solid-state imaging element that photoelectrically converts light transmitted through the transparent member to generate image data, and a manufacturing method thereof. This brings about an effect that the function of the semiconductor package is improved by the circuit embedded in the embedding resin.

[0007] In addition, in the first aspect, the semiconductor device may further include a redistribution layer in which a signal line is wired to connect the embedded circuit and the solid-state imaging element, thereby providing an effect of transmitting data between the embedded circuit and the solid-state imaging element.

[0008] In addition, in the first aspect, an external terminal arranged in the fan-out region may be further included, thereby providing an effect that data is transmitted between an external device and the external terminal arranged in the fan-out region.

[0009] In addition, in the first aspect, the semiconductor memory device may further include external terminals arranged in the fan-out region and the fan-in region, thereby providing an effect that data is transmitted between an external device and the external terminals arranged in the fan-out region and the fan-in region.

[0010] In addition, in the first side, an opening may be formed in a region corresponding to the transparent member, and a frame may be further provided that is laminated on the embedding resin, thereby improving heat dissipation and reinforcing the semiconductor package.

[0011] In addition, in the first aspect, the solid-state imaging device may further include a ceramic substrate having a cavity and an external terminal formed on the ceramic substrate, and the solid-state imaging element may be provided in the cavity and connected to the ceramic substrate by a wire, thereby improving the functionality of the ceramic package.

[0012] In addition, in the first aspect, the device may further include a heater that heats the transparent member when the humidity in the cavity exceeds a predetermined threshold, and the embedded circuit may include a humidity sensor that measures the humidity and detects whether the humidity exceeds the threshold, thereby providing the effect of heating the transparent member in response to the humidity.

[0013] In addition, in the first aspect, the embedded circuit may include a control circuit that controls optical characteristics of the transparent member, thereby providing an effect that the optical characteristics of the transparent member are adjusted.

[0014] In addition, in the first aspect, an antenna may be further provided, and the embedded circuit may include a wireless circuit that performs wireless communication via the antenna, thereby achieving an effect of achieving wireless communication functionality.

[0015] In addition, in the first aspect, the semiconductor device may further include a heat dissipation member embedded in the embedding resin, the heat dissipation member dissipating heat generated in the embedded circuit, thereby providing an effect of suppressing a temperature rise in the embedded circuit.

[0016] In the first aspect, the heat dissipation member may be shaped like a column, thereby providing an effect that the columnar heat dissipation member suppresses a temperature rise in the embedded circuit.

[0017] In addition, in the first aspect, the display device may further include a resin dam formed between a periphery of a pixel array portion of the solid-state imaging element and the transparent member, thereby providing an effect of forming a space between the solid-state imaging element and the transparent member.

[0018] In the first aspect, the solid-state imaging element may be connected to the transparent member via a bump, thereby preventing chip shift.

[0019] A second aspect of the present technology is an electronic device including a transparent member, an embedding resin formed around the transparent member, an embedding circuit embedded in the embedding resin, a solid-state image sensor that photoelectrically converts light transmitted through the transparent member to generate image data, and an optical unit that collects incident light and guides it to the transparent member. This provides an effect that the function of the electronic device is improved by the circuit embedded in the embedding resin. [Brief description of the drawings]

[0020] [Figure 1] 1 is a block diagram showing a configuration example of an electronic device according to a first embodiment of the present technology. [Diagram 2] 1 is a cross-sectional view showing a configuration example of a semiconductor package according to a first embodiment of the present technology. [Diagram 3] 1 is an example of a plan view of a semiconductor package according to a first embodiment of the present technology. [Figure 4] 1 is an example of a plan view of a semiconductor package to which an embedded circuit is added according to a first embodiment of the present technology. [Diagram 5] 4A to 4C are diagrams for explaining a manufacturing process of a semiconductor package up to the formation of a redistribution layer in the first embodiment of the present technology. [Figure 6] 2A to 2C are diagrams for explaining a manufacturing process of a semiconductor package up to dicing of an image sensor wafer in the first embodiment of the present technology. [Figure 7]3A to 3C are diagrams for explaining a manufacturing process of a semiconductor package up to the formation of external terminals in the first embodiment of the present technology. [Figure 8] 2A to 2C are diagrams for explaining steps up to dicing in the first embodiment of the present technology. [Figure 9] 4 is a flowchart showing an example of a manufacturing process of a semiconductor package according to the first embodiment of the present technology. [Figure 10] 10A to 10D are diagrams for explaining a manufacturing process of a semiconductor package up to the formation of a redistribution layer in a first modified example of the first embodiment of the present technology. [Figure 11] 10A to 10C are diagrams for explaining a manufacturing process of a semiconductor package up to dicing of an image sensor wafer in a first modified example of the first embodiment of the present technology. [Figure 12] 10A to 10D are diagrams for explaining a manufacturing process of a semiconductor package up to the formation of an external terminal in a first modified example of the first embodiment of the present technology. [Figure 13] 10A to 10C are views for explaining a dicing step in a first modified example of the first embodiment of the present technology. [Figure 14] 11 is a cross-sectional view showing a configuration example of a semiconductor package according to a second modified example of the first embodiment of the present technology. FIG. [Figure 15] 13A to 13C are diagrams for explaining a manufacturing process of a semiconductor package up to the formation of a redistribution layer in the second modified example of the first embodiment of the present technology. [Figure 16] 13A to 13C are diagrams for explaining a manufacturing process of a semiconductor package up to dicing in a second modified example of the first embodiment of the present technology. [Figure 17] 13A to 13C are diagrams for explaining a manufacturing process of a semiconductor package up to wire bonding in a second modified example of the first embodiment of the present technology. [Figure 18] 11 is a cross-sectional view showing a configuration example of a semiconductor package according to a third modified example of the first embodiment of the present technology. FIG. [Figure 19] 11 is a cross-sectional view showing a configuration example of a semiconductor package according to a second embodiment of the present technology. FIG. [Figure 20] 13 is an example of a top view of a semiconductor package according to a second embodiment of the present technology. [Figure 21] 13 is an example of a bottom view of a semiconductor package according to a second embodiment of the present technology. [Figure 22] 11A to 11C are diagrams for explaining a manufacturing process of a semiconductor package up to embedding of a circuit according to a second embodiment of the present technology. [Figure 23] 11A to 11C are diagrams for explaining a manufacturing process of a semiconductor package up to flip chip connection according to a second embodiment of the present technology. [Figure 24] 11A to 11C are diagrams for explaining a manufacturing process of a semiconductor package up to the formation of external terminals according to a second embodiment of the present technology. [Diagram 25] 13A to 13C are diagrams for explaining a dicing process according to a second embodiment of the present technology. [Figure 26] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a third embodiment of the present technology. FIG. [Figure 27] 13A to 13C are diagrams for explaining a manufacturing process of a semiconductor package up to drilling in a third embodiment of the present technology. [Figure 28] 13A to 13C are diagrams for explaining a manufacturing process of a semiconductor package up to a layup according to a third embodiment of the present technology. [Figure 29] 13 is a diagram for explaining a collective pressing process according to a third embodiment of the present technology. FIG. [Diagram 30] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a fourth embodiment of the present technology. FIG. [Diagram 31] 13 is an example of a top view of a semiconductor package according to a fourth embodiment of the present technology. [Diagram 32] 13 is an example of a cross-sectional view of a semiconductor package according to a fourth embodiment of the present technology. [Diagram 33] 13A to 13C are diagrams for explaining a manufacturing process of a semiconductor package up to the formation of a measurement hole in a fourth embodiment of the present technology. [Diagram 34]13A to 13C are diagrams for explaining a manufacturing process of a semiconductor package up to wire bonding according to a fourth embodiment of the present technology. [Diagram 35] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a first modified example of a fourth embodiment of the present technology. FIG. [Diagram 36] 13 is an example of a cross-sectional view of a semiconductor package according to a first modified example of the fourth embodiment of the present technology. [Figure 37] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a second modified example of the fourth embodiment of the present technology. FIG. [Figure 38] 13 is an example of a cross-sectional view of a semiconductor package according to a second modified example of the fourth embodiment of the present technology. [Figure 39] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a fifth embodiment of the present technology. FIG. [Diagram 40] 13 is an example of a top view of a semiconductor package according to a fifth embodiment of the present technology. [Diagram 41] 13A to 13C are diagrams for explaining a manufacturing process of a semiconductor package up to peeling off of a support substrate according to a fifth embodiment of the present technology. [Diagram 42] 13A to 13C are diagrams for explaining a manufacturing process of a semiconductor package up to the formation of a redistribution layer according to a fifth embodiment of the present technology. [Diagram 43] 13A to 13C are diagrams for explaining a manufacturing process of a transparent member and a heat dissipation member in a first modified example of the fifth embodiment of the present technology. [Diagram 44] FIG. 23 is a cross-sectional view showing a configuration example of a semiconductor package according to a second modified example of the fifth embodiment of the present technology. [Diagram 45] 23A to 23D are diagrams for explaining a manufacturing process of a semiconductor package up to mounting a solid-state imaging element and an embedded circuit in a second modified example of the fifth embodiment of the present technology. [Figure 46] 13A to 13C are views for explaining a step of forming a redistribution layer in the second modified example of the fifth embodiment of the present technology. [Figure 47]FIG. 23 is a cross-sectional view showing a configuration example of a semiconductor package according to a third modified example of the fifth embodiment of the present technology. [Figure 48] 23A to 23D are diagrams for explaining a manufacturing process of a semiconductor package up to mounting a solid-state imaging element and an embedded circuit in a third modified example of the fifth embodiment of the present technology. [Figure 49] 13A to 13C are views for explaining a step of forming a redistribution layer in the third modified example of the fifth embodiment of the present technology. [Figure 50] FIG. 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a fourth modified example of the fifth embodiment of the present technology. [Figure 51] FIG. 23 is an example of a top view of a semiconductor package according to a fourth modified example of the fifth embodiment of the present technology. [Figure 52] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Diagram 53] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (example in which a circuit is embedded around a transparent member) 2. Second embodiment (an example in which a circuit is embedded around a transparent member and an external terminal is provided at the fan-in) 3. Third embodiment (an example in which a circuit is embedded around a transparent member and multiple layers are laminated) 4. Fourth embodiment (an example in which a circuit is embedded around a transparent member and the transparent member is heated according to humidity) 5. Fifth embodiment (an example in which a circuit is embedded around a transparent member and a heat dissipation member is provided) 6. Mobile application examples

[0022] <1. First embodiment> [Example of electronic device configuration] 1 is a block diagram showing a configuration example of an electronic device 100 according to a first embodiment of the present technology. The electronic device 100 is a device for capturing image data, and includes an optical unit 110, a solid-state imaging element 240, and a DSP (Digital Signal Processing) circuit 120. The electronic device 100 further includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. Examples of the electronic device 100 include digital cameras such as digital still cameras, as well as smartphones, personal computers, and vehicle-mounted cameras.

[0023] The optical unit 110 collects light from a subject and guides it to the solid-state imaging element 240. The solid-state imaging element 240 photoelectrically converts the incident light in synchronization with a vertical synchronization signal to generate image data. Here, the vertical synchronization signal is a periodic signal of a predetermined frequency that indicates the timing of imaging. The solid-state imaging element 240 supplies the generated image data to the DSP circuit 120.

[0024] The DSP circuit 120 executes a predetermined signal processing on the image data from the solid-state imaging device 240. The DSP circuit 120 outputs the processed image data via a bus 150 to a frame memory 160 or the like.

[0025] The display unit 130 displays image data. For example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal in accordance with a user's operation.

[0026] The bus 150 is a common path for the optical unit 110, the solid-state imaging device 240, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170 and the power supply unit 180 to exchange data with one another.

[0027] The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state imaging element 240, the DSP circuit 120, the display unit 130, and the like.

[0028] In the above-described configuration, for example, the solid-state imaging device 240 and the DSP circuit 120 are mounted in a semiconductor package.

[0029] [Example of semiconductor package configuration] 2 is a cross-sectional view showing an example of a configuration of a semiconductor package 200 according to the first embodiment of the present technology. The semiconductor package 200 includes an embedding resin 210, a transparent member 220, a rewiring layer 230, a solid-state imaging element 240, external terminals 251, bumps 252, and an underfill material 253.

[0030] The transparent member 220 transmits the incident light from the optical unit 110. For example, glass is used as the transparent member 220. The arrow in the figure indicates the incident direction of the incident light.

[0031] Hereinafter, the optical axis of the incident light is referred to as the "Z axis." A specific direction perpendicular to the Z axis is referred to as the "X axis," and a direction perpendicular to the X and Z axes is referred to as the "Y axis." The figure is a cross-sectional view seen from the Y axis direction.

[0032] The embedding resin 210 is a resin formed around the transparent member 220 when viewed from the Z-axis direction. Circuits such as embedded circuits 211 and 212 are embedded in this embedding resin 210. As the embedded circuit 211, for example, a circuit (such as the DSP circuit 120) that processes image data is provided. Furthermore, as the embedded circuit 212, for example, a memory that holds image data is provided. Furthermore, passive elements and active elements can be disposed in the embedded circuits 211 and 212.

[0033] The rewiring layer 230 is an insulating layer in which signal lines are wired to electrically connect the embedded circuits 211 and 212 to the solid-state imaging element 240. The rewiring layer 230 is formed below the embedding resin 210 with the optical section 110 facing upward.

[0034] Also, when viewed from the Z-axis direction, the redistribution layer 230 has an opening at its center, and the shape of the opening is similar to that of the transparent member 220, and the area thereof is slightly smaller than that of the transparent member 220. Therefore, when viewed from the Z-axis direction, a part of the inner side of the redistribution layer 230 overlaps with the vicinity of the outer periphery of the solid-state imaging element 240. A bump 252 is provided in this overlapping portion. The solid-state imaging element 240 and the signal line in the redistribution layer 230 are electrically connected via this bump 252.

[0035] The external terminals 251 are formed in a region on the lower surface of the redistribution layer 230 that is outside the solid-state imaging element 240. This outside region is also called a fan-out region. As the external terminals 251, for example, solder balls are provided.

[0036] The underfill material 253 is a member that encloses and seals the connection portion between the solid-state imaging element 240 and the rewiring layer 230 without any gaps in order to improve connection reliability, and is made of a resin or the like.

[0037] With the above-mentioned configuration, the solid-state imaging element 240 photoelectrically converts the light transmitted through the transparent member 220 to generate image data. Then, the solid-state imaging element 240 supplies the image data to the embedded circuits 211 and 212 via the signal lines in the rewiring layer 230.

[0038] As illustrated in the figure, the semiconductor package 200 does not have a package substrate. Instead, a rewiring layer 230 that draws out wiring from terminals (such as bumps 252) of a chip (such as a solid-state imaging element 240) is formed in a wafer-level process described below, and is connected to an external terminal 251 in a fan-out region. Such a semiconductor package 200 is generally called a FOWLP (Fan Out Wafer Level Package).

[0039] 3 is an example of a plan view of a semiconductor package 200 according to the first embodiment of the present technology. As illustrated in the figure, a transparent member 220 is rectangular when viewed from the Z-axis direction, and an embedding resin 210 having a rectangular outer periphery is formed around the transparent member 220. Embedded circuits 211 and 212 are embedded in the embedding resin 210.

[0040] As shown in the figure, by embedding embedded circuits 211 and 212 in embedding resin 210 around transparent member 220, it is possible to add circuits and increase functionality while suppressing an increase in the size of semiconductor package 200.

[0041] Using SiP technology, it is possible to add circuits, but in that case the size of the semiconductor package increases. For example, in the side-by-side SiP method, in which an additional semiconductor chip is arranged next to a semiconductor chip, the area of ​​the semiconductor package becomes larger. Also, in the stacked SiP method, in which multiple semiconductor chips are stacked, the thickness of the semiconductor package increases.

[0042] Although two circuits, ie, embedding circuits 211 and 212, are embedded, the number of embedding circuits is not limited to 2. For example, as illustrated in FIG. 4, in addition to the embedding circuits 211 and 212, an embedding circuit 213 can also be embedded.

[0043] Next, a method for manufacturing the semiconductor package 200 will be described.

[0044] [Semiconductor package manufacturing method] 5 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to the formation of the redistribution layer 230 in the first embodiment of the present technology. In the diagram, "a" is a diagram for explaining the process of placing the transparent member 220 and the embedded circuits 211 and 212 on the support substrate 701. In the diagram, "b" is a diagram for explaining the process of forming the embedding resin 210. In the diagram, "c" is a diagram for explaining the process of forming the redistribution layer 230.

[0045] The manufacturing system for semiconductor package 200 first places support substrate 701. The shape of support substrate 701 is circular when viewed from the Z direction, and its surface is divided into a plurality of rectangular chip regions. As illustrated in FIG. 1A, the manufacturing system places transparent member 220 on each of the chip regions on support substrate 701, and places embedded circuits 211 and 212 around the transparent member 220.

[0046] Next, as illustrated in FIG. 13B, the manufacturing system forms an embedding resin 210 around the transparent member 220 and embeds embedded circuits 211 and 212 therein.

[0047] Next, the manufacturing system forms a redistribution layer 230, as illustrated in FIG.

[0048] 6 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to dicing of the image sensor wafer 702 in the first embodiment of the present technology. In the diagram, "a" is a diagram for explaining the process of forming the solid-state imaging elements 240 and the like on the image sensor wafer 702. In the diagram, "b" is a diagram for explaining the process of dicing the image sensor wafer 702.

[0049] As shown in FIG. 1A, the manufacturing system divides the surface of the image sensor wafer 702 into a plurality of rectangular chip regions, and forms the solid-state imaging elements 240 and the bumps 252 for each chip region. Next, as shown in FIG. 1B, the manufacturing system separates the image sensor wafer 702 into individual chip regions by dicing.

[0050] The process illustrated in Fig. 5 and the process illustrated in Fig. 6 are executed in parallel. Note that the manufacturing system can also execute these processes in sequence.

[0051] 7 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to the formation of the external terminals 251 in the first embodiment of the present technology. In the diagram, "a" is a diagram for explaining the flip-chip connection process. In the diagram, "b" is a diagram for explaining the process of applying the underfill material 253. In the diagram, "c" is a diagram for explaining the process of mounting the external terminals 251.

[0052] As illustrated in FIG. 13A, the manufacturing system connects each of the individual solid-state imaging elements 240 to the corresponding rewiring layer 230 via bumps 252 (that is, flip-chip connection).

[0053] Next, as illustrated in FIG. 1B, the manufacturing system applies an underfill material 253 to the connection portion between the solid-state imaging element 240 and the rewiring layer 230 to seal it.

[0054] Next, as illustrated in c in the same figure, the manufacturing system mounts a predetermined number of external terminals 251 on the rewiring layer 230.

[0055] 8 is a diagram for explaining the process up to dicing in the first embodiment of the present technology. In the diagram, "a" is a diagram for explaining the process of peeling off the support substrate 701. In the diagram, "b" is a diagram for explaining the dicing process.

[0056] As illustrated in FIG. 13A, the manufacturing system peels off the support substrate 701 by heat, ultraviolet light, a laser, etc. Next, as illustrated in FIG. 13B, the manufacturing system dices the wafer on which the solid-state imaging elements 240 are mounted into individual chip regions.

[0057] FIG. 9 is a flowchart showing an example of a manufacturing process for the semiconductor package 200 according to the first embodiment of the present technology.

[0058] The manufacturing system for semiconductor package 200 places transparent member 220 on each chip region on support substrate 701, and places embedded circuits 211 and 212 around the transparent member 220 (step S901). The manufacturing system forms embedding resin 210 around transparent member 220 (step S902), and forms rewiring layer 230 (step S903).

[0059] The manufacturing system also divides the image sensor wafer into individual pieces, and flip-chip connects each of the divided solid-state imaging elements 240 to the corresponding redistribution layer 230 (step S904).

[0060] Next, the manufacturing system applies and seals the connection points between the solid-state imaging element 240 and the rewiring layer 230 with underfill material 253 (step S905), and mounts external terminals 251 (step S906). The manufacturing system then peels off the support substrate 701 (step S907), and dices the wafer into individual pieces (step S908). After step S908, the manufacturing system performs an inspection process or the like as necessary, and completes the manufacturing process for the semiconductor package 200.

[0061] Thus, according to the first embodiment of the present technology, by embedding the embedded circuits 211 and 212 in the embedding resin 210 formed around the transparent member 220, it is possible to suppress an increase in package size while increasing functionality by adding circuits.

[0062] [First Modification] In the above-described first embodiment, the support substrate 701 is peeled off after the solid-state imaging element 240 is flip-chip connected, but it can also be peeled off before flip-chip connection. The manufacturing method of the semiconductor package 200 of the first modified example of the first embodiment differs from the first embodiment in that the support substrate 701 is peeled off before flip-chip connection.

[0063] 10 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to the formation of the redistribution layer 230 in the first modified example of the first embodiment of the present technology. In the figure, "a" is a diagram for explaining the process of placing the transparent member 220 and the embedded circuits 211 and 212 on the support substrate 701. In the figure, "b" is a diagram for explaining the process of forming the embedding resin 210. In the figure, "c" is a diagram for explaining the process of forming the redistribution layer 230.

[0064] The manufacturing system places transparent members 220 in each of the chip regions on the support substrate 701, and places embedded circuits 211 and 212 around the transparent members 220, as shown in FIG. 13. Next, the manufacturing system forms an embedding resin 210 around the transparent members 220, as shown in FIG. 13, and forms a rewiring layer 230, as shown in FIG. 13.

[0065] 11 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to dicing of the image sensor wafer 702 in the first modified example of the first embodiment of the present technology. In the diagram, "a" is a diagram for explaining the process of peeling off the support substrate 701. In the diagram, "b" is a diagram for explaining the process of forming the solid-state imaging elements 240 and the like on the image sensor wafer 702. In the diagram, "c" is a diagram for explaining the process of dicing the image sensor wafer 702.

[0066] As shown in FIG. 11A, the manufacturing system peels off the support substrate 701. As shown in FIG. 11B, the manufacturing system forms the solid-state imaging elements 240 and the bumps 252 on the image sensor wafer 702. Next, as shown in FIG. 11C, the manufacturing system separates the image sensor wafer 702 into individual chip regions by dicing.

[0067] 10 to 11, and steps b and c in FIG. 11 are executed in parallel. The manufacturing system can also execute these steps in sequence. In addition, the steps after peeling off the support substrate 701 are executed on a dicing sheet, for example.

[0068] 12 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to the formation of the external terminals 251 in the first modified example of the first embodiment of the present technology. In the diagram, "a" is a diagram for explaining the flip-chip connection process. In the diagram, "b" is a diagram for explaining the process of applying the underfill material 253. In the diagram, "c" is a diagram for explaining the process of mounting the external terminals 251.

[0069] As shown in FIG. 1A, the manufacturing system flip-chip connects each of the individualized solid-state imaging elements 240. Next, as shown in FIG. 1B, the manufacturing system applies an underfill material 253 to the connection points between the solid-state imaging elements 240 and the rewiring layer 230 to seal them. Next, as shown in FIG. 1C, the manufacturing system mounts a predetermined number of external terminals 251 on the rewiring layer 230.

[0070] 13 is a diagram for explaining a dicing process in the first modified example of the first embodiment of the present technology. As illustrated in the figure, the manufacturing system separates a wafer on which solid-state imaging elements 240 are mounted into individual chip regions by dicing.

[0071] In this manner, in the first modified example of the first embodiment of the present technology, since the support substrate 701 is peeled off before flip-chip bonding, it is possible to omit the procedure of peeling off the support substrate 701 immediately before dicing.

[0072] [Second modified example] In the above-described first embodiment, the embedded circuits 211 and 212 are embedded around the transparent member 220 in the FOWLP, but the technique for embedding the embedded circuits 211 and 212 can also be applied to a ceramic package. The semiconductor package 200 of the second modified example of the first embodiment differs from the first embodiment in that the embedded circuits 211 and 212 are embedded around the transparent member 220 in the ceramic package.

[0073] 14 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a second modified example of the first embodiment of the present technology. As shown in the figure, the semiconductor package 200 in the second modified example of the first embodiment of the present technology is different from the first embodiment in that it includes a ceramic substrate 260 instead of the bumps 252 and the underfill material 253.

[0074] The ceramic substrate 260 is a substrate made of ceramic with a cavity formed therein. A predetermined number of signal lines 262 are wired in the ceramic substrate 260. The solid-state imaging element 240 is provided in the cavity, and is connected to the signal lines 262 by wires 261. The light-receiving surface is the upper surface, and the lower surface of the solid-state imaging element 240 is bonded to the ceramic substrate 260 by adhesive 263. The external terminals 251 are disposed on the lower surface of the ceramic substrate 260.

[0075] Furthermore, the cavity in the ceramic substrate 260 is sealed by the transparent member 220 and the redistribution layer 230. This sealed space is called a cavity.

[0076] 15 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to the formation of the redistribution layer 230 in the second modified example of the first embodiment of the present technology. In the diagram, "a" is a diagram for explaining the process of placing the transparent member 220 and the embedded circuits 211 and 212 on the support substrate 701. In the diagram, "b" is a diagram for explaining the process of forming the embedding resin 210. In the diagram, "c" is a diagram for explaining the process of forming the redistribution layer 230.

[0077] The manufacturing system places transparent members 220 in each of the chip regions on the support substrate 701, and places embedded circuits 211 and 212 around the transparent members 220, as shown in FIG. 13. Next, the manufacturing system forms an embedding resin 210 around the transparent members 220, as shown in FIG. 13, and forms a rewiring layer 230, as shown in FIG. 13.

[0078] 16 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to dicing in the second modified example of the first embodiment of the present technology. In the diagram, "a" is a diagram for explaining the process of peeling off the support substrate 701. In the diagram, "b" is a diagram for explaining the dicing process.

[0079] As shown in FIG. 7A, the manufacturing system peels off the support substrate 701, and as shown in FIG. 7B, the manufacturing system separates the support substrate 701 by dicing.

[0080] 17 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to wire bonding in the second modified example of the first embodiment of the present technology. In the diagram, "a" is a diagram for explaining the process of adhering the solid-state imaging element 240. In the diagram, "b" is a diagram for explaining the process of wire bonding.

[0081] As illustrated in FIG. 13A, the manufacturing system adheres the solid-state imaging element 240 to a silicon die used as a ceramic substrate 260 with an adhesive 263. Then, as illustrated in FIG. 13B, the manufacturing system connects the solid-state imaging element 240 to the ceramic substrate 260 with a wire 261 (i.e., wire bonding).

[0082] Then, the manufacturing system seals the cavity of the ceramic substrate 260 with the members separated by the process of FIG. 16 (that is, the transparent member 220, the embedding resin 210, and the rewiring layer 230).

[0083] The process illustrated in Fig. 16 and the process illustrated in Fig. 17 are executed in parallel. Note that the manufacturing system can also execute these processes in sequence.

[0084] In this manner, in the second variant of the first embodiment of the present technology, by embedding the embedded circuits 211 and 212 around the transparent member 220 in the ceramic package, it is possible to increase the functionality of the ceramic package while suppressing an increase in its size.

[0085] [Third modified example] In the above-described first embodiment, the embedded circuits 211 and 212 are embedded in the embedding resin 210 around the transparent member 220, but these circuits may generate heat when they operate. In addition, the strength of the semiconductor package 200 may be insufficient. The semiconductor package 200 of the third modified example of the first embodiment differs from the first embodiment in that a frame 270 is provided for the purpose of improving heat dissipation and providing reinforcement.

[0086] 18 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a third modified example of the first embodiment of the present technology. The semiconductor package 200 in the third modified example of the first embodiment of the present technology differs from the first embodiment in that it further includes a frame 270.

[0087] The frame 270 is a member in which an opening is formed when viewed from the Z direction, and the shape and area of ​​the opening approximately coincide with those of the transparent member 220. A material (such as copper or aluminum) having higher thermal conductivity and rigidity than the embedding resin 210 is used as the material for the frame 270. The frame 270 is laminated on the light-receiving side surface of the embedding resin 210.

[0088] The metal frame 270 is laminated to improve heat dissipation and reinforce the semiconductor package 200. The first or second modification of the first embodiment can be applied to the third modification of the first embodiment.

[0089] In this manner, according to the third modified example of the first embodiment of the present technology, by laminating the metal frame 270 on the embedding resin 210, the heat dissipation property of the semiconductor package 200 can be improved and reinforced.

[0090] <2. Second embodiment> In the above-described first embodiment, the external terminals 251 are provided in the fan-out region, but this configuration may result in an insufficient number of external terminals 251. The semiconductor package 200 of the second embodiment differs from the first embodiment in that the external terminals 251 are also provided in the fan-in region.

[0091] 19 is a cross-sectional view showing a configuration example of a semiconductor package 200 according to a second embodiment of the present technology. The rewiring layer 230 according to the second embodiment is formed around the solid-state imaging element 240 when viewed from the Z direction. In addition, a TMV (Through Mold Via) 231 is formed in the rewiring layer 230. In the fan-out region, an external terminal 251 is connected to the TMV 231. In addition, the rewiring layer 230 is formed on the lower surface of the semiconductor package 200 with the light-receiving side surface as the upper surface, and an external terminal 251 is also provided on the lower surface of the solid-state imaging element 240. This region below the solid-state imaging element 240 is called a fan-in region.

[0092] 20 is an example of a top view of a semiconductor package 200 according to the second embodiment of the present technology. As illustrated in the figure, in addition to embedded circuits 211 and 212, passive components 310 to 318 are further embedded in an embedding resin 210.

[0093] 21 is an example of a bottom view of a semiconductor package 200 according to the second embodiment of the present technology. The area surrounded by a dotted line in the figure corresponds to a fan-in area. The area around the fan-in area corresponds to a fan-out area. As illustrated in the figure, the external terminal 251 is arranged in the fan-in area in addition to the fan-out area.

[0094] 22 is a diagram for explaining a manufacturing process of a semiconductor package up to embedding of a circuit in the second embodiment of the present technology. In the diagram, "a" is a diagram for explaining a process of placing a transparent member 220 on a support substrate 701. In the diagram, "b" is a diagram for explaining a process of placing embedded circuits 211 and 212 on the support substrate 701. In the diagram, "c" is a diagram for explaining a process of forming an embedding resin 210.

[0095] As shown in FIG. 13A, the manufacturing system places transparent members 220 in each of the chip regions on the support substrate 701, and places embedded circuits 211 and 212 around the transparent members 220 as shown in FIG. 13B. Then, as shown in FIG. 13C, the manufacturing system forms embedding resin 210 around the transparent members 220, and embeds the embedded circuits 211 and 212 in the embedding resin 210.

[0096] 23 is a diagram for explaining the manufacturing process of a semiconductor package up to flip chip connection in the second embodiment of the present technology. In the diagram, a is a diagram for explaining the process of peeling off the support substrate 701. In the diagram, b is a diagram for explaining the wiring process of rewiring. In the diagram, c is a diagram for explaining the flip chip connection process.

[0097] The manufacturing system peels off the support substrate as shown in FIG. 1A, and wires signal lines (rewiring) as shown in FIG. 1B, and then flip-chip connects the solid-state imaging element 240 as shown in FIG. 1C.

[0098] 24 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to the formation of the external terminals in the second embodiment of the present technology. In the diagram, "a" is a diagram for explaining the process of forming the TMV 230. In the diagram, "b" is a diagram for explaining the process of forming the redistribution layer 231. In the diagram, "c" is a diagram for explaining the process of mounting the external terminals 251.

[0099] As shown in FIG. 13A, the manufacturing system forms a TMV 230 around a solid-state imaging element 240, and as shown in FIG. 13B, a redistribution layer 231 is formed in the redistribution layer 230. Then, as shown in FIG. 13C, external terminals 251 are mounted in the fan-in region and the fan-out region.

[0100] 25 is a diagram for explaining a dicing process according to the second embodiment of the present technology. As illustrated in the diagram, the manufacturing system performs individual division by dicing.

[0101] Thus, according to the second embodiment of the present technology, by arranging the external terminals 251 in the fan-in region in addition to the fan-out region, it is possible to arrange more external terminals 251 than when arranging them only in the fan-in region.

[0102] <3. Third embodiment> In the above-described first embodiment, the semiconductor package 200 is manufactured by sequentially performing processes such as forming the redistribution layer 230 and mounting the solid-state imaging element 240, but it is difficult to shorten the manufacturing lead time and reduce costs. The semiconductor package 200 of the third embodiment differs from the first embodiment in that the semiconductor package 200 is manufactured in a lump by stacking a plurality of layers and thermocompression bonding.

[0103] 26 is a cross-sectional view showing a configuration example of a semiconductor package 200 according to the third embodiment of the present technology. The semiconductor package 200 according to the third embodiment includes a laminated substrate 410 instead of the bumps 252 and the underfill material 253.

[0104] The laminated substrate 410 is formed by laminating a plurality of base materials. The solid-state imaging element 240 is provided in the laminated substrate 410. The laminated substrate 410 also has built-in components 411 and 412, such as resistors and capacitors, and a signal line 413 is wired thereto. The light-receiving surface is the upper surface, and mounted components 421 and 422 are mounted on the lower surface of the laminated substrate 410. Although the laminated substrate 310 has built-in components 411 and 412 built therein, it may have a configuration in which these built-in components are not included at all.

[0105] 27 is a diagram for explaining a manufacturing process of a semiconductor package up to drilling in the third embodiment of the present technology. In the diagram, a is a diagram for explaining a process of forming a conductive film. In the diagram, b is a diagram for explaining an etching process. In the diagram, c is a diagram for explaining a process of drilling.

[0106] As shown in FIG. 13A, the manufacturing system prepares a thermoplastic resin (such as a liquid crystal polymer) or an epoxy resin as a substrate 450, and forms a conductive film on the surface of the substrate 450. Then, as shown in FIG. 13B, the manufacturing system processes the conductive film by etching to form a signal line 413. Next, as shown in FIG. 13C, the manufacturing system uses a laser or the like to make holes in the substrate 450.

[0107] 28 is a diagram for explaining a manufacturing process of a semiconductor package up to layup in the third embodiment of the present technology. In the figure, a is a diagram for explaining a process of filling a conductive paste. In the figure, b is a diagram for explaining a process of layup.

[0108] As illustrated in FIG. 13A, the manufacturing system fills holes made by a laser or the like with a conductive paste (such as solder paste).

[0109] The manufacturing system also manufactures a plurality of base materials by the same manufacturing process. An opening having an area smaller than that of the solid-state imaging element 240 is provided in the base material 460 among these base materials, and a via for connecting to the solid-state imaging element 240 is formed around the opening. A composite material made of the transparent member 220 and the embedding resin 210 is also formed by the same method as in the first embodiment.

[0110] As illustrated in FIG. 13B, the manufacturing system lays up a composite material, a plurality of base materials, a rewiring layer 230, and a solid-state imaging element 240 in this order from the bottom up.

[0111] 29 is a diagram for explaining a batch pressing process in the third embodiment of the present technology. As illustrated in the figure, the manufacturing system heats the laid-up layers and presses them together (i.e., thermocompression bonding). This thermocompression bonding bonds the vias of the substrate to the solid-state imaging element 240. By stacking and thermocompression bonding multiple layers, the manufacturing lead time of the semiconductor package 200 can be shortened, and costs can be reduced.

[0112] As described above, according to the third embodiment of the present technology, a plurality of layers including the solid-state imaging element 240 and the like are stacked and thermocompression bonded, thereby simplifying the manufacturing process of the semiconductor package 200.

[0113] <4. Fourth embodiment> In the above-described first embodiment, the solid-state imaging element 240 is sealed by the transparent member 220, but if moisture is contained in the sealed space, the moisture may condense when the temperature drops, causing the transparent member 220 to cloud over. The semiconductor package 200 of this fourth embodiment differs from the first embodiment in that it measures humidity and heats the transparent member 220 when the humidity exceeds a threshold value.

[0114] 30 is a cross-sectional view showing a configuration example of a semiconductor package 200 according to a fourth embodiment of the present technology. In the semiconductor package 200 according to the fourth embodiment, a humidity sensor 510 is disposed in place of the embedded circuits 211 and 212. Furthermore, a measurement hole 511 penetrating from the cavity to the humidity sensor 510 is formed in the embedding resin 210 and the rewiring layer 230. Furthermore, a heater 512 is formed on the lower surface of the transparent member 220, with the light-receiving side surface serving as the upper surface.

[0115] Moreover, the semiconductor package 200 of the fourth embodiment is provided with a ceramic substrate 260 instead of the bumps 252 and the underfill material 253. The configuration of the ceramic substrate 260 of the fourth embodiment is similar to that of the second modified example of the first embodiment illustrated in FIG.

[0116] Humidity sensor 510 measures the humidity in a hollow (i.e., a cavity) in ceramic substrate 260 through measurement hole 511, and detects whether the humidity exceeds a predetermined threshold. This humidity sensor 510 supplies the detection result to heater 512. Heater 512 heats transparent member 220 when the humidity exceeds the threshold. Heating by heater 512 can prevent transparent member 220 from fogging due to condensation when the humidity increases.

[0117] 31 is an example of a top view of a semiconductor package 200 according to the fourth embodiment of the present technology. As illustrated in the figure, a humidity sensor 510 and passive components 521, 522, and 523 such as resistors and capacitors are embedded in an embedding resin 210 around a transparent member 220. The humidity sensor 510 and the passive components 521, 522, and 523 are an example of an embedded circuit as described in the claims.

[0118] Fig. 32 is an example of a cross-sectional view of the semiconductor package 200 in the fourth embodiment of the present technology. Fig. 32 shows a cross-sectional view of the semiconductor package 200 cut along the X1-X2 axis in Fig. 30. As illustrated in Fig. 32, a measurement hole 511 is opened in the rewiring layer 230 below the humidity sensor 510. In addition, a heater 512 is formed below the transparent member 220. For example, a transparent wiring is used as the heater 512. By using the transparent wiring, it is possible to suppress a decrease in translucency.

[0119] 33 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to the formation of the measurement hole 511 in the fourth embodiment of the present technology. In the figure, "a" is a diagram for explaining the process of placing the transparent member 220 and the humidity sensor 510 on the support substrate 701. In the figure, "b" is a diagram for explaining the process of forming the embedding resin 210. In the figure, "c" is a diagram for explaining the process of forming the rewiring layer 230 and the measurement hole 511.

[0120] As shown in FIG. 13A, the manufacturing system places transparent members 220 in each of the chip regions on support substrate 701, and places humidity sensors 510 around the transparent members 220. As shown in FIG. 13B, the manufacturing system then forms embedding resin 210 around the transparent members 220 and embeds the humidity sensors 510. As shown in FIG. 13C, the manufacturing system forms a rewiring layer 230 and forms a measurement hole 511 that penetrates the rewiring layer 230 and the embedding resin 210.

[0121] 34 is a diagram for explaining the manufacturing process of a semiconductor package up to wire bonding according to the fourth embodiment of the present technology. In the diagram, a is a diagram for explaining the process of adhering the solid-state imaging element 240. In the diagram, b is a diagram for explaining the process of wire bonding.

[0122] As illustrated in FIG. 13A, the manufacturing system bonds a solid-state imaging element 240 to a silicon die. Then, as illustrated in FIG. 13B, the manufacturing system connects the solid-state imaging element 240 to a ceramic substrate 260 by a wire 261.

[0123] The manufacturing system then seals the cavity in the ceramic substrate 260 with the individual members separated by the process of FIG.

[0124] The process illustrated in Fig. 33 and the process illustrated in Fig. 34 are executed in parallel. Note that the manufacturing system can also execute these processes in sequence.

[0125] In this way, according to the fourth embodiment of the present technology, when the humidity inside the cavity exceeds a threshold value, heater 512 heats transparent member 220, thereby making it possible to prevent transparent member 220 from fogging due to condensation.

[0126] [First Modification] In the above-described fourth embodiment, heater 512 heats transparent member 220 in response to humidity, but optical characteristics such as the amount of incident light and wavelength of transparent member 220 may be insufficient. The semiconductor package 200 of the first modification of the fourth embodiment differs from the fourth embodiment in that a circuit for controlling optical characteristics is embedded.

[0127] 35 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a first modified example of the fourth embodiment of the present technology. The semiconductor package 200 in the first modified example of the fourth embodiment differs from the fourth embodiment in that it includes a control circuit 531 instead of the humidity sensor 510 and includes a light control glass 532 instead of the transparent member 220. In addition, the measurement hole 511 is not formed, and the heater 512 is not arranged.

[0128] The control circuit 531 controls the optical characteristics of the light control glass 532. The light control glass 532 changes optical characteristics such as the amount of incident light and wavelength according to the control of the control circuit 531.

[0129] Fig. 36 is an example of a cross-sectional view of a semiconductor package 200 in a first modified example of the fourth embodiment of the present technology. Fig. 36 shows a cross-sectional view of the semiconductor package 200 cut along the X1-X2 axis in Fig. 35. As illustrated in Fig. 36, a control circuit 531 is connected to a light control glass 532 through a via.

[0130] Although the control circuit 531 is provided instead of the humidity sensor 510 and the heater 512, it is also possible to provide both the humidity sensor 510 and the control circuit 531 without eliminating the humidity sensor 510 and the heater 512. In other words, the first modified example of the fourth embodiment can be applied to the fourth embodiment.

[0131] In this way, according to the first modified example of the fourth embodiment of the present technology, the optical characteristics of the light control glass 532 are controlled by the control circuit 531, so that the optical characteristics can be adjusted to appropriate values.

[0132] [Second modified example] In the above-described fourth embodiment, the heater 512 heats the transparent member 220 in accordance with the humidity, but wireless transmission of image data may be required depending on the usage mode of the semiconductor package 200. The semiconductor package 200 of the second modification of the fourth embodiment differs from the fourth embodiment in that a wireless circuit is embedded.

[0133] 37 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a second modified example of the fourth embodiment of the present technology. The semiconductor package 200 in the second modified example of the fourth embodiment differs from the fourth embodiment in that it includes a wireless circuit 541 instead of the humidity sensor 510. In addition, the measurement hole 511 is not formed, and the heater 512 is not arranged.

[0134] Fig. 38 is an example of a cross-sectional view of the semiconductor package 200 in the second modified example of the fourth embodiment of the present technology. Fig. 38 shows a cross-sectional view of the semiconductor package 200 cut along the X1-X2 axis in Fig. 37. As illustrated in Fig. 38, an antenna 542 is formed in the rewiring layer 230 and is connected to a wireless circuit 541.

[0135] The wireless circuit 541 performs wireless communication via the antenna 542. For example, the wireless circuit 541 wirelessly transmits image data. Note that the wireless circuit 541 can also wirelessly receive data from the outside.

[0136] Although wireless circuit 541 and the like are provided instead of humidity sensor 510 and heater 512, it is also possible to dispose both humidity sensor 510 and the like and wireless circuit 541 and the like without eliminating humidity sensor 510 and heater 512. In other words, the second modified example of the fourth embodiment can be applied to the fourth embodiment. Moreover, the first modified example of the fourth embodiment can be applied to the second modified example of the fourth embodiment.

[0137] In this manner, according to the second modification of the fourth embodiment of the present technology, by providing the radio circuit 541 and the antenna 542, wireless communication can be performed.

[0138] <5. Fifth embodiment> In the above-mentioned first embodiment, embedded circuits 211 and 212 are embedded around transparent member 220, but these circuits generate heat when they operate, and if the amount of heat dissipation is insufficient, it is difficult to suppress the temperature rise. The semiconductor package 200 of this fifth embodiment differs from the first embodiment in that a heat dissipation member is further provided to dissipate heat generated in embedded circuits 211 and 212 to the outside.

[0139] 39 is a cross-sectional view showing a configuration example of a semiconductor package 200 according to the fifth embodiment of the present technology. The semiconductor package 200 according to the fifth embodiment includes a composite material 610, a rewiring layer 230, and an external terminal 251.

[0140] The composite material 610 is a member formed by combining the transparent member 220 with an embedding resin 611. The solid-state imaging element 240 is provided below the transparent member 220, and the embedding resin 611 is formed around the transparent member 220 and the solid-state imaging element 240.

[0141] In the embedding resin 611, embedded circuits 211 and 212 are embedded in a circuit layer 613 around the solid-state imaging element 240. In addition, in the embedding resin 611, a heat dissipation layer 612 around the transparent member 220 has a heat dissipation member 614 embedded therein.

[0142] In addition, a rewiring layer 230 is formed below the composite material 610, and a predetermined number of external terminals 251 are mounted below the rewiring layer 230.

[0143] The heat dissipation member 614 dissipates heat generated in the embedded circuits 211 and 212. The heat dissipation member 614 is formed in the embedding resin 611 so as to penetrate from the embedded circuits 211 and 212 to the upper surface of the semiconductor package 200. The heat dissipation member 614 is made of a metal having good thermal conductivity, such as copper.

[0144] 40 is an example of a top view of the semiconductor package 200 according to the fifth embodiment of the present technology. As illustrated in the figure, a rectangular heat dissipation member 614 is formed around the transparent member 220 in the embedding resin 210. By dissipating heat from the heat dissipation member 614, it is possible to suppress a rise in temperature of the embedded circuits 211 and 212 during operation.

[0145] 41 is a diagram for explaining a manufacturing process of a semiconductor package up to peeling off of a support substrate 701 according to a fifth embodiment of the present technology. In the diagram, "a" is a diagram for explaining a process of placing a transparent member 220 and a heat dissipation member 614 on the support substrate 701. "b" in the diagram is a diagram for explaining a process of forming an embedding resin 611. "c" in the diagram is a diagram for explaining a process of peeling off the support substrate 701.

[0146] As shown in FIG. 13A, the manufacturing system places the transparent member 220 on the support substrate 701, and places the heat dissipation member 614 around the transparent member 220. Then, as shown in FIG. 13B, the manufacturing system forms an embedding resin 210 around the transparent member 220, and embeds the heat dissipation member 614. Next, as shown in FIG. 13C, the manufacturing system peels off the support substrate 701.

[0147] 42 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to the formation of the redistribution layer 230 in the fifth embodiment of the present technology. In the diagram, "a" is a diagram for explaining the process of bonding the embedded circuits 211 and 212 to the solid-state imaging element 240. In the diagram, "b" is a diagram for explaining the process of forming the embedding resin 611. In the diagram, "c" is a diagram for explaining the process of forming the redistribution layer 230.

[0148] As shown in FIG. 13A, the manufacturing system bonds the embedded circuits 211 and 212 and the solid-state imaging element 240 to a composite material with their terminal sides facing downward. The filter surface of the solid-state imaging element 240 is covered with a cover 241. It is desirable to bond the heat dissipation member 614 and the embedded circuits 211 and 212 with a material having good thermal conductivity.

[0149] Then, as illustrated in b in the figure, the manufacturing system forms an embedding resin 611 around the solid-state imaging element 240 and embeds the embedded circuits 211 and 212. Next, as illustrated in c in the figure, a rewiring layer 230 is formed and the terminals are exposed by grinding.

[0150] Then, the manufacturing system mounts the external terminals 251 to manufacture the semiconductor package 200 having the structure illustrated in FIG.

[0151] In the manufacturing system, the solid-state imaging element 240 and the like are bonded after peeling off the support substrate 701, but the manufacturing method is not limited to this. If warping is a problem in the process, the solid-state imaging element 240 and the like can be bonded with the support substrate 701 still attached.

[0152] As described above, according to the fifth embodiment of the present technology, by embedding the heat dissipation member 614 that dissipates heat generated in the embedded circuits 211 and 212, it is possible to suppress a rise in temperature of the embedded circuits 211 and 212 during operation.

[0153] [First Modification] In the above-described fifth embodiment, transparent member 220 is placed on supporting substrate 701, and heat dissipation member 614 is placed around it, but this manufacturing method makes it difficult to shorten the manufacturing lead time and reduce costs of semiconductor package 200. The manufacturing method of the first modified example of the fifth embodiment differs from the fifth embodiment in that the process of placing transparent member 220 and heat dissipation member 614 is simplified.

[0154] FIG. 43 is a diagram for explaining a manufacturing process of transparent member 220 and heat dissipation member 614 in the first modified example of the fifth embodiment of the present technology. As illustrated in the figure, the manufacturing system prepares a circular glass-mounted wafer 705. This glass-mounted wafer 705 is divided into a plurality of chip regions. Among the dotted line regions in the figure, the regions surrounded by solid lines around a rectangle correspond to the chip regions. Each chip region is provided with transparent member 220 and heat dissipation member 614 formed around it.

[0155] The manufacturing system separates the glass-mounted wafer 705 along the dicing lines. This provides each chip with a transparent member 220 and a heat dissipation member 614. The process after dicing is the same as in the fifth embodiment.

[0156] In this manner, in the first variant of the fifth embodiment of the present technology, the glass-mounted wafer 705 is diced into individual chips, thereby providing a transparent member 220 and a heat dissipation member 614 for each chip, thereby simplifying the manufacturing process.

[0157] [Second modified example] In the above-described fifth embodiment, the image surface side of the solid-state imaging element 240 is bonded to the composite material 610, but it is preferable to form a space between the solid-state imaging element 240 and the transparent member 220. The semiconductor package 200 of the second modified example of the fifth embodiment differs from the fifth embodiment in that a resin dam is provided to form a space between the solid-state imaging element 240 and the transparent member 220.

[0158] 44 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a second modified example of the fifth embodiment of the present technology. The semiconductor package 200 in the second modified example of the fifth embodiment differs from the fifth embodiment in that it further includes a resin dam 620.

[0159] The resin dam 620 is a resin formed between the periphery of the pixel array portion of the solid-state imaging device and the transparent member 220 .

[0160] 45 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to the mounting of the solid-state imaging element 240 and the embedded circuits 211 and 212 in the second modified example of the fifth embodiment of the present technology. In the figure, "a" is a diagram for explaining the process of applying ultraviolet curable resin. In the figure, "b" is a diagram for explaining the process of forming a resin dam 620. In the figure, "c" is a diagram for explaining the process of mounting the solid-state imaging element 240 and the embedded circuits 211 and 212.

[0161] As shown in FIG. 13A, the manufacturing system applies ultraviolet curing resin or the like to the surface of the composite material 610 with the heat dissipation member 614 embedded therein. Then, the manufacturing system uses a mask to irradiate ultraviolet rays only to the portion of the ultraviolet curing resin that is to be left as the resin dam 620, thereby curing the resin, and removes the remainder with a developer to form the resin dam 620. Next, the manufacturing system mounts the solid-state imaging element 240 and the embedded circuits 211 and 212, as shown in FIG. 13C.

[0162] Fig. 46 is a diagram for explaining a process of forming a redistribution layer 230 in the second modified example of the fifth embodiment of the present technology. As illustrated in the figure, the manufacturing system forms the redistribution layer 230 and exposes the terminals by grinding. Then, the manufacturing system places the external terminals 251 to manufacture the semiconductor package 200 having the structure illustrated in Fig. 39.

[0163] Thus, according to the second variant of the fifth embodiment of the present technology, by placing a resin dam 620 between the solid-state imaging element 240 and the transparent member 220, a space can be provided between the solid-state imaging element 240 and the transparent member 220.

[0164] [Third modified example] In the second modified example of the fifth embodiment described above, the resin dam 620 is disposed between the solid-state imaging element 240 and the transparent member 220. However, in this configuration, since the resin dam 620 is liquid before hardening, the position of the solid-state imaging element 240 may deviate from a specified position. This phenomenon is also called chip shift. The semiconductor package 200 of the third modified example of the fifth embodiment differs from the second modified example of the fifth embodiment in that chip shift is prevented by connection using bumps.

[0165] 47 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a third modified example of the fifth embodiment of the present technology. The semiconductor package 200 in the third modified example of the fifth embodiment differs from the second modified example of the fifth embodiment in that a bump 621 is further provided.

[0166] The bumps 621 are disposed around the pixel array portion of the solid-state imaging element 240. The solid-state imaging element 240 and the transparent member 220 are connected via the bumps 621. This makes it possible to fix the position of the solid-state imaging element 240 and prevent chip shift.

[0167] 48 is a diagram for explaining the manufacturing process of the semiconductor package 200 up to the mounting of the solid-state imaging element 240 and the embedded circuits 211 and 212 in the third modified example of the fifth embodiment of the present technology. In the figure, "a" is a diagram for explaining the process of applying ultraviolet curable resin. In the figure, "b" is a diagram for explaining the process of forming the bumps 621 and the resin dams 620. In the figure, "c" is a diagram for explaining the process of mounting the solid-state imaging element 240 and the embedded circuits 211 and 212.

[0168] As shown in FIG. 1A, the manufacturing system applies ultraviolet curing resin or the like to the surface of the composite material 610 in which the heat dissipation member 614 is embedded. Then, the manufacturing system uses a mask to irradiate ultraviolet rays only to a portion of the ultraviolet curing resin to be left as the resin dam 620, hardening it, and removes the remainder with a developer to form the resin dam 620. The manufacturing system also provides a predetermined number of bumps 621 on the inside of the resin dam 620. Next, the manufacturing system mounts the solid-state imaging element 240 and the embedded circuits 211 and 212, as shown in FIG. 1C. The solid-state imaging element 240 is connected to the transparent member 220 via the bumps 621.

[0169] Fig. 49 is a diagram for explaining a process of forming a redistribution layer 230 in the third modified example of the fifth embodiment of the present technology. As illustrated in the figure, the manufacturing system forms the redistribution layer 230 and exposes the terminals by grinding. Then, the manufacturing system places the external terminals 251 to manufacture the semiconductor package 200 having the structure illustrated in Fig. 39.

[0170] In the fifth embodiment and the first to third modified examples thereof, the solid-state imaging element 240 is disposed in the center of the semiconductor package 200, but the present invention is not limited to this configuration. As described later, the solid-state imaging element 240 may be disposed in a position shifted from the center of the semiconductor package 200. The composite material 610 may have a structure having a heat path using the rewiring layer 230 in order to move heat generated by the solid-state imaging element 240 itself through a heat dissipation path to the upper surface. To realize this structure, for example, a heat dissipation member such as a metal penetrating the embedded resin 611 may be further disposed from the rewiring layer 230 to the upper surface of the semiconductor package 200.

[0171] Thus, according to the third variant of the fifth embodiment of the present technology, by connecting the solid-state imaging element 240 and the transparent member 220 via the bump 621, it is possible to prevent misalignment of the solid-state imaging element 240 (in other words, chip shift).

[0172] [Fourth Variation] In the above-described fifth embodiment, the heat dissipation member 614 having a rectangular outer periphery is formed around the transparent member 220 when viewed from the Z direction, but the shape of the heat dissipation member 614 may be columnar. This fourth modification of the fifth embodiment differs from the fifth embodiment in that a columnar heat dissipation member 614 is arranged.

[0173] 50 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a fourth modified example of the fifth embodiment of the present technology. The semiconductor package 200 in the fourth modified example of the fifth embodiment differs from the fifth embodiment in that the shape of the heat dissipation member 614 is a columnar shape (for example, a cylindrical shape) extending along the Z direction. In addition, the solid-state imaging element 240 is disposed at a position shifted from the center of the semiconductor package 200.

[0174] 51 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a fifth modified example of the fifth embodiment of the present technology. As shown in the figure, when the heat dissipation member 614 is cylindrical, the shape of the heat dissipation member 614 is circular when viewed from the Z direction.

[0175] In this manner, according to the fourth modification of the fifth embodiment of the present technology, by embedding the columnar heat dissipation members 614, it is possible to suppress an increase in temperature of the embedded circuits 211 and 212 during operation.

[0176] <6. Application examples for mobile devices> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0177] FIG. 52 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0178] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 52, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0179] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0180] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0181] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0182] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0183] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0184] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0185] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0186] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0187] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 52, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0188] FIG. 53 is a diagram showing an example of the installation position of the imaging unit 12031.

[0189] In FIG. 53, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0190] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0191] 53 shows an example of the imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0192] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0193] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0194] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0195] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0196] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, the electronic device 100 in FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to suppress an increase in the size of the imaging unit 12031 while increasing its functionality by adding a circuit.

[0197] The above-mentioned embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specified in the claims correspond to each other. Similarly, the matters specified in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist of the technology.

[0198] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0199] The present technology can also be configured as follows. (1) a transparent member; An embedding resin formed around the transparent member; an embedded circuit embedded in the embedding resin; a solid-state image sensor that generates image data by photoelectrically converting light that has passed through the transparent member; A semiconductor package comprising: (2) The semiconductor package according to (1) above, further comprising a rewiring layer on which signal lines connecting the embedded circuit and the solid-state imaging element are wired. (3) The semiconductor package according to (2) above, further comprising an external terminal arranged in a fan-out region. (4) The semiconductor package according to (2) above, further comprising external terminals arranged in the fan-out region and the fan-in region. (5) The semiconductor package according to any one of (2) to (4), further comprising a frame having an opening in an area corresponding to the transparent member and laminated to the embedding resin. (6) a ceramic substrate having a cavity formed therein; an external terminal formed on the ceramic substrate; Further comprising: The solid-state imaging element is provided in the cavity and is connected to the ceramic substrate by a wire. The semiconductor package according to (2) above. (7) further comprising a heater that heats the transparent member when the humidity in the cavity exceeds a predetermined threshold; The embedded circuitry includes a humidity sensor that measures the humidity and detects whether the humidity exceeds the threshold. The semiconductor package according to (6) above. (8) The embedded circuit includes a control circuit for controlling the optical characteristics of the transparent member. The semiconductor package according to (6) or (7) above. (9) further comprising an antenna; The embedded circuit includes a radio circuit for performing wireless communication via the antenna. A semiconductor package according to any one of (6) to (8). (10) Further comprising a heat dissipation member embedded in the embedding resin, The heat dissipation member dissipates heat generated in the embedded circuit. The semiconductor package according to (1) above. (11) The heat dissipation member has a columnar shape. The semiconductor package according to (10) above. (12) The imaging device further includes a resin dam formed between a periphery of a pixel array portion of the solid-state imaging element and the transparent member. The semiconductor package according to (10) or (11) above. (13) The solid-state imaging element is connected to the transparent member via bumps. The semiconductor package according to (12) above. (14) a transparent member; An embedding resin formed around the transparent member; an embedded circuit embedded in the embedding resin; a solid-state image sensor that photoelectrically converts light transmitted through the transparent member to generate image data; an optical unit that condenses incident light and guides it to the transparent member; An electronic device comprising: (15) an embedding resin forming step of forming an embedding resin around the transparent member on a support substrate on which the transparent member and the embedded circuit are placed, and embedding the embedded circuit in the embedding resin; A mounting procedure for mounting a solid-state imaging element that generates image data; A method for manufacturing a semiconductor package comprising the steps of: (16) a rewiring layer forming step of forming a rewiring layer in which a signal line connecting the embedded circuit and the solid-state imaging element is wired; a peeling step of peeling off the support substrate after the solid-state imaging element is mounted; Further comprising A method for manufacturing a semiconductor package according to (15) above. (17) a rewiring layer forming step of forming a rewiring layer in which a signal line connecting the embedded circuit and the solid-state imaging element is wired; a peeling step of peeling off the support substrate after the redistribution layer is formed; Further comprising: In the placement step, the solid-state imaging element is mounted after the support substrate is peeled off. A method for manufacturing a semiconductor package according to (15) above. (18) The method further includes a dicing step for dividing a plurality of chip regions on a wafer on which a transparent member and a heat dissipation member formed around the transparent member are formed. A method for manufacturing a semiconductor package according to (15) above. (19) forming an embedding resin around the transparent member and embedding the embedded circuit in the embedding resin; a lamination step of laminating and thermocompression bonding a composite material made of the transparent member and the embedding resin, a plurality of base materials each having a signal line formed thereon, a rewiring layer, and a solid-state imaging element that photoelectrically converts light transmitted through the transparent member to generate image data; A method for manufacturing a semiconductor package comprising the steps of: [Explanation of symbols]

[0200] 100 Electronic equipment 110 Optics Department 120 DSP circuits 130 Display section 140 Operation section 150 Bus 160 Frame Memory 170 Storage section 180 Power supply section 200 Semiconductor Packages 210, 611 Embedding resin 211~213 Embedded circuit 220 Transparent materials 230 Redistribution layer 231 TMV 240 Solid-state image sensor 251 External terminal 252, 621 Bump 253 Underfill material 260 Ceramic Substrate 261 Wire 262, 413 signal line 263 Adhesive 270 frames 310~318, 521~523 Passive Components 410 Laminated Board 411, 412 Internal parts 421, 422 Mounting parts 450, 460 base material 510 Temperature Sensor 511 Measuring hole 512 Heater 531 Control circuit 532 Photochromic Glass 541 Radio circuit 542 Antenna 610 Composite Materials 612 Heat dissipation layer 613 Circuit layer 614 Heat dissipation materials 620 Resin Dam 701 Support Substrate 702 Image sensor wafer 705 Glass-mounted wafer 12031 Imaging unit

Claims

1. A transparent member; An embedding resin formed around the transparent member; an embedded circuit embedded in the embedding resin; a solid-state image sensor that generates image data by photoelectrically converting light that has passed through the transparent member; Equipped with a ceramic substrate having a cavity formed therein; an external terminal formed on the ceramic substrate; Further comprising: the solid-state imaging element is provided in the cavity and connected to the ceramic substrate by a wire; the embedding resin overlaps with a region of the cavity surrounding the solid-state imaging element when viewed from the optical axis direction, One end of the wire is connected to the surrounding area. Semiconductor package.

2. 2. The semiconductor package according to claim 1, further comprising a rewiring layer on which signal lines connecting said embedded circuit and said solid-state image sensor are wired.

3. 3. The semiconductor package of claim 2, further comprising external terminals disposed in the fan-out region.

4. 3. The semiconductor package according to claim 2, further comprising external terminals disposed in the fan-out region and the fan-in region.

5. 3. The semiconductor package according to claim 2, further comprising a frame having an opening in a region corresponding to the transparent member and laminated on the embedding resin.

6. a heater for heating the transparent member when the humidity in the cavity exceeds a predetermined threshold; The embedded circuitry includes a humidity sensor that measures the humidity and detects whether the humidity exceeds the threshold.

2. The semiconductor package of claim 1.

7. The embedded circuitry includes a control circuit that controls an optical characteristic of the transparent member.

2. The semiconductor package of claim 1.

8. Further comprising an antenna, The embedded circuit includes a radio circuit for performing wireless communication via the antenna.

2. The semiconductor package of claim 1.

9. A transparent member; An embedding resin formed around the transparent member; an embedded circuit embedded in the embedding resin; a solid-state image sensor that generates image data by photoelectrically converting light that has passed through the transparent member; Equipped with Further comprising a heat dissipation member embedded in the embedding resin, The heat dissipation member dissipates heat generated in the embedded circuit, a resin dam formed between a periphery of a pixel array portion of the solid-state imaging element and the transparent member; the embedding resin includes a circuit layer in which the embedded circuit is embedded and a heat dissipation layer in which the heat dissipation member is embedded, The position on the optical axis of the boundary surface between the circuit layer and the heat dissipation layer is the same as the position on the optical axis of the boundary surface between the transparent member and the resin dam. Semiconductor package.

10. The heat dissipation member has a columnar shape.

10. The semiconductor package of claim 9.

11. The solid-state imaging element is connected to the transparent member via bumps.

10. The semiconductor package of claim 9.

12. A transparent member; An embedding resin formed around the transparent member; an embedded circuit embedded in the embedding resin; a solid-state image sensor that photoelectrically converts light transmitted through the transparent member to generate image data; an optical unit that condenses incident light and guides it to the transparent member; Equipped with a ceramic substrate having a cavity formed therein; an external terminal formed on the ceramic substrate; Further comprising: the solid-state imaging element is provided in the cavity and connected to the ceramic substrate by a wire; the embedding resin overlaps with a region of the cavity surrounding the solid-state imaging element when viewed from a direction perpendicular to a substrate plane of the ceramic substrate, One end of the wire is connected to the surrounding area. electronic equipment.

13. an embedding resin forming step of forming an embedding resin around the transparent member on a support substrate on which the transparent member and the embedded circuit are placed, and embedding the embedded circuit in the embedding resin; A mounting procedure for mounting a solid-state imaging element that generates image data; A method for manufacturing a semiconductor package comprising the steps of:

14. a rewiring layer forming step of forming a rewiring layer in which a signal line connecting the embedded circuit and the solid-state imaging element is wired; a peeling step of peeling off the support substrate after the solid-state imaging element is mounted; Further comprising The method for manufacturing a semiconductor package according to claim 13.

15. a rewiring layer forming step of forming a rewiring layer in which a signal line connecting the embedded circuit and the solid-state imaging element is wired; a peeling step of peeling off the support substrate after the redistribution layer is formed; Further comprising: In the mounting step, the solid-state imaging element is mounted after the support substrate is peeled off. The method for manufacturing a semiconductor package according to claim 13.

16. The method further includes a dicing step for dividing a plurality of chip regions on a wafer, each of which has a transparent member and a heat dissipation member formed around the transparent member. The method for manufacturing a semiconductor package according to claim 13.

17. an embedding resin forming step of forming an embedding resin around the transparent member and embedding the embedded circuit in the embedding resin; a lamination step of laminating and thermocompression bonding a composite material made of the transparent member and the embedding resin, a plurality of base materials each having a signal line formed thereon, a rewiring layer, and a solid-state imaging element that photoelectrically converts light transmitted through the transparent member to generate image data; A method for manufacturing a semiconductor package comprising the steps of:

Images