Flash memory

Abstract

To provide an AND-type flash memory that enables high integration by miniaturizing the memory cell size.SOLUTION: An AND-type flash memory according to the present invention includes a plurality of diffusion regions 70 formed in the column direction in a substrate, a plurality of gates 20 formed between opposing diffusion regions 70, selection control lines SGD, SGS, and a plurality of word lines WL0 to WLn-1, the selection control line SGD is connected to the gate of the bit line side selection transistor, the selection control line SGS is connected to the gate of the source line side selection transistor, the word lines WL0 to WLn-1 are connected to the gates of the memory cells, and the bit line side selection transistor, the source line side selection transistor, and the plurality of memory cells each have a channel area along the row direction.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present invention relates to a flash memory having an AND-type memory cell array structure. [Background technology]

[0002] Figure 1(A) shows an equivalent circuit of a conventional NOR type flash memory. As shown in the figure, the source / drain of each memory cell is connected between a bit line BL and a source line SL (virtual ground), and the gate is connected to a word line WL, allowing individual memory cells to be read or programmed. In a program operation, for example, 5V is applied to the bit line BL of a selected memory cell, 0V is applied to the source line SL, and 12V is applied to the word line WL, and 0V is applied to the bit line BL, source line SL, and word line WL of unselected memory cells.

[0003] In NOR flash memory, the gate length of the memory cell cannot be scaled below 100 nm, so there is a limit to the scaling of the memory cell. One of the reasons why the gate length cannot be scaled is the problem of punch-through during programming. If the gate length is scaled to be smaller than 100 nm in order to apply a large voltage to the bit line BL, punch-through occurs between the source and drain of the memory cell, making it difficult to suppress current leakage from the bit line BL to the source line SL. In addition, if the gate length cannot be scaled, the channel width cannot be scaled to obtain a read current during a read operation. Therefore, the memory cell size of NOR flash memory is almost at its limit.

[0004] FIG. 1(B) is a diagram showing an equivalent circuit of an AND-type flash memory (Non-Patent Document 1). In an AND-type flash memory, a plurality of memory cells are connected in parallel between a local bit line LBL and a local source line LSL, and each gate of the memory cells is connected to a word line WL. The local bit line LBL is connected to a bit line BL via a selection transistor on the bit line side, and the local source line LSL is connected to a source line SL via a selection transistor on the source line side. When a memory cell is selected, the selection transistor on the bit line side is turned on by a selection control line SG1, and the selection transistor on the source line side is turned on by a selection control line SG2.

[0005] In a program operation, for example, 4.5V is applied to the local bit line LBL of a selected memory cell, the local source line LSL is floated, and -9.5V is applied to the word line WL, while 0V is applied to the local bit line LBL of an unselected memory cell, the local source line LSL is floated, and 3V is applied to the word line. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] “A Shallow-Trench-Isolation Flash Memory Technology with a Source-Bias Programming Method” Masataka Kato, Tetsuo Adachi, and Toshihiro Tanaka, 1996 IEDM, p177-180. Summary of the Invention [Problem to be solved by the invention]

[0007] In the conventional AND-type flash memory described above, during program operation, the local source line LSL is floated, and electrons are removed from the floating gate FG to the drain due to the potential difference between the drain and floating gate. In this case, if the gate length is reduced, the source potential rises due to punch-through between the source and drain, and the potential of the floating gate FG rises due to the capacitance between the source and floating gate. This makes it difficult to remove electrons from the floating gate FG to the local bit line LBL via the drain. This has led to the issue that it is difficult to reduce the cell size.

[0008] An object of the present invention is to provide an AND-type flash memory that solves the conventional problems, reduces the memory cell size, and enables high integration. [Means for solving the problem]

[0009] The AND-type flash memory of the present invention comprises a memory cell array including a plurality of memory cells electrically connected in parallel between a source line and a bit line, and has a plurality of elongated diffusion regions formed in a substrate in the column direction, a plurality of gates formed between the opposing diffusion regions, a first selection line connected to each gate of the bit line side selection transistors in the row direction, a second selection line connected to each gate of the source line side selection transistors in the row direction, and a plurality of word lines respectively connected to each gate of the memory cells in the row direction, and the bit line side selection transistor, the source line side selection transistor and the plurality of memory cells each have a channel area along the row direction.

[0010] In one embodiment, the diffusion regions of the bit line side select transistor and the source line side select transistor are isolated from the diffusion regions of the memory cells. In one embodiment, the diffusion region includes a first isolation region that electrically isolates the diffusion region of the bit line side select transistor from the diffusion region of the memory cell adjacent to the bit line side select transistor, and a second isolation region that electrically isolates the diffusion region of the source line side select transistor from the diffusion region of the memory cell adjacent to the source line side select transistor. In one embodiment, the first and second isolation regions have a different conductivity type from the other diffusion regions. In one embodiment, the flash memory further includes a plurality of bit lines and a plurality of source lines formed on the substrate along the diffusion region, the bit lines being electrically connected to the diffusion region of the bit line side select transistor through contacts, and the source lines being electrically connected to the diffusion region of the source line side select transistor through contacts. In one embodiment, the diffusion region includes a metal silicide region. In one embodiment, an element isolation region is formed between one of the opposing diffusion regions and another of the opposing diffusion regions adjacent to the one of the opposing diffusion regions. In one embodiment, the memory cell includes at least three or more stacked insulator layers including a charge storage layer between the gate and the substrate. In one embodiment, the stacked insulator layers are separated for each memory cell. In one embodiment, when a program voltage is applied to the gate of a selected memory cell, the charge storage layer stores charge tunneled from the channel by FN tunneling. In one embodiment, when an erase voltage is applied to a well region, the charge storage layer releases the stored charge to the channel by tunneling. Effect of the Invention

[0011] According to the present invention, in an AND-type memory cell array, the bit line side select transistor, the source line side select transistor, and the multiple memory cells are each configured to have a channel area along the row direction, so that the design of the memory cell array can be facilitated and the memory cell array can be highly integrated. In addition, by reducing the resistance of the diffusion region by the metal silicide region, the number of memory cells connected in parallel between the bit line side select transistor and the source line side select transistor can be increased, and the memory cell array can be highly integrated. Furthermore, since the memory cell is configured to have at least three or more layers of stacked insulators including a charge storage layer, the memory cells can be miniaturized compared to conventional AND-type flash memories, and the manufacturing process can be simplified. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1A is an equivalent circuit of a NOR type flash memory, and FIG. 1B is an equivalent circuit of an AND type flash memory. [Figure 2A] 1 is a schematic cross-sectional view of a substrate of an AND-type flash memory according to an embodiment of the present invention. [Figure 2B] 1 is a schematic plan view of a memory cell array portion of an AND-type flash memory according to an embodiment of the present invention; [Diagram 3] 1A to 1C are plan views showing a manufacturing process of an AND-type flash memory according to an embodiment of the present invention, and are schematic plan views of a memory cell array portion. [Figure 4] 4 is a cross-sectional view taken along line AA in FIG. 3 after an element isolation region has been formed. [Diagram 5] 4 is a cross-sectional view taken along line AA in FIG. 3 after a mask material M2 is formed over the entire surface. [Figure 6] 11 is a schematic plan view of a memory cell array portion after an N-type impurity diffusion layer is formed. FIG. [Figure 7] 7 is a cross-sectional view taken along line AA in FIG. 6. [Figure 8] FIG. 13 is a schematic plan view of the memory cell array portion after the mask material M2 is removed. [Figure 9]9 is a cross-sectional view taken along line AA in FIG. 8. [Figure 10] 9 is a cross-sectional view taken along line AA in FIG. 8 after an interlayer insulating film has been formed. [Figure 11] 11 is a schematic plan view of a memory cell array portion after a metal material is formed over the entire surface of a substrate. FIG. [Figure 12] 12 is a cross-sectional view taken along line AA in FIG. 11. [Figure 13] FIG. 13(A) is a schematic plan view of the memory cell array portion after patterning the metal material, and FIGS. 13(B), (C), (D), and (E) are cross-sectional views along lines BB, CC, DD, and AA in FIG. 13(A). [Figure 13A] FIG. 11 is a schematic plan view showing a relationship between the selection control lines SGD / SGS and the diffusion regions. [Figure 14] 14A is a schematic plan view of the memory cell array portion after bit lines and source lines are formed, and FIG. 14B is a cross-sectional view taken along line AA in FIG. 14A. [Figure 15A] 2 is an equivalent circuit diagram of a memory cell array including two blocks of an AND-type flash memory according to the present embodiment. [Figure 15B] 11 is a table showing an example of settings of operating biases applied to each part of the AND-type flash memory of the present embodiment. [Figure 16] 1 is a diagram showing a current path during a read operation of the AND-type flash memory of the present embodiment. [Figure 17] 4 is a diagram for explaining a threshold distribution of memory cells of the AND-type flash memory of the present embodiment. FIG. [Figure 18] 1 is a block diagram showing an electrical configuration of an AND-type flash memory according to an embodiment of the present invention; [Figure 19] FIG. 19A is a schematic plan view of a memory cell array of an AND-type flash memory according to another embodiment of the present invention, and FIG. 19B is a cross-sectional view taken along line AA of FIG. 19A. [Figure 20] 11 is an equivalent circuit diagram of a memory cell array including two blocks of an AND-type flash memory according to another embodiment of the present invention. [Figure 21]11 is a table showing an example of settings of operating biases applied to each portion of an AND-type flash memory according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The present invention relates to a flash memory having an AND-type memory cell array structure of MONOS type or SONOS type, and employs a configuration in which charges are trapped from the channel to a silicon nitride film (SiN) by FN tunneling, or charges are discharged from the silicon nitride film to the channel, thereby eliminating the problem of punch-through from the drain to the source of the memory cell, minimizing the overlap area from the drain to the gate, and enabling miniaturization of the memory cell and simplification of the manufacturing process.

[0014] The AND-type flash memory of this embodiment has the following features: As shown in the equivalent circuit of Fig. 15A, the AND-type flash memory has two select gates (a bit line side select transistor and a source line side select transistor) for block operation on both ends of the memory cell array. 1. The two select gates have a new structure having channel areas aligned in the row direction of the select control lines SGD and SGS, similar to the memory cells. 2. It has a new structure in which the diffusion region formed in the memory cell array is physically divided into two parts to separate the diffusion region connected to the select gate. 3. The number of memory cells connected in parallel between two select gates can be increased to 32 or more by salicideing the diffusion region to reduce the resistance of the diffusion region, thereby reducing the cell size. EXAMPLES

[0015] Next, an embodiment of the present invention will be described in detail with reference to the drawings. Note that the drawings do not necessarily accurately depict the size of an actual device, and may include exaggerated portions in order to facilitate understanding of the invention.

[0016] The equivalent circuit of the AND type flash memory of this embodiment is the same as that of the AND type flash memory shown in FIG. 1(B), but the structure of the memory cell array, the structure of the memory cell, and the read / program / erase operations are different from those of the conventional one.

[0017] FIG. 2A is a schematic cross-sectional view showing a well structure of an AND-type flash memory according to an embodiment of the present invention. The flash memory 100 of this embodiment includes a P-type silicon substrate 10, in which an n-well 12 and a p-well 14 are formed. The p-well 14 provides an area for forming memory cells, and the other P-type silicon area forms an area for forming peripheral circuits. It is also possible to use an N-type silicon substrate, in which case the order of the two wells is reversed. The n-well 12 and the p-well 14 are electrically connected, and a high voltage is applied to the two wells 12 and 14 during erasure. Also, as shown in the bias table of FIG. 15B, in other operations, the two wells 12 and 14 are grounded, and the P-type silicon substrate 10 always remains grounded.

[0018] 2B is a top view of a part of a memory cell array of an AND-type flash memory according to an embodiment of the present invention. On a substrate constituting the memory cell array, a plurality of elongated bit lines BL and a plurality of source lines SL are arranged in a column direction so as to alternate with each other, and below them, a plurality of elongated word lines WL0, WL1, . . . , WLn-1 and selection control lines SGD and SGS are formed extending in the row direction. The plurality of word lines WL0 to WLn-1 are arranged between the selection control line SGD and the selection control line SGS.

[0019] The source line SL and the bit line BL are made of, for example, a metal layer, the source line SL has a contact SL_CT electrically connected to one of the diffusion regions (or metal silicide regions) of the select transistor on the source line side, and the bit line BL has a contact BL_CT electrically connected to one of the diffusion regions (or metal silicide regions) of the select transistor on the bit line side. In the example shown in the figure, the source line contacts SL_CT and the bit line contacts BL_CT are arranged in a staggered pattern, but the arrangement is not limited to this and may be as shown in FIG.

[0020] The selection control lines SGD / SGS and word lines WL are, for example, made of conductive polysilicon layers. The gates of the source line side selection transistors in the row direction are commonly connected to the corresponding selection control lines SGS, and the gates of the bit line side selection transistors are commonly connected to the corresponding selection control lines SGD. Also, the gates of the memory cells in the row direction are commonly connected to the corresponding word lines WL.

[0021] 2B shows one memory cell MC, and the other rectangular areas show the source line side select transistor SEL_SL and the bit line side select transistor SEL_BL. The source line side select transistor SEL_SL and the bit line side select transistor SEL_BL have a channel area along the row direction, in other words, a source / drain along the row direction, like the memory cell MC.

[0022] Next, the details will be described with reference to the manufacturing method of the AND-type flash memory of this embodiment. Fig. 3 is a top view of a part of a memory cell array. In the figure, a plurality of gate materials 20 formed in a column direction on a substrate and side walls SW formed on the side surfaces of the gate materials 20 are shown. Also, the blank areas are trenches 30 or element isolation regions 60 formed in the substrate.

[0023] Fig. 4 is a cross-sectional view taken along line AA in Fig. 3. After an n-well 12 and a p-well 14 are formed in a silicon substrate 10, a P-type impurity such as boron is implanted into the surface of the silicon substrate to form a P-type implantation layer 40. The P-type implantation layer 40 enables adjustment of the threshold voltages Vt of the memory cells MC, the bit line side select transistor SEL_BL, and the source line side select transistor SEL_SL. As will be described later, the P-type implantation layer 40 electrically isolates the diffusion regions of the bit line side select transistor SEL_BL and the source line side select transistor SEL_SL from the diffusion region of the memory cell MC.

[0024] Next, a laminated insulator 50, which is a laminate of at least three insulating films, is deposited as a gate insulating film. The laminated insulator 50 includes a charge storage layer (e.g., SiN) sandwiched between insulating films, and is configured, for example, with an ONO structure (SiO2 / SiN / SiO2). The charge storage layer stores electrons tunneled from the channel by FN tunneling during programming, for example.

[0025] Next, a gate material 20 such as polysilicon and a mask material M1 (e.g., resist, silicon oxide film, silicon nitride film, etc.) are deposited, and then the mask material M1, the gate material 20, and the laminated insulator 50 are patterned into vertical stripes as shown in Fig. 3. At this time, the P-type implantation layer 40 remains without being etched.

[0026] Next, a sidewall material is deposited on the entire surface of the substrate, and the sidewall material is anisotropically etched so that the sidewall material remains on the sides of the gate material 20 and the mask material M1, forming a sidewall SW. Next, the sidewall SW and the mask material M1 are used as a mask to etch the silicon substrate surface, forming a groove (trench) 30 for element isolation as shown in FIG. 4. A P-type implanted layer 40 remains directly below the sidewall SW and the stacked insulator 50. Next, an interlayer insulating film (e.g., a silicon oxide film, etc.) 60 is deposited on the entire surface of the substrate, and then the interlayer insulating film 60 is planarized (e.g., CMP) to expose the top of the mask material M1. The interlayer insulating film 60 formed in the trench 30 becomes an element isolation region.

[0027] After planarizing the interlayer insulating film 60, the interlayer insulating film 60 and the sidewall SW are etched until the silicon surface and the P-type implantation layer 40 are exposed as shown in Fig. 5. This exposes the area covered by the sidewall SW, i.e., a part of the P-type implantation layer 40. Next, as shown in Fig. 5, a mask material M2 (e.g., a resist, a silicon oxide film, a silicon nitride film, etc.) is deposited on the entire surface of the substrate.

[0028] Next, as shown in FIG. 6, the mask material M2 is partially etched to leave the mask material M2 in the rectangular MR region. FIG. 7 is a cross section taken along the line AA in FIG. 6 after the mask material M2 has been etched. After etching the mask material M2, high-concentration N-type impurities (e.g., phosphorus or arsenic) are ion-implanted using the mask material M2 as a mask. This forms an N-type diffusion region 70 on the silicon substrate surface except for the regions covered by the interlayer insulating film 60 and the mask materials M1 and M2. The N-type diffusion region 70 provides the source / drain of the memory cell, the bit line side select transistor, and the source line side select transistor.

[0029] Since the region covered by the mask material M2 is the P-type implantation layer 40, the N-type diffusion region 70 is physically separated by the P-type implantation layer 40. In other words, the mask material M2 defines a region for separating the N-type diffusion region 70 of the bit line side select transistor and the source line side select transistor from the N-type diffusion region 70 of the memory cell.

[0030] In a preferred embodiment, after forming the N-type diffusion region 70, a high melting point metal (e.g., cobalt or nickel) is deposited over the entire surface of the substrate, followed by heat treatment to form a metal silicide region (e.g., CoSi2 or NiSi) on the surface of the N-type diffusion region 70. By silicidating the surface of the N-type diffusion region 70, the resistance of the N-type diffusion region 70 is reduced. Thereafter, the unreacted high melting point metal is removed by etching. It should be noted that a salicide process is used to form the metal silicide region in a self-aligned manner with the N-type diffusion region 70 exposed on the silicon substrate surface.

[0031] After forming the metal silicide region in the N-type diffusion region 70, the mask material M2 is removed. A top view at this stage is shown in Fig. 8. The region covered by the mask material M2 is the P-type implantation layer 40, and the N-type diffusion region 70 is electrically isolated by the intermediate P-type implantation layer 40. Fig. 9 is a cross-sectional view taken along the line AA in Fig. 8.

[0032] Next, as shown in Fig. 10, an interlayer insulating film 62 (e.g., a silicon oxide film, etc.) is deposited on the entire surface of the substrate, and the interlayer insulating film 62 is planarized until the gate material 20 is exposed. Next, as shown in Fig. 11, a metal material 80 is deposited on the entire surface of the substrate. Fig. 12 is a cross-sectional view taken along line AA in Fig. 11. The metal material 80 is electrically connected to the gate material 20.

[0033] Next, the metal material 80, the gate material 20, and the laminated insulator 50 are simultaneously etched to form the selection control lines SGD / SGS, the word lines WL0 to WLn-1, the bit line side selection transistors, the source line side selection transistors, and the memory cells as shown in Fig. 13. Fig. 13(A) is a top view of the memory cell array section, and Figs. 13(B), (C), (D), and (E) are cross-sectional views along lines BB, CC, DD, and AA in Fig. 13(A). Fig. 13A also shows a schematic diagram of the positional relationship when the selection control lines SGD / SGS and the word lines WL0 to WLn-1 overlap the N-type diffusion region 70 and the P-type implantation layer 40.

[0034] 13(E), the patterned gate material 20 is the gate of the transistor, the laminated insulator 50 is the gate insulating film, the N-type diffusion region 70 is the source / drain, and the silicon region directly below the laminated insulator 50 is the channel. In addition, the patterned metal material 80 is the selection control lines SGD / SGS and the word lines WL. The selection control lines SGD / SGS are electrically connected to the gate materials 20 of the bit line side selection transistor and the source line side selection transistor, and the word lines WL0 to WLn-1 arranged between the selection control lines SGD and SGS are electrically connected to the gate materials 20 of the memory cells.

[0035] Fig. 13(C) shows an N+ diffusion region 70, and Fig. 13(D) shows an element isolation region 60 extending in the column direction that isolates the memory cells in the row direction. Fig. 13(E) shows two memory cells in the row direction. Also, as shown in Fig. 13A, one N-type diffusion region 70 of the bit line side select transistor is separated from one N-type diffusion region 70 of the memory cell by a P-type implantation layer 40, and the other N-type diffusion region 70 of the source line side select transistor is separated from the other N-type diffusion region 70 of the memory cell by a P-type implantation layer 40.

[0036] Next, the spaces between the word lines and the spaces between the word lines and the selection control lines SGD / SGS are filled with an interlayer insulating film, and then, as shown in Fig. 14, source lines SL and bit lines BL having source line contacts SL_CT and bit line contacts CT_BL electrically connected to the N-type diffusion region 70 are formed at the ends of the memory cell array. In this way, the memory cell array shown in Fig. 2B is formed.

[0037] In the AND-type flash memory of this embodiment, unlike the conventional AND-type flash memory, the selection control lines SGD / SGS and the word lines WL extending in the row direction can be formed simultaneously. Also, unlike the conventional AND-type flash memory, a floating gate (FG) is not used for the charge storage layer, but a dielectric (SiN: silicon nitride layer) is used as the charge storage layer, so that the process for manufacturing the memory cells can be simplified.

[0038] Also, by forming the bit line side select transistors and the source line side select transistors in the row direction (horizontal direction) between the opposing N-type diffusion regions 70, like the memory cells, the layout efficiency of the transistors can be improved and the memory cell array can be highly integrated. Furthermore, by forming a silicide region in the N-type diffusion region 70, the resistance of the N-type diffusion region 70 can be reduced, and this allows the number of memory cells connected in parallel to be increased. Furthermore, the insulator layer 50 including the charge storage layer is separated between the memory cells, so that the diffusion of charge from one memory cell to an adjacent memory cell is avoided, and data retention is improved.

[0039] Next, the equivalent circuit and operation of the AND-type flash memory of this embodiment will be described. The AND-type flash memory of this embodiment is unique in that it utilizes electron tunneling between a charge storage layer (e.g., SiN) and a channel. Figure 15A illustrates an equivalent circuit of a memory cell array including two blocks. For example, in block i, n memory cells connected in parallel are connected in parallel between a bit line side select transistor and a source line side select transistor, a select control line SGS is commonly connected to each gate of the select transistor at the upper end of block i, a select control line SGD is commonly connected to each gate of the select transistor at the lower end, and WL0, WL1, ..., WLn-1 are commonly connected to each gate of the memory cells in the row direction.

[0040] A block is a unit of erase for the cell array. An AND-type array is composed of a set of gates (SGS, SGD, and WL0 to WLn-1) and a set of source lines SL and bit lines BL, and a block has multiple sets of source lines SL and bit lines BL.

[0041] The setting of the operating bias of the memory cell array is shown in the table of FIG. 15B. The read / write (program) / erase operations are performed in the selected block. "CG" is synonymous with word line WL and is a control gate. Here, it is assumed that the memory cell connected to CG1 of the selected block is selected. As with the 2D NAND flash memory, reading and programming can be performed in word line units (page units), and erasing can be performed in block units. FIG. 15B shows the voltages applied to each part of the selected block and non-selected blocks when reading, programming, and erasing.

[0042] [Read operation] In the case of a single bit per memory cell, about 4V is applied to the CG1 of the selected memory cell, about 0.6V to the bit line BL, and the source line SL is grounded for reading. -0.6 to 0V is applied to the CG of the unselected memory cells. A voltage higher than the threshold Vt of the selected transistor is applied to the selection control line SGS / SGD. For example, if the threshold Vt of the memory cell connected to CG1 of the selected block is lower than the voltage applied to CG1, the cell current flows from the bit line BL to the source line SL. On the other hand, if the threshold Vt of the memory cell connected to CG1 is higher than the voltage applied to CG1, no current flows from the bit line BL to the source line SL. To correctly read the data of the memory cells, the threshold Vt of the unselected memory cells must be higher than the CG bias of the unselected memory cells.

[0043] 16 illustrates the current path from the bit line BL to the source line SL during a read operation. The source and drain of the bit line side select transistor are formed by N+ diffusion regions 70 along the source line SL and bit line BL, and a channel is formed between the source and drain below the select control line SGD. For reading, a voltage higher than the threshold Vt of the source line side select transistor and the bit line side select transistor is applied to the select control lines SGS, SGD, turning on the source line side select transistor and the bit line side select transistor.

[0044] A current applied to the bit line BL flows through the N+ diffusion region 70 formed along the bit line BL via the contact BL_CT. The current flowing through the N+ diffusion region 70 is isolated by the P-type implantation layer 40 in region Q, and therefore does not flow through the N+ diffusion region 70 of the memory cell. The current flowing through the N+ diffusion region 70 then flows through the channel of the bit line side select transistor that is turned on ("1" in FIG. 16), and then passes through the N+ diffusion region 70 formed along the source SL ("2" in FIG. 16).

[0045] The selected memory cell for reading is on word line WL1, and the voltage V WL1 If the voltage V of the word line WL1 is higher than the threshold voltage Vt of the memory cell, current can pass through the channel under the word line WL1 ("3" in FIG. 16). If the voltage V of the word line WL1 If V is less than the threshold voltage Vt of the memory cell, no current flows.

[0046] The current that has flowed through the channel of the word line WL1 flows through the N+ diffusion region 70 formed along the bit line BL ("4" in FIG. 16). Finally, the current passes through the channel of the source line side select transistor that is turned on ("5" in FIG. 16), and becomes a path that flows to the source line SL via the N+ diffusion region 70 and the contact SL_CT. Again, the current path between two adjacent N+ diffusion regions 70 in region Q is blocked by the stopper of the P-type implantation layer 40.

[0047] In order to avoid leakage paths from other memory cells (word line WL0, word lines 2 to WLn-1), the threshold voltage Vt of these memory cells must be higher than the bias (-0.6 to 0V) of these word lines. In other words, as shown in FIG. 17, the threshold voltage Vt of the memory cell must be set higher than Vunselected. If the source line SL is set to a positive voltage of about 0.2V during reading, the threshold voltage of the memory cell rises due to the substrate bias effect. Therefore, as shown in FIG. 17, the voltage V applied to the selected word line for reading is between the threshold voltage distribution of memory cells that store "1" (memory cells in an erased state) and the threshold voltage distribution of memory cells that store "0" (memory cells in a programmed state). read In the table of FIG. 15B, the voltage V applied to the selected word line is read is 4V, and the voltage V applied to the unselected word lines is unselected-WL is −0.6 to 0 V. However, this value is just an example and can be changed. Furthermore, in order to suppress leakage current of the unselected blocks, the selection control lines SGS / SGD of the unselected blocks are grounded.

[0048] [Program operation] In programming, a high voltage (e.g., 8-14V) is applied to the selected CG1, and an intermediate voltage (e.g., 5-7V) is applied to the unselected CGs. In the case of "0" programming (when electrons are injected into the charge storage layer), 0V is applied to the bit line BL, and the same voltage as the bit line BL is applied to the source line SL. In the case of "1" programming (when electrons are not injected into the charge storage layer, program inhibit), a positive voltage (e.g., up to 1.6V) is applied to the bit line BL, and the same voltage as the bit line BL is applied to the source line SL.

[0049] In "0" programming, a voltage (up to 1.5V) higher than the threshold Vt (e.g., up to 1V) of the select transistor is applied to the select control line SGD, turning on the select transistor and electrically connecting the bit line BL to the N+ diffusion region 70. A voltage (up to 1.5V) higher than the threshold Vt (e.g., up to 1V) of the select transistor is also applied to the select control line SGS. As a result, electrons tunneled from the channel are injected into the charge storage layer of the selected memory cell, and the electrons are stored in the charge storage layer. An intermediate voltage that is not sufficient for tunneling from the channel is applied to the gates of unselected memory cells, so they are not programmed to "0".

[0050] In the "1" program, since a positive voltage is applied to the bit line, even if a high voltage is applied to the selection control line SGD, the selection transistor is turned off and the N+ diffusion region 70 is in a floating state. In addition, since a positive voltage is applied to the source line, the selection transistor is turned off. As a result, if a high voltage is applied to CG1 and a potential between CG1 and 0V is applied to the other CGs, the potentials of the diffusion region and the channel are self-boosted by coupling, and the potential difference between the channel and the charge storage layer is not large enough for tunneling. For this reason, programming is not performed on the selected memory cell or the unselected memory cell.

[0051] Furthermore, 0V is applied to the selection control lines SGS, SGD of the unselected blocks to turn off the selection transistors and isolate the N+ diffusion regions 70 of the memory cells from the source lines SL / bit lines BL.

[0052] In one embodiment, the stacked insulator 50 includes at least three insulating layers. The first is a lower insulating layer (e.g., oxide layer) facing the silicon surface, the second is a SiN layer that stores charge for data identification, and the third is an upper insulating layer (e.g., oxide layer) facing the gate / word line WL. The effective oxide thickness of the lower insulating layer is smaller than the effective oxide thickness of the upper insulating layer. The reverse is also possible, but in this case, the charge flow to the SiN layer during programming and erasing is different. If the effective oxide thickness of the lower insulating layer is smaller, the charge flows between the silicon surface and the SiN layer during programming and erasing. On the other hand, if the thicknesses of the two insulating layers are reversed, the charge flows between the SiN and the gate / word line WL during programming and erasing.

[0053] Here, the first case (thickness of the lower insulating layer is thinner than that of the upper insulating layer) is explained as a representative example. When the bit line BL is grounded, the memory cell connected to CG1 is programmed to "0" (electron injection from the channel to the SiN layer). When a positive voltage (~1.6V) is applied to the bit line BL and the source line, the two N+ diffusion regions 70 on the source line side and the bit line side are isolated from the bit line BL and the source line SL. Therefore, both the diffusion region 70 and the region of the channel are self-boosted by applying a high voltage and an intermediate voltage to CG1 and other CGs, the voltage difference between the diffusion region 70 and CG1 becomes small, and in the memory cell connected to CG1, electron injection from the substrate to the SiN layer does not occur.

[0054] [Erase operation] In the case of erasure, the memory cells of the selected block are erased simultaneously. Two wells, an n-well and a p-well, formed in the substrate are electrically connected, and during erasure, a high voltage (e.g., 8 to 14 V) is applied to the p-well, all CGs in the selected block are grounded, and the bit line BL and the source line SL are made floating. Then, electrons are tunneled from the SiN layer to the p-well, or holes are injected from the p-well into the SiN layer of the memory cell and recombined with the electrons. This causes the threshold voltage Vt of the memory cell to drop below the read voltage applied to the selected CG during the read operation. Meanwhile, in the unselected blocks, all CGs are floating. When a high voltage is applied to the p-well, the floating CG is self-boosted, and erasure does not occur in the unselected blocks. It is preferable to perform erasure on a block-by-block basis, but it is also possible to perform it on a word-line-by-word-line basis.

[0055] 18 is a block diagram showing the main electrical configuration of the AND-type flash memory of this embodiment. As shown in the figure, the flash memory 100 includes a memory cell array 110 having an AND-type memory cell array structure, an address buffer 120 for holding addresses input from the outside, a row selection / driving circuit 130 for selecting word lines based on row addresses and driving the selected word lines, a column selection circuit 140 for selecting bit lines and source lines based on column addresses, an input / output circuit 150 for transmitting and receiving data and commands between an external host device, and a read / write control unit 160 for sensing data read from a selected memory cell during a read operation, applying a bias voltage to the bit lines for writing data to the selected memory cell during a program operation, and applying an erase voltage to the P-well during an erase operation. Each unit is connected by an internal bus capable of transmitting and receiving addresses, data, control signals, and the like, and also includes a voltage generating circuit for generating various bias voltages, which is not shown here.

[0056] The row selection / drive circuit 130 selects a word line WL based on a row address, and drives the selected word line WL and unselected word lines with a voltage according to the operation. The row selection / drive circuit 130 applies voltages as shown in Fig. 8B to the word line WL (CG) and selection control line (SG). The column selection circuit 140 selects a bit line BL and source line SL based on a column address, and applies a voltage according to the operation to the selected bit line BL and source line SL, or sets them in a floating state.

[0057] The read / write control unit 160 controls operations such as reading, programming, and erasing in response to commands received from an external host device. The read / write control unit 160 includes a sense amplifier and a write amplifier, and the sense amplifier senses the current and voltage flowing through the bit line BL and source line SL connected to the selected memory cell during a read operation, and the write amplifier applies a read voltage to the selected bit line during a read operation, applies a voltage to the selected bit line and unselected bit lines during a program operation, and further puts the bit line and source line into a floating state during an erase operation.

[0058] Next, an AND-type flash memory according to another embodiment of the present invention will be described. In the previous embodiment, the bit lines and source lines formed on the memory cell array are laid out so as to be parallel to each other, but in this embodiment, the bit lines and source lines are laid out so as to be perpendicular to each other.

[0059] Fig. 19(A) is a schematic plan view of a memory cell array of an AND-type flash memory according to this embodiment, and Fig. 19(B) is a cross-sectional view taken along line AA in Fig. 19(A). As shown in the figure, a common source line SL extends in the row direction together with a word line WL and a selection control line SGS / SGD, and a bit line BL extends in the column direction so as to be perpendicular to the common source line SL.

[0060] In one embodiment, the word lines WL and the selection control lines SGS / SGD are formed by a first level metal wiring, and the common source line SL is formed by a second level metal wiring that is a layer higher than the first level, whereby the common source line SL is commonly connected to the diffusion regions (or metal silicide regions) of the source line side selection transistors of multiple blocks in the row direction via the contacts SL_CT.

[0061] The process steps up to the formation of the bit lines BL and the source lines SL are the same as those in the previous embodiment. Although the bit lines BL are formed above the common source lines SL, this relationship may be reversed, and the common source lines SL may be formed above the bit lines BL.

[0062] 20 is an equivalent circuit diagram of a memory cell array including two blocks of an AND-type flash memory according to this embodiment. The difference from the equivalent circuit diagram of the previous embodiment (FIG. 15A) is that a common source line SL extends parallel to the word line WL and is commonly connected to multiple blocks in the row direction.

[0063] 21 is a table showing an example of setting the operating bias applied to each part of the AND-type flash memory according to this embodiment. The difference from the operating bias (FIG. 15B) of the previous embodiment is the potential of the selection control line SGS and the common source line SL during writing. That is, the selection control line SGS is set to 0V, and the source line side selection transistor connected to the selection control line SGS is turned off. In addition, the potential of the source line SL is set to 0.5 to 1V, which prevents the self-boosted potential of the channel part from leaking to the source line SL during "1" programming.

[0064] Although a preferred embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0065] 10: P-type silicon substrate 12: n-well 14: p-well 20: gate material 30: Element isolation region 40: P-type injection layer 50: laminated insulator 60: interlayer insulating film (element isolation region) 70: N-type diffusion region 80: Metal material

Claims

1. An AND-type flash memory having a memory cell array including a plurality of memory cells electrically connected in parallel between a source line and a bit line, a plurality of elongated diffusion regions formed in a substrate in a column direction; a plurality of gates formed between opposing diffusion regions; a first selection line connected to each gate of the bit line side selection transistors in the row direction; a second selection line connected to each gate of the source line side selection transistor in the row direction; a plurality of word lines respectively connected to the gates of the memory cells in a row direction; each of the bit line side select transistor, the source line side select transistor and the plurality of memory cells has a channel region between the opposing diffusion regions and has a channel area along a row direction; a diffusion region including a first isolation region that electrically isolates a diffusion region of a bit line side select transistor from a diffusion region of a memory cell adjacent to the bit line side select transistor, and a second isolation region that electrically isolates a diffusion region of a source line side select transistor from a diffusion region of a memory cell adjacent to the source line side select transistor, and the first and second isolation regions have a different conductivity type from other diffusion regions.

2. 2. The flash memory of claim 1, wherein the diffusion regions of the bit line side select transistor and the source line side select transistor are isolated from the diffusion regions of the plurality of memory cells.

3. 2. The flash memory of claim 1, further comprising a plurality of bit lines and a plurality of source lines formed on the substrate along the diffusion region, the bit lines being electrically connected to the diffusion region of the bit line side select transistor via a contact, and the source lines being electrically connected to the diffusion region of the source line side select transistor via a contact.

4. The flash memory of claim 1 , wherein the diffusion region comprises a metal silicide region.

5. 2. The flash memory according to claim 1, wherein an isolation region is formed between one of the opposing diffusion regions and another of the opposing diffusion regions adjacent to the one of the opposing diffusion regions.

6. 2. The flash memory of claim 1, wherein the memory cell includes at least three or more stacked insulator layers including a charge storage layer between the gate and the substrate.

7. The flash memory according to claim 6 , wherein the stacked insulator is separated for each memory cell.

8. 7. The flash memory according to claim 6, wherein the charge storage layer stores charges tunneled from a channel by FN tunneling when a program voltage is applied to a gate of a selected memory cell.

9. 7. The flash memory according to claim 6, wherein when an erase voltage is applied to a well region, the charge storage layer releases the stored charges to a channel by tunneling.

10. 2. The flash memory of claim 1, further comprising a plurality of bit lines formed on the substrate along the diffusion regions, the bit lines being electrically connected to the diffusion regions of the bit line side select transistors via contacts, and source lines being arranged parallel to the word lines and electrically connected to the diffusion regions of the source line side select transistors via contacts.

11. 11. The flash memory according to claim 10, wherein the memory cell array includes a plurality of blocks arranged in rows and columns, and the source line is commonly connected to the plurality of blocks in the row direction.

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