Trench under-shield method and approach for trenched semiconductor device structures

Abstract

A semiconductor device and a method for forming a semiconductor device including a polysilicon layer that can improve device reliability and / or device functionality. An exemplary device can include a wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

Description

[Technical field]

[0001] This application claims the benefit of priority to U.S. Patent Application No. 17 / 018,305, filed in the U.S. Patent and Trademark Office on September 11, 2020, the entire contents of which are incorporated by reference for all purposes.

[0002] The present invention relates to power semiconductor devices, and more particularly to power semiconductor devices having gate trenches and methods of making such devices. [Background technology]

[0003] A metal insulator semiconductor field effect transistor (MISFET) is a well-known type of semiconductor transistor that can be used as a switching device. A MISFET is a three-terminal device having a gate, drain, and source terminals, and a semiconductor body. Source and drain regions are formed in the semiconductor body separated by a channel region, and a gate electrode (which can serve as the gate terminal or be electrically connected to the gate terminal) is disposed adjacent to the channel region. A MISFET can be turned on or off by applying a bias voltage to the gate electrode. When a MISFET is turned on (i.e., the MISFET is in its "on-state"), current is conducted through the channel region of the MISFET between the source and drain regions. When the bias voltage is removed from the gate electrode (or reduced below a threshold level), current stops conducting through the channel region. By way of example, an n-type MISFET has n-type source and drain regions and a p-type channel. Thus, an n-type MISFET has an "npn" design. An n-type MISFET turns on when a gate bias voltage is applied to the gate electrode that is sufficient to create a conductive n-type inversion layer in the p-type channel region that electrically connects the n-type source and drain regions, thereby allowing majority carrier conduction between the source and drain regions. The gate electrode of a power MISFET is typically separated from the channel region by a thin gate dielectric layer.

[0004] In some applications, the MISFET may need to carry large currents and / or be capable of blocking high voltages. Such MISFETs are often referred to as "power" MISFETs. A variety of other power semiconductor devices are known in the art, including, for example, bipolar junction transistors ("BJTs"), insulated gate bipolar transistors ("IGBTs"), junction barrier Schottky diodes, gate turn-off transistors ("GTOs"), MOS controlled thyristors, and various other devices. These power semiconductor devices are often fabricated from wide bandgap semiconductor materials, such as silicon carbide ("SiC") or gallium nitride ("GaN") based semiconductor materials. As used herein, wide bandgap semiconductor materials refer to semiconductor materials having a bandgap greater than 1.40 eV.

[0005] A power semiconductor device may have a lateral or vertical structure. In a device having a lateral structure, the terminals of the device (e.g., the drain, gate, and source terminals for a power MOSFET device) are on the same major (i.e., top or bottom) surface of a semiconductor layer structure. In contrast, in a device having a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET device, the source may be on the top surface of the semiconductor layer structure and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate. As used herein, the term "semiconductor layer structure" refers to a structure that includes one or more semiconductor layers, such as a semiconductor substrate and / or a semiconductor epitaxial layer.

[0006] A conventional power semiconductor device typically has a semiconductor substrate, such as a silicon carbide substrate having a first conductivity type (e.g., an n-type substrate), on which an epitaxial layer structure having a first conductivity type (e.g., n-type) is formed. A portion of the epitaxial layer structure (which may comprise one or more separate layers) serves as a drift region for the power semiconductor device. The device typically includes an "active region" that includes one or more power semiconductor devices having a junction, such as a pn junction. The active region may be formed on and / or within the drift region. The active region serves as a primary junction to block voltage in a reverse bias direction and provide current in a forward bias direction. The power semiconductor device may also have an edge termination in a termination region adjacent to the active region. One or more power semiconductor devices may be formed on the substrate, with each power semiconductor device typically having its own edge termination. After the substrate is fully processed, the resulting structure may be diced to separate the individual edge-terminated power semiconductor devices. The power semiconductor devices may have a unit cell structure, in which the active area of ​​each power semiconductor device includes a plurality of individual "unit cell" devices arranged parallel to one another and together function as a single power semiconductor device.

[0007] Power semiconductor devices are designed to block (in forward or reverse blocking conditions) or pass (in forward operating conditions) high voltages and / or currents. For example, in blocking conditions, a power semiconductor device may be designed to maintain a potential of hundreds or thousands of volts. However, when the applied voltage approaches or exceeds the voltage level that the device is designed to block, a significant level of current may begin to flow through the power semiconductor device. Such current, typically referred to as "leakage current," may be highly undesirable. Leakage current may begin to flow when the voltage increases beyond the designed voltage blocking capability of the device, which blocking capability may be a function of, among other things, the doping and thickness of the drift region. Leakage current may also occur for other reasons, such as failure of edge terminations and / or primary junctions of the device. If the voltage applied to the device increases beyond the breakdown voltage and reaches a critical level, the increase in electric field may result in uncontrolled and undesirable runaway generation of charge carriers in the semiconductor device, leading to a condition known as avalanche breakdown.

[0008] Power semiconductor devices may also begin to allow a significant amount of leakage current to flow at voltage levels below the designed breakdown voltage of the device. In particular, leakage current may begin to flow at the edges of the active area where high electric fields may occur due to electric field crowding effects. To reduce this electric field crowding (and the resulting increase in leakage current), edge terminations as discussed above may be provided that surround some or all of the active area of ​​the power semiconductor device. These edge terminations may spread the electric field over a larger area, thereby reducing the electric field crowding.

[0009] Vertical power semiconductor devices, including MOSFET transistors, can have a standard gate electrode design, in which the transistor's gate electrode is formed on top of the semiconductor layer structure, or alternatively, can have the gate electrode recessed in a trench within the semiconductor layer structure. MOSFETs with recessed gate electrodes are typically referred to as gated trench MOSFETs. With a standard gate electrode design, the channel region of each unit cell transistor is disposed horizontally beneath the gate electrode. In contrast, in a gated trench MOSFET design, the channel is disposed vertically. Gated trench MOSFETs can provide improved performance, but typically require a more complicated manufacturing process. Summary of the Invention [Means for solving the problem]

[0010] According to some embodiments of the inventive concepts, a device may be provided that includes a wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening, and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

[0011] In some embodiments, the device may include an oxide layer on each polysilicon layer. In some embodiments, the device may include a gate structure in each gate trench, each gate structure including a gate oxide. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type. In some embodiments, the device may include a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface. In some embodiments, each gate trench extends a predetermined length in a direction parallel to a top surface of the semiconductor layer structure, and each polysilicon layer extends the length of the respective gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to a top surface of the semiconductor layer structure, and each gate trench includes a first length including a respective polysilicon layer and a second length free of a respective polysilicon layer.

[0012] In some embodiments, the device may include a channel region in a first sidewall of the gate trench and in a second sidewall of the second length of the gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region is in the well region. In some embodiments, each gate trench includes a third length on the first sidewall of each gate trench, the third length including a polysilicon layer. In some embodiments, the device may include a channel region in a first sidewall of the gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region is in the well region. In some embodiments, the wide bandgap semiconductor includes silicon carbide. In some embodiments, the device may include a bottom oxide layer on a lower surface, a first sidewall, and a second sidewall of each gate trench. In some embodiments, the device may include a top oxide layer on the polysilicon layer.

[0013] In accordance with some embodiments of the inventive concepts, a device may be provided that includes a wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening, and a plurality of polysilicon layers, each polysilicon layer underlying a respective one of the plurality of gate trenches.

[0014] In some embodiments, the plurality of gate trenches comprises first gate trenches, each having a respective polysilicon layer below a lower surface thereof, and second gate trenches, each lacking a polysilicon layer below a lower surface thereof. In some embodiments, the device may comprise a gate structure within each second gate trench. In some embodiments, each gate trench of the device may comprise a respective polysilicon layer of the plurality of polysilicon layers. In some embodiments, the device may comprise a gate structure within each gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to a top surface of the semiconductor layer structure, and each polysilicon layer extends the length of the respective gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to a top surface of the semiconductor layer structure, and each gate trench comprises a first length portion comprising a respective polysilicon layer and a second length portion lacking a respective polysilicon layer. In some embodiments, the device may include a channel region in a first sidewall of the gate trench and in a second sidewall of the second length of the gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region is in the well region. In some embodiments, the device may include an oxide layer on each polysilicon layer. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type. In some embodiments, the device may include a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface. In some embodiments, the device may include a channel region in a first sidewall of each gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region is in the well region. In some embodiments, the wide bandgap semiconductor includes silicon carbide.

[0015] According to some embodiments of the inventive concepts, a device may be provided that includes a wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening, each gate trench comprising a plurality of first length portions and a plurality of second length portions alternating along a length of the gate trench, and a plurality of polysilicon layers, each polysilicon layer on a second sidewall of a respective gate trench within the first length portions. The second length portions of each gate trench may be free of the polysilicon layer.

[0016] In some embodiments, the device may include an oxide layer in each gate trench. In some embodiments, the oxide layer has a first cross-section in a first length of each gate trench and a second cross-section in a second length of each gate trench. In some embodiments, the device may include a gate structure in each gate trench, the gate structure comprising a gate electrode. In some embodiments, the gate electrode has a first cross-section in a first length of each gate trench and a second cross-section in a second length of each gate trench. In some embodiments, the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type. In some embodiments, the device may include a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface. In some embodiments, the wide bandgap semiconductor comprises silicon carbide.

[0017] According to some embodiments of the inventive concepts, a device may be provided that may include a wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening, the plurality of gate trenches comprising first and second gate trenches, a plurality of polysilicon layers, each polysilicon layer below a respective first gate trench of the plurality of gate trenches, and a plurality of gate electrodes, each gate electrode disposed within a respective second gate trench of the plurality of gate trenches. A second length of each gate trench may be free of the polysilicon layer.

[0018] In some embodiments, each gate trench extends a predetermined length in a direction parallel to an upper surface of the semiconductor layer structure, and each polysilicon layer extends the length of a respective first gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to an upper surface of the semiconductor layer structure. In some embodiments, the device can include a channel region in a first sidewall of the second gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region can be in the well region. In some embodiments, the wide bandgap semiconductor includes silicon carbide.

[0019] In accordance with some embodiments of the inventive concepts, there is provided a method of forming a semiconductor device, the method including forming a wide bandgap semiconductor layer structure over a substrate, the semiconductor layer structure including a drift region having a first conductivity type, forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches being spaced apart from one another, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening, and forming a polysilicon layer along the second sidewall of each gate trench.

[0020] In some embodiments, the method may include forming an oxide layer on the polysilicon layer. In some embodiments, the method may include forming a bottom oxide layer on a lower surface, a first sidewall, and a second sidewall of each gate trench, and forming the polysilicon layer includes forming a polysilicon layer on the bottom oxide layer. In some embodiments, the method may include forming an top oxide layer on the polysilicon layer. In some embodiments, the method may include forming a gate structure in each gate trench, each gate structure comprising a gate electrode. In some embodiments, the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type. In some embodiments, the method may include forming a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface. In some embodiments, each gate trench extends a predetermined length in a direction parallel to a top surface of the semiconductor layer structure, and each polysilicon layer extends the length of a respective gate trench. In some embodiments, each gate trench extends a length in a direction parallel to a top surface of the semiconductor layer structure, each gate trench having a first length portion including a respective polysilicon layer and a second length portion free of a respective polysilicon layer. In some embodiments, a channel region is formed within a first sidewall of the gate trench and within a second sidewall of the second length portion of the gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region can be within the well region. In some embodiments, the channel region is formed within a first sidewall of the gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region can be within the well region. In some embodiments, the wide bandgap semiconductor includes silicon carbide.

[0021] According to some embodiments of the present disclosure, a method of forming a semiconductor device may be provided, the method may include forming a wide bandgap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region having a first conductivity type, forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches being spaced apart from one another, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening, and forming a polysilicon layer in lower portions of at least some of the gate trenches.

[0022] In some embodiments, the plurality of gate trenches comprises first gate trenches, each having a respective polysilicon layer on a lower surface thereof, and second gate trenches, each lacking a polysilicon layer on a lower surface thereof. In some embodiments, the method can include forming a gate structure in each second gate trench. In some embodiments, a polysilicon layer is formed in each gate trench of the semiconductor device. In some embodiments, the method can include forming a gate structure in each gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to an upper surface of the semiconductor layer structure, and each polysilicon layer extends the length of the respective gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to an upper surface of the semiconductor layer structure, and each gate trench comprises a first length portion comprising a respective polysilicon layer and a second length portion lacking a respective polysilicon layer. In some embodiments, the method may include forming an oxide layer on each polysilicon layer. In some embodiments, the method may include forming a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface. In some embodiments, the wide bandgap semiconductor includes silicon carbide.

[0023] According to some embodiments of the present disclosure, a method of forming a semiconductor device may be provided. The method may include forming a wide bandgap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region having a first conductivity type, forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, each gate trench comprising a plurality of first length portions and a plurality of second length portions alternating along a length of the gate trench, and forming a plurality of polysilicon layers, each polysilicon layer on a second sidewall of a respective gate trench within the first length portions. The second length portions of each gate trench may be free of the polysilicon layer.

[0024] In some embodiments, the method may further include forming an oxide layer in each gate trench. In some embodiments, the oxide layer has a first cross-section within a first length of each gate trench and a second cross-section within a second length of each gate trench. In some embodiments, the method may include forming a gate structure in each gate trench, the gate structure comprising a gate electrode. In some embodiments, the gate electrode has a first cross-section within the first length of each gate trench and a second cross-section within the second length of each gate trench. In some embodiments, the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type. In some embodiments, the method may include forming a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface. In some embodiments, the wide bandgap semiconductor comprises silicon carbide.

[0025] According to some embodiments of the present disclosure, a device is provided that includes a wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of source trenches in an upper portion of the semiconductor layer structure, each source trench having a lower surface, a first sidewall, a second sidewall, and a top opening, a plurality of gate trenches in the upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening, and a plurality of polysilicon layers, each polysilicon layer underlying a respective one of the plurality of source trenches.

[0026] In some embodiments, the plurality of source trenches comprises first source trenches each having a respective polysilicon layer below its lower surface, and each gate trench is free of a polysilicon layer below its lower surface. In some embodiments, the device may include a gate structure within each gate trench. In some embodiments, each gate trench and each source trench extends a length in a direction parallel to an upper surface of the semiconductor layer structure, and each polysilicon layer extends the length of the respective source trench. In some embodiments, the device may include a channel region within first and second sidewalls of each gate trench. In some embodiments, the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type, and the channel region is within the well region. In some embodiments, the device may include a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface.

[0027] According to some embodiments of the present disclosure, a device is provided, the device may include a wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening, each gate trench comprising a plurality of first lengths, a plurality of second lengths, and a plurality of third lengths, a plurality of first polysilicon layers, each first polysilicon layer on a first sidewall of a respective gate trench in the first lengths, and a plurality of second polysilicon layers, each second polysilicon layer on a second sidewall of a respective gate trench in the second lengths. The first and second sidewalls of each gate trench in the third lengths may be free of the first and second polysilicon layers.

[0028] In some embodiments, the device may include an oxide layer in each gate trench. The oxide layer may have a first cross-section in a first length of each gate trench, a second cross-section in a second length of each gate trench, and a third cross-section in a third length of each gate trench. In some embodiments, the device may include a gate structure in each gate trench, the gate structure comprising a gate electrode. The gate electrode may have a first cross-section in a first length of each gate trench, a second cross-section in a second length of each gate trench, and a third cross-section in a third length of each gate trench. In some embodiments, the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type. In some embodiments, the device may include a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface. In some embodiments, the wide bandgap semiconductor comprises silicon carbide.

[0029] According to some embodiments of the present disclosure, a device is provided that may include a wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening, each gate trench comprising a plurality of first lengths and a plurality of second lengths, and a plurality of polysilicon layers, each first polysilicon layer on first and second sidewalls of a respective gate trench in the first lengths. The first and second sidewalls of each gate trench in the second lengths may be free of the polysilicon layer.

[0030] In some embodiments, the device may include an oxide layer in each gate trench. The oxide layer may have a first cross-section in a first length of each gate trench and a second cross-section in a second length of each gate trench. In some embodiments, the device may include a gate structure in each gate trench, the gate structure comprising a gate electrode. The gate electrode may have a first cross-section in a first length of each gate trench and a second cross-section in a second length of each gate trench. In some embodiments, the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type. In some embodiments, the device may include a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface. In some embodiments, the wide bandgap semiconductor comprises silicon carbide.

[0031] According to some embodiments of the present disclosure, a device is provided that includes a wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening, each gate trench exposing a side of the drift region, and a plurality of polysilicon layers, each polysilicon layer overlying at least a portion of the first and second sidewalls of a respective gate trench.

[0032] In some embodiments, the device may include an oxide layer in each gate trench. In some embodiments, the device may include a gate structure in each gate trench, the gate structure comprising a gate electrode. In some embodiments, the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type. In some embodiments, the device may include a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface. In some embodiments, the wide bandgap semiconductor comprises silicon carbide. [Brief description of the drawings]

[0033] [Figure 1A] A schematic cross-section of a gate trench power MOSFET showing the ideal gate trench and implant shield. [Figure 1B] FIG. 1 is a schematic cross-sectional view of a gate trench power MOSFET showing the gate trench and implant shield that may result in exposed channel and drift regions. [Figure 2A] FIG. 2 is a schematic cross-sectional view of a first related art approach that addresses the problem presented by the gate trench power MOSFET of FIG. 1B. [Figure 2B]FIG. 2 is a schematic cross-sectional view of a first related art approach that addresses the problem presented by the gate trench power MOSFET of FIG. 1B. [Figure 2C] FIG. 2 is a schematic cross-sectional view of a first related art approach that addresses the problem presented by the gate trench power MOSFET of FIG. 1B. [Figure 3A] FIG. 2 is a schematic cross-sectional view of a second related art approach that addresses the problem presented by the gate trench power MOSFET of FIG. 1B. [Figure 3B] FIG. 2 is a schematic cross-sectional view of a second related art approach that addresses the problem presented by the gate trench power MOSFET of FIG. 1B. [Figure 3C] FIG. 2 is a schematic cross-sectional view of a second related art approach that addresses the problem presented by the gate trench power MOSFET of FIG. 1B. [Figure 4A] 1 is a schematic diagram of a gate trench power MOSFET according to an embodiment of the inventive concept; [Figure 4B] 1 is a schematic diagram of a gate trench power MOSFET according to an embodiment of the inventive concept; [Figure 4C] 1 is a schematic diagram of a gate trench power MOSFET according to an embodiment of the inventive concept; [Figure 4D] 1 is a schematic diagram of a gate trench power MOSFET according to an embodiment of the inventive concept; [Figure 4E] 1 is a schematic diagram of a gate trench power MOSFET according to an embodiment of the inventive concept; [Figure 4F] 1 is a schematic diagram of a gate trench power MOSFET according to an embodiment of the inventive concept; [Figure 5A] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 5B] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 5C] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 5D] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 5E] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 5F] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 5G] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 6A] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 6B] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 6C] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 6D] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 7] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 8] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 9] 1 is a flow chart illustrating a method of fabricating a gate trench power semiconductor device according to an embodiment of the inventive concept. [Figure 10] 1 is a flow chart illustrating a method of fabricating a gate trench power semiconductor device according to an embodiment of the inventive concept. [Figure 11] 1 is a flow chart illustrating a method of fabricating a gate trench power semiconductor device according to an embodiment of the inventive concept. [Figure 12] 1 is a flow chart illustrating a method of fabricating a gate trench power semiconductor device according to an embodiment of the inventive concept. [Figure 13] 1 is a flow chart illustrating a method of fabricating a gate trench power semiconductor device according to an embodiment of the inventive concept. [Figure 14] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 15A] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. [Figure 15B] FIG. 1 is a schematic diagram illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] In most cases, MISFETs include a gate dielectric layer formed as an oxide layer (e.g., a silicon oxide layer). MISFETs with an oxide gate dielectric layer are called metal oxide semiconductor field effect transistors, or MOSFETs. As discussed in more detail below, the oxide gate dielectric layer in these devices can be susceptible to damage when exposed to high electric fields. Therefore, power MOSFETs (and other power semiconductor devices) that include gate trenches often have shielding regions formed under the gate trenches that help reduce the electric field levels in the oxide gate dielectric layer during reverse blocking operation. Because oxide gate dielectric layers are almost always used due to their superior electrical properties, the following discussion of embodiments of the invention will focus on MOSFETs as opposed to MISFETs, although it will be recognized that the techniques according to embodiments of the invention described herein are equally applicable to devices having gate dielectric layers formed of materials other than oxide.

[0035] SiC-gate trench MOSFET vertical power devices are attractive due to their inherent low specific on-resistance, which may result in more efficient operation for power switching operations requiring low to moderate reverse blocking voltage levels (e.g., 650-1200 V). Trench MOSFET vertical power devices can exhibit low specific resistance during on-state operation because the channel is formed on the sidewall of the gate trench and the trench design reduces the overall pitch of the device, allowing for high integration. Furthermore, the carrier mobility in the sidewall channel of a trench MOSFET has been found to be 2-4 times higher than the corresponding carrier mobility in the channel of a planar (e.g., lateral structure) device. This increased carrier mobility also increases the current density. However, SiC-gate trench MOSFET vertical power devices may suffer from oxide reliability issues due to the presence of steep high-field corners at the bottom edges of the trench, which may break down the gate oxide over time, ultimately resulting in device failure.

[0036] FIG. 1A is a schematic cross-sectional view of a first wide bandgap power MOSFET 100A. As shown in FIG. 1A, the power MOSFET 100A has a heavily doped (n + ) n-type silicon carbide substrate 110. - 1. A silicon carbide drift region 120 is provided on the substrate 110. A lightly doped p-type silicon carbide layer 170 is formed on an upper surface of the n-type drift region 120. The lightly doped p-type silicon carbide layer 170 may be formed by, for example, epitaxial growth. The lightly doped p-type silicon carbide layer 170 may provide a p-well 172 for the device 100. A transistor channel may be formed in the p-well 172, as discussed below. A lightly doped n-type silicon carbide layer 170 may be formed on an upper surface of the n-type drift region 120. The lightly doped p-type silicon carbide layer 170 may be formed by, for example, epitaxial growth. The lightly doped p-type silicon carbide layer 170 may provide a p-well 172 for the device 100. A transistor channel may be formed in the p-well 172, as discussed below. + The silicon carbide source layer 160 may be formed in an upper region of the p-type silicon carbide layer 170. +The silicon carbide source layer 160 may be formed, for example, by ion implantation.

[0037] The substrate 110, the drift region 120, the moderately doped p-type layer 170, and the heavily doped n + The silicon carbide source layer 160, together with various regions / patterns formed therein, constitutes the semiconductor layer structure 106 of the MOSFET 100A.

[0038] A gate trench 180 is formed in the semiconductor layer structure 106. The gate trench 180 is formed by a heavily doped n + The silicon carbide source layer 160 may extend through the moderately doped p-type layer 170 and into the drift region 120. A gate insulation layer 182 may be formed on a lower surface and sidewalls of each gate trench 180. A gate electrode 184 may be formed on each gate insulation layer 182 to fill the respective gate trench 180. A vertical channel region 178 is provided in the p-well 172 adjacent the gate insulation layer 182.

[0039] The source contact (not shown) is a heavily doped n-type source layer 160. A drain contact (not shown) may be formed on the lower surface of the substrate 110. A gate contact (not shown) may be formed on the gate electrode 184.

[0040] If the gate insulation layer 182, typically implemented as a silicon oxide layer, is subjected to excessively high electric fields, the gate insulation layer 182 will degrade over time and eventually fail to insulate the gate electrode 184 from the semiconductor layer structure, which may result in device failure. Corners of the gate insulation layer 182 (e.g., areas where the gate insulation layer 182 transitions from a vertical surface to a lateral surface) are particularly susceptible to such high electric fields. To improve the reliability of the gate insulation layer 182, the power MOSFET 100 includes a deep shield pattern 140 beneath the gate trench 180. The deep shield pattern 140 is formed by ion implantation into a heavily doped (p + ) silicon carbide pattern.

[0041] The deep shield pattern 140 can be very effective in protecting the corners of the gate insulating layer 182 from high electric fields during reverse blocking operation. The deep shield pattern 140 can provide a shield for the gate insulating layer 182 and can provide desired device performance due to the utilization of two sidewall surfaces for current conduction.

[0042] The deep shield pattern 140 of the power MOSFET 100A may be formed following the formation of the gate trench 180 and prior to the formation of the gate insulating layer 182 and the gate electrode 184 therein. Ion implantation may be used to form the deep shield pattern 140. The depth to which ions are implanted is directly related to the energy of the implant, i.e., ions implanted into a semiconductor layer with higher energy tend to penetrate deeper into the layer. Therefore, forming a deep shield pattern (which may have a thickness of 1-5 microns) by ion implantation requires a high energy implant.

[0043] When dopant ions are implanted into a semiconductor layer, the ions damage the crystal lattice of the semiconductor layer, and this damage can typically only be partially repaired by thermal annealing. Furthermore, the amount of lattice damage is also directly related to the implant energy, with higher energy implants tending to cause more lattice damage compared to lower energy implants, and the uniformity of the ion implant also tends to decrease with increasing implant depth. Therefore, to form an implanted region with good doping uniformity with depth and / or an acceptable level of lattice damage, it may be necessary to perform multiple successive epitaxial growth / ion implantation steps to form deep implants. This may significantly increase the complexity and cost of the manufacturing process and may not be a commercially viable option in many cases.

[0044] Furthermore, the formation of the deep shield pattern 140 may be a challenge due to anisotropic etching of the silicon carbide layers 160, 170, and 120 during the formation of the gate trench 180. Whereas FIG. 1A shows an ideal trench 180 and deep shield pattern 140, FIG. 1B is a schematic cross-sectional view of a power MOSFET 100B during the formation of the deep shield pattern 140 by ion implantation 190, which may result from current formation techniques. As can be seen, the sidewalls of the trench 180B are angled (i.e., not vertical) due to the anisotropic etching. Due to the angle of the sidewalls and ion scattering effects, p-type ions are implanted into the semiconductor region, and p + During the formation of the deep shield pattern 140, the sidewalls of the gate trench 180 are formed. The implantation of p-type ions into these regions of the device changes the effective doping level of these regions. Furthermore, the drift region 120 is doped with a lightly doped (n - ) region (e.g., heavily doped (p +) orders of magnitude lower than the deep shield pattern 140, the n-type dopants in the upper portion of the drift region 120 can be at least partially compensated for by unintentional doping of p-type dopants into the trench sidewalls that may occur during the ion implantation step used to form the deep shield pattern 140. This can result in an increase in JEFT resistance (as the effective n-type doping level is reduced by the implantation of compensating p-type ions) and in some cases, as shown in FIG. 1B, the p-type dopants can completely overwhelm the background n-type doping of the drift region 120, forming a p-type pinch region 144 that is dominated by highly doped (p + ) connecting the deep shield pattern 140 to the moderately doped p-type layer 170. If this happens, the current will be pinched off, causing the power MOSFET 100B to become unusable or to perform severely degraded.

[0045] This approach to ensure that the sidewalls of the drift region 120 exposed by the trench 180 between the p-well 172 and the deep shield pattern 140 are not unintentionally doped with p-type dopants during the formation of the deep shield pattern 140 is described below with reference to FIGS. 2A-3C. FIGS. 2A-2C show operations 200A-200C, respectively, of a first related art approach to forming a power MOSFET that addresses the problem presented by the gated trench power MOSFET of FIG. 1B. Prior to operation 200A shown in FIG. 2A, a trench etch oxide mask 210 may be formed on the upper surface of the device and the gate trench 180 may be formed by etching. In operation 200A of FIG. 2A, with the trench etch oxide mask 210 still present, a sidewall oxide mask 220 is formed over the heavily doped n-type dopant exposed by the gate trench 180. + A silicon carbide source layer 160, a moderately doped p-type layer 170, and a lightly doped n -The sidewall oxide mask may be formed by oxidizing portions of the silicon carbide drift region 120. The sidewall oxide mask may be formed by thermal oxidation.

[0046] In operation 200B, shown in FIG. 2B, ion implantation 190 is performed on the lightly doped n-type silicon exposed at the bottom of trench 180. - In the silicon carbide drift region 120 portion, heavily doped (p + ) may be performed to implant deep shield patterns 240 of silicon carbide. Ion implantation 190 may also be performed on exposed surfaces of trench etch oxide mask 210 and sidewall oxide mask 220, causing portions 211 of trench etch oxide mask 210 and portions 221 of sidewall oxide mask 220 to be implanted with a p-type dopant.

[0047] In operation 200C, shown in FIG. 2C, oxide masks 210 and 220 may be removed along with portions 211 and 221, respectively, that were ion implanted in operation 200B. Removal of oxide masks 210 and 220 may result in the lightly doped n-type silicon nitride (NbSi) exposed by the trench. - This ensures that portion 120S of silicon carbide drift region 120 is not substantially counter-doped with p-type dopants, and thus the problems of power MOSFET 100B of FIG. 1B may be avoided.

[0048] One advantage of the approach of Figures 2A-2C is that when a device is formed on a SiC wafer with an exposed (0001) surface, crystal orientation effects result in the sidewall oxide mask 220 forming much more quickly than the oxide that forms on the portion of the drift region 120 exposed at the bottom of the gate trench 180. On the other hand, a disadvantage of the approach of Figures 2A-2C is that the resulting gate trench 180W formed following operation 200C is wider and deeper than the original gate trench 180 formed prior to operation 200A of Figure 2A. As a result, the width of the deep shield pattern 240 is narrower than the width of the gate trench 180, which means that the deep shield pattern 240 will not extend to cover the bottom corners of the gate insulating layer subsequently formed in the gate trench 180W, and therefore the deep shield pattern provides insufficient protection for the most vulnerable portion of the gate insulating layer. Similarly, the formation of the sidewall oxide mask 220 in operation 200A may result in a ledge surface 220L (see FIG. 2A ) that may scatter the implant in operation 200B in an unintended direction, resulting in, for example, a heavier p-type doping of the channel region (requiring a thicker sidewall oxide mask 220 and making the resulting gate trench 180W wider).

[0049] 3A-3C illustrate a second related art approach to a method of forming a power MOSFET that addresses the problems presented by the gate trench power MOSFET of FIG. 1B. Prior to operation 300A shown in FIG. 3A, a trench etch oxide mask 210 is formed using a heavily doped n + 3A, and with the trench etch oxide mask 210 still present, a sidewall oxide mask 320 is etched over the upper surfaces of the silicon carbide source layer 160 and the moderately doped p-type layer 170 that is exposed by the gate trench 180. +A silicon carbide source layer 160, a moderately doped p-type layer 170, and a lightly doped n - The trench etch oxide mask 210 may be formed by depositing a mask material (e.g., SiO2) over portions of the silicon carbide drift region 120 and over the upper surface of the trench etch oxide mask 210.

[0050] In operation 300B shown in FIG. 3B, ion implantation 190 is performed on a lightly doped n - In the silicon carbide drift region 120, heavily doped (p + ) may be performed to implant deep shield patterns 340 of silicon carbide. Ion implantation 190 may also be performed on exposed surfaces of trench etch oxide mask 210 and sidewall oxide mask 320, to remove portions of trench etch oxide mask 210 and sidewall oxide mask 320. 320 This results in a portion 321 of the substrate being implanted with ions.

[0051] In operation 300C, shown in FIG. 3C, the oxide masks 210 and 320 may be removed along with those portions that were ion implanted in operation 300B. As in the operations of FIGS. 2A-2C, removal of the oxide masks 210 and 320 may result in the removal of the heavily doped (p + ) a lightly doped n-type semiconductor that is substantially unaffected by the silicon carbide deep shield pattern 340 - 1B. This results in portion 120S of silicon carbide drift region 120, and therefore the problem of power MOSFET 100B in FIG. 1B may be avoided.

[0052] The approach of Figures 3A-3C provides an advantage in that the resulting gate trench following operation 300C of Figure 3C has the same width as the original gate trench 180 etched prior to operation 300A of Figure 3A because, unlike operations 200A-C, none of the drift region 120, p-type layer 170, and source layer 160 materials are thermally oxidized. Ledge surfaces similar to surface 200L are also advantageously avoided. However, a disadvantage of the approach of Figures 3A-3C is that deposition of sidewall mask material to form sidewall oxide mask 320 may result in a thicker mask being applied to the lower portion of gate trench 180 (e.g., to the upper surface of drift region 120 exposed by gate trench 180) compared to along the sidewalls of gate trench 180. This thicker mask at the lower portion of gate trench 180 may be formed by deposition of highly doped (p + ) may possibly unacceptably block the implantation of ions used to form silicon carbide deep shield pattern 340. Thinning sidewall oxide mask 320 (e.g., by depositing less material), on the other hand, may possibly necessitate re-etching of gate trench 180 to remove implanted material in the sidewalls of drift region 120, p-type layer 170, and source layer 160, still resulting in a gate trench that is wider and deeper than the original gate trench 180 formed prior to operation 300A of FIG.

[0053] As discussed above, the formation of deep shield regions may be time consuming and may result in implantation damage to the semiconductor device structure. According to embodiments of the present invention, gate trench wide bandgap power semiconductor devices, such as power MOSFETs and power IGBTs, are provided that lack a deep trench shield pattern below the gate trench. Instead, doped polysilicon material may be used as a shielding material to shield a portion of the bottom of the gate trench and portions of one sidewall of the gate trench. Using highly doped polysilicon as a blocking material may simplify the operations of forming the gate trench wide bandgap power semiconductor device and may reduce implantation damage to the device. Thus, exemplary embodiments of the present disclosure may reduce or avoid the disadvantages of the approaches of FIGS. 1B, 2A-2C, and 3A-3C. Additionally, in some embodiments, the doped polysilicon region may be connected to the source of the power semiconductor device, which may be advantageous when the device is in a blocking mode of operation.

[0054] The new approach to forming the doped polysilicon blocking region can reduce or even eliminate the implanted p-type dopants in the portion of the drift region between the p-well channel and the deep shield pattern. As such, devices according to embodiments of the invention can exhibit improved performance compared to devices formed using the techniques discussed above with respect to the power MOSFET 100B of FIG. 1B. Furthermore, the approach according to embodiments of the invention can avoid the difficulties in forming wider and / or deeper gate trenches as in FIGS. 2A-2C, or deep shield patterns as in FIGS. 3A-3C.

[0055] Embodiments of the present invention will now be described with reference to Figures 4A-13. It will be appreciated that the features of the different embodiments disclosed herein may be combined in any manner to provide many further embodiments. Thus, for example, features of any MOSFET embodiment described herein may be incorporated within an IGBT embodiment, and vice versa. Thus, although various features of the inventive concepts are described below with respect to specific examples, it will be appreciated that these features may be added to other embodiments and / or substituted for example features of other embodiments to provide many further embodiments. Thus, it should be understood that the present invention encompasses these different combinations.

[0056] 4A-4D are schematic diagrams illustrating a trench-gated power MOSFET according to an embodiment of the inventive concept. More specifically, FIG. 4A is a plan view of the upper surface of the semiconductor layer structure of a trench-gated power MOSFET device. FIG. 4B is a cross-sectional view taken along line BB in FIG. 4A, and FIG. 4C is a corresponding perspective view. FIG. 4D is a cross-sectional view taken along line BB in FIG. 4A, showing the device after gate material 490 (not shown in FIGS. 4A-4C) has been formed in the gate trench. Additionally, oxide layer 455 (discussed below) has been omitted in FIGS. 4A and 4C to better illustrate and explain the trench-gated power MOSFET device.

[0057] 4A-4D, a gated trench power MOSFET device 400 can include a semiconductor layer structure 406. The semiconductor device can include a heavily doped (n + ) n-type silicon carbide substrate 410. - A heavily doped (n) silicon carbide drift region 420 may be formed on the substrate 410 by epitaxial growth. A moderately doped p-type layer is formed on the upper surface of the n-type silicon carbide drift region 420. +A region of n-type silicon carbide is formed in the upper region of the moderately doped p-type layer by ion implantation. A region of highly doped (n + The n-type silicon carbide region can be the source region. All of the layers described above can be grown in a single epitaxial growth process that has a process stop that switches between n-type and p-type doping (heavily doped (n) in the upper region of the moderately doped p-type layer). + ) with a subsequent ion implantation step to form n-type silicon carbide regions. The layers described above comprise a semiconductor layer structure 406.

[0058] A gate trench 480 may be etched into the upper surface of the semiconductor layer structure 406. Although only one gate trench 480 is shown in Figures 4B-4D, it will be appreciated that a plurality of gate trenches 480 will typically be provided, with each gate trench 480 extending in a first direction (e.g., from the upper surface of the n-type silicon carbide layer towards the substrate 410) and spaced apart from one another in a second direction such that the gate trenches 480 extend a predetermined length parallel to one another. The gate trenches 480 may extend a predetermined length in a third direction, which may be perpendicular to the first direction and may be parallel to the upper surface of the substrate 410.

[0059] Each gate trench 480 may extend through the heavily doped n-type silicon carbide layer to convert it into a number of spaced apart regions 464 that will ultimately serve as source regions of the power MOSFET. Each gate trench 480 may also extend through the moderately doped p-type silicon carbide layer to convert it into a number of p-wells 472. Each gate trench 480 may also extend into the upper surface of the n-type drift region 420.

[0060] 4B, the etching of the gate trench 480 can result in non-parallel sidewall surfaces thereof. In other words, the sidewalls can be angled with respect to the normal (perpendicular) to the top surface of the substrate 410.

[0061] After etching the gate trench 480, a polysilicon layer 450 may be deposited on top of the upper surface of the semiconductor layer structure 406. The polysilicon layer 450 may be a heavily doped p-type polysilicon layer. The polysilicon layer 450 may be deposited along one sidewall of the gate trench 480 and may conform to the sidewall of the gate trench 480. The polysilicon layer 450 may be a continuous layer that extends parallel to the length of the gate trench 480. The polysilicon layer 450 may be formed, for example, by blanket forming a polysilicon layer on the device and using an etch mask to selectively etch the blanket polysilicon layer. Alternatively, a mask may be formed first and a polysilicon layer may be selectively deposited in openings in the mask. Other techniques may also be used.

[0062] In other words, polysilicon layer 450 may be deposited on the sidewalls of n-type drift region 420 and the sidewalls of the p-type silicon carbide layer, both of which are exposed by etched gate trench 480. In some embodiments, a photoprocess may be used to define polysilicon layer 450 on the sidewalls of gate trench 480. In some illustrative embodiments, and as seen in FIG. 4B , polysilicon layer 450 may also be deposited on a portion of the lower portion of gate trench 480 (e.g., on the upper surface of n-type drift region 420 exposed by gate trench 480) and on an upper portion of p-well 472. In some embodiments, the thickness of polysilicon layer 450 may be in the range of 100 nanometers (nm) to 500 nm, although the disclosure is not limited thereto.

[0063] 4A and 4C, the gate trench 480 and polysilicon layer 450 may extend uninterrupted along the length of the device 400 and / or the length of the semiconductor layer structure 406.

[0064] After the polysilicon layer 450 is deposited, an oxide layer 455 may be formed. The oxide layer 455 may be formed both on / in the upper surface of the polysilicon layer and on the exposed portions of the silicon carbide semiconductor layer structure 406, as shown in FIG. 4B. In some embodiments, the oxide layer 455 may be formed by oxidizing the polysilicon layer 450 and the exposed silicon carbide by annealing in an oxygen-containing environment. It will be appreciated that when the oxide layer 455 is formed by thermal oxidation, the polysilicon layer 450 may oxidize more quickly than the exposed silicon carbide surfaces (and the exposed silicon carbide surfaces may also oxidize at different rates depending on which sides of the crystal structure are exposed), and thus the oxide layer 455 may not have a uniform thickness. Additionally or alternatively, the oxide layer 455 may be formed by deposition. Any unwanted portions of the oxide layer 455 (e.g., the oxidized silicon carbide surfaces outside the gate trench 480) may be removed. After formation of polysilicon layer 450 and oxide layer 455, further processing (e.g., forming a gate insulation layer, a gate electrode, and contacts) may be performed to form a power MOSFET. For example, gate electrode 490 shown in FIG. 4D may be formed.

[0065] 4A-4D avoids the shortcomings of Figures 2A-3C discussed above, as well as possible problems that may result from implantation of ions into n-type drift region 420. Formation of polysilicon layer 450 may also provide for a reduced number of operations and / or simplified manufacture of the device.

[0066] 4E and 4F are schematic diagrams illustrating a gate trench power MOSFET according to an embodiment of the inventive concept. FIG. 4E is a cross-sectional view, and FIG. 4F is a corresponding perspective view. FIGS. 4E and 4F show that in some embodiments, a polysilicon layer 450 may be formed on both sides of a gate trench 480. Indeed, in some embodiments, some gate trenches 480 may have a polysilicon layer 450 formed on the "right" sidewall, while other gate trenches 480 in the device may have a polysilicon layer 450 formed on the "left" sidewall (i.e., some gate trenches may have the design of FIGS. 4B-4D, while other gate trenches have the design of FIGS. 4E-4F). Thus, the gate trenches 480 of these devices may have a first sidewall (which may be the left sidewall for some gate trenches and the right sidewall for other gate trenches) that does not include the polysilicon layer 450 and a second sidewall (which may again be the left sidewall for some gate trenches and the right sidewall for other gate trenches) that has the polysilicon layer 450 formed thereon.

[0067] FIG. 14 is a schematic diagram illustrating a gate trench power MOSFET 1400 according to a further embodiment of the inventive concept. FIG. 14 illustrates that in some embodiments, the gate trench 480 can be etched to extend deeper into the n-type drift region 420 from a top surface of the n-type drift region 420. A polysilicon layer 1450 can be formed or deposited to completely cover a first sidewall of the gate trench 480 and partially cover a second sidewall of the gate trench 480. The polysilicon layer 1450 can also completely cover a bottom surface of the gate trench 480. The gate trench 480 and the polysilicon layer 1450 can extend uninterrupted along the length of the device 400 and / or the length of the semiconductor layer structure 406.

[0068] 5A-5E are schematic diagrams illustrating a trench gated power MOSFET according to an embodiment of the inventive concept. More specifically, FIG. 5A is a plan view of the top surface of the trench gated power MOSFET device, and FIGS. 5B, 5C, 5D, and 5E are cross-sectional views. FIG. 5B is taken along line BB of FIG. 5A. FIG. 5C is taken along line CC of FIG. 5A. FIGS. 5D and 5E correspond to FIGS. 5B and 5C, respectively, but also include gate material 590 that was eliminated from FIGS. 5A-5C to better illustrate the polysilicon layer in the gate trench. Additionally, oxide layer 555 is omitted in FIGS. 5A, 5B, and 5C to better illustrate and explain the trench gated power MOSFET device.

[0069] 5A-5E, a gated trench power MOSFET device 500 can include a semiconductor layer structure 506. Once formed, the semiconductor layer structure 506 can be identical to the semiconductor layer structure 406 of FIGS. 4A-4D, and therefore further description thereof will be omitted here.

[0070] A gate trench 480 may be etched into an upper surface of the semiconductor layer structure 506. The gate trench 480 may be identical to the gate trench 480 of Figures 4A-4D, and therefore further description thereof will be omitted here.

[0071] The polysilicon layer 550 may be deposited on top of the upper surface of the semiconductor layer structure 506. The polysilicon layer 550 may be a heavily doped p-type polysilicon layer. The polysilicon layer 550 may be deposited in non-contiguous regions along one sidewall of the gate trench 480, and each of the non-contiguous regions may coincide with a sidewall of the gate trench 480. In other words, there may be a first region 480-1 of the gate trench 480 in which the polysilicon layer 550 is deposited, and there may be a second region 480-2 of the gate trench 480 in which the polysilicon layer 550 is absent. The first region 480-1 of the gate trench 480 may alternate with the second region 480-2 of the gate trench 480 in a third direction (e.g., in the direction in which the gate trench 480 extends for a given length). Each first region 480-1 of the gate trench 480 may be between a pair of adjacent second regions 480-2 of the gate trench 480, and / or each second region 480- 2 may be between a pair of adjacent first regions 480-1 of the gate trench 480. In some demonstrative embodiments, a patterned mask layer and / or a photoprocess may be used to deposit a polysilicon layer 550 in the first regions 480-1 of the gate trench 480.

[0072] The polysilicon layer 550 in the first region 480-1 may be deposited on one of the sidewalls of the trench 480. For example, as shown in FIG. 5B, each sidewall of the gate trench 480 is formed by an exposed portion of the n-type drift region 420 and one of the p-wells 472. In some example embodiments, as shown in FIG. 5B, the polysilicon layer 550 may be deposited on the first sidewall of the gate trench 480. region 480-1 (e.g., on the upper surface of the n-type drift region 420 exposed by the gate trench 480) and on the first regionIt may also be deposited on an upper portion of p-well 472 adjacent 480-1. In some embodiments, polysilicon layer 450 may be in the range of 100 nanometers (nm) to 500 nm thick, although the disclosure is not limited thereto.

[0073] After the polysilicon layer 550 is deposited in the first region 480-1 of the etched gate trench 480, an oxide layer 555 may be formed. The oxide layer 555 may include a first portion 555-1 formed on the polysilicon layer 550, or in other words, formed on the polysilicon layer 550 in the first region 480-1 of the etched gate trench 480. The oxide layer 555 may also include a second portion 555-2 formed on the components of the semiconductor layer structure 506, such as the drift region 420, the p-well 472, and the heavily doped n-type silicon carbide region 464, that are exposed in the second region 480-2 of the gate trench 480. For example, in the first region 480-1 of the gate trench, the polysilicon layer 550 may be oxidized by annealing in an oxygen-containing environment, resulting in a first portion 555-1 of the oxide layer 555. In the second region 480-2 of the gate trench, the surfaces of the drift region 420, the p-type silicon carbide layer 470, and the heavily doped n-type silicon carbide region 464 exposed in the second region 480-2 may be oxidized by annealing in an oxygen-containing environment to result in a second portion 555-2 of the oxide layer 555. Additionally or alternatively, the oxide layer 455 may be formed by deposition. The first portion 555-1 of the oxide layer 555 may have a different cross-section than the second portion 555-2 of the oxide layer. The oxide layer 555 may have different thicknesses in different regions for the same reasons as discussed above with respect to the embodiment of FIGS. 4A-4D.

[0074] After formation of the polysilicon layer 450 and the oxide layer 555, further processing (e.g., forming a gate insulation layer, a gate electrode, and contacts) may be performed to form a power MOSFET. For example, the gate electrode 590 shown in Figures 5D and 5E may be formed. As with the oxide layer 555, the gate electrode 590 may have a different cross-section 590-1 in a first region 480-1 of the gate trench compared to a cross-section 590-2 in a second region 480-2.

[0075] The illustrative embodiment of FIGS. 5A-5E may provide that in the second region 480-2 where the sidewalls of the gate trench 480 are free of the polysilicon layer 550, a channel may conduct current along the sidewalls, e.g., by a p-well formed in the sidewall. Note that in FIG. 5A, the polysilicon layers in adjacent gate trenches are shown as aligned. It will be appreciated that embodiments of the invention are not limited to such an arrangement. For example, in other embodiments, the polysilicon layers 455 in adjacent trenches may be completely offset from one another (i.e., such that no portion of the polysilicon layers are aligned in the horizontal direction of the view of FIG. 5A) or may be partially offset from one another.

[0076] 5F and 5G are schematic diagrams illustrating a gate trench power MOSFET according to further embodiments of the inventive concept. FIG. 5F is a cross-sectional view, and FIG. 5G includes gate material 590 removed from FIG. 5F to better illustrate the polysilicon layer in the gate trench of FIG. 5F. FIGS. 5F and 5G illustrate that in some embodiments, polysilicon layer 550 may be formed on both sides of gate trench 480. Furthermore, in some embodiments, gate trench 480 may comprise a first region 480-1 (seen in FIG. 5B), a second region 480-2 (seen in FIG. 5C), and a third region 480-3 (seen in FIG. 5G). Within first region 480-1 of gate trench 480, polysilicon layer 550 may be formed on a first sidewall 480-R of gate trench 480. In a third region 480-3 of the gate trench 480, a polysilicon layer 550 may be formed on a second sidewall 480-L of the gate trench 480. In a second region 480-2, both the first and second sidewalls 480-R, 480-L of the gate trench may be free of the polysilicon layer 550. In the first and third regions 480-1 and 480-3, the channel may conduct current by the sidewalls free of the polysilicon layer 550, and in the second region 480-2 (where both sidewalls of the gate trench 480 are free of the polysilicon layer 550), the channel may conduct current along both sidewalls, e.g., by a p-well formed in the sidewall.

[0077] 15A and 15B are schematic diagrams illustrating a gate trench power MOSFET 1500 according to further embodiments of the inventive concept. FIGs. 15A and 15B illustrate that in some embodiments, in a first region 480-1, a polysilicon layer 1550 may be formed on both sides of the gate trench 480, and in a second region 480-2, both the first and second sidewalls of the gate trench may be free of the polysilicon layer 1550. In the first region 480-1, no current may be conducted since both sidewalls are covered by the polysilicon layer 1550, and in the second region 480-2 (both sidewalls of the gate trench 480 are free of the polysilicon layer 1550), a channel may conduct current along both sidewalls, e.g., by a p-well formed in the sidewall.

[0078] Figures 6A-6B are schematic cross-sectional views of a gated trench power MOSFET device 600 according to an embodiment of the inventive concept. Figures 6C and 6D are cross-sectional views of a gated trench power MOSFET device 600' illustrating regions of the device having a different cross-section than that shown in Figures 6A and 6B.

[0079] 6A and 6B, a gated trench power MOSFET device 600 may be similar to the gated trench power MOSFET device 400 described with reference to FIGS. 4A-4D, except that the MOSFET device 600 further includes an additional oxide layer 654 between the sidewalls of the gate trench 480 and the polysilicon layer 450.

[0080] The gate trench power MOSFET device 600 may include a semiconductor layer structure 406 having a gate trench 480 formed therein. The semiconductor layer structure 406 and the gate trench 480 may be identical to the semiconductor layer structure 406 and the gate trench, respectively, of the embodiment of Figures 4A-4D, and therefore further description thereof will be omitted here.

[0081] Prior to deposition of polysilicon layer 450, an under oxide layer 654 may be formed. For example, surfaces of drift region 420, p-type well 472, and heavily doped n-type silicon carbide region 464 exposed in gate trench 480 may be oxidized by annealing in an oxygen-containing environment to result in under oxide layer 654. Additionally or alternatively, under oxide layer 654 may be formed by deposition.

[0082] Polysilicon layer 450 may be deposited on top of the upper surface of semiconductor layer structure 506 and / or on the upper surface of bottom oxide layer 654. Polysilicon layer 450 may be identical to polysilicon layer 450 discussed above with reference to the embodiment of Figures 4A-4D, except that in the embodiment of Figures 6A-6B, polysilicon layer 450 is formed on bottom oxide layer 654, as opposed to being formed directly on the underlying semiconductor layer structure 606. Accordingly, further description of polysilicon layer 450 is omitted here.

[0083] After the polysilicon layer 450 is deposited, a top oxide layer 655 may be formed. For example, the polysilicon layer 450 and the exposed surfaces of the semiconductor layer structure 606 may be oxidized by annealing in an oxygen-containing environment. Additionally or alternatively, the top oxide layer 655 may be formed by deposition. The top oxide layer 655 may be formed by a different process than the bottom oxide layer 654. After the formation of the polysilicon layer 450 and the top oxide layer 655, further processing (e.g., forming a gate insulating layer, a gate electrode, and contacts) may be performed to form a power MOSFET. For example, the gate electrode 490 shown in FIG. 6B may be formed.

[0084] The gated trench power MOSFET device 600 corresponds to the gated trench power MOSFET device 400 of FIGS. 4A-4D with the addition of a bottom oxide layer 654. It will be appreciated that the gated trench power MOSFET device 500 of FIGS. 5A-5D may similarly be modified to include a bottom oxide layer 654 to provide a gated trench power MOSFET device 600'. FIGS. 6A-6D illustrate such a gated trench power MOSFET device 600'. In particular, FIGS. 6A-6B discussed above illustrate a cross section of the device 600' including the polysilicon layer 450 (and thus correspond to the cross sections of FIGS. 5B and 5D). FIGS. 6C and 6D illustrate a cross section of the device 600' without the polysilicon layer 450 (and thus correspond to the cross sections of FIGS. 5C and 5E).

[0085] As shown in FIGS. 6C-6D, a bottom oxide layer is formed throughout gate trench 480 (including portion 480-2 of gate trench 480 that does not include polysilicon layer 550).

[0086] After the bottom oxide layer 654 is formed, the polysilicon layer 550 may be deposited in non-contiguous regions along one sidewall of the gate trench 480, and each of the non-contiguous regions may coincide with a sidewall of the gate trench 480. In other words, there may be a first region 480-1 of the gate trench 480 in which the polysilicon layer 550 is deposited, and there may be a second region 480-2 of the gate trench 480 in which the polysilicon layer 550 is absent. The first regions 480-1 of the gate trench 480 may alternate with the second regions 480-2 of the gate trench 480 in a third direction (e.g., in the direction in which the gate trench 480 extends for a given length). Each first region 480-1 of the gate trench 480 may be between a pair of adjacent second regions 480-2 of the gate trench 480, and / or each second region 480- 2may be between a pair of adjacent first regions 480-1 of the gate trench 480. In some demonstrative embodiments, a patterned mask layer and / or a photoprocess may be used to deposit a polysilicon layer 550 in the first regions 480-1 of the gate trench 480.

[0087] As mentioned above, the portion of the gate trench power MOSFET 650 having the first region 480-1 of the gate trench 480 may be identical to the gate trench power MOSFET 600 shown in Figures 6A-6B, to which reference is made above. After the polysilicon layer is deposited in the first region 480-1 of the etched gate trench 480, a top oxide layer 655 may be formed. The top oxide layer 655 may include a first portion formed on the polysilicon layer 550, or in other words, formed on the polysilicon layer in the first region 480-1 of the etched gate trench 480. The top oxide layer 655 may also include a second portion formed on the surfaces of the components of the semiconductor layer structure, such as the drift region 420, the p-type well 472, and the heavily doped n-type silicon carbide region 464, that are exposed in the second region 480-2 of the gate trench 480.

[0088] The addition of bottom oxide layer 655 may provide the additional benefit of blocking hole injection into polysilicon layer 450 when a high voltage is applied to the drain.

[0089] FIG. 7 is a schematic cross-sectional view illustrating a gated trench power MOSFET 700 according to an embodiment of the inventive concept.

[0090] The gated trench power MOSFET device 700 can include a semiconductor layer structure 706. The semiconductor layer structure 706 can be similar to the semiconductor layer structure 406 of FIGS. 4A-4D. For example, the semiconductor layer structure 706 can be a heavily doped (n + ) n-type silicon carbide substrate 410, lightly doped (n- ) silicon carbide drift region 420, a moderately doped p-well 472 formed on the upper surface of n-type silicon carbide drift region 420, and a heavily doped (n + ) n-type silicon carbide region 464.

[0091] The gate trenches 480 may be etched into the upper surface of the semiconductor layer structure 706. Although only one gate trench 480 is shown in FIG. 7, it will be appreciated that a plurality of gate trenches 480 are typically provided, with each gate trench 480 extending in a first direction (e.g., from the upper surface of the n-type silicon carbide layer toward the substrate 410) and spaced apart from one another in a second direction such that the gate trenches 480 extend parallel to one another. The gate trenches 480 may be substantially identical to the gate trenches 480 of the embodiment of FIGS. 4A-4D, except that the gate trenches of this embodiment may extend deeper into the semiconductor layer structure 706. Each gate trench 480 may also extend into the upper surface of the n-type drift region 420.

[0092] The polysilicon layer 750 may be deposited on the bottom of the gate trench 480. The polysilicon layer 750 may fill a lower portion of the gate trench 480. The polysilicon layer 750 may be a continuous layer extending parallel to the length of the gate trench 480. In other words, the polysilicon layer 750 may be deposited on the top surface of the n-type drift region 420 exposed by the gate trench 480, but the sidewalls of the p-well 472 may be free of the polysilicon layer 750. A photoprocess may be used to define the polysilicon layer 750 at the bottom of the gate trench 480.

[0093] In some embodiments, referring to FIGS. 5B-5E, polysilicon layer 750 may be deposited along one sidewall of gate trench 480 and in at least a first region 480-1 of gate trench 480.

[0094] After the polysilicon layer 750 is deposited, an oxide layer 755 may be formed. For example, the polysilicon layer 750 and the semiconductor layer structure 706 The exposed surfaces of the polysilicon layer 750 may be oxidized by annealing in an oxygen-containing environment. Additionally or alternatively, an oxide layer 755 may be formed by deposition. After formation of the polysilicon layer 750 and the oxide layer 755, further processing (e.g., forming a gate insulation layer, a gate electrode, and contacts) may be performed to form a power MOSFET. For example, as seen in FIG. 7, an intermetal dielectric layer 785, a source contact 796, a drain contact 765, and a gate electrode 490 may be formed.

[0095] FIG. 8 is a schematic cross-sectional view of a gated trench power MOSFET according to an embodiment of the inventive concept. The gated trench power MOSFET device 800 can include a semiconductor layer structure 806. The semiconductor layer structure 806 can be similar to the semiconductor layer structure 406 of FIGS. 4A-4D. For example, the semiconductor layer structure 806 can include a heavily doped (n + ) n-type silicon carbide substrate 410, lightly doped (n - ) silicon carbide drift region 420, a moderately doped p-type layer formed on the upper surface of n-type silicon carbide drift region 420, and a heavily doped (n + ) n-type silicon carbide layer. Silicon carbide region 464 can be the source region. All of the layers described above can be grown in a single epitaxial growth process with a process stop that switches between n-type and p-type doping.

[0096] A plurality of gate trenches 480 may be etched into the upper surface of the semiconductor layer structure 806 (only one gate trench 480 is shown in FIG. 8 ). Each gate trench 480 extends in a first direction (e.g., from the upper surface of the n-type silicon carbide layer toward the substrate 410) and the gate trenches 480 are spaced apart from one another in a second direction such that the gate trenches 480 extend parallel to one another. The gate trenches 480 may extend a length in a third direction, which may be perpendicular to the first direction and parallel to the upper surface of the substrate 410. Additionally, a plurality of source trenches 481 may be etched into the upper surface of the semiconductor layer structure 806 (two source trenches 481 are shown in FIG. 8 ). The source trenches 481 may be formed in the same etching process used to form the gate trenches 480 or may be at least partially formed in a different etching process. For example, the source trench 481 may be formed to be deeper than the gate trench 480 so that a polysilicon layer (described below) formed in the lower portion of the source trench 481 may provide better protection for the lower portion of the gate trench 480. The trenches 480, 481 may extend through the heavily doped n-type silicon carbide layer to convert the heavily doped n-type silicon carbide layer into a plurality of spaced apart regions 464 that will ultimately serve as the source regions 460 of the power MOSFET. The trenches 480, 481 may similarly extend through the moderately doped p-type silicon carbide layer to convert the moderately doped p-type silicon carbide layer into a plurality of p-wells 472. The trenches 480, 481 may also extend into the upper surface of the n-type drift region 420.

[0097] An oxide layer 855 may be formed within each gate trench 480. For example, a semiconductor layer structure 806The exposed surfaces of may be oxidized by annealing in an oxygen-containing environment. Additionally or alternatively, an oxide layer 855 may be formed by deposition. After formation of the oxide layer 855, a gate electrode 890 may be formed in the gate trench 480 and an intermetal dielectric layer 785 may be formed over the gate electrode. A corresponding oxide layer 855 may also be formed in the source trenches 481 (not shown), which may then be optionally removed. Next, a polysilicon layer 850 may be deposited in the lower portion of each source trench 481. The polysilicon layer 850 may be a continuous layer extending parallel to the length of the source trenches 481. A source metallization 796 may then be deposited over the top of the device in the source trenches to form a source contact.

[0098] 9-13 are flow charts illustrating methods of fabricating gated trench power semiconductor devices according to embodiments of the inventive concepts.

[0099] 9 and 4A-4D, operations may begin with the formation of a wide bandgap semiconductor layer structure (block 900). The semiconductor layer structure may include a substrate and a plurality of semiconductor layers, the plurality of semiconductor layers grown on the substrate by epitaxial growth and / or formed by ion implantation. The semiconductor layer structure may include a drift region having a first conductivity type. The semiconductor layer structure may further include a well region having a second conductivity type on the drift region, and a source region having the first conductivity type in an upper portion of the well region. In some embodiments, the semiconductor layer structure may include a current spreading layer having the first conductivity type. A plurality of gate trenches are formed in an upper surface of the semiconductor layer structure (block 910). The gate trenches may extend in a first direction and may be spaced apart from one another in a second direction perpendicular to the first direction. Each gate trench may extend a predetermined length in a third direction perpendicular to the first direction. Each gate trench may have a lower surface, a first sidewall extending in a first direction, and a second sidewall extending in the first direction. A polysilicon layer may be formed on the sidewalls (e.g., the second sidewalls) of the gate trench (block 920). In some embodiments, the polysilicon layer may be deposited on one or more upper surfaces of the semiconductor layer structure. The polysilicon layer and / or one or more upper surfaces of the semiconductor layer structure may be oxidized or an oxide may be deposited, resulting in an oxide layer (block 930). Additional components, such as gate insulation layers, gate electrodes, and contacts, may be formed on the upper and lower surfaces of the semiconductor layer structure to complete the device (block 940).

[0100] 10 and 5A-5E, operations may begin with the formation of a wide bandgap semiconductor layer structure (block 1000). The semiconductor layer structure may be formed in the same manner as described above with reference to block 900 of FIG. 9, and therefore further description thereof will be omitted. A plurality of gate trenches may be formed in an upper surface of the semiconductor layer structure (block 1010). The gate trenches may be formed in the same manner as described above with reference to block 910 of FIG. 9, and therefore further description thereof will be omitted. A polysilicon layer may be formed on a first region of a sidewall (e.g., a second sidewall) of the gate trench (block 1020). In other words, a polysilicon layer may be formed in a first region of the gate trench. The sidewall and the second region of the gate trench may be free of the polysilicon layer. A polysilicon layer may be deposited on one or more upper surfaces of the semiconductor layer structure. One or more upper surfaces of the polysilicon layer and / or the semiconductor layer structure may be oxidized or an oxide may be deposited, resulting in an oxide layer (block 1030). The oxide layer may have a first cross-section in a first portion of the gate trench and a second, different cross-section in a second portion of the gate trench. Further components, such as a gate insulating layer, a gate electrode, and contacts, may be formed on the upper and lower surfaces of the semiconductor layer structure to complete the device (block 1040). The gate electrode may have a first cross-section in the first portion of the gate trench and a second, different cross-section in the second portion of the gate trench.

[0101] 11 and 6A-6D, operations may begin with the formation of a wide bandgap semiconductor layer structure (block 1100). The semiconductor layer structure may be formed in the same manner as described above with reference to block 900 of FIG. 9, and therefore further description thereof will be omitted. A plurality of gate trenches may be formed in an upper surface of the semiconductor layer structure (block 1110). The gate trenches may be formed in the same manner as described above with reference to block 910 of FIG. 9, and therefore further description thereof will be omitted. One or more upper surfaces of the semiconductor layer structure may be oxidized, or an oxide may be deposited, resulting in a lower oxide layer (block 1120). A polysilicon layer may be formed on a sidewall (e.g., a second sidewall) of the gate trench (block 1130). The polysilicon layer may be deposited on one or more upper surfaces of the semiconductor layer structure. In some embodiments, the polysilicon layer may be a continuous region extending the length of the gate trench in a third direction. In another embodiment, a polysilicon layer may be formed in a first region of the gate trench and a second region of the gate trench may be free of the polysilicon layer. The polysilicon layer and / or one or more upper surfaces of the semiconductor layer structure may be oxidized to result in an upper oxide layer (block 1140). Further components, such as a gate insulation layer, gate electrodes, and contacts, may be formed on the upper and lower surfaces of the semiconductor layer structure to complete the device (block 1150).

[0102] 12 and 7, operations may begin with the formation of a wide bandgap semiconductor layer structure (block 1200). The semiconductor layer structure may be formed in the same manner as described above with reference to block 900 of FIG. 9, and therefore further description thereof will be omitted. A plurality of gate trenches may be formed in an upper surface of the semiconductor layer structure (block 1210). The gate trenches may be formed in the same manner as described above with reference to block 910 of FIG. 9, and therefore further description thereof will be omitted. A polysilicon layer may be formed on a lower portion (e.g., a second sidewall) of each gate trench (block 1220). In some embodiments, the polysilicon layer may be deposited. One or more upper surfaces of the polysilicon layer and / or the semiconductor layer structure may be oxidized or an oxide may be deposited, resulting in an oxide layer (block 1230). Additional components, such as gate insulation layers, gate electrodes, and contacts, may be formed on the upper and lower surfaces of the semiconductor layer structure to complete the device (block 1240).

[0103] 13 and 8, operations may begin with the formation of a wide bandgap semiconductor layer structure (block 1300). The semiconductor layer structure may include a substrate and a plurality of semiconductor layers, the plurality of semiconductor layers grown on the substrate by epitaxial growth and / or formed by ion implantation. The semiconductor layer structure may include a drift region having a first conductivity type. The semiconductor layer structure may further include a well region having a second conductivity type on the drift region, and a source region having the first conductivity type in an upper portion of the well region. In some embodiments, the semiconductor layer structure may include a current spreading layer having the first conductivity type. A plurality of gate trenches are formed in an upper surface of the semiconductor layer structure (block 1310). The gate trenches may extend in a first direction and may be spaced apart from one another in a second direction perpendicular to the first direction. Each gate trench may extend a predetermined length in a third direction perpendicular to the first direction. Each gate trench can have a lower surface, a first sidewall extending in a first direction, and a second sidewall extending in the first direction. The plurality of gate trenches can include first gate trenches and second gate trenches that can alternate in a second direction. A polysilicon layer can be formed on a lower portion (e.g., on a second sidewall) of each first gate trench (block 1320). In some embodiments, a polysilicon layer can be deposited. The polysilicon layer and / or one or more upper surfaces of the semiconductor layer structure can be oxidized or an oxide can be deposited, resulting in an oxide layer (block 1330). Additional components, such as gate insulation layers, gate electrodes, and contacts, can be formed on the upper and lower surfaces of the semiconductor layer structure to complete the device (block 1340). For example, a gate electrode can be formed in each second gate trench.

[0104] In the above description, each exemplary embodiment has a particular conductivity type. It will be appreciated that an opposite conductivity type device can be formed by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments. Therefore, it will be appreciated that the present invention covers both n-channel and p-channel devices for each different device structure (e.g., MOSFET, IGBT, etc.). In this specification, when a contact can be either a source contact or a drain contact, the contact can be referred to as a "source / drain contact."

[0105] Although the present invention is described above with respect to power MOSFET and IGBT implementations, it will be appreciated that the techniques described herein apply equally well to other similar vertical power devices having gate trenches. As such, embodiments of the present invention are not limited to MOSFETs and IGBTs, and the techniques disclosed herein may be used with any suitable gate trench device.

[0106] The present invention has been discussed above primarily with respect to silicon carbide-based power semiconductor devices. However, it will be appreciated that silicon carbide is used as an example herein and that the devices discussed herein may be formed in any suitable wide bandgap semiconductor material system. By way of example, gallium nitride-based semiconductor materials (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used in place of silicon carbide in any of the embodiments described above.

[0107] It will also be appreciated that different features of different embodiments described herein may be combined to provide further embodiments. For example, it was discussed above with respect to one embodiment that a junction termination extension may be used in place of a guard ring. This is true in each embodiment disclosed herein. Similarly, a shield region under the gate trench may be included or omitted in any of the embodiments. Any of the embodiments may also include well regions having various dopant concentrations, including a lightly doped channel region.

[0108] Embodiments of the present invention have been described above with reference to the accompanying drawings, in which embodiments of the present invention are shown. It will be appreciated, however, that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth above. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numerals refer to like elements throughout.

[0109] Although the terms first, second, etc. are used throughout this specification to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the present invention. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0110] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0111] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that it can be directly on or extending directly onto the other element, or that intervening elements can be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that it can be directly connected to or coupled to the other element, or that intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0112] Relative terms such as "below" or "above" or "upper" or "lower" or "top" or "bottom" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0113] Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances are expected. Embodiments of the present invention are also described with reference to flow charts. It will be appreciated that the steps shown in the flow charts do not have to be performed in the order shown.

[0114] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions that are characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration within the layer and / or region. Thus, an n-type material has a majority equilibrium concentration of negatively charged electrons, while a p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated with a "+" or "-" (as in n+, n-, p+, p-, n++, n--, p++, p--, or the like) to indicate a relatively higher ("+") or lower ("-") concentration of majority carriers compared to another layer or region. However, such designations do not imply the presence of a particular concentration of majority or minority carriers within the layer or region.

[0115] In the drawings and specification, exemplary embodiments of the invention have been disclosed and, although specific terms have been used, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the appended claims.

Claims

1. A device, comprising: a wide bandgap semiconductor layer structure including a drift region having a first conductivity type; a plurality of gate trenches in an upper portion of the wide bandgap semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening; a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench; a plurality of gate electrodes, each in a respective gate trench and separated from the polysilicon layer on the second sidewall of each gate trench by an oxide layer; Equipped with a lower surface of each polysilicon layer directly contacting a portion of the wide bandgap semiconductor layer structure having the first conductivity type or an oxide layer; Each polysilicon layer extends to an upper surface of the wide bandgap semiconductor layer structure.

2. The device of claim 1 , further comprising a gate structure in each gate trench, each gate structure including a gate oxide.

3. 10. The device of claim 1, wherein the wide bandgap semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type.

4. 10. The device of claim 1 further comprising a first source / drain contact on a first major surface of the wide bandgap semiconductor layer structure and a second source / drain contact on a second major surface of the wide bandgap semiconductor layer structure opposite the first major surface.

5. 2. The device of claim 1, wherein each gate trench extends a predetermined length in a direction parallel to an upper surface of said wide bandgap semiconductor layer structure, and each polysilicon layer extends the length of said respective gate trench.

6. 2. The device of claim 1 , wherein each gate trench extends a length in a direction parallel to an upper surface of the wide bandgap semiconductor layer structure, each gate trench having a first length comprising the respective polysilicon layer and a second length free of the respective polysilicon layer.

7. 7. The device of claim 6, further comprising a channel region in the first sidewall of the gate trench and in the second sidewall of the second length of the gate trench.

8. 8. The device of claim 7, wherein the wide bandgap semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type, and the channel region is within the well region.

9. 2. The device of claim 1, wherein each gate trench comprises a third length comprising a polysilicon layer on the first sidewall of each gate trench.

10. The device of claim 1 further comprising a channel region in the first sidewall of the gate trench.

11. 11. The device of claim 10, wherein the wide bandgap semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type, and the channel region is within the well region.

12. The device of claim 1 , wherein the wide bandgap semiconductor layer structure comprises a silicon carbide wide bandgap semiconductor layer structure.

13. 2. The device of claim 1, further comprising an under oxide layer on said lower surface, said first sidewall, and said second sidewall of each gate trench, said polysilicon layer being on said under oxide layer.

14. The device of claim 13, wherein the oxide layer comprises a top oxide layer.

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