Semiconductor Device

Abstract

To provide a semiconductor device that can suppress the ingress of moisture and movable ions.SOLUTION: A semiconductor device of an embodiment comprises: a semiconductor layer; a first insulating layer provided on the semiconductor layer; a first metal layer provided on the first insulating layer and including aluminum (Al); a second metal layer provided on the first insulating layer and including aluminum (Al); and a second insulating layer provided on top of the first insulating layer and between the first metal layer and the second metal layer, with the top surface in contact with a side surface of the first metal layer and the top surface in contact with a side surface of the second metal layer, and containing silicon (Si) and nitrogen (N).SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] When moisture or mobile ions penetrate into a semiconductor device, the device characteristics fluctuate and the reliability of the semiconductor device decreases. For this reason, a protective insulating layer of, for example, silicon nitride is formed on the surface of the semiconductor device to suppress the penetration of moisture and mobile ions into the semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-55015 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of suppressing the intrusion of moisture and mobile ions. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a semiconductor layer, a first insulating layer provided on the semiconductor layer, a first metal layer provided on the first insulating layer and containing aluminum (Al), a second metal layer provided on the first insulating layer and containing aluminum (Al), a second insulating layer provided on the first insulating layer and between the first metal layer and the second metal layer, the second insulating layer having an upper surface in contact with a side surface of the first metal layer and the second metal layer, the second insulating layer containing silicon (Si) and nitrogen (N), and a gate electrode provided between the semiconductor layer and the first insulating layer. a resin layer provided on the first metal layer, the second metal layer, and the first insulating layer; Equipped with. [Brief description of the drawings]

[0006] [Figure 1] FIG. 2 is a chip image diagram of the semiconductor device according to the embodiment. [Diagram 2] FIG. 2 is an enlarged schematic cross-sectional view of the semiconductor device according to the embodiment. [Diagram 3] 1 is a schematic diagram of a semiconductor device according to an embodiment; [Figure 4] 1 is a schematic top view of a semiconductor device according to an embodiment; [Diagram 5] FIG. 2 is an enlarged schematic cross-sectional view of the semiconductor device according to the embodiment. [Figure 6] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the embodiment. [Figure 7] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the embodiment. [Figure 8] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the embodiment. [Figure 9] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the embodiment. [Figure 10] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the embodiment. [Figure 11] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the embodiment. [Figure 12] FIG. 11 is a schematic cross-sectional view of a semiconductor device of a comparative example. [Figure 13] 11A and 11B are diagrams illustrating problems in a semiconductor device of a comparative example. [Figure 14] FIG. 4 is a schematic cross-sectional view of a first modified example of the semiconductor device of the embodiment. [Figure 15] FIG. 11 is a schematic cross-sectional view of a second modified example of the semiconductor device of the embodiment. [Figure 16] FIG. 11 is a schematic cross-sectional view of a third modified example of the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same reference numerals will be used to designate the same or similar components, and the description of components that have already been described may be omitted as appropriate.

[0008] In the following description, n + , n, n - And, p + , p, p - When n is used, it indicates the relative impurity concentration of each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + shape, n - Simply put, n-type and p-type + shape, p - The shape is sometimes simply described as p-shape.

[0009] The thickness of the metal layer and the insulating layer in this specification can be measured on an image of, for example, an SEM or a Transmission Electron Microscope (TEM). Qualitative and quantitative analysis of the chemical composition of the members constituting the semiconductor device can be performed by, for example, SIMS, Electron Energy Loss Spectroscopy (EELS), or Energy Dispersive X-ray Spectroscopy (EDX).

[0010] The semiconductor device of the embodiment includes a semiconductor layer, a first insulating layer provided on the semiconductor layer, a first metal layer provided on the first insulating layer and containing aluminum (Al), a second metal layer provided on the first insulating layer and containing aluminum (Al), and a second insulating layer provided on the first insulating layer, between the first metal layer and the second metal layer, having an upper surface in contact with a side surface of the first metal layer and an upper surface in contact with a side surface of the second metal layer, and containing silicon (Si) and nitrogen (N).

[0011] Fig. 1 is a chip image diagram of a semiconductor device of an embodiment. Fig. 1 is a diagram showing the relationship between an element region and a termination region of the semiconductor device of an embodiment. Fig. 2 is an enlarged schematic cross-sectional view of the semiconductor device of an embodiment. Fig. 2 is a cross-sectional view of an element region of the semiconductor device of an embodiment. Fig. 2 is a cross-sectional view taken along line AA' in Fig. 1.

[0012] Fig. 3 is a schematic diagram of a semiconductor device according to an embodiment, Fig. 3(a) is a top view, Fig. 3(b) is a cross-sectional view, and Fig. 3(b) is a cross-sectional view taken along line BB' of Fig. 3(a).

[0013] Fig. 4 is a schematic top view of the semiconductor device of the embodiment, which is a view of Fig. 3(a) from which the resin layer is removed.

[0014] Fig. 5 is an enlarged schematic cross-sectional view of the semiconductor device according to the embodiment, and is an enlarged view of a region X shown in Fig. 3(b).

[0015] The semiconductor device of the embodiment is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The semiconductor device of the embodiment is a planar gate vertical MOSFET 100 for high voltage applications. The MOSFET 100 is a power semiconductor device. The MOSFET 100 is a vertical n-channel MOSFET that uses electrons as carriers.

[0016] 1, the MOSFET 100 of the embodiment includes an element region 101 and a termination region 102. A transistor is provided in the element region 101. The termination region 102 surrounds the element region 101. A structure (not shown) for improving the breakdown voltage of the MOSFET 100 is provided in the termination region 102. The structure for improving the breakdown voltage of the MOSFET 100 is, for example, a resurf or a guard ring.

[0017] Hereinafter, as shown in FIG. 1, one direction parallel to the chip surface of the MOSFET 100 is defined as a first direction, and a direction parallel to the chip surface of the MOSFET 100 and perpendicular to the first direction is defined as a second direction.

[0018] The MOSFET 100 includes a semiconductor layer 10, a source electrode 12 (first metal layer), a drain electrode 14 (third metal layer), a gate insulating layer 16, a gate electrode 18, an interlayer insulating layer 20 (first insulating layer), a gate wiring 22 (second metal layer), a gate pad 24, a first protective insulating layer 26 (second insulating layer), a second protective insulating layer 28 (third insulating layer), and a polyimide layer 30 (resin layer).

[0019] The semiconductor layer 10 is, for example, single crystal silicon. + 32, n-type drain region - a p-type drift region 34, a p-type body region 36, and an n + The source region 38 includes a mold.

[0020] The source electrode 12 is an example of a first metal layer. The drain electrode 14 is an example of a third metal layer. The interlayer insulating layer 20 is an example of a first insulating layer. The gate wiring 22 is an example of a second metal layer. The first protective insulating layer 26 is an example of a second insulating layer. The second protective insulating layer 28 is an example of a third insulating layer. The polyimide layer 30 is an example of a resin layer.

[0021] 2, a vertical transistor is formed in an element region 101 of a MOSFET 100. A source electrode 12, a drain electrode 14, a gate insulating layer 16, a gate electrode 18, and a n + 32, n-type drain region - a p-type drift region 34, a p-type body region 36, and an n + The source region 38 constitutes a vertical transistor.

[0022] The semiconductor layer 10 is provided between the source electrode 12 and the drain electrode 14. The gate insulating layer 16 is provided between the gate electrode 18 and the semiconductor layer 10. The gate electrode 18 is provided between the interlayer insulating layer 20 and the semiconductor layer 10. The interlayer insulating layer 20 is provided between the source electrode 12 and the gate electrode 18.

[0023] The drain electrode 14 is electrically connected to the semiconductor layer 10. The drain electrode 14 is electrically connected to the drain region 32. The drain electrode 14 contacts the semiconductor layer 10.

[0024] The interlayer insulating layer 20 is provided on the semiconductor layer 10. The interlayer insulating layer 20 is provided on the gate electrode 18. The interlayer insulating layer 20 has a function of electrically isolating the gate electrode 18 and the source electrode 12 from each other.

[0025] The interlayer insulating layer 20 includes, for example, silicon (Si) and oxygen (O). The interlayer insulating layer 20 includes, for example, silicon oxide. The interlayer insulating layer 20 is, for example, a silicon oxide layer.

[0026] The source electrode 12 is provided in the element region 101. The source electrode 12 is provided on the interlayer insulating layer 20. The source electrode 12 is provided on the semiconductor layer .

[0027] The source electrode 12 is electrically connected to the semiconductor layer 10. The source electrode 12 is electrically connected to the source region 38. The source electrode 12 contacts the semiconductor layer 10.

[0028] The source electrode 12 includes aluminum (Al). The source electrode 12 is, for example, an aluminum layer. The source electrode 12 may have a laminated structure of a barrier metal layer and an aluminum layer. The barrier metal layer is, for example, a titanium layer or a titanium nitride layer.

[0029] The thickness (t1 in FIG. 5) of the source electrode 12 is, for example, not less than 1 μm and not more than 10 μm. The width (w1 in FIG. 4) of the source electrode 12 in the first direction is, for example, not less than 100 μm and not more than 500 μm.

[0030] The gate wiring 22 is provided in the element region 101 or the termination region 102. The gate wiring 22 is provided on the interlayer insulating layer 20. The gate wiring 22 is provided on the semiconductor layer 10.

[0031] The gate wiring 22 is electrically connected to the gate electrode 18. The gate wiring 22 has a function of applying a gate voltage to the gate electrode 18 in the element region 101.

[0032] The gate wiring 22 includes aluminum (Al). The gate wiring 22 is, for example, an aluminum layer. The gate wiring 22 may have a laminated structure of a barrier metal layer and an aluminum layer. The barrier metal layer is, for example, a titanium layer or a titanium nitride layer.

[0033] The gate line 22 is formed of, for example, the same material as the source electrode 12 .

[0034] The thickness (t2 in FIG. 5) of the gate wiring 22 is, for example, 1 μm or more and 10 μm or less. The width (w2 in FIG. 4) of the gate wiring 22 in the first direction is, for example, 1 μm or more and 20 μm or less.

[0035] A first distance (d1 in FIG. 4) in a first direction between the source electrode 12 and the gate line 22 is, for example, not less than 1 μm and not more than 10 μm.

[0036] The gate pad 24 is provided in the termination region 102. The gate pad 24 is provided on the interlayer insulating layer 20. The gate pad 24 is provided on the semiconductor layer 10.

[0037] The gate pad 24 is connected to the gate wiring 22. The gate pad 24 has a function of applying a gate voltage to the gate electrode 18 via the gate wiring 22. To the gate pad 24, for example, a bonding wire is connected.

[0038] The gate pad 24 includes aluminum (Al). The gate pad 24 is, for example, an aluminum layer. The gate pad 24 may have a laminated structure of a barrier metal layer and an aluminum layer. The barrier metal layer is, for example, a titanium layer or a titanium nitride layer.

[0039] The gate pad 24 is formed of, for example, the same material as the source electrode 12 and the gate line 22 .

[0040] The first protective insulating layer 26 is provided on the interlayer insulating layer 20. The first protective insulating layer 26 is provided on the second protective insulating layer 28. The first protective insulating layer 26 is provided between the source electrode 12 and the gate line 22.

[0041] The first protective insulating layer 26 has a function of suppressing the intrusion of moisture and mobile ions into the element region 101. By providing the first protective insulating layer 26, fluctuations in the characteristics of the MOSFET 100 are suppressed, and the reliability of the MOSFET 100 is improved.

[0042] The first protective insulating layer 26 includes silicon (Si) and nitrogen (N). The first protective insulating layer 26 includes, for example, silicon nitride. The first protective insulating layer 26 is, for example, a silicon nitride layer.

[0043] The first protective insulating layer 26 includes, for example, silicon (Si), nitrogen (N), and oxygen (O). The first protective insulating layer 26 includes, for example, silicon oxynitride. The first protective insulating layer 26 is, for example, a silicon oxynitride layer.

[0044] The thickness of the first protective insulating layer 26 (t3 in FIG. 5) is, for example, not less than 0.1 μm and not more than 2 μm.

[0045] The upper surface of the first protective insulating layer 26 is in contact with the side surface of the source electrode 12. The first protective insulating layer 26 is not in contact with the upper surface of the source electrode 12. The first protective insulating layer 26 is not provided on the source electrode 12.

[0046] A second distance (d2 in FIG. 5) from the surface of the semiconductor layer 10 to a position where the upper surface of the first protective insulating layer 26 contacts the side surface of the source electrode 12 is smaller than a third distance (d3 in FIG. 5) from the surface of the semiconductor layer 10 to the upper surface of the source electrode 12. The difference (s1 in FIG. 5) between the third distance d3 and the second distance d2 is, for example, not less than 0.1 μm and not more than 1 μm.

[0047] The upper surface of the first protective insulating layer 26 contacts the side surface of the gate line 22. The first protective insulating layer 26 does not contact the upper surface of the gate line 22. The first protective insulating layer 26 is not provided on the gate line 22.

[0048] A fourth distance (d4 in FIG. 5) from the surface of the semiconductor layer 10 to a position where the upper surface of the first protective insulating layer 26 contacts the side surface of the gate wiring 22 is smaller than a fifth distance (d5 in FIG. 5) from the surface of the semiconductor layer 10 to the upper surface of the gate wiring 22. The difference (s2 in FIG. 5) between the fifth distance d5 and the fourth distance d4 is, for example, not less than 0.1 μm and not more than 1 μm.

[0049] The second protective insulating layer is provided on the interlayer insulating layer 20. The second protective insulating layer is provided between the interlayer insulating layer 20 and the first protective insulating layer .

[0050] The second protective insulating layer 28 includes, for example, silicon (Si) and oxygen (O). The second protective insulating layer 28 includes, for example, silicon oxide. The second protective insulating layer 28 is, for example, a silicon oxide layer.

[0051] The thickness (t4 in FIG. 5) of the second protective insulating layer 28 is, for example, not less than 0.1 μm and not more than 2 μm.

[0052] The thickness t3 of the first protective insulating layer 26 is, for example, smaller than the thickness t4 of the second protective insulating layer 28.

[0053] The second protective insulating layer 28 contacts a side surface of the source electrode 12. The second protective insulating layer 28 contacts a side surface of the gate line 22.

[0054] The polyimide layer 30 is provided on the source electrode 12. The polyimide layer 30 is provided on the gate line 22. The polyimide layer 30 is provided on the first protective insulating layer .

[0055] The polyimide layer 30 contacts the upper surface and side surfaces of the source electrode 12. The polyimide layer 30 covers the corners of the upper surface and side surfaces of the source electrode 12.

[0056] The polyimide layer 30 is in contact with the upper surface and side surfaces of the gate line 22. The polyimide layer 30 covers the corners of the upper surface and side surfaces of the gate line 22.

[0057] The thickness of the polyimide layer 30 is, for example, not less than 3 μm and not more than 10 μm.

[0058] Next, an example of a method for manufacturing the semiconductor device of the embodiment will be described, in particular, a method for forming the first protective insulating layer 26 and the second protective insulating layer 28 will be described.

[0059] 6, 7, 8, 9, 10, and 11 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment. 6 to 11 are cross-sectional views corresponding to FIG.

[0060] Using a known process technology, an interlayer insulating layer 20 is formed on the semiconductor layer 10. Next, using a known process technology, a source electrode 12 and a gate wiring 22 are formed on the interlayer insulating layer 20 (FIG. 6).

[0061] Next, the silicon oxide film 50 is formed (FIG. 7). The silicon oxide film 50 is formed so as to fill the gap between the source electrode 12 and the gate wiring 22. The silicon oxide film 50 is formed by, for example, a chemical vapor deposition method (CVD method).

[0062] Next, the silicon oxide film 50 on the source electrode 12 and on the gate wiring 22 is removed (FIG. 8). The upper surface of the source electrode 12 and the upper surface of the gate wiring 22 are exposed. The silicon oxide film 50 is removed by, for example, a reactive ion etching method (RIE method). The processed silicon oxide film 50 is an example of the second protective insulating layer 28.

[0063] Next, a silicon nitride film 52 is formed (FIG. 9). The silicon nitride film 52 is formed so as to fill the space between the source electrode 12 and the gate wiring 22. The silicon nitride film 52 is formed by, for example, a CVD method.

[0064] Next, the silicon nitride film 52 on the source electrode 12 and on the gate wiring 22 is removed (FIG. 10). The upper surface of the source electrode 12 and the upper surface of the gate wiring 22 are exposed. The silicon nitride film 52 is removed by, for example, the RIE method. The processed silicon nitride film 52 is an example of the first protective insulating layer 26.

[0065] Next, a polyimide film 54 is formed (FIG. 11). After that, a part of the polyimide film 54 on the source electrode 12 is removed. The polyimide film 54 is removed by, for example, wet etching. The processed polyimide film 54 is an example of the polyimide layer 30.

[0066] By the above-described manufacturing method, the semiconductor device according to the embodiment is manufactured.

[0067] Next, the operation and effects of the semiconductor device of the embodiment will be described.

[0068] 12 is a schematic cross-sectional view of a semiconductor device of a comparative example. The semiconductor device of the comparative example is a MOSFET 900. The MOSFET 900 is a planar gate vertical MOSFET for high voltage applications, similar to the MOSFET 100 of the embodiment.

[0069] The MOSFET 900 of the comparative example differs from the MOSFET 100 of the embodiment in that the first protective insulating layer 26 and the second protective insulating layer 28 are provided on the source electrode 12. The MOSFET 900 of the comparative example also differs from the MOSFET 100 of the embodiment in that the first protective insulating layer 26 and the second protective insulating layer 28 are provided on the gate wiring 22.

[0070] In the MOSFET 900, the first protective insulating layer 26 contacts the upper surface and side surfaces of the source electrode 12. The first protective insulating layer 26 and the second protective insulating layer 28 cover the upper surface and corners of the side surfaces of the source electrode 12.

[0071] In the MOSFET 900, the second protective insulating layer 28 contacts the upper surface and side surfaces of the gate wiring 22. The first protective insulating layer 26 and the second protective insulating layer 28 cover the upper surface and corners of the side surfaces of the gate wiring 22.

[0072] 13 is an explanatory diagram of a problem with the semiconductor device of the comparative example. For example, the MOSFET 900 undergoes temperature changes during use. The temperature changes cause stress due to differences in the thermal expansion coefficients of the materials that make up the MOSFET 900.

[0073] 13, at the corners of the metal gate wiring 22, the stress applied to the first protective insulating layer 26 and the second protective insulating layer 28, which are insulating materials, increases due to the effect of the shape. Therefore, for example, as shown in FIG. 13, cracks 60 occur in the first protective insulating layer 26 and the second protective insulating layer 28.

[0074] In particular, if a crack occurs in the first protective insulating layer 26 made of silicon nitride or silicon oxynitride, the intrusion of moisture and mobile ions from the outside is promoted, and the reliability of the MOSFET 900 is reduced.

[0075] Power semiconductor devices such as the MOSFET 900 are often used in hotter and more humid environments than logic devices and memory devices, for example. In addition, the voltage applied to the device is also high. Therefore, in the power semiconductor device, cracks are likely to occur in the protective insulating layer, and there is a great concern about a decrease in reliability when cracks occur in the protective insulating layer.

[0076] In the MOSFET 100 of the embodiment, the first protective insulating layer 26 and the second protective insulating layer 28 do not cover the corners of the upper surface and side surface of the source electrode 12. In addition, in the MOSFET 100, the first protective insulating layer 26 and the second protective insulating layer 28 do not cover the corners of the upper surface and side surface of the gate wiring 22.

[0077] This suppresses the occurrence of cracks at the corners of the source electrode 12 and the corners of the gate wiring 22. This suppresses the intrusion of moisture and mobile ions from the outside, thereby improving the reliability of the MOSFET 100.

[0078] The thickness t3 of the first protective insulating layer 26 is preferably thinner than the thickness t4 of the second protective insulating layer 28. The stress generated by the first protective insulating layer 26 containing nitrogen (N) is greater than, for example, the stress generated by the second protective insulating layer 28 not containing nitrogen (N). By reducing the thickness t3 of the first protective insulating layer 26, for example, the occurrence of stress migration in the gate wiring 22 is suppressed.

[0079] It is preferable that the first protective insulating layer 26 is a silicon nitride layer. By using a silicon nitride layer for the first protective insulating layer 26, the intrusion of moisture and mobile ions from the outside can be effectively suppressed.

[0080] The difference between the third distance d3 and the second distance d2 (s1 in FIG. 5) is preferably 1 μm or less. The difference between the fifth distance d5 and the fourth distance d4 (s2 in FIG. 5) is preferably 1 μm or less. For example, by setting the difference s1 and the difference s2 within the above range, the occurrence of cracks in the polyimide layer 30 at the corners of the source electrode 12 and the gate wiring 22 is suppressed.

[0081] (First Modification) Fig. 14 is a schematic cross-sectional view of a first modified example of the semiconductor device of the embodiment. Fig. 14 is a view corresponding to Fig. 5 of the embodiment. The MOSFET of the first modified example differs from the MOSFET 100 of the embodiment in that it does not include the polyimide layer 30. The MOSFET of the first modified example also has improved reliability due to the same action as the MOSFET 100 of the embodiment.

[0082] (Second Modification) Fig. 15 is a schematic cross-sectional view of a second modified example of the semiconductor device of the embodiment. Fig. 15 is a view corresponding to Fig. 5 of the embodiment. The MOSFET of the second modified example differs from the MOSFET 100 of the embodiment in that it does not include the second protective insulating layer 28. The MOSFET of the second modified example also has improved reliability due to the same action as the MOSFET 100 of the embodiment. In addition, by thickening the first protective insulating layer 26, the intrusion of moisture and mobile ions from the outside is effectively suppressed.

[0083] (Third Modification) FIG. 16 is a schematic cross-sectional view of a third modified example of the semiconductor device of the embodiment. FIG. 16 is a view corresponding to FIG. 5 of the embodiment. The MOSFET of the third modified example differs from the MOSFET of the second modified example in that the thickness (t5 in FIG. 16) of the portion of the first protective insulating layer 26 in contact with the source electrode 12 is thinner than the thickness (t7 in FIG. 16) of the first protective insulating layer 26 at the intermediate position between the source electrode 12 and the gate wiring 22. The MOSFET of the third modified example differs from the MOSFET of the second modified example in that the thickness (t6 in FIG. 16) of the portion of the first protective insulating layer 26 in contact with the gate wiring 22 is thinner than the thickness (t7 in FIG. 16) of the first protective insulating layer 26 at the intermediate position between the source electrode 12 and the gate wiring 22. The MOSFET of the third modified example differs from the MOSFET of the second modified example in that a second protective insulating layer 28 is provided on the side of the source electrode 12 and the side of the gate wiring 22.

[0084] The reliability of the MOSFET of the third modified example is improved by the same action as that of the MOSFET 100 of the embodiment. In addition, the thickness t5 of the portion of the first protective insulating layer 26 in contact with the source electrode 12 and the thickness t6 of the portion of the first protective insulating layer 26 in contact with the gate wiring 22 are reduced, thereby suppressing the occurrence of, for example, stress migration.

[0085] As described above, according to the embodiment and its modified examples, it is possible to provide a semiconductor device in which the occurrence of cracks in the protective insulating layer is suppressed and the reliability can be improved.

[0086] In the embodiment, the semiconductor layer is made of silicon, but the semiconductor layer is not limited to silicon. For example, the semiconductor layer may be made of silicon carbide or a nitride semiconductor.

[0087] In the embodiment, a planar gate type vertical MOSFET has been described as an example, but the present invention can also be applied to a trench gate type vertical MOSFET, for example. The present invention can also be applied to a lateral MOSFET. The present invention can also be applied to a semiconductor device other than a MOSFET. For example, the present invention can also be applied to an Insulated Gate Bipolar Transistor (IGBT), a diode, or a photocoupler.

[0088] In the embodiment, the resin layer is formed of polyimide, but the resin layer may be formed of other resins such as silicone.

[0089] In the embodiment, an example has been described in which the first metal layer is a source electrode and the second metal layer is a gate wiring, but the first metal layer is not limited to a source electrode and the second metal layer is not limited to a gate wiring.

[0090] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0091] 10 Semiconductor layer 12 Source electrode (first metal layer) 14 Drain electrode (third metal layer) 16 Gate insulating layer 20 Interlayer insulating layer (first insulating layer) 22 Gate wiring (second metal layer) 26 First protective insulating layer (second insulating layer) 28 Second protective insulating layer (third insulating layer) 30 Polyimide layer (resin layer) 100 MOSFET (semiconductor device)

Claims

1. A semiconductor layer; a first insulating layer provided on the semiconductor layer; a first metal layer provided on the first insulating layer and including aluminum (Al); a second metal layer including aluminum (Al) provided on the first insulating layer; a second insulating layer provided on the first insulating layer, between the first metal layer and the second metal layer, the upper surface of the second insulating layer being in contact with a side surface of the first metal layer and the upper surface of the second insulating layer being in contact with a side surface of the second metal layer, the second insulating layer including silicon (Si) and nitrogen (N); a gate electrode provided between the semiconductor layer and the first insulating layer; a resin layer provided on the first metal layer, the second metal layer, and the first insulating layer; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, further comprising: a third insulating layer provided between the first insulating layer and the second insulating layer, and between the first metal layer and the second metal layer, the third insulating layer containing silicon (Si) and oxygen (O).

3. 3. The semiconductor device according to claim 2, wherein the second insulating layer is thinner than the third insulating layer.

4. 3. The semiconductor device according to claim 2, wherein a thickness of the portion of the second insulating layer in contact with the first metal layer is thinner than a thickness of the second insulating layer at a midpoint between the first metal layer and the second metal layer.

5. 5. The semiconductor device according to claim 1, wherein the second insulating layer contains oxygen (O).

6. 6. The semiconductor device according to claim 1, wherein the distance between the first metal layer and the second metal layer is not less than 1 [mu]m and not more than 10 [mu]m.

7. 7. The semiconductor device according to claim 1, wherein the first metal layer and the second metal layer have a thickness of 1 [mu]m or more and 10 [mu]m or less.

8. 8. The semiconductor device according to claim 1, further comprising a third metal layer, the third metal layer being provided with the semiconductor layer between the first metal layer and the third metal layer.

9. A semiconductor layer; a first insulating layer provided on the semiconductor layer; a first metal layer provided on the first insulating layer and including aluminum (Al); a second metal layer including aluminum (Al) provided on the first insulating layer; a second insulating layer provided on the first insulating layer, between the first metal layer and the second metal layer, the upper surface of the second insulating layer being in contact with a side surface of the first metal layer and the upper surface of the second insulating layer being in contact with a side surface of the second metal layer, the second insulating layer including silicon (Si) and nitrogen (N); a third insulating layer provided between the first insulating layer and the second insulating layer, and between the first metal layer and the second metal layer, the third insulating layer containing silicon (Si) and oxygen (O); Equipped with A semiconductor device, wherein a thickness of the portion of the second insulating layer in contact with the first metal layer is thinner than a thickness of the second insulating layer at a midpoint between the first metal layer and the second metal layer.

10. The semiconductor device according to claim 9 , further comprising a resin layer provided on the first metal layer, the second metal layer, and the first insulating layer.

11. 11. The semiconductor device according to claim 9, wherein the second insulating layer contains oxygen (O).

12. 12. The semiconductor device according to claim 9, wherein a distance between the first metal layer and the second metal layer is not less than 1 [mu]m and not more than 10 [mu]m.

13. 13. The semiconductor device according to claim 9, wherein the first metal layer and the second metal layer have a thickness of 1 [mu]m or more and 10 [mu]m or less.

14. 14. The semiconductor device according to claim 9, further comprising a third metal layer between the first metal layer and the semiconductor layer.

Images