Semiconductor Device

Abstract

To provide a semiconductor device with improved reliability.SOLUTION: A semiconductor device includes: a leadframe; a first bonding material provided on the leadframe; a semiconductor chip provided on the first bonding material, the semiconductor chip including a lower surface, an upper surface, a first electrode provided on the lower surface and connected to the first bonding material, a second electrode provided on the upper surface, and a plurality of electrode pads connected to the second electrode; a plurality of second bonding materials respectively provided on the plurality of electrode pads; and a first connector connected to at least one of the plurality of second bonding materials. The second bonding material which is not connected to the first connector is not connected to a connector or a wire.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices having semiconductor chips such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used for applications such as power conversion. For example, when the above-mentioned semiconductor device is a vertical MOSFET, a source electrode provided on the upper surface of the semiconductor chip is connected to, for example, a connector provided on the MOSFET. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-035913 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device with improved reliability. [Means for solving the problem]

[0005] The semiconductor device of the embodiment has a lead frame, a first bonding material provided on the lead frame, a lower surface, an upper surface, a first electrode provided on the lower surface and connected to the first bonding material, a second electrode provided on the upper surface, and a plurality of electrode pads connected to the second electrode, and is equipped with a semiconductor chip provided on the first bonding material, a plurality of second bonding materials respectively provided on the plurality of electrode pads, and a first connector connected to at least one of the plurality of second bonding materials, and the second bonding material not connected to the first connector is not connected to a connector or a wire. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic top view of a semiconductor device according to a first embodiment; [Diagram 2] 1 is a schematic cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Diagram 3] FIG. 2 is a schematic diagram of the AA′ cross section in FIG. [Figure 4] FIG. 4 is a schematic top view of a semiconductor device according to another aspect of the first embodiment. [Diagram 5] FIG. 2 is a schematic top view of a semiconductor device according to a first comparative example of the first embodiment. [Figure 6] FIG. 6 is a schematic diagram of a cross section taken along line AA' in FIG. [Figure 7] 11 is a schematic top view of a semiconductor device according to a second comparative example of the first embodiment. FIG. [Figure 8] 3A to 3C are schematic diagrams showing the effects of the semiconductor device according to the first embodiment; [Figure 9] FIG. 11 is a schematic top view of a semiconductor device according to a second embodiment. [Figure 10] FIG. 11 is a schematic cross-sectional view of a main part of a semiconductor device according to a second embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view of a main part of a semiconductor device according to a second embodiment. [Figure 12] FIG. 13 is a schematic top view of a semiconductor device according to a third embodiment. [Figure 13] FIG. 13 is a schematic top view of a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 13 is a schematic top view of a semiconductor device according to a fifth embodiment. [Figure 15] FIG. 13 is a schematic top view of a semiconductor device according to a sixth embodiment. [Figure 16] FIG. 13 is a schematic top view of a semiconductor device according to a seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same members are designated by the same reference numerals, and the description of members that have already been described will be omitted as appropriate.

[0008] In this specification, in order to indicate the positional relationship of parts, etc., the upward direction of the drawing is described as "upper" and the downward direction of the drawing is described as "lower." In this specification, the concepts of "upper" and "lower" are not necessarily terms that indicate a relationship with the direction of gravity.

[0009] In the following, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type.

[0010] In the following description, n + , n, n - and p + , p, p - The notation indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The types are simply n-type and p-type. + type, p - The type is sometimes simply referred to as p-type.

[0011] (First embodiment) The semiconductor device of this embodiment has a lead frame, a first bonding material provided on the lead frame, a lower surface, an upper surface, a first electrode provided on the lower surface and connected to the first bonding material, a second electrode provided on the upper surface, and a plurality of electrode pads connected to the second electrode, and is equipped with a semiconductor chip provided on the first bonding material, a plurality of second bonding materials respectively provided on the plurality of electrode pads, and a first connector connected to at least one of the plurality of second bonding materials, and the second bonding material not connected to the first connector is not connected to a connector or a wire.

[0012] In addition, the semiconductor device of this embodiment has a lead frame, a first bonding material provided on the lead frame, a lower surface, an upper surface, a first electrode provided on the lower surface and connected to the first bonding material, a second electrode provided on the upper surface, and a plurality of electrode pads connected to the second electrode, and is equipped with a semiconductor chip provided on the first bonding material, a plurality of second bonding materials respectively provided on the plurality of electrode pads, a first connector connected to at least one of the plurality of second bonding materials, and a sealing resin provided on the second bonding material that is not electrically connected to the first connector.

[0013] FIG. 1 is a schematic top view of the semiconductor device 100 of this embodiment. FIG. 2 is a schematic cross-sectional view of a main part of the semiconductor device 100 of this embodiment. FIG. 2 is a schematic view of the A-A' cross section in FIG. 1. FIG. 3 is a schematic view of the A-A' cross section in FIG. 1. FIG. 3(a) is a schematic view of the A-A' cross section in the vicinity of the second bonding material 20a. FIG. 3(b) is a schematic view of the A-A' cross section in the vicinity of the second bonding material 20b. In FIGS. 3(a) and 3(b), the sealing resin 82 is also shown. Note that the sealing resin 82 is not shown in FIGS. 1 and 2.

[0014] A semiconductor device 100 according to the present embodiment will be described with reference to FIGS. 1, 2 and 3. FIG.

[0015] The lead frame 2 is a member containing a conductive material such as Cu (copper) on which the semiconductor chip 10 is arranged. The lead frame 2 has a first bed portion 3 and a first outer lead 6. The first bed portion 3 has a first bed surface 4. The semiconductor chip 10 is provided on the first bed surface 4. The first outer lead 6 is connected to the first bed portion 3. The first outer lead 6 is used to connect the semiconductor chip 10 to an external circuit (not shown).

[0016] The first bonding material 70 is provided between the first bed surface 4 of the lead frame 2 and the semiconductor chip 10. The first bonding material 70 is provided on the first bed surface 4 of the lead frame 2. The first bonding material 70 bonds the first bed surface 4 to the drain electrode (an example of a first electrode) 11 of the semiconductor chip 10. For example, when a MOSFET is provided on the semiconductor chip 10, the first bonding material 70 connects the drain electrode 11 of the semiconductor chip 10 to the first bed surface 4.

[0017] The semiconductor chip 10 is provided on a first bonding material 70. The semiconductor chip 10 has a lower surface 10a and an upper surface 10b. The semiconductor chip 10 also has a drain electrode 11 provided on the lower surface 10a, a source electrode (an example of a second electrode) 16 provided on the upper surface 10b, a plurality of electrode pads 17 provided on the source electrode 16, and a third insulating film 12 provided on the source electrode 16. The semiconductor chip 10 is provided with a vertical MOSFET, an IGBT (Insulated Gate Bipolar Transistor), or the like on a semiconductor substrate such as Si (silicon), SiC (silicon carbide), GaAs (gallium arsenide), or GaN (gallium nitride).

[0018] Here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X direction and the Y direction are defined. The first bed surface 4, the lower surface 10a, and the upper surface 10b are arranged parallel to the XY plane.

[0019] For example, when a MOSFET is provided on the semiconductor chip 10, the source electrode 16 corresponds to the source electrode of the MOSFET. The source electrode 16 includes, for example, Al (aluminum).

[0020] The third insulating film 12 is provided on the source electrode 16 of the semiconductor chip 10. The third insulating film 12 is provided, for example, on an end of the semiconductor chip 10 and on an end of the source electrode 16. The third insulating film 12 has an opening 13a and an opening 13b on the source electrode 16. The opening 13a and the opening 13b penetrate the third insulating film 12. The third insulating film 12 includes an insulating material such as polyimide. The number of openings 13 is not limited to that shown in this embodiment.

[0021] The electrode pads 17 are provided on the source electrode 16 in the opening 13. The electrode pads 17 are connected to the source electrode 16. The electrode pad 17a is provided on the source electrode 16 in the opening 13a. The electrode pad 17b is provided on the source electrode 16 in the opening 13b. The number of the electrode pads 17 is not limited to that shown in the present embodiment. The electrode pad 17 has, for example, a first layer 14 containing Ni (nickel) and a second layer 15 provided on the first layer and containing Au (gold). The configuration of the electrode pad 17 is not limited to the above. For example, the electrode pad 17 may contain an alloy of Ni and Au. Also, for example, the electrode pad 17 may have a layer containing Ni, a layer containing Pd (palladium) provided on the layer containing Ni, and a layer containing Au provided on the layer containing Pd. Also, the electrode pad 17 may contain, for example, Cu. The electrode pad 17 may have a layer containing Cu, for example. The electrode pad 17 is provided to increase the bonding strength between the source electrode 16 and the second bonding material 20, for example.

[0022] The multiple second bonding materials 20 are provided on the multiple electrode pads 17, respectively. The second bonding material 20a is provided on the electrode pad 17a. The second bonding material 20b is provided on the electrode pad 17b.

[0023] The first connector 50 has a first end 51a and a second end 51b. The first connector 50 includes a conductive material such as Cu. The surface of the first connector 50 may be plated with a material including Sn. The first end 51a is provided on the second bonding material 20a in the opening 13 and is connected to the second bonding material 20a. As a result, the first connector 50 is electrically connected to the electrode pad 17a through the second bonding material 20a. On the other hand, the first connector 50 is not connected to the second bonding material 20b. The first connector 50 is not connected to the electrode pad 17b through the second bonding material 20b. The second end 51b is provided on the second bed portion 58 and is connected to the second bed portion 58 using a third bonding material 59. The first connector 50 is provided extending in the Y direction across the first post portion 54 to which the second end 51b is connected and the lead frame 2. Even when a wire is used to connect the electrode pad 17a and the second bed portion 58 instead of the first connector 50, the wire is not connected to the second bonding material 20b. Moreover, the wire is not connected to the electrode pad 17a via the second bonding material 20b.

[0024] The sealing resin 82 is provided on the third insulating film 12 and the second bonding material 20 so as to cover at least the third insulating film 12, the electrode pad 17, and the second bonding material 20. Here, as shown in FIG. 3(a), the sealing resin 82 is provided around the second bonding material 20a so as to cover the second bonding material 20a and the periphery of the first end 51a of the first connector 50. On the other hand, as shown in FIG. 3(b), the sealing resin 82 is provided around the second bonding material 20b so as to cover the second bonding material 20b. In this case, the entire upper surface of the second bonding member 20b is in direct contact with the sealing resin 82. The sealing resin 82 includes a resin such as an epoxy resin. Furthermore, the sealing resin 82 may include a filler such as silica or alumina.

[0025] The first post portion 54 includes a second bed portion 58 and a second outer lead 56. The first post portion 54 includes a conductive material such as Cu. The second outer lead 56 is used to connect the semiconductor chip 10 to an external circuit (not shown).

[0026] The second post portion 64 includes a second bed portion 68 and a third outer lead 66. The second post portion 64 includes a conductive material such as Cu. The third outer lead 66 is used to connect the semiconductor chip 10 to an external circuit (not shown).

[0027] The third bonding material 59 is provided between the second bed portion 58 and the second end portion 51b. The third bonding material 59 connects the second bed portion 58 and the second end portion 51b.

[0028] The third connector 60 has a third end 61a and a fourth end 61b. The third connector 60 includes a conductive material such as Cu. The surface of the third connector 60 may be plated with a material including Sn. The third end 61a is electrically connected to the semiconductor chip 10 via a fourth bonding material 80 provided on the semiconductor chip 10. The fourth bonding material 80 is electrically connected to a gate electrode of a MOSFET, for example.

[0029] It should be noted that the first connector 50 and the third connector 60 are hard connectors that cannot be easily bent, and are different from wires used for bonding.

[0030] The fifth bonding material 69 is provided between the second bed portion 68 and the fourth end portion 61b. The fifth bonding material 69 connects the second bed portion 68 and the fourth end portion 61b.

[0031] 4 is a schematic top view of a semiconductor device 105 according to another aspect of the present embodiment. A wire 62 is used instead of the third connector 60. A wire 62 may be used instead of the third connector 60. An end 63a of the wire 62 is connected to a fourth bonding material 80. An end 63b of the wire 62 is connected to a fifth bonding material 69.

[0032] As the first bonding material 70, the second bonding material 20, the third bonding material 59, the fourth bonding material 80 and the fifth bonding material 69, for example, a solder containing Pb (lead) and Sn (tin), a solder containing Pb, Ag (silver) and Sn (tin), a solder containing Sn and Sb (antimony), a solder containing Au (gold) and Sn, a solder containing Au and Si, or a solder containing Au and Ge (germanium), Ag paste, ultrasonic solder, etc. can be preferably used.

[0033] Next, the effects of the semiconductor device of this embodiment will be described.

[0034] 5 is a schematic top view of a semiconductor device 1000 as a first comparative example of the present embodiment. The number of openings 13 and the number of second bonding materials 20 are one. The number of electrode pads 17 not shown in FIG. 5 is also one. The area of ​​the openings 13, the area of ​​the second bonding material 20, and the area of ​​the electrode pads 17 in the XY plane are each larger than those in the semiconductor device 100.

[0035] The semiconductor chip 10 itself tends to warp due to the internal stress of the semiconductor chip when the Z direction is upward, for example. On the other hand, particularly when the electrode pad 17 contains Ni, the tensile stress of Ni cancels out the internal stress of the semiconductor chip, thereby suppressing warping of the semiconductor chip and the wafer. In this way, problems with the transportation of the semiconductor chip and the wafer are prevented. For example, when the electrode pad 17 contains Cu, problems with the transportation of the semiconductor chip and the wafer can be similarly prevented.

[0036] In order to reduce the on-resistance of the semiconductor device as much as possible, the semiconductor device 1000 uses a connector 500 having a larger volume than the connector 50 used in the semiconductor device 100. The connector 500 has an end 510a connected to the second bonding material 20 and an end 510b connected to the third bonding material 59.

[0037] 6 is a schematic diagram of a cross section of a semiconductor device 1000 taken along line A-A' as a first comparative example of this embodiment. The arrows shown on the lead frame 2, the semiconductor chip 10, and the connector 500 indicate the thermal expansion of the semiconductor device 1000 when the temperature is increased due to a reliability evaluation such as a temperature cycle test.

[0038] In general, the thermal expansion coefficient of the Cu or the like used for the lead frame 2 and the connector 500 is larger than that of the Si or other semiconductor material used for the semiconductor chip 10. Therefore, when the temperature of the semiconductor device 1000 rises, the semiconductor chip 10 is strongly stretched in the XY plane. Therefore, when reliability evaluation such as a temperature cycle test is performed, cracks are generated in the semiconductor chip 10, and high reliability may not be achieved.

[0039] 7 is a schematic top view of a semiconductor device 1100 as a second comparative embodiment of the present embodiment. The number of openings 13 and the number of second bonding materials 20 are one. The number of electrode pads 17 not shown in FIG. 5 is also one. The area of ​​the openings 13, the area of ​​the second bonding material 20, and the area of ​​the electrode pads 17 in the XY plane are each smaller than those of the semiconductor device 1100.

[0040] In order to achieve high reliability, the volume of the connector 50 is made smaller than the volume of the connector 500 of the semiconductor device 1100 shown in Figs. 5 and 6. This prevents the semiconductor chip 10 from being strongly stretched in the XY plane when the temperature of the semiconductor chip 10 rises. However, in this case, the area of ​​the electrode pads 17 is smaller due to the use of the connector 50 having a small volume. Therefore, the tensile stress of the electrode pads 17 is reduced, and it may not be possible to suppress warpage of the semiconductor chip or wafer. This may cause a problem that the semiconductor chip and wafer cannot be transported.

[0041] Therefore, the semiconductor device 100 of the present embodiment includes a first connector 50 electrically connected to at least one of the plurality of electrode pads 17.

[0042] 8 is a schematic diagram showing the function and effect of the semiconductor device 100 of this embodiment. The arrows shown on the lead frame 2, the semiconductor chip 10, and the connector 50 typically indicate thermal expansion of the semiconductor device 100 due to a rise in temperature.

[0043] By reducing the volume of the first connector 50, the amount of thermal expansion of the first connector 50 can be reduced. As a result, the semiconductor chip 10 is less likely to break (crack). Furthermore, by providing the second bonding material 20b that is not connected to the first connector 50 or the wire, warping due to internal stress in the semiconductor chip or wafer state can be counteracted by the tensile stress of the electrode pad 17b provided under the second bonding material 20b. Therefore, warping in the semiconductor chip or wafer state can be suppressed. This makes it possible to prevent problems in transporting the semiconductor chip and wafer. Therefore, it is possible to provide a semiconductor device 100 with improved reliability.

[0044] The second bonding material 20b that is not electrically connected to the first connector 50 is covered with the sealing resin 82. Alternatively, the second bonding material 20b that is not electrically connected to the first connector 50 is not connected to a connector or a wire.

[0045] According to the semiconductor device 100 of this embodiment, it is possible to provide a semiconductor device 100 with improved reliability.

[0046] Second embodiment The semiconductor device of this embodiment differs from the semiconductor device of the first embodiment in that the semiconductor chip further includes a first semiconductor layer of a first conductivity type provided on the first electrode, a first semiconductor region of a second conductivity type provided on the first semiconductor layer, a second semiconductor region of the first conductivity type provided on the first semiconductor region, a second electrode provided on the second semiconductor region and electrically connected to the second semiconductor region, and a third electrode provided in a first trench extending from above the first semiconductor region to the first semiconductor layer through the first semiconductor layer and a first insulating film, the first trench extending in a first direction parallel to the upper surface, and an electrode pad provided on the first trench and not electrically connected to the first connector through a second bonding material extending in a second direction parallel to the upper surface and intersecting the first direction. Here, description of contents that overlap with the semiconductor device of the first embodiment will be omitted.

[0047] FIG. 9 is a schematic top view of a semiconductor device 110 of the present embodiment.

[0048] 9, the second bonding material 20 is omitted, and only the electrode pad 17 provided below the second bonding material 20 is shown. The same applies to the figures from FIG. 10 onwards.

[0049] The first end 51a of the first connector 50 is connected to the electrode pad 17a1 and the electrode pad 17a2 via the second bonding material 20. Note that the first end 51a may be connected to one electrode pad.

[0050] Furthermore, a plurality of electrode pads 17b are provided on the semiconductor device 110. Each of the electrode pads 17b extends in the X direction.

[0051] 10 is a schematic cross-sectional view of a main part of a semiconductor device 110 of this embodiment. A trench-type MOSFET is provided in a semiconductor chip 10 of the semiconductor device 110. Note that, for example, a trench-type IGBT may also be provided in the semiconductor chip 10.

[0052] The drain electrode 11 functions as the drain electrode of the MOSFET.

[0053] The drain layer 109 is provided on the drain electrode 11. The drain layer 109 is, for example, + The present invention includes semiconductor materials of the type.

[0054] The drift layer (an example of a first semiconductor layer) 112 is provided on the drain layer 109. The drift layer 112 is a layer that functions as a drift layer of a MOSFET. The drift layer 112 is, for example, - The present invention includes semiconductor materials of the type.

[0055] A base region (an example of a first semiconductor region) 114 is provided on the drift layer 112. The base region 114 functions as a base of the MOSFET. The base region 114 is a region that forms a channel when a voltage is applied to a gate electrode 128 (described later) and allows carriers to flow between the drain layer 109 and a source region 116 (described later). The base region 114 includes, for example, a p-type semiconductor material.

[0056] A source region (an example of a second semiconductor region) 116 is provided on the base region 114. The source region 116 is a region that functions as a source of the MOSFET. When an appropriate voltage is applied to a gate electrode 128, which will be described later, carriers flow between the source region 116 and the drain layer 109. The source region 116 is, for example, an n + The present invention includes semiconductor materials of the type.

[0057] The contact region 118 is provided on the base region 114 and is electrically connected to the base region 114 and the source region 116. The contact region 118 is provided to improve electrical contact between the base region 114 and the source region 116 and the source electrode 16. The contact region 118 is, for example, a p + The present invention includes semiconductor materials of the type.

[0058] The trench 119 is provided so as to reach the drift layer 112 from above the base region 114 and the source region 116. The trench 119 extends in the direction into the page (Y direction, an example of a first direction). In other words, the trench 119 extends in the Y direction perpendicularly intersecting the direction in which the electrode pad 17b extends (X direction, an example of a second direction).

[0059] The first insulating film 122 is provided in the trench 119. For example, the first insulating film 122 is provided so as to cover a field plate electrode 124 described below. The first insulating film 122 is a field plate insulating film. Also, for example, the first insulating film 122 is provided between the field plate electrode 124 and the gate electrode 128. However, the form of the first insulating film 122 is not limited to this. The first insulating film 122 is made of SiO x (silicon oxide), but is not limited to this.

[0060] The fifth insulating film 121 is provided in the trench 119 on the first insulating film 122 between the base region 114 and the gate electrode 128 and between an interlayer insulating film 195 (to be described later) and the source region 116. The fifth insulating film 121 is a gate insulating film. The fifth insulating film 121 is made of SiO x (silicon oxide), but is not limited to this.

[0061] A field plate electrode (an example of a third electrode) 124 is provided in the trench 119 on the drift layer 112 via a first insulating film 122, facing the drift layer 112. For example, the field plate electrode 124 is provided alongside the drift layer 112. The field plate electrode 124 extends in the Y direction, similar to the trench 119. The field plate electrode 124 is provided, for example, to promote the extension of a depletion layer from the base region 114 to the drift layer 112 and increase the breakdown voltage.

[0062] The gate electrode 128 is provided on the field plate electrode 124. The gate electrode 128 is provided between the multiple base regions 114 with the fifth insulating film 121 interposed therebetween. The gate electrode 128 extends in the Y direction. The gate electrode 128 is an electrode that functions as a gate of the MOSFET.

[0063] The interlayer insulating film 195 is provided on the source region 116, the gate electrode 128, and the fifth insulating film 121. The interlayer insulating film 195 is made of, for example, SiO x This includes, but is not limited to:

[0064] The source electrode 16 is provided on the source region 116 and the contact region 118, and is electrically connected to the source region 116 and the contact region 118. In addition, an electrode pad 17 (not shown in FIG. 10) is appropriately provided on the source electrode 16.

[0065] Fig. 11 is a schematic cross-sectional view of a main part of a semiconductor device 110 of this embodiment. Fig. 11 is a schematic cross-sectional view for showing an example of a method for connecting a field plate electrode 124 and a source electrode 16, and an example of a method for connecting a gate electrode 128 and a gate metal 198. For example, the schematic cross-sectional view of Fig. 10 corresponds to the schematic cross-sectional view of the D-D' cross section of Fig. 10.

[0066] The field plate electrode 124 has a portion extending in the Z direction. Using the portion extending in the Z direction, the field plate electrode 124 is electrically connected to the source electrode 16 via a contact hole provided in the interlayer insulating film 195.

[0067] The gate electrode 128 is electrically connected to the gate metal 198 through a contact hole provided in the interlayer insulating film 195. For example, the gate metal 198 is provided under the fourth bonding material 80 (FIG. 1) and is electrically connected to the fourth bonding material 80.

[0068] The portion of the gate electrode 128 extending in the Y direction may be provided, for example, below the space between the electrode pads 17a1 and 17a2 (FIG. 9). In this case, the portion of the gate electrode 128 extending in the Y direction is an example of a connection wiring connected to the gate electrode 128.

[0069] Next, the effects of the semiconductor device of this embodiment will be described.

[0070] In the case of the semiconductor chip 10 having the trench 119, the internal stress is high in a plane perpendicular to the extension direction of the trench 119, and the chip is highly likely to warp. For example, in the case of the semiconductor device 110 in which the trench 119 extends in the Y direction, the internal stress is high in the XZ plane compared to the YZ plane, and the chip is highly likely to warp.

[0071] Therefore, in the semiconductor device 110, the electrode pads 17 are provided so as to extend in the X direction, which can better suppress warping of the semiconductor chip 10 in the XZ plane.

[0072] The semiconductor device 110 of this embodiment also makes it possible to provide a semiconductor device 110 with improved reliability.

[0073] Third embodiment The semiconductor device of this embodiment differs from the semiconductor devices of the first and second embodiments in that the semiconductor chip further has a fourth electrode provided in a second trench that reaches the first semiconductor layer from above the first semiconductor region, via the first semiconductor layer and a second insulating film, the second trench extends in a third direction that is parallel to the upper surface and intersects with the first direction, and an electrode pad provided on the second trench and not electrically connected to the first connector via the second bonding material extends in a fourth direction that is parallel to the upper surface and intersects with the third direction. Here, descriptions of contents that overlap with the first and second embodiments will be omitted.

[0074] FIG. 12 is a schematic top view of a semiconductor device 120 of the present embodiment.

[0075] In the first region 16a on the source electrode 16, the electrode pad 17b extends in the X direction (an example of the second direction). The trench 119 (an example of the first trench), the first insulating film 122 (an example of the second insulating film), and the field plate electrode 124 below the electrode pad 17b extend in the Y direction (an example of the first direction).

[0076] In the second region 16b on the source electrode 16, the electrode pad 17c extends in the Y direction (an example of a fourth direction). The trench 119 (an example of a second trench), the first insulating film 122 (an example of a second insulating film), and the field plate electrode 124 (an example of a fourth electrode) below the electrode pad 17c extend in the X direction (an example of a third direction).

[0077] Even in the case of the semiconductor device 120 in which the extending direction of the trench 119 differs depending on the region, warping of the semiconductor chip 10 can be suppressed more effectively.

[0078] The semiconductor device 120 of this embodiment also makes it possible to provide a semiconductor device 120 with improved reliability.

[0079] (Fourth embodiment) The semiconductor device of this embodiment differs from the semiconductor device of the first embodiment in that a plurality of electrode pads that are not connected to the first connector are provided. Here, descriptions of contents that overlap with the first to third embodiments will be omitted.

[0080] 13 is a schematic top view of a semiconductor device 130 of this embodiment. The electrode pad 17a is electrically connected to a first end 51a of the first connector 50. On the other hand, the electrode pads 17b, 17c, 17d, 17e, and 17f are not electrically connected to the first connector 50.

[0081] The semiconductor device 130 of this embodiment also makes it possible to provide a semiconductor device 130 with improved reliability.

[0082] Fifth embodiment The semiconductor device of this embodiment differs from the semiconductor device of the fourth embodiment in that the semiconductor device of this embodiment includes a second connector connected to a plurality of electrode pads that are not connected to the first connector. Here, descriptions of contents that overlap with the first to fourth embodiments will be omitted.

[0083] 14 is a schematic top view of a semiconductor device 140 of this embodiment. A second connector 53 is connected to the electrode pads 17b, 17c, 17d, 17e and 17f.

[0084] For example, when the first connector 50 is connected to the electrode pad 17a by reflow soldering, the first connector 50 may be hardened at a position shifted from a predetermined position when the molten bonding material hardens. By providing the second connector 53, such a shift is suppressed.

[0085] The semiconductor device 140 of this embodiment also makes it possible to provide a semiconductor device 140 with improved reliability.

[0086] Sixth embodiment 15 is a schematic top view of a semiconductor device 150 of this embodiment. Descriptions of contents that overlap with the first to fifth embodiments will be omitted. A first connector 50 is connected to the electrode pads 17a and 17b. No connector or wire is connected to the electrode pads 17c and 17d.

[0087] The semiconductor device 150 of this embodiment also makes it possible to provide a semiconductor device 150 with improved reliability.

[0088] Seventh embodiment Fig. 16 is a schematic top view of a semiconductor device 160 of this embodiment. Description of contents overlapping with the first to sixth embodiments will be omitted. The difference from the semiconductor device 150 shown in Fig. 15 is that a second connector 53 is connected to the electrode pads 17c and 17d.

[0089] The semiconductor device 160 of this embodiment also makes it possible to provide a semiconductor device 160 with improved reliability.

[0090] Although some embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0091] 2: Lead frame 10: Semiconductor chips 10a: Bottom surface 10b:Top surface 11: Drain electrode (first electrode) 16: Source electrode (second electrode) 17: Electrode pads 20:Second bonding material 50: First connector 53: Second connector 62: Wire 70: 1st bonding material 82: Sealing resin 100: Semiconductor device 105: Semiconductor device 110: Semiconductor device 112: First semiconductor layer (drift layer) 114: First semiconductor region (base region) 116: Second semiconductor region (source region) 119: Trench 120: Semiconductor device 122: first insulating film, second insulating film 124: Field plate electrode (third electrode, fourth electrode) 130: Semiconductor device 140: Semiconductor device 150: Semiconductor device 160: Semiconductor device

Claims

1. A lead frame; A first bonding material provided on the lead frame; a semiconductor chip provided on the first bonding material, the semiconductor chip having a lower surface, an upper surface, a first electrode provided on the lower surface and connected to the first bonding material, a second electrode provided on the upper surface, and a plurality of electrode pads connected to the second electrode; A plurality of second bonding materials provided on the plurality of electrode pads, respectively; a first connector connected to at least one of the plurality of second bonding materials; Equipped with The second bonding material that is not connected to the first connector is not connected to a connector or a wire. Semiconductor device.

2. A lead frame; A first bonding material provided on the lead frame; a semiconductor chip provided on the first bonding material, the semiconductor chip having a lower surface, an upper surface, a first electrode provided on the lower surface and connected to the first bonding material, a second electrode provided on the upper surface, and a plurality of electrode pads connected to the second electrode; A plurality of second bonding materials provided on the plurality of electrode pads, respectively; a first connector connected to at least one of the plurality of second bonding materials; a sealing resin provided on the second bonding material that is not electrically connected to the first connector; A semiconductor device comprising:

3. Further comprising a second connector connected to the second bonding material that is not electrically connected to the first connector.

3. The semiconductor device according to claim 2.

4. the sealing resin covers the second bonding material that is not electrically connected to the first connector; 3. The semiconductor device according to claim 2.

5. The semiconductor chip comprises: a first semiconductor layer of a first conductivity type provided on the first electrode; a first semiconductor region of a second conductivity type provided on the first semiconductor layer; a second semiconductor region of a first conductivity type provided on the first semiconductor region; The second electrode is provided on the second semiconductor region and is electrically connected to the second semiconductor region; a third electrode provided in a first trench extending from above the first semiconductor region to the first semiconductor layer, with the first semiconductor layer and a first insulating film interposed therebetween; and The first trench extends in a first direction parallel to the top surface; The electrode pad provided on the first trench and not electrically connected to the first connector via the second bonding material extends in a second direction parallel to the upper surface and intersecting the first direction.

5. The semiconductor device according to claim 1.

6. the first connector is connected to at least two of the plurality of electrode pads via the second bonding material; the semiconductor device further includes a connection wiring connected to the third electrode and provided below and between the two electrode pads electrically connected to the first connector; 6. The semiconductor device according to claim 5.

7. The semiconductor chip comprises: a fourth electrode provided in a second trench extending from above the first semiconductor region to the first semiconductor layer via the first semiconductor layer and a second insulating film; the second trench extends in a third direction parallel to the top surface and intersecting the first direction; The electrode pad provided on the second trench and not electrically connected to the first connector via the second bonding material extends in a fourth direction parallel to the upper surface and intersecting the third direction.

7. The semiconductor device according to claim 5.

8. Each of the plurality of electrode pads includes Ni or Cu.

8. The semiconductor device according to claim 1.

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