SiC Semiconductor Device

Abstract

To provide an SiC semiconductor device capable of suppressing wet spreading of a conductive joining material in an SiC semiconductor layer including a side surface having a rough surface region.SOLUTION: An SiC semiconductor device 1 includes: an SiC semiconductor layer 2 (SiC chip) having a stacked structure including an SiC semiconductor substrate 6 (SiC substrate) and an SiC epitaxial layer 7, and including a first main surface 3 at the SiC epitaxial layer 7 side, a second main surface 4 of the SiC semiconductor substrate 6, and side surfaces 5A to 5D; rough surface regions 20A to 20D formed in a portion composed of the SiC semiconductor substrate 6 among the side surfaces 5A to 5D; and smooth surface regions 21A to 21D formed in a portion composed of the SiC epitaxial layer 7 among the side surfaces 5A to 5D.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a SiC semiconductor device. [Background technology]

[0002] In recent years, a processing method for SiC semiconductor wafers called the stealth dicing method has been attracting attention. In the stealth dicing method, a SiC semiconductor wafer is selectively irradiated with laser light, and then the SiC semiconductor wafer is cut along the portion irradiated with the laser light. This method can cut a SiC semiconductor wafer having a relatively high hardness without using a cutting member such as a dicing blade, thereby shortening the manufacturing time.

[0003] Patent Document 1 discloses a method for manufacturing a SiC semiconductor device using a stealth dicing method, in which a rough surface region is formed on the entire area of ​​each side surface of a SiC semiconductor layer cut from a SiC semiconductor wafer, the rough surface region being made up of multiple rows of laser irradiation marks formed by laser irradiation. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-146878 A Summary of the Invention [Problem to be solved by the invention]

[0005] The SiC semiconductor device is mounted on a connection target via a conductive bonding material such as solder. Examples of the connection target include a lead frame, a circuit board, and an electronic component. In a SiC semiconductor layer having a rough surface region on its side, the conductive bonding material spreads over the side of the SiC semiconductor layer due to capillary action occurring in the rough surface region.

[0006] In a structure in which a rough surface region is formed over the entire side surface of the SiC semiconductor layer, most of the SiC semiconductor layer may be covered with a conductive bonding material, which may cause a short circuit in the SiC semiconductor layer and / or between the SiC semiconductor layer and a connection object.

[0007] One embodiment provides a SiC semiconductor device capable of suppressing the wetting and spreading of a conductive bonding material in a SiC semiconductor layer including a side surface having a roughened region. [Means for solving the problem]

[0008] One embodiment provides a SiC semiconductor device including a SiC single crystal, the SiC semiconductor layer having a mounting surface, a non-mounting surface opposite the mounting surface, and a side surface connecting the mounting surface and the non-mounting surface and including a roughened region and a smooth region formed in an area different from the roughened region.

[0009] In this SiC semiconductor device, the smooth surface region can suppress the capillary phenomenon that occurs in the rough surface region, thereby suppressing the conductive bonding material from spreading over the side surfaces of the SiC semiconductor layer.

[0010] One embodiment provides a SiC semiconductor device having a stacked structure including a SiC semiconductor substrate and a SiC epitaxial layer, the SiC semiconductor layer having an element formation surface consisting of the SiC epitaxial layer, a roughened surface region formed in a portion of the side surface of the SiC semiconductor layer consisting of the SiC semiconductor substrate and exposing the SiC epitaxial layer, and a smooth surface region formed in the portion of the side surface of the SiC semiconductor layer consisting of the SiC epitaxial layer.

[0011] In this SiC semiconductor device, the smooth surface region can suppress the capillary phenomenon that occurs in the rough surface region, thereby suppressing the conductive bonding material from spreading over the side surfaces of the SiC semiconductor layer. One embodiment provides a SiC semiconductor device having a layered structure including a SiC substrate and a SiC epitaxial layer, the SiC chip including a first main surface on the SiC epitaxial layer side, a second main surface on the SiC substrate side, and a side surface, a first rough surface region formed on a portion of the side surface consisting of the SiC substrate, and a second rough surface region formed on a portion of the side surface consisting of the SiC epitaxial layer. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing a unit cell of a 4H—SiC single crystal applied to an embodiment of the present invention. [Diagram 2] FIG. 2 is a plan view showing the silicon surface of the unit cell of the 4H—SiC single crystal shown in FIG. [Diagram 3] FIG. 3 is a perspective view of the SiC semiconductor device according to the first embodiment of the present invention as viewed from one angle, showing a first example of the rough surface region and the smooth surface region. [Figure 4] FIG. 4 is a perspective view of the SiC semiconductor device shown in FIG. 3 as viewed from a different angle. [Diagram 5] FIG. 5 is an enlarged view of region V shown in FIG. [Figure 6] FIG. 6 is an enlarged view of region VI shown in FIG. [Figure 7] FIG. 7 is a plan view of the SiC semiconductor device shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 9] FIG. 9 is a perspective view showing a SiC semiconductor wafer used for manufacturing the SiC semiconductor device shown in FIG. [Figure 10A] FIG. 10A is a cross-sectional view showing an example of a method for manufacturing the SiC semiconductor device shown in FIG. [Figure 10B] FIG. 10B is a diagram showing a step subsequent to that of FIG. 10A. [Figure 10C] FIG. 10C is a diagram showing a step subsequent to that of FIG. 10B. [Figure 10D] FIG. 10D is a diagram showing a step subsequent to that of FIG. 10C. [Figure 10E] FIG. 10E is a diagram showing a step subsequent to that of FIG. 10D. [Figure 10F] FIG. 10F is a diagram showing a step subsequent to that of FIG. 10E. [Figure 10G] FIG. 10G is a diagram showing a step subsequent to that of FIG. 10F. [Figure 10H] FIG. 10H is a diagram showing a step subsequent to that of FIG. 10G. [Figure 10I] FIG. 10I is a diagram showing a step subsequent to that of FIG. 10H. [Figure 10J] FIG. 10J is a diagram showing a step subsequent to FIG. 10I. [Figure 10K] FIG. 10K is a diagram showing a step subsequent to that of FIG. 10J. [Figure 10L] FIG. 10L shows a process subsequent to that of FIG. 10K. [Figure 10M] FIG. 10M is a diagram showing a step subsequent to that of FIG. 10L. [Figure 11] FIG. 11 is a perspective view showing a semiconductor package incorporating a SiC semiconductor device, with the sealing resin seen through. [Figure 12] FIG. 12 is a perspective view specifically showing a mounting state of the SiC semiconductor device shown in FIG. [Figure 13A] FIG. 13A is a perspective view showing the SiC semiconductor device shown in FIG. 3, illustrating a second example of the rough surface region and the smooth surface region. [Figure 13B] FIG. 13B is a perspective view showing the SiC semiconductor device shown in FIG. 3, illustrating a third example of the rough surface region and the smooth surface region. [Figure 13C] FIG. 13C is a perspective view showing the SiC semiconductor device shown in FIG. 3, illustrating a fourth example of the rough surface region and the smooth surface region. [Figure 13D] FIG. 13D is a perspective view showing the SiC semiconductor device shown in FIG. 3, illustrating a fifth example of the rough surface region and the smooth surface region. [Figure 13E] FIG. 13E is a perspective view showing the SiC semiconductor device shown in FIG. 3, illustrating a sixth example of the rough surface region and the smooth surface region. [Figure 13F] FIG. 13F is a perspective view showing the SiC semiconductor device shown in FIG. 3, illustrating a seventh example of the rough surface region and the smooth surface region. [Figure 13G] FIG. 13G is a perspective view showing the SiC semiconductor device shown in FIG. 3, illustrating an eighth example of the rough surface region and the smooth surface region. [Figure 14]FIG. 14 is a perspective view showing a SiC semiconductor device according to a second embodiment of the present invention, showing a structure to which the rough surface region and the smooth surface region according to the first embodiment are applied. [Figure 15] FIG. 15 is a perspective view of a SiC semiconductor device according to a third embodiment of the present invention, seen from one angle, illustrating a structure to which the rough surface region and smooth surface region according to the first embodiment are applied. [Figure 16] FIG. 16 is a perspective view of the SiC semiconductor device shown in FIG. 15 as viewed from a different angle. [Figure 17] FIG. 17 is a plan view showing the SiC semiconductor device shown in FIG. [Figure 18] FIG. 18 is a plan view of FIG. 17 with the resin layer removed. [Figure 19] FIG. 19 is an enlarged view of a region XIX shown in FIG. 18, and is a diagram for explaining the structure of the first main surface of the SiC semiconductor layer. [Figure 20] FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. [Figure 21] FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG. [Figure 22] FIG. 22 is an enlarged view of region XXII shown in FIG. [Figure 23] FIG. 23 is a cross-sectional view taken along the line XXIII-XXIII shown in FIG. [Figure 24] FIG. 24 is an enlarged view of region XXIV shown in FIG. [Diagram 25] FIG. 25 is a graph for explaining the sheet resistance. [Figure 26] FIG. 26 is an enlarged view of a region corresponding to FIG. 19, showing a SiC semiconductor device according to a fourth embodiment of the present invention. [Figure 27] FIG. 27 is a cross-sectional view taken along the line XXVII-XXVII shown in FIG. [Figure 28] FIG. 28 is an enlarged view of a region corresponding to FIG. 22, showing a SiC semiconductor device according to a fifth embodiment of the present invention. [Figure 29]FIG. 29 is an enlarged view of a region corresponding to FIG. 19, showing a SiC semiconductor device according to a sixth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0014] In the embodiment of the present invention, a SiC (silicon carbide) single crystal made of a hexagonal crystal is applied. The SiC single crystal made of a hexagonal crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal according to the period of the atomic arrangement. In the embodiment of the present invention, an example in which a 4H-SiC single crystal is applied will be described, but other polytypes are not excluded from the present invention.

[0015] The crystal structure of the 4H-SiC single crystal will be described below. Fig. 1 is a diagram showing a unit cell of a 4H-SiC single crystal (hereinafter simply referred to as a "unit cell") applied to an embodiment of the present invention. Fig. 2 is a plan view showing the silicon surface of the unit cell shown in Fig. 1.

[0016] 1 and 2, the unit cell includes a tetrahedral structure in which one Si atom and four C atoms are bonded in a tetrahedral arrangement (regular tetrahedral arrangement). The unit cell has an atomic arrangement in which four periods of tetrahedral structures are stacked. The unit cell has a hexagonal prism structure having regular hexagonal silicon faces, regular hexagonal carbon faces, and six side faces connecting the silicon faces and the carbon faces.

[0017] A silicon surface is a surface terminated by silicon atoms, with one silicon atom located at each of the six vertices of a regular hexagon and one silicon atom located at the center of the regular hexagon.

[0018] A carbon face is a terminal face terminated by C atoms, with one C atom located at each of the six vertices of a regular hexagon and one C atom located at the center of the regular hexagon.

[0019] The crystal plane of the unit cell is defined by four coordinate axes (a1, a2, a3, c) including the a1 axis, a2 axis, a3 axis, and c axis. The value of a3 among the four coordinate axes is -(a1+a2). Below, the crystal plane of a 4H-SiC single crystal is explained based on the silicon plane as an example of a hexagonal crystal termination plane.

[0020] The a1, a2 and a3 axes are set along the arrangement direction of the nearest Si atoms (hereinafter simply referred to as the "nearest atom direction") with respect to the Si atom located at the center in a plan view of the silicon surface seen from the c-axis. The a1, a2 and a3 axes are set at angles shifted by 120° each, following the arrangement of the Si atoms.

[0021] The c-axis is set in the normal direction to the silicon surface, based on the Si atom located at the center. The silicon surface is the (0001) surface. The carbon surface is the (000-1) surface.

[0022] The side surface of the hexagonal prism includes six crystal planes along the nearest-neighbor atom direction in a planar view of the silicon surface from the c-axis. More specifically, the side surface of the hexagonal prism includes six crystal planes each including two nearest-neighbor Si atoms in a planar view of the silicon surface from the c-axis.

[0023] The side surface of the hexagonal prism includes, in a plan view of the silicon surface seen from the c-axis, the (1-100), (0-110), (-1010), (-1100), (01-10), and (10-10) planes clockwise from the tip of the a1 axis.

[0024] The diagonal plane along the diagonal line of the hexagonal prism includes six crystal planes along a crossing direction that crosses the nearest-neighbor atom direction in a planar view of the silicon surface from the c-axis. More specifically, the diagonal plane of the hexagonal prism includes six crystal planes each including two non-neighboring Si atoms in a planar view of the silicon surface from the c-axis. When viewed from the perspective of the Si atom located at the center, the crossing direction of the nearest-neighbor atom direction is an orthogonal direction that is perpendicular to the nearest-neighbor atom direction.

[0025] The diagonal faces of the hexagonal prism include the (11-20), (1-210), (-2110), (-1-120), (-12-10) and (2-1-10) faces in plan view of the silicon surface from the c-axis.

[0026] The crystal directions of the unit cell are defined by the normal directions of the crystal planes. The normal direction of the (1-100) plane is the [1-100] direction. The normal direction of the (0-110) plane is the [0-110] direction. The normal direction of the (-1010) plane is the [-1010] direction. The normal direction of the (-1100) plane is the [-1100] direction. The normal direction of the (01-10) plane is the [01-10] direction. The normal direction of the (10-10) plane is the [10-10] direction.

[0027] The normal direction of the (11-20) plane is the [11-20] direction. The normal direction of the (1-210) plane is the [1-210] direction. The normal direction of the (-2110) plane is the [-2110] direction. The normal direction of the (-1-120) plane is the [-1-120] direction. The normal direction of the (-12-10) plane is the [-12-10] direction. The normal direction of the (2-1-10) plane is the [2-1-10] direction.

[0028] Hexagonal crystals have six-fold symmetry, and there are equivalent crystal planes and equivalent crystal directions every 60°. For example, the (1-100), (0-110), (-1010), (-1100), (01-10), and (10-10) planes form equivalent crystal planes.

[0029] Additionally, the [1-100], [0-110], [-1010], [-1100], [01-10], and [10-10] directions form equivalent crystal directions, while the [11-20], [1-210], [-2110], [-1-120], [-12-10], and [2-1-10] directions form equivalent crystal directions.

[0030] The c-axis is in the

[0001] direction ([000-1] direction). The a1-axis is in the [2-1-10] direction ([-2110] direction). The a2-axis is in the [-12-10] direction ([1-210] direction). The a3-axis is in the [-1-120] direction ([11-20] direction).

[0031] The (0001) and (000-1) planes are collectively referred to as c-planes. The

[0001] and [000-1] directions are collectively referred to as the c-axis directions. The (11-20) and (-1-120) planes are collectively referred to as a-planes. The [11-20] and [-1-120] directions are collectively referred to as the a-axis directions. The (1-100) and (-1100) planes are collectively referred to as m-planes. The [1-100] and [-1100] directions are collectively referred to as the m-axis directions.

[0032] Fig. 3 is a perspective view of the SiC semiconductor device 1 according to the first embodiment of the present invention, seen from one angle, and showing a first embodiment of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D. Fig. 4 is a perspective view of the SiC semiconductor device 1 shown in Fig. 3, seen from another angle.

[0033] Fig. 5 is an enlarged view of region V shown in Fig. 3. Fig. 6 is an enlarged view of region VI shown in Fig. 3. Fig. 7 is a plan view of the SiC semiconductor device 1 shown in Fig. 3. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 7.

[0034] 3 to 8, SiC semiconductor device 1 includes a SiC semiconductor layer 2. SiC semiconductor layer 2 includes a 4H—SiC single crystal as an example of a SiC single crystal made of hexagonal crystals. SiC semiconductor layer 2 is formed in the shape of a rectangular parallelepiped chip.

[0035] The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (square shape in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0036] The first main surface 3 is an element formation surface on which a semiconductor element is formed. The second main surface 4 of the SiC semiconductor layer 2 is a ground surface having grinding marks. The side surfaces 5A to 5D are each a cleavage plane facing a crystal plane of the SiC single crystal. The side surfaces 5A to 5D do not have grinding marks.

[0037] In this embodiment, the first main surface 3 of the SiC semiconductor layer 2 is formed as a non-mounting surface. In this embodiment, the second main surface 4 of the SiC semiconductor layer 2 is formed as a mounting surface. When the SiC semiconductor layer 2 is mounted on an object to be connected, the SiC semiconductor layer 2 is mounted on the object to be connected with the second main surface 4 facing the object. Examples of the object to be connected include electronic components, lead frames, circuit boards, etc.

[0038] The thickness TL of the SiC semiconductor layer 2 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less. The thickness TL is preferably 60 μm or more and 150 μm or less.

[0039] In this embodiment, the first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The first main surface 3 faces the (0001) plane (silicon plane). The second main surface 4 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0040] The first principal surface 3 and the second principal surface 4 have an off angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0041] The off angle θ may be 0° or more and 5.0° or less. The off angle θ may be set in the range of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. The off angle θ is preferably greater than 0°. The off angle θ may be less than 4.0°.

[0042] The off angle θ may be set in the range of 3.0° to 4.5° inclusive. In this case, the off angle θ is preferably set in the range of 3.0° to 3.5° inclusive or 3.5° to 4.0° inclusive.

[0043] The off angle θ may be set in the range of 1.5° to 3.0° inclusive. In this case, the off angle θ is preferably set in the range of 1.5° to 2.0° inclusive or 2.0° to 2.5° inclusive.

[0044] The length of each of the side surfaces 5A to 5D may be 0.5 mm or more and 10 mm or less. In this embodiment, the surface areas of the side surfaces 5A to 5D are equal to each other. When the first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view, the surface areas of the side surfaces 5A and 5C may be less than the surface areas of the side surfaces 5B and 5D, or may be greater than the surface areas of the side surfaces 5B and 5D.

[0045] In this embodiment, the side surface 5A and the side surface 5C extend along a first direction X and face each other in a second direction Y that intersects with the first direction X. In this embodiment, the side surface 5B and the side surface 5D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is a direction perpendicular to the first direction X.

[0046] In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

[0047] Side 5A and side 5C are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction. Side 5A is formed by the (-1-120) plane of the SiC single crystal. Side 5C is formed by the (11-20) plane of the SiC single crystal.

[0048] Side 5B and side 5D are formed by the m-plane of the SiC single crystal and face each other in the m-axis direction. Side 5B is formed by the (-1100) plane of the SiC single crystal. Side 5D is formed by the (1-100) plane of the SiC single crystal.

[0049] Side 5A and side 5C may form an inclined surface that is inclined toward the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal to first main surface 3 of SiC semiconductor layer 2.

[0050] In this case, when a normal to the first main surface 3 of the SiC semiconductor layer 2 is defined as 0°, the side surface 5A and the side surface 5C may be inclined at an angle corresponding to the off angle θ with respect to the normal to the first main surface 3 of the SiC semiconductor layer 2. The angle corresponding to the off angle θ may be equal to the off angle θ or may be an angle exceeding 0° and less than the off angle θ.

[0051] On the other hand, the side surface 5B and the side surface 5D extend planarly along the normal to the first main surface 3 of the SiC semiconductor layer 2. More specifically, the side surface 5B and the side surface 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4.

[0052] In this embodiment, the SiC semiconductor layer 2 is + The SiC semiconductor layer 2 has a layered structure including an n-type SiC semiconductor substrate 6 and an n-type SiC epitaxial layer 7. The SiC semiconductor substrate 6 forms the second main surface 4 of the SiC semiconductor layer 2.

[0053] The first main surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 7. The SiC semiconductor substrate 6 and the SiC epitaxial layer 7 form side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0054] The n-type impurity concentration of the SiC epitaxial layer 7 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 6. More specifically, the n-type impurity concentration of the SiC epitaxial layer 7 is lower than the n-type impurity concentration of the SiC semiconductor substrate 6. The n-type impurity concentration of the SiC semiconductor substrate 6 is 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 7 may be 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 It may be the following.

[0055] The thickness TS of the SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. The thickness TS may be 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 6, the resistance value can be reduced by shortening the current path.

[0056] The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness TE may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

[0057] The SiC semiconductor layer 2 has an active region 8 and an outer region 9. The active region 8 is a region in which a Schottky barrier diode D, which is an example of a semiconductor element, is formed. The outer region 9 is a region outside the active region 8.

[0058] The active region 8 is set in the center of the SiC semiconductor layer 2 at a distance inward from the side surfaces 5A-5D of the SiC semiconductor layer 2 in a plan view. The active region 8 is set in a quadrangle shape having four sides parallel to the side surfaces 5A-5D of the SiC semiconductor layer 2 in a plan view.

[0059] The outer region 9 is set in a region between the side surfaces 5A-5D of the SiC semiconductor layer 2 and the periphery of the active region 8. The outer region 9 is set in an endless shape (a square ring shape in this embodiment) surrounding the active region 8 in a plan view.

[0060] A main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. The main surface insulating layer 10 selectively covers the active region 8 and the outer region 9. The main surface insulating layer 10 may have a single-layer structure made of a silicon oxide (SiO2) layer or a silicon nitride (SiN) layer.

[0061] The main surface insulating layer 10 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the main surface insulating layer 10 has a single layer structure made of a silicon oxide layer.

[0062] The main surface insulating layer 10 has insulating side surfaces 11A, 11B, 11C, and 11D exposed from the side surfaces 5A to 5D of the SiC semiconductor layer 2. The insulating side surfaces 11A to 11D are continuous with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are formed flush with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are made of cleavage planes.

[0063] The thickness of the main surface insulating layer 10 may be 1 μm or more and 50 μm or less. The thickness of the main surface insulating layer 10 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0064] A first principal surface electrode layer 12 is formed on the principal surface insulating layer 10. The first principal surface electrode layer 12 is formed in the center of the SiC semiconductor layer 2 with a gap in between in an inner region from the side surfaces 5A-5D of the SiC semiconductor layer 2 in a plan view.

[0065] A passivation layer 13 (insulating layer) is formed on the main surface insulating layer 10. The passivation layer 13 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer.

[0066] The passivation layer 13 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the passivation layer 13 has a single-layer structure made of a silicon nitride layer.

[0067] Sides 14A, 14B, 14C, and 14D of passivation layer 13 are formed at intervals inward from side surfaces 5A to 5D of SiC semiconductor layer 2 in a plan view. Passivation layer 13 exposes the peripheral portion of first main surface 3 of SiC semiconductor layer 2 in a plan view. Passivation layer 13 exposes main surface insulating layer 10.

[0068] A subpad opening 15 that exposes a part of the first principal surface electrode layer 12 as a pad region is formed in the passivation layer 13. The subpad opening 15 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0069] The thickness of the passivation layer 13 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 13 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0070] A resin layer 16 (insulating layer) is formed on the passivation layer 13. The passivation layer 13 and the resin layer 16 form one insulating laminated structure (insulating layer). In Fig. 7, the resin layer 16 is indicated by hatching.

[0071] The resin layer 16 may include a negative type or a positive type photosensitive resin. In this embodiment, the resin layer 16 includes polybenzoxazole as an example of a positive type photosensitive resin. The resin layer 16 may include polyimide as an example of a negative type photosensitive resin.

[0072] Resin side surfaces 17A, 17B, 17C, and 17D of resin layer 16 are formed at intervals inward from side surfaces 5A to 5D of SiC semiconductor layer 2 in plan view. Resin layer 16 exposes the peripheral portion of first main surface 3 of SiC semiconductor layer 2 in plan view. Resin layer 16 exposes main surface insulating layer 10 together with passivation layer 13. In this embodiment, resin side surfaces 17A to 17D of resin layer 16 are formed flush with side surfaces 14A to 14D of passivation layer 13.

[0073] Resin side surfaces 17A-17D of resin layer 16 are portions that define dicing streets when SiC semiconductor device 1 is cut out from one SiC semiconductor wafer. In this embodiment, side surfaces 14A-14D of passivation layer 13 are also portions that define dicing streets.

[0074] By exposing the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 from the resin layer 16 and the passivation layer 13, it is not necessary to physically cut the resin layer 16 and the passivation layer 13. This makes it possible to smoothly cut out the SiC semiconductor device 1 from one SiC semiconductor wafer. Also, the insulation distance from the side surfaces 5A to 5D of the SiC semiconductor layer 2 can be increased.

[0075] The distance between the side surfaces 5A-5D and the resin side surfaces 17A-17D (side surfaces 14A-14D) may be 1 μm or more and 25 μm or less. The distance between the side surfaces 5A-5D and the resin side surfaces 17A-17D (side surfaces 14A-14D) may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. Of course, the side surfaces 14A-14D of the passivation layer 13 may be formed flush with the side surfaces 5A-5D of the SiC semiconductor layer 2.

[0076] A pad opening 18 that exposes a part of the first principal surface electrode layer 12 as a pad region is formed in the resin layer 16. The pad opening 18 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0077] The pad opening 18 communicates with the sub-pad opening 15. The inner wall of the pad opening 18 is formed flush with the inner wall of the sub-pad opening 15. The inner wall of the pad opening 18 may be located on the side surfaces 5A to 5D side of the SiC semiconductor layer 2 with respect to the inner wall of the sub-pad opening 15. The inner wall of the pad opening 18 may be located in the inner region of the SiC semiconductor layer 2 with respect to the inner wall of the sub-pad opening 15. The resin layer 16 may cover the inner wall of the sub-pad opening 15.

[0078] The thickness of the resin layer 16 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 16 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0079] A second main surface electrode layer 19 is formed on the second main surface 4 of the SiC semiconductor layer 2. The second main surface electrode layer 19 forms an ohmic contact with the second main surface 4 (SiC semiconductor substrate 6) of the SiC semiconductor layer 2.

[0080] On the side surfaces 5A to 5D of the SiC semiconductor layer 2, rough surface regions 20A to 20D and smooth surface regions 21A to 21D are respectively formed. The rough surface regions 20A to 20D are regions where a part of the side surfaces 5A to 5D is roughened by the introduction of a predetermined surface roughness Rr. The smooth surface regions 21A to 21D are regions having a surface roughness Rs (Rs < Rr) less than the surface roughness Rr of the rough surface regions 20A to 20D on the side surfaces 5A to 5D.

[0081] The rough surface regions 20A to 20D include the rough surface region 20A formed on the side surface 5A, the rough surface region 20B formed on the side surface 5B, the rough surface region 20C formed on the side surface 5C, and the rough surface region 20D formed on the side surface 5D. The smooth surface regions 21A to 21D include the smooth surface region 21A formed on the side surface 5A, the smooth surface region 21B formed on the side surface 5B, the smooth surface region 21C formed on the side surface 5C, and the smooth surface region 21D formed on the side surface 5D.

[0082] Rough surface regions 20A-20D are formed in regions of side surfaces 5A-5D on the second main surface 4 side of SiC semiconductor layer 2. In this embodiment, rough surface regions 20A-20D are formed from corners of side surfaces 5A-5D on the second main surface 4 side to a middle portion of SiC semiconductor layer 2 in the thickness direction.

[0083] Rough surface regions 20A-20D are formed at intervals from first main surface 3 to second main surface 4 of SiC semiconductor layer 2. Rough surface regions 20A-20D expose surface portions of first main surface 3 of SiC semiconductor layer 2 from side surfaces 5A-5D. Rough surface regions 20A-20D are not formed on main surface insulating layer 10, passivation layer 13, or resin layer 16.

[0084] More specifically, rough surface regions 20A-20D are formed in a middle portion in the thickness direction of SiC semiconductor substrate 6. More specifically, rough surface regions 20A-20D are formed at intervals from the boundary between SiC semiconductor substrate 6 and SiC epitaxial layer 7 to second main surface 4. As a result, rough surface regions 20A-20D expose parts of SiC semiconductor substrate 6 and SiC epitaxial layer 7 in the surface layer portion of first main surface 3 of SiC semiconductor layer 2.

[0085] The rough surface regions 20A-20D extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. The tangential direction of the first main surface 3 is a direction perpendicular to the normal direction Z. The tangential direction includes a first direction X (the m-axis direction of the SiC single crystal) and a second direction Y (the a-axis direction of the SiC single crystal).

[0086] Rough surface region 20A is formed in a band shape extending linearly along the m-axis direction on side surface 5A. Rough surface region 20B is formed in a band shape extending linearly along the a-axis direction on side surface 5B. Rough surface region 20C is formed in a band shape extending linearly along the m-axis direction on side surface 5C. Rough surface region 20D is formed in a band shape extending linearly along the a-axis direction on side surface 5D.

[0087] The rough surface regions 20A and 20B are connected to each other at the corner connecting the side surfaces 5A and 5B in the SiC semiconductor layer 2. The rough surface regions 20B and 20C are connected to each other at the corner connecting the side surfaces 5B and 5C in the SiC semiconductor layer 2.

[0088] The rough surface regions 20C and 20D are connected to each other at the corner connecting the side surfaces 5C and 5D in the SiC semiconductor layer 2. The rough surface regions 20D and 20A are connected to each other at the corner connecting the side surfaces 5D and 5A in the SiC semiconductor layer 2.

[0089] As a result, the rough surface regions 20A to 20D are integrally formed so as to surround the SiC semiconductor layer 2. The rough surface regions 20A to 20D form one endless (ring-shaped) rough surface region surrounding the SiC semiconductor layer 2 on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0090] With respect to the normal direction Z, the thickness TR of the rough surface regions 20A to 20D is less than the thickness TL of the SiC semiconductor layer 2 (TR < TL). It is preferable that the thickness TR of the rough surface regions 20A to 20D is less than the thickness TS of the SiC semiconductor substrate 6 (TR < TS).

[0091] The thickness TR of the rough surface regions 20A to 20D may be greater than or equal to the thickness TE of the SiC epitaxial layer 7 (TR ≧ TE). The thicknesses of the thickness TR of the rough surface region 20A, the thickness TR of the rough surface region 20B, the thickness TR of the rough surface region 20C, and the thickness TR of the rough surface region 20D may be equal to each other or different from each other.

[0092] The ratio TR / TL of the thickness TR of the rough surface regions 20A to 20D to the thickness TL of the SiC semiconductor layer 2 is preferably 0.1 or more and less than 1.0. The ratio TR / TL may be 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and less than 1.0.

[0093] The ratio TR / TL may be 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio TR / TL is preferably 0.2 or more and 0.5 or less.

[0094] It is more preferable that the ratio TR / TS of the thickness TR of the rough surface regions 20A-20D to the thickness TS of the SiC semiconductor substrate 6 is 0.1 or more and less than 1.0. The ratio TR / TS may be 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and less than 1.0.

[0095] The ratio TR / TS may be 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio TR / TS is preferably 0.2 or more and 0.5 or less.

[0096] In this embodiment, the rough surface regions 20A-20D include modification lines 22A-22D (modified layers), respectively. The modification lines 22A-22D include layered regions in which parts of the SiC single crystals forming the side surfaces 5A-5D are modified to have properties different from those of the SiC single crystals. In other words, the rough surface regions 20A-20D are regions roughened by the modification lines 22A-22D.

[0097] The modified lines 22A to 22D include regions in which the density, refractive index, mechanical strength (crystal strength), or other physical properties are modified to have properties different from those of a SiC single crystal. The modified lines 22A to 22D may include at least one layer selected from the group consisting of a melt-rehardened layer, a defect layer, a dielectric breakdown layer, and a refractive index change layer.

[0098] The melt-rehardened layer is a layer formed by melting a part of the SiC semiconductor layer 2 and then hardening again. The defect layer is a layer including voids, cracks, etc. formed in the SiC semiconductor layer 2. The dielectric breakdown layer is a layer in which dielectric breakdown has occurred in a part of the SiC semiconductor layer 2. The refractive index change layer is a layer in which a part of the SiC semiconductor layer 2 has changed to a refractive index different from that of the SiC single crystal.

[0099] The rough surface region 20A includes one or more layers (two or more layers; in this embodiment, two layers) of reforming lines 22A. In this embodiment, the reforming lines 22A extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. More specifically, the reforming lines 22A are each formed in a strip shape extending linearly along the m-axis direction on the side surface 5A.

[0100] The multiple reforming lines 22A are formed to be shifted from one another in the normal direction Z. The multiple reforming lines 22A may be formed to be spaced apart from one another in the normal direction Z. The multiple reforming lines 22A may overlap one another in the normal direction Z. The thickness TR of the rough surface region 20A is determined by the sum of the thicknesses of the multiple reforming lines 22A. The thicknesses of the multiple reforming lines 22A may be equal to one another or different from one another.

[0101] The rough surface region 20B includes one or more layers (two or more layers; in this embodiment, two layers) of reforming lines 22B. In this embodiment, the reforming lines 22B extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. More specifically, the reforming lines 22B are each formed in a strip shape extending linearly along the a-axis direction on the side surface 5B.

[0102] The multiple reforming lines 22B are formed to be shifted from one another in the normal direction Z. The multiple reforming lines 22B may be formed to be spaced apart from one another in the normal direction Z. The multiple reforming lines 22B may overlap one another in the normal direction Z. The thickness TR of the rough surface region 20B is determined by the sum of the thicknesses of the multiple reforming lines 22B. The thicknesses of the multiple reforming lines 22B may be equal to one another or different from one another.

[0103] The rough surface region 20C includes one or more layers (two or more layers; in this embodiment, two layers) of reforming lines 22C. In this embodiment, the reforming lines 22C extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. More specifically, the reforming lines 22C are each formed in a strip shape extending linearly along the m-axis direction on the side surface 5C.

[0104] The multiple reforming lines 22C are formed to be shifted from one another in the normal direction Z. The multiple reforming lines 22C may be formed to be spaced apart from one another in the normal direction Z. The multiple reforming lines 22C may overlap one another in the normal direction Z. The thickness TR of the rough surface region 20C is determined by the sum of the thicknesses of the multiple reforming lines 22C. The thicknesses of the multiple reforming lines 22C may be equal to one another or different from one another.

[0105] The rough surface region 20D includes one or more layers (two or more layers; in this embodiment, two layers) of reforming lines 22D. In this embodiment, the reforming lines 22D extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. More specifically, the reforming lines 22D are each formed in a strip shape extending linearly along the a-axis direction on the side surface 5D.

[0106] The multiple reforming lines 22D are formed to be shifted from one another in the normal direction Z. The multiple reforming lines 22D may be formed to be spaced apart from one another in the normal direction Z. The multiple reforming lines 22D may overlap one another in the normal direction Z. The thickness TR of the rough surface region 20D is determined by the sum of the thicknesses of the multiple reforming lines 22D. The thicknesses of the multiple reforming lines 22D may be equal to one another or different from one another.

[0107] The reforming line 22A and the reforming line 22B are connected to each other at a corner portion connecting the side surface 5A and the side surface 5B of the SiC semiconductor layer 2. The reforming line 22B and the reforming line 22C are connected to each other at a corner portion connecting the side surface 5B and the side surface 5C of the SiC semiconductor layer 2.

[0108] The reforming line 22C and the reforming line 22D are connected to each other at a corner portion connecting the side surface 5C and the side surface 5D of the SiC semiconductor layer 2. The reforming line 22D and the reforming line 22A are connected to each other at a corner portion connecting the side surface 5D and the side surface 5A of the SiC semiconductor layer 2.

[0109] As a result, the reforming lines 22A to 22D are integrally formed so as to surround the SiC semiconductor layer 2. The reforming lines 22A to 22D form one endless (annular) reforming line that surrounds the SiC semiconductor layer 2 on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0110] 5, the modification line 22A includes a plurality of a-plane modified portions 28 (modified portions). In other words, the modification line 22A is formed by an assembly of a plurality of a-plane modified portions 28. The plurality of a-plane modified portions 28 are portions in which the SiC single crystal exposed from the side surface 5A has been modified to have properties different from those of the SiC single crystal. The region around each a-plane modified portion 28 on the side surface 5A may be modified to have properties different from those of the SiC single crystal.

[0111] Each of the multiple a-plane modified portions 28 includes one end portion 28a located on the first main surface 3 side, the other end portion 28b located on the second main surface 4 side, and a connection portion 28c connecting the one end portion 28a and the other end portion 28b.

[0112] The multiple a-plane modified regions 28 are each formed in a line extending in the normal direction Z. As a result, the multiple a-plane modified regions 28 are formed in a striped pattern as a whole. The multiple a-plane modified regions 28 may include multiple a-plane modified regions 28 formed in a tapered shape in which the width in the m-axis direction narrows from one end 28a side to the other end 28b side.

[0113] The multiple a-plane modified parts 28 are formed at intervals in the m-axis direction so as to face each other in the m-axis direction. The multiple a-plane modified parts 28 may overlap each other in the m-axis direction. A band-shaped region extending in the m-axis direction is formed by a line connecting one end 28a of the multiple a-plane modified parts 28 and a line connecting the other end 28b of the multiple a-plane modified parts 28. The modification line 22A is formed by this band-shaped region.

[0114] Each of the multiple a-plane modified regions 28 may form a notch by cutting out the side surface 5A. Each of the multiple a-plane modified regions 28 may form a recess recessed from the side surface 5A toward the a-axis direction. The multiple a-plane modified regions 28 may be formed in a dot shape according to their length in the normal direction Z and their width in the m-axis direction.

[0115] In the m-axis direction, the pitch PR between the central portions of adjacent a-plane modified portions 28 may be more than 0 μm and not more than 20 μm. The pitch PR may be more than 0 μm and not more than 5 μm, 5 μm or more to 10 μm or less, 10 μm or more to 15 μm or less, or 15 μm or more to 20 μm or less.

[0116] In the m-axis direction, the width WR of each a-plane modified portion 28 may be greater than 0 μm and less than or equal to 20 μm. The width WR may be greater than 0 μm and less than or equal to 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, or greater than or equal to 15 μm and less than or equal to 20 μm.

[0117] In this manner, the rough surface region 20A is roughened by the modification lines 22A that extend along the normal direction Z and include a plurality of a-plane modified portions 28 that face each other along the m-axis direction. The rough surface region 20A has a surface roughness Rr that corresponds to the pitch PR and width WR of the a-plane modified portions 28.

[0118] The rough surface region 20C (modified line 22C) has a structure similar to that of the rough surface region 20A (modified line 22A) except that it is formed on the side surface 5C. The description of the rough surface region 20A (modified line 22A) applies mutatis mutandis to the description of the rough surface region 20C (modified line 22C) with "side surface 5A" read as "side surface 5C".

[0119] 6, the modification line 22D includes a plurality of m-plane modified portions 29 (modified portions). In other words, the modification line 22D is formed by an assembly of a plurality of m-plane modified portions 29. The plurality of m-plane modified portions 29 are portions in which the SiC single crystal exposed from the side surface 5D has been modified to have properties different from those of the SiC single crystal. The region around each m-plane modified portion 29 on the side surface 5D may be modified to have properties different from those of the SiC single crystal.

[0120] Each of the multiple m-plane modified portions 29 includes one end portion 29a located on the first principal surface 3 side, the other end portion 29b located on the second principal surface 4 side, and a connection portion 29c connecting the one end portion 29a and the other end portion 29b.

[0121] The multiple m-plane modified regions 29 are each formed in a line extending in the normal direction Z. As a result, the multiple m-plane modified regions 29 are formed in a striped pattern as a whole. The multiple m-plane modified regions 29 may include multiple m-plane modified regions 29 formed in a tapered shape in which the width in the a-axis direction narrows from one end 29a to the other end 29b.

[0122] The multiple m-plane modified regions 29 are formed at intervals in the a-axis direction so as to face each other in the a-axis direction. The multiple m-plane modified regions 29 may overlap each other in the a-axis direction. A band-shaped region extending in the a-axis direction is formed by a line connecting one ends 29a of the multiple m-plane modified regions 29 and a line connecting the other ends 29b of the multiple m-plane modified regions 29. The modification line 22D is formed by this band-shaped region.

[0123] Each of the multiple m-plane modified regions 29 may form a notch by cutting out the side surface 5D. Each of the multiple m-plane modified regions 29 may form a recess that is recessed from the side surface 5D toward the m-axis direction. The multiple m-plane modified regions 29 may be formed in a dot pattern according to their length in the normal direction Z and their width in the a-axis direction.

[0124] In the a-axis direction, the pitch PR between the central portions of adjacent m-plane modified portions 29 may be 0 μm or more and 20 μm or less. The pitch PR may be 0 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

[0125] In the a-axis direction, the width WR of each m-plane modified region 29 may be greater than 0 μm and less than or equal to 20 μm. The width WR may be greater than 0 μm and less than or equal to 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, or greater than or equal to 15 μm and less than or equal to 20 μm.

[0126] In this manner, the rough surface region 20D is roughened by modification lines 22D that extend along the normal direction Z and include multiple m-plane modified portions 29 that face each other along the a-axis direction. The rough surface region 20D has a surface roughness Rr that corresponds to the pitch PR and width WR of the multiple m-plane modified portions 29.

[0127] The rough surface region 20B (modified line 22B) has a structure similar to that of the rough surface region 20D (modified line 22D), except that the rough surface region 20B (modified line 22B) is formed on the side surface 5B. The description of the rough surface region 20D (modified line 22D) applies mutatis mutandis to the description of the rough surface region 20B (modified line 22B), with "side surface 5D" read as "side surface 5B."

[0128] 3 and 4 again, smooth surface regions 21A-21D are formed in regions different from rough surface regions 20A-20D on side surfaces 5A-5D of SiC semiconductor layer 2. Smooth surface regions 21A-21D are formed in regions on side surfaces 5A-5D other than rough surface regions 20A-20D.

[0129] The smooth surface regions 21A-21D are formed in regions on the side surfaces 5A-5D on the first main surface 3 side of the SiC semiconductor layer 2. The smooth surface regions 21A-21D are formed on the side surfaces 5A-5D from the first main surface 3 of the SiC semiconductor layer 2 to a middle portion of the SiC semiconductor layer 2 in the thickness direction. More specifically, the smooth surface regions 21A-21D are formed in the SiC epitaxial layer 7. The smooth surface regions 21A-21D expose the SiC epitaxial layer 7.

[0130] More specifically, the smooth surface regions 21A-21D are formed across the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 on both the SiC epitaxial layer 7 and the SiC semiconductor substrate 6. The smooth surface regions 21A-21D expose both the SiC epitaxial layer 7 and the SiC semiconductor substrate 6.

[0131] The smooth surface regions 21A-21D extend in a band shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. The smooth surface region 21A is formed in a band shape extending linearly along the m-axis direction on the side surface 5A. The smooth surface region 21B is formed in a band shape extending linearly along the a-axis direction on the side surface 5B. The smooth surface region 21C is formed in a band shape extending linearly along the m-axis direction on the side surface 5C. The smooth surface region 21D is formed in a band shape extending linearly along the a-axis direction on the side surface 5D.

[0132] Smooth surface region 21A and smooth surface region 21B are connected to each other at a corner connecting side surface 5A and side surface 5B of SiC semiconductor layer 2. Smooth surface region 21B and smooth surface region 21C are connected to each other at a corner connecting side surface 5B and side surface 5C of SiC semiconductor layer 2.

[0133] Smooth surface region 21C and smooth surface region 21D are connected to each other at a corner connecting side surface 5C and side surface 5D of SiC semiconductor layer 2. Smooth surface region 21D and smooth surface region 21A are connected to each other at a corner connecting side surface 5D and side surface 5A of SiC semiconductor layer 2.

[0134] As a result, the smooth surface regions 21A to 21D are integrally formed so as to surround the SiC semiconductor layer 2. The smooth surface regions 21A to 21D form one endless (annular) smooth surface region surrounding the SiC semiconductor layer 2 on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0135] In the normal direction Z, the thickness TRs of the smooth surface regions 21A to 21D is a value obtained by subtracting the thickness TR of the rough surface regions 20A to 20D from the thickness TL of the SiC semiconductor layer 2 (TRs = TL - TR). The thickness TRs of the smooth surface regions 21A to 21D can take various values according to the thickness TR of the rough surface regions 20A to 20D.

[0136] The thickness TRs of the smooth surface regions 21A to 21D is preferably equal to or greater than the thickness TR of the rough surface regions 20A to 20D (TR ≦ TRs). The ratio TRs / TL of the thickness TRs of the smooth surface regions 21A to 21D to the thickness TL of the SiC semiconductor layer 2 is preferably 0.5 or more. More preferably, the thickness TRs of the smooth surface regions 21A to 21D exceeds the thickness TR of the rough surface regions 20A to 20D (TR < TRs). More preferably, the ratio TRs / TL exceeds 0.5.

[0137] The thicknesses of the thickness TRs of the smooth surface region 21A, the smooth surface region 21B, the smooth surface region 21C, and the smooth surface region 21D may be equal to each other or may be different from each other.

[0138] Unlike the rough surface regions 20A to 20D, the smooth surface regions 21A to 21D do not have the modification lines 22A to 22D (modified layers). The smooth surface regions 21A to 21D are composed of smooth cleavage surfaces formed by the crystal planes of the SiC single crystal. The smooth surface regions 21A to 21D have a surface roughness Rs corresponding to the crystal planes (cleavage surfaces) of the SiC single crystal.

[0139] The smooth surface region 21A is composed of the a-plane of the SiC single crystal forming the side surface 5A. The smooth surface region 21B is composed of the m-plane of the SiC single crystal forming the side surface 5B. The smooth surface region 21C is composed of the a-plane of the SiC single crystal forming the side surface 5C. The smooth surface region 21D is composed of the m-plane of the SiC single crystal forming the side surface 5D.

[0140] In this way, rough surface regions 20A-20D having a surface roughness Rr corresponding to the modification of the SiC single crystal, and smooth surface regions 21A-21D having a surface roughness Rs corresponding to the crystal plane (cleavage plane) of the SiC single crystal are formed on the side surfaces 5A-5D of the SiC semiconductor layer 2.

[0141] The insulating side surfaces 11A-11D of the main surface insulating layer 10 are continuous with the smooth surface regions 21A-21D. The insulating side surfaces 11A-11D are formed flush with the smooth surface regions 21A-21D. The insulating side surfaces 11A-11D are made of smooth cleavage surfaces. The insulating side surfaces 11A-11D form one smooth surface region with the smooth surface regions 21A-21D.

[0142] 8, in active region 8, an n-type diode region 35 is formed in a surface layer portion of first main surface 3 of SiC semiconductor layer 2. In this embodiment, diode region 35 is formed in the center of first main surface 3 of SiC semiconductor layer 2. In this embodiment, diode region 35 is set in a quadrangle shape having four sides parallel to side surfaces 5A-5D of SiC semiconductor layer 2 in plan view.

[0143] The n-type impurity concentration of the diode region 35 may be equal to or higher than the n-type impurity concentration of the SiC epitaxial layer 7. In this embodiment, the diode region 35 is formed by utilizing a part of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 35 is equal to the n-type impurity concentration of the SiC epitaxial layer 7. The diode region 35 may be formed by introducing an n-type impurity into a surface portion of the SiC epitaxial layer 7.

[0144] In the outer region 9, the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2 is + A mold guard region 36 is formed. The guard region 36 is formed in a strip shape extending along the diode region 35 in a plan view.

[0145] More specifically, the guard region 36 is formed in an endless shape (for example, a square ring shape, a square ring shape with chamfered corners, or a circular ring shape) surrounding the diode region 35 in a plan view. Thus, the guard region 36 is formed as a guard ring region. In this embodiment, the diode region 35 is defined by the guard region 36. In addition, the active region 8 is defined by the guard region 36.

[0146] The p-type impurities in the guard region 36 may not be activated. In this case, the guard region 36 is formed as a non-semiconductor region. The p-type impurities in the guard region 36 may be activated. In this case, the guard region 36 is formed as a p-type semiconductor region.

[0147] The aforementioned main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. A diode opening 37 that exposes the diode region 35 is formed in the main surface insulating layer 10. The diode opening 37 exposes the inner periphery of the guard region 36 in addition to the diode region 35. The diode opening 37 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0148] The above-mentioned first principal surface electrode layer 12 is formed on the principal surface insulating layer 10. The first principal surface electrode layer 12 extends into the diode opening 37 from above the insulating layer. The first principal surface electrode layer 12 is electrically connected to the diode region 35 in the diode opening 37.

[0149] More specifically, the first principal surface electrode layer 12 forms a Schottky junction with the diode region 35. This forms a Schottky barrier diode D with the first principal surface electrode layer 12 as the anode and the diode region 35 as the cathode. On the principal surface insulating layer 10, the aforementioned passivation layer 13 and resin layer 16 are formed.

[0150] FIG. 9 is a perspective view showing a SiC semiconductor wafer 41 used for manufacturing the SiC semiconductor device 1 shown in FIG.

[0151] The SiC semiconductor wafer 41 is a member that serves as the base of the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 includes a 4H-SiC single crystal as an example of a hexagonal SiC single crystal. In this form, the SiC semiconductor wafer 41 has an n-type impurity concentration corresponding to the n-type impurity concentration of the SiC semiconductor substrate 6.

[0152] The SiC semiconductor wafer 41 is formed in a plate shape or a disk shape. The SiC semiconductor wafer 41 may be formed in a disk shape. The SiC semiconductor wafer 41 has a first wafer main surface 42 on one side, a second wafer main surface 43 on the other side, and a wafer side surface 44 connecting the first wafer main surface 42 and the second wafer main surface 43.

[0153] The thickness TW of the SiC semiconductor wafer 41 exceeds the thickness TS of the SiC semiconductor substrate 6 (TS < TW). The thickness TW of the SiC semiconductor wafer 41 is adjusted to the thickness TS of the SiC semiconductor substrate 6 by grinding.

[0154] The thickness TW may be more than 150 μm and 750 μm or less. The thickness TW may be more than 150 μm and 300 μm or less, 300 μm or more and 450 μm or less, 450 μm or more and 600 μm or less, or 600 μm or more and 750 μm or less. Considering the grinding time of the SiC semiconductor wafer 41, the thickness TW is preferably more than 150 μm and 500 μm or less. The thickness TW is typically 300 μm or more and 450 μm or less.

[0155] In this form, the first wafer main surface 42 and the second wafer main surface 43 face the c-plane of the SiC single crystal. The first wafer main surface 42 faces the (0001) plane (silicon plane). The second wafer main surface 43 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0156] The first wafer main surface 42 and the second wafer main surface 43 have an off angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z of the first wafer main surface 42 is inclined by the off angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0157] The off angle θ may be 0° or more and 5.0° or less. The off angle θ may be set in the range of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. The off angle θ is preferably greater than 0°. The off angle θ may be less than 4.0°.

[0158] The off angle θ may be set in the range of 3.0° to 4.5° inclusive. In this case, the off angle θ is preferably set in the range of 3.0° to 3.5° inclusive or 3.5° to 4.0° inclusive.

[0159] The off angle θ may be set in the range of 1.5° to 3.0° inclusive. In this case, the off angle θ is preferably set in the range of 1.5° to 2.0° inclusive or 2.0° to 2.5° inclusive.

[0160] The SiC semiconductor wafer 41 includes a first wafer corner 45 connecting the first wafer main surface 42 and the wafer side surface 44, and a second wafer corner 46 connecting the second wafer main surface 43 and the wafer side surface 44. The first wafer corner 45 has a first chamfered portion 47 sloping downward from the first wafer main surface 42 toward the wafer side surface 44. The second wafer corner 46 has a second chamfered portion 48 sloping downward from the second wafer main surface 43 toward the wafer side surface 44.

[0161] The first chamfered portion 47 may be formed in a convex curved shape. The second chamfered portion 48 may be formed in a convex curved shape. The first chamfered portion 47 and the second chamfered portion 48 suppress cracks in the SiC semiconductor wafer 41.

[0162] An orientation flat 49 is formed on the wafer side surface 44 of the SiC semiconductor wafer 41 as an example of a mark indicating the crystal orientation of the SiC single crystal. The orientation flat 49 is a notch formed on the wafer side surface 44 of the SiC semiconductor wafer 41. In this embodiment, the orientation flat 49 extends linearly along the a-axis direction ([11-20] direction) of the SiC single crystal.

[0163] A plurality of (e.g., two) orientation flats 49 indicating a crystal orientation may be formed on the wafer side surface 44 of the SiC semiconductor wafer 41. The plurality of (e.g., two) orientation flats 49 may include a first orientation flat and a second orientation flat.

[0164] The first orientation flat may be a notch that extends linearly along the a-axis direction ([11-20] direction) of the SiC single crystal, and the second orientation flat may be a notch that extends linearly along the m-axis direction ([1-100] direction) of the SiC single crystal.

[0165] A plurality of device formation regions 51 each corresponding to a SiC semiconductor device 1 are defined on the first wafer main surface 42 of the SiC semiconductor wafer 41. The device formation regions 51 are defined in a matrix array at intervals in the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction).

[0166] Each device formation region 51 has four sides 52A, 52B, 52C, and 52D along the crystal orientation of the SiC single crystal. The four sides 52A to 52D respectively correspond to the four side surfaces 5A to 5D of the SiC semiconductor layer 2. The four sides 52A to 52D include two sides 52A and 52C along the m-axis direction ([1-100] direction) and two sides 52B and 52D along the a-axis direction ([11-20] direction).

[0167] The device formation regions 51 are each partitioned by a lattice of cutting lines 53 extending along the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction). The cutting lines 53 include a plurality of first cutting lines 54 and a plurality of second cutting lines 55.

[0168] The first lines to cut 54 each extend along the m-axis direction (the [1-100] direction). The second lines to cut 55 each extend along the a-axis direction (the [11-20] direction). After predetermined structures are formed in the device formation regions 51, the SiC semiconductor wafer 41 is cut along the lines to cut 53 to cut out the SiC semiconductor devices 1.

[0169] Figures 10A to 10M are cross-sectional views showing an example of a method for manufacturing the SiC semiconductor device 1 shown in Figure 3. For convenience of explanation, Figures 10A to 10M show only regions in which three SiC semiconductor devices 1 are formed, and omit illustration of other regions.

[0170] 10A, in manufacturing SiC semiconductor device 1, first, SiC semiconductor wafer 41 is prepared (also see FIG. 9). Next, n-type SiC epitaxial layer 7 is formed on first wafer main surface 42 of SiC semiconductor wafer 41.

[0171] In the step of forming the SiC epitaxial layer 7, SiC is epitaxially grown from the first wafer main surface 42 of the SiC semiconductor wafer 41. The thickness TE of the SiC epitaxial layer 7 may be not less than 1 μm and not more than 50 μm.

[0172] Thereby, a SiC semiconductor wafer structure 61 is formed, which includes the SiC semiconductor wafer 41 and the SiC epitaxial layer 7. The SiC semiconductor wafer structure 61 includes a first main surface 62 and a second main surface 63.

[0173] The first and second main surfaces 62, 63 of the SiC semiconductor wafer structure 61 correspond to the first and second main surfaces 3, 4, respectively, of the SiC semiconductor layer 2. The thickness TWS of the SiC semiconductor wafer structure 61 may be greater than 150 μm and not greater than 800 μm. The thickness TWS is preferably greater than 150 μm and not greater than 550 μm.

[0174] Next, referring to FIG. 10B, a p + A p-type guard region 36 is formed. The step of forming the guard region 36 includes a step of selectively introducing a p-type impurity into a surface layer portion of the first main surface 62 of the SiC semiconductor wafer structure 61 via an ion implantation mask (not shown). More specifically, the guard region 36 is formed in a surface layer portion of the SiC epitaxial layer 7.

[0175] The guard region 36 defines an active region 8 and an outer region 9 in the SiC semiconductor wafer structure 61. In the region surrounded by the guard region 36 (the active region 8), an n-type diode region 35 is defined.

[0176] The diode region 35 may be formed by selectively introducing n-type impurities into a surface layer portion of the first main surface 62 of the SiC semiconductor wafer structure 61 through an ion implantation mask (not shown).

[0177] 10C, a main surface insulating layer 10 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The main surface insulating layer 10 includes silicon oxide (SiO2). The main surface insulating layer 10 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (for example, a thermal oxidation treatment method).

[0178] 10D, a mask 64 having a predetermined pattern is formed on the main surface insulating layer 10. The mask 64 has a plurality of openings 65. The plurality of openings 65 each exposes an area in the main surface insulating layer 10 where the diode opening 37 is to be formed.

[0179] Next, unnecessary portions of the main surface insulating layer 10 are removed by an etching method via the mask 64. This forms a diode opening 37 in the main surface insulating layer 10. After the diode opening 37 is formed, the mask 64 is removed.

[0180] 10E, a base electrode layer 66 serving as a base for the first main surface electrode layer 12 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The base electrode layer 66 is formed over the entire first main surface 62 of the SiC semiconductor wafer structure 61, and covers the main surface insulating layer 10. The first main surface electrode layer 12 may be formed by a vapor deposition method, a sputtering method, or a plating method.

[0181] 10F, a mask 67 having a predetermined pattern is formed on the base electrode layer 66. The mask 67 has openings 68 that expose areas of the base electrode layer 66 other than the areas where the first principal surface electrode layer 12 is to be formed.

[0182] Next, unnecessary portions of the base electrode layer 66 are removed by an etching method through the mask 67. This divides the base electrode layer 66 into a plurality of first principal surface electrode layers 12. After the first principal surface electrode layers 12 are formed, the mask 67 is removed.

[0183] 10G, a passivation layer 13 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The passivation layer 13 includes silicon nitride (SiN). The passivation layer 13 may be formed by a CVD method.

[0184] 10H, a resin layer 16 is applied on the passivation layer 13. The resin layer 16 collectively covers the active region 8 and the outer region 9. The resin layer 16 may contain polybenzoxazole as an example of a positive type photosensitive resin.

[0185] 10I, the resin layer 16 is selectively exposed to light and then developed. As a result, pad openings 18 are formed in the resin layer 16. Also, dicing streets 69 are defined in the resin layer 16 along the cutting lines 53 (sides 52A to 52D of each device formation region 51).

[0186] Next, unnecessary portions of the passivation layer 13 are removed. The unnecessary portions of the passivation layer 13 may be removed by an etching method via the resin layer 16. As a result, subpad openings 15 are formed in the passivation layer 13. Also, dicing streets 69 are defined in the passivation layer 13 along the cutting lines 53.

[0187] 10J, the second main surface 63 of the SiC semiconductor wafer structure 61 (the second wafer main surface 43 of the SiC semiconductor wafer 41) is ground. This causes the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) to be thinned. In addition, grinding marks are formed on the second main surface 63 of the SiC semiconductor wafer structure 61.

[0188] The SiC semiconductor wafer structure 61 is ground to a thickness TWS corresponding to the thickness TL of the SiC semiconductor layer 2. The SiC semiconductor wafer structure 61 may be ground to a thickness TWS of 40 μm or more and 200 μm or less.

[0189] That is, the SiC semiconductor wafer 41 is ground until it has a thickness TW corresponding to the thickness TS of the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 may be ground until it has a thickness TW of not less than 40 μm and not more than 150 μm.

[0190] 10K, a plurality of modified lines 70 (modified layers) that become bases of the rough surface regions 20A-20D (modified lines 22A-22D) are formed. In the process of forming the modified lines 70, a pulsed laser beam is irradiated from a laser beam irradiation device 71 toward the SiC semiconductor wafer structure 61.

[0191] In this embodiment, the laser light is applied to the SiC semiconductor wafer structure 61 from the first main surface 62 side of the SiC semiconductor wafer structure 61 through the main surface insulating layer 10. The laser light may be applied directly to the SiC semiconductor wafer structure 61 from the second main surface 63 side of the SiC semiconductor wafer structure 61.

[0192] The focusing portion (focus) of the laser light is set at a midpoint in the thickness direction of the SiC semiconductor wafer structure 61. The irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the lines to cut 53 (the four sides 52A to 52D of each device formation region 51).

[0193] More specifically, the irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the first line to cut 54. In addition, the irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the second line to cut 55.

[0194] As a result, multiple modification lines 70 are formed in the middle of the thickness direction of the SiC semiconductor wafer structure 61, extending along the intended cutting lines 53 (the four sides 52A to 52D of each device formation region 51) and modifying the crystalline state of the SiC single crystal to properties different from those in other regions.

[0195] The two modified lines 70 along the sides 52A and 52C of the device formation region 51 each include an a-plane modified portion 28. The two modified lines 70 along the sides 52B and 52D of the device formation region 51 each include an m-plane modified portion 29.

[0196] The multiple modification lines 70 are formed in one or multiple layers (two or more layers; in this embodiment, two layers) in a one-to-one correspondence with the four sides 52A-52D of each device formation region 51. The multiple modification lines 70 are also laser processing marks formed in the middle of the thickness direction of the SiC semiconductor wafer structure 61. More specifically, the a-plane modified portion 28 and the m-plane modified portion 29 of the modification line 70 are laser processing marks.

[0197] The focused portion (focal point) of the laser light, the laser energy, the pulse duty ratio, the irradiation speed, etc. are determined to arbitrary values ​​depending on the position, size, shape, thickness, etc. of the modified line 70 (rough surface regions 20A to 20D) to be formed.

[0198] 10L, a second principal surface electrode layer 19 is formed on the second principal surface 63 of the SiC semiconductor wafer structure 61. The second principal surface electrode layer 19 may be formed by a vapor deposition method, a sputtering method, or a plating method.

[0199] Prior to the step of forming the second principal surface electrode layer 19, an annealing treatment may be performed on the second principal surface 63 (ground surface) of the SiC semiconductor wafer structure 61. The annealing treatment may be performed by a laser annealing method using laser light.

[0200] According to the laser annealing method, the SiC single crystal in the surface layer portion of the second main surface 63 of the SiC semiconductor wafer structure 61 is modified to form a Si amorphous layer. In this case, a SiC semiconductor device 1 having a Si amorphous layer in the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 is manufactured. On the second main surface 4 of the SiC semiconductor layer 2, grinding marks and a Si amorphous layer coexist. According to the laser annealing method, the ohmic property of the second main surface electrode layer 19 with respect to the second main surface 4 of the SiC semiconductor layer 2 can be improved.

[0201] 10M, a plurality of SiC semiconductor devices 1 are cut out from the SiC semiconductor wafer structure 61. In this step, a tape-shaped supporting member 73 is attached to the second main surface 63 side of the SiC semiconductor wafer structure 61.

[0202] Next, an external force is applied to the lines to cut 53 from the second main surface 63 side of the SiC semiconductor wafer structure 61 via the support member 73. The external force to the lines to cut 53 may be applied by a pressing member such as a blade.

[0203] In another embodiment, a support member 73 may be attached to the first main surface 62 side of the SiC semiconductor wafer structure 61. In this case, an external force may be applied to the line to cut 53 from the first main surface 62 side of the SiC semiconductor wafer structure 61 via the support member 73. The external force may be applied by a pressing member such as a blade.

[0204] In still another embodiment, a stretchable support member 73 may be attached to the first main surface 62 side or the second main surface 63 side of the SiC semiconductor wafer structure 61. In this case, the SiC semiconductor wafer structure 61 may be cleaved by stretching the stretchable support member 73 in the m-axis direction and the a-axis direction.

[0205] When the SiC semiconductor wafer structure 61 is cleaved using the support member 73, it is preferable that the support member 73 be attached to the second main surface 63 side of the SiC semiconductor wafer structure 61 where there are fewer obstacles.

[0206] In this manner, the SiC semiconductor wafer structure 61 is cleaved along the lines to be cut 53 starting from the modification lines 70, and a plurality of SiC semiconductor devices 1 are cut out from one SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).

[0207] The portion of the modified line 70 along the side 52A of each device formation region 51 becomes the rough surface region 20A (modified line 22A). The portion of the modified line 70 along the side 52B of each device formation region 51 becomes the rough surface region 20B (modified line 22B). The portion of the modified line 70 along the side 52C of each device formation region 51 becomes the rough surface region 20C (modified line 22C). The portion of the modified line 70 along the side 52D of each device formation region 51 becomes the rough surface region 20D (modified line 22D). The SiC semiconductor device 1 is manufactured through the processes including those described above.

[0208] In this embodiment, the grinding step (FIG. 10J) of the SiC semiconductor wafer structure 61 is performed prior to the forming step (FIG. 10K) of the modification line 70. However, the grinding step (FIG. 10J) of the SiC semiconductor wafer structure 61 may be performed at any timing after the preparing step (FIG. 10A) of the SiC semiconductor wafer 41 and before the forming step (FIG. 10L) of the second principal surface electrode layer 19.

[0209] For example, the grinding step of the SiC semiconductor wafer structure 61 (FIG. 10J) may be performed prior to the formation step of the SiC epitaxial layer 7 (FIG. 10A). Also, the grinding step of the SiC semiconductor wafer structure 61 (FIG. 10J) may be performed after the formation step of the modification line 70 (FIG. 10K).

[0210] Furthermore, the grinding step (FIG. 10J) of the SiC semiconductor wafer structure 61 may be performed in multiple steps at any timing after the preparation step (FIG. 10A) of the SiC semiconductor wafer 41 and before the formation step (FIG. 10K) of the modification line 70. Furthermore, the grinding step (FIG. 10J) of the SiC semiconductor wafer structure 61 may be performed in multiple steps at any timing after the preparation step (FIG. 10A) of the SiC semiconductor wafer 41 and before the formation step (FIG. 10L) of the second principal surface electrode layer 19.

[0211] FIG. 11 is a perspective view showing a semiconductor package 74 in which the SiC semiconductor device 1 is assembled, with a sealing resin 79 seen through.

[0212] 11, in this embodiment, a semiconductor package 74 is a so-called TO-220 type. The semiconductor package 74 includes a SiC semiconductor device 1, a pad portion 75, a heat sink 76, a plurality of terminals 77 (two in this embodiment), a plurality of conductive wires 78 (two in this embodiment), and a sealing resin 79. The pad portion 75, the heat sink 76, and the plurality of terminals 77 form a lead frame as an example of an object to be connected.

[0213] The pad portion 75 includes a metal plate. The pad portion 75 may include iron, gold, silver, copper, aluminum, or the like. The pad portion 75 is formed in a quadrangular shape in a plan view. The pad portion 75 has a planar area equal to or larger than the planar area of ​​the SiC semiconductor device 1. The SiC semiconductor device 1 is disposed on the pad portion 75.

[0214] The second principal surface electrode layer 19 of the SiC semiconductor device 1 is electrically connected to the pad portion 75 via a conductive bonding material 80. The conductive bonding material 80 is interposed in the region between the second principal surface electrode layer 19 and the pad portion 75.

[0215] The conductive bonding material 80 may be a metallic paste or a solder. The metallic paste may be a conductive paste containing Au (gold), Ag (silver) or Cu (copper). The conductive bonding material 80 is preferably made of solder. The solder may be a lead-free solder. The solder may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi or SnSbNi.

[0216] The heat sink 76 is connected to one side of the pad portion 75. In this embodiment, the pad portion 75 and the heat sink 76 are formed from a single metal plate. A through hole 76a is formed in the heat sink 76. The through hole 76a is formed in a circular shape.

[0217] The multiple terminals 77 are arranged along the side of the pad portion 75 opposite to the heat sink 76. Each of the multiple terminals 77 includes a metal plate. The terminals 77 may include iron, gold, silver, copper, aluminum, or the like.

[0218] The multiple terminals 77 include a first terminal 77A and a second terminal 77B. The first terminals 77A and the second terminals 77B are arranged at intervals along the side of the pad portion 75 opposite to the heat sink 76. The first terminals 77A and the second terminals 77B extend in a strip shape in a direction perpendicular to the direction in which they are arranged.

[0219] The plurality of conductors 78 may be bonding wires or the like. The plurality of conductors 78 include conductor 78A and conductor 78B. Conductor 78A is electrically connected to first terminal 77A and first principal surface electrode layer 12 of SiC semiconductor device 1. As a result, first terminal 77A is electrically connected to first principal surface electrode layer 12 of SiC semiconductor device 1 via conductor 78A.

[0220] Conductive wire 78B is electrically connected to second terminal 77B and pad portion 75. As a result, second terminal 77B is electrically connected to second main surface electrode layer 19 of SiC semiconductor device 1 via conductive wire 78B. Second terminal 77B may be formed integrally with pad portion 75.

[0221] Sealing resin 79 seals SiC semiconductor device 1, pad portion 75, and multiple conductive wires 78 so as to expose heat sink 76 and parts of multiple terminals 77. Sealing resin 79 is formed in a rectangular parallelepiped shape.

[0222] The form of the semiconductor package 74 is not limited to TO-220. As the semiconductor package 74, a small outline package (SOP), a quad flat non-leaded package (QFN), a dual flat package (DFP), a dual inline package (DIP), a quad flat package (QFP), a single inline package (SIP), a small outline J-leaded package (SOJ), or various forms similar thereto may be applied.

[0223] FIG. 12 is a perspective view specifically showing a mounting state of the SiC semiconductor device 1 shown in FIG.

[0224] 12, the SiC semiconductor device 1 is disposed on the pad portion 75 with the second main surface 4 of the SiC semiconductor layer 2 facing each other. The second main surface electrode layer 19 of the SiC semiconductor device 1 is electrically connected to the pad portion 75 via the conductive bonding material 80.

[0225] The conductive bonding material 80 includes a film-like conductive bonding material film 80a formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2. The conductive bonding material film 80a is a region where a part of the conductive bonding material 80 has spread in a film shape and wetted the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0226] When the rough surface regions 20A to 20D are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2, the conductive bonding material 80 spreads and wets the side surfaces 5A to 5D due to the capillary action occurring in the rough surface regions 20A to 20D. In this form, an example is shown in which the conductive bonding material 80 has spread and wetted the entire area of the rough surface regions 20A to 20D, and a conductive bonding material film 80a covering the entire area of the rough surface regions 20A to 20D is formed.

[0227] On the side surfaces 5A to 5D of the SiC semiconductor layer 2, smooth surface regions 21A to 21D are formed in the regions between the first main surface 3 and the rough surface regions 20A to 20D. The smooth surface regions 21A to 21D have a surface roughness Rs (Rs < Rr) that is less than the surface roughness Rr of the rough surface regions 20A to 20D.

[0228] The capillary action occurring in the rough surface regions 20A to 20D is suppressed by the smooth surface regions 21A to 21D. Therefore, the spreading and wetting of the conductive bonding material 80 on the side surfaces 5A to 5D are suppressed by the smooth surface regions 21A to 21D. In this form, the conductive bonding material film 80a has an end portion located in the middle of the thickness direction of the smooth surface regions 21A to 21D across the boundary between the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D.

[0229] Also, the smooth surface regions 21A to 21D are formed in the regions on the first main surface 3 side with respect to the rough surface regions 20A to 20D on the side surfaces 5A to 5D of the SiC semiconductor layer 2. Thereby, the smooth surface regions 21A to 21D suppress the intrusion of the conductive bonding material 80 into the first main surface 3.

[0230] In this manner, in the SiC semiconductor device 1, a short circuit of the SiC semiconductor layer 2 via the conductive bonding material 80 (conductive bonding material film 80a) is suppressed by the smooth surface regions 21A-21D. More specifically, a short circuit of the first principal surface electrode layer 12 and the second principal surface electrode layer 19 (pad portion 75) via the conductive bonding material 80 (conductive bonding material film 80a) is suppressed by the smooth surface regions 21A-21D. The short circuit may include one caused by a discharge phenomenon between the conductive bonding material 80 (conductive bonding material film 80a) and the first principal surface electrode layer 12.

[0231] The risk of a short circuit caused by the formation of the conductive bonding material film 80a increases as the area of ​​the side surfaces 5A-5D of the SiC semiconductor layer 2 decreases. That is, the smaller the thickness TL of the SiC semiconductor layer 2, the greater the risk of a short circuit caused by the formation of the conductive bonding material film 80a. The structure in which the smooth regions 21A-21D suppress the formation of the conductive bonding material film 80a is particularly effective when the thickness TL of the SiC semiconductor layer 2 is 40 μm or more and 200 μm or less.

[0232] As described above, according to the SiC semiconductor device 1, the capillary phenomenon occurring in the rough surface regions 20A-20D can be suppressed by the smooth surface regions 21A-21D, and therefore it is possible to suppress the wetting and spreading of the conductive bonding material 80 on the side surfaces 5A-5D of the SiC semiconductor layer 2. Therefore, it is possible to suppress short circuits caused by the wetting and spreading of the conductive bonding material 80.

[0233] Furthermore, according to the SiC semiconductor device 1, the rough surface regions 20A-20D are formed in the region on the second main surface 4 side of the SiC semiconductor layer 2, and the smooth surface regions 21A-21D are formed in the region on the first main surface 3 side of the SiC semiconductor layer 2 with respect to the rough surface regions 20A-20D. This makes it possible to appropriately prevent the conductive bonding material 80 from wrapping around the first main surface 3 of the SiC semiconductor layer 2. Therefore, it is possible to appropriately prevent a short circuit caused by the wetting and spreading of the conductive bonding material 80.

[0234] In particular, according to SiC semiconductor device 1, rough surface regions 20A-20D are formed in SiC semiconductor substrate 6, and smooth surface regions 21A-21D are formed in SiC epitaxial layer 7. It is preferable that smooth surface regions 21A-21D are formed in SiC semiconductor substrate 6 and SiC epitaxial layer 7 across the boundary between SiC semiconductor substrate 6 and SiC epitaxial layer 7.

[0235] This makes it possible to appropriately prevent the conductive bonding material 80 from spreading over the SiC epitaxial layer 7. This makes it possible to prevent short circuits and fluctuations in electrical characteristics of the semiconductor element (Schottky barrier diode D in this embodiment) caused by the conductive bonding material 80.

[0236] Moreover, the SiC semiconductor device 1 includes a main surface insulating layer 10 and a first main surface electrode layer 12 formed on the first main surface 3 of the SiC semiconductor layer 2. The main surface insulating layer 10 has insulating side surfaces 11A-11D continuous with the side surfaces 5A-5D of the SiC semiconductor layer 2.

[0237] In a structure in which rough surface regions 20A-20D are formed on the side surfaces 5A-5D of the SiC semiconductor layer 2, the main surface insulating layer 10 enhances insulation between the side surfaces 5A-5D of the SiC semiconductor layer 2 and the first main surface electrode layer 12.

[0238] This makes it possible to appropriately suppress short circuits caused by the wetting and spreading of the conductive bonding material 80 while suppressing the wetting and spreading of the conductive bonding material 80. Such a structure is also effective in suppressing discharge phenomena between the conductive bonding material 80 (conductive bonding material film 80a) and the first principal surface electrode layer 12.

[0239] Fig. 13A is a perspective view showing the SiC semiconductor device 1 shown in Fig. 3, and is a perspective view showing a second embodiment of the rough surface regions 20A-20D and the smooth surface regions 21A-21D. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0240] The rough surface regions 20A-20D according to the first embodiment are formed on the side surfaces 5A-5D of the SiC semiconductor layer 2 from corners on the second main surface 4 side to a middle portion in the thickness direction of the SiC semiconductor layer 2. In contrast, the rough surface regions 20A-20D according to the second embodiment are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. The rough surface regions 20A-20D expose surface portions of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A-5D.

[0241] In this embodiment, the rough surface regions 20A-20D are formed, each including one layer of the modified lines 22A-22D. The modified lines 22A-22D are formed one by one in a one-to-one correspondence in the middle of the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A-5D.

[0242] In this embodiment, smooth surface regions 21A-21D are formed on side surfaces 5A-5D in regions on the second main surface 4 side as well as in regions on the first main surface 3 side. Smooth surface regions 21A-21D on the second main surface 4 side are formed from the second main surface 4 to a thickness-wise midpoint of the SiC semiconductor layer 2. Smooth surface regions 21A-21D on the second main surface 4 side are formed on SiC semiconductor substrate 6.

[0243] The rough surface regions 20A to 20D according to the second embodiment are formed by adjusting the focusing portion (focus) of the laser light in the process of forming the modified lines 70 (rough surface regions 20A to 20D) (also see FIG. 10K).

[0244] As described above, even when the rough surface regions 20A-20D and smooth surface regions 21A-21D according to the second embodiment are formed, the same effects can be achieved as when the rough surface regions 20A-20D and smooth surface regions 21A-21D according to the first embodiment are formed.

[0245] In particular, according to the SiC semiconductor device 1 having the rough surface regions 20A-20D and the smooth surface regions 21A-21D of the second embodiment, the side surfaces 5A-5D also have the smooth surface regions 21A-21D in the regions on the second main surface 4 side. This makes it possible to suppress the wet spreading of the conductive bonding material 80 in the regions on the second main surface 4 side of the side surfaces 5A-5D. Therefore, it is possible to appropriately suppress short circuits caused by the wet spreading of the conductive bonding material 80.

[0246] Furthermore, in the manufacturing process of the SiC semiconductor device 1, a grinding step (FIG. 10J) is performed on the SiC semiconductor wafer structure 61. The thinned SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) allows the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) to be appropriately cleaved even without forming a plurality of modified lines 70 (rough surface regions 20A-20D) at intervals in the normal direction Z.

[0247] In other words, since the thinning process of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) is performed, the SiC semiconductor wafer structure 61 can be appropriately cleaved by the single layer of modification line 70. This makes it possible to shorten the time required for the process of forming the modification line 70.

[0248] This eliminates the need to form the rough surface regions 20A-20D at intervals in the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A-5D, thereby appropriately reducing the formation area of ​​the rough surface regions 20A-20D. This appropriately suppresses the wetting and spreading of the conductive bonding material 80 caused by the rough surface regions 20A-20D.

[0249] In this case, the second main surface 4 of the SiC semiconductor layer 2 is composed of a ground surface. The SiC semiconductor device 1 preferably includes a SiC semiconductor layer 2 having a thickness TL of 40 μm or more and 200 μm or less. The SiC semiconductor layer 2 having such a thickness TL can be appropriately cut out from the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).

[0250] In the SiC semiconductor layer 2, the thickness TS of the SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. In the SiC semiconductor layer 2, the thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. Thinning the SiC semiconductor layer 2 is also effective in reducing the resistance value.

[0251] Fig. 13B is a perspective view showing the SiC semiconductor device 1 shown in Fig. 3, and is a perspective view showing a third embodiment of the rough surface regions 20A-20D and the smooth surface regions 21A-21D. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0252] The rough surface regions 20A-20D according to the first embodiment are continuous with each other at corners connecting the side surfaces 5A-5D of the SiC semiconductor layer 2. In contrast, the rough surface regions 20A-20D according to the third embodiment are formed spaced apart from each other at corners connecting the side surfaces 5A-5D of the SiC semiconductor layer 2.

[0253] In this embodiment, rough surface regions 20A-20D are formed at intervals from second main surface 4 to first main surface 3 of SiC semiconductor layer 2. Rough surface regions 20A-20D expose surface portions of second main surface 4 of SiC semiconductor layer 2 from side surfaces 5A-5D.

[0254] In this embodiment, the rough surface regions 20A-20D are formed, each including one layer of the modified lines 22A-22D. The modified lines 22A-22D are formed one by one in a one-to-one correspondence in the middle of the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A-5D.

[0255] Rough surface region 20A and rough surface region 20B are formed at intervals from each other in normal direction Z at a corner connecting side surface 5A and side surface 5B of SiC semiconductor layer 2. Rough surface region 20B and rough surface region 20C are formed at intervals from each other in normal direction Z at a corner connecting side surface 5B and side surface 5C of SiC semiconductor layer 2.

[0256] Rough surface region 20C and rough surface region 20D are formed at intervals from each other in normal direction Z at a corner connecting side surface 5C and side surface 5D of SiC semiconductor layer 2. Rough surface region 20D and rough surface region 20A are formed at intervals from each other in normal direction Z at a corner connecting side surface 5D and side surface 5A of SiC semiconductor layer 2.

[0257] Of course, at least one of rough surface regions 20A-20D may be formed spaced apart from the other rough surface regions 20A-20D at a corner connecting any of side surfaces 5A-5D of SiC semiconductor layer 2. Two or three of rough surface regions 20A-20D may be connected to one another at a corner connecting any of side surfaces 5A-5D of SiC semiconductor layer 2.

[0258] In this embodiment, smooth surface regions 21A-21D are formed on side surfaces 5A-5D in regions on the second main surface 4 side as well as in regions on the first main surface 3 side. Smooth surface regions 21A-21D on the second main surface 4 side are formed from the second main surface 4 to a thickness-wise midpoint of the SiC semiconductor layer 2. Smooth surface regions 21A-21D on the second main surface 4 side are formed on SiC semiconductor substrate 6.

[0259] The rough surface regions 20A to 20D according to the third embodiment are formed by adjusting the focusing portion (focus) of the laser light in the process of forming the modified lines 70 (rough surface regions 20A to 20D) (also see FIG. 10K).

[0260] As described above, even when the rough surface regions 20A-20D and smooth surface regions 21A-21D according to the third embodiment are formed, the same effects can be achieved as when the rough surface regions 20A-20D and smooth surface regions 21A-21D according to the first and second embodiments are formed.

[0261] Fig. 13C is a perspective view showing the SiC semiconductor device 1 shown in Fig. 3, and is a perspective view showing a fourth embodiment of the rough surface regions 20A-20D and the smooth surface regions 21A-21D. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0262] The rough surface regions 20A-20D according to the first embodiment are formed in stripes extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, the rough surface regions 20A-20D according to the fourth embodiment are formed in stripes extending in a downwardly sloping manner from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2.

[0263] In this embodiment, rough surface regions 20A-20D are formed at intervals from second main surface 4 to first main surface 3 of SiC semiconductor layer 2. Rough surface regions 20A-20D expose surface portions of second main surface 4 of SiC semiconductor layer 2 from side surfaces 5A-5D.

[0264] In this embodiment, the rough surface regions 20A-20D are formed, each including one layer of the modified lines 22A-22D. The modified lines 22A-22D are formed one by one in a one-to-one correspondence in the middle of the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A-5D.

[0265] More specifically, the rough surface regions 20A to 20D according to the fourth embodiment each include a first end region 81, a second end region 82, and an inclined region 83. The first end region 81 is located on the first main surface 3 side of the SiC semiconductor layer 2 in the vicinity of a corner of the SiC semiconductor layer 2. The second end region 82 is located on the second main surface 4 side of the SiC semiconductor layer 2 relative to the first end region 81 in the vicinity of the corner of the SiC semiconductor layer 2. The inclined region 83 slopes downward from the first main surface 3 toward the second main surface 4 in a region between the first end region 81 and the second end region 82.

[0266] A first end region 81 of rough surface region 20A and a first end region 81 of rough surface region 20B may be located at a corner connecting side surface 5A and side surface 5B in SiC semiconductor layer 2. A second end region 82 of rough surface region 20A and a second end region 82 of rough surface region 20B may be located at a corner connecting side surface 5A and side surface 5B in SiC semiconductor layer 2.

[0267] A first end region 81 of rough surface region 20A and a second end region 82 of rough surface region 20B may be located at a corner connecting side surface 5A and side surface 5B in SiC semiconductor layer 2. A second end region 82 of rough surface region 20A and a first end region 81 of rough surface region 20B may be located at a corner connecting side surface 5A and side surface 5B in SiC semiconductor layer 2.

[0268] Rough surface region 20A and rough surface region 20B may be continuous with each other at a corner portion connecting side surface 5A and side surface 5B of SiC semiconductor layer 2, or may be formed with a gap between them.

[0269] A first end region 81 of rough surface region 20B and a first end region 81 of rough surface region 20C may be located at a corner connecting side surface 5B and side surface 5C in SiC semiconductor layer 2. A second end region 82 of rough surface region 20B and a second end region 82 of rough surface region 20C may be located at a corner connecting side surface 5B and side surface 5C in SiC semiconductor layer 2.

[0270] A first end region 81 of rough surface region 20B and a second end region 82 of rough surface region 20C may be located at a corner connecting side surface 5B and side surface 5C in SiC semiconductor layer 2. A second end region 82 of rough surface region 20B and a first end region 81 of rough surface region 20C may be located at a corner connecting side surface 5B and side surface 5C in SiC semiconductor layer 2.

[0271] Rough surface region 20B and rough surface region 20C may be continuous with each other at a corner portion connecting side surface 5B and side surface 5C of SiC semiconductor layer 2, or may be formed with a gap between them.

[0272] A first end region 81 of rough surface region 20C and a first end region 81 of rough surface region 20D may be located at a corner connecting side surface 5C and side surface 5D in SiC semiconductor layer 2. A second end region 82 of rough surface region 20C and a second end region 82 of rough surface region 20D may be located at a corner connecting side surface 5C and side surface 5D in SiC semiconductor layer 2.

[0273] A first end region 81 of rough surface region 20C and a second end region 82 of rough surface region 20D may be located at a corner connecting side surface 5C and side surface 5D in SiC semiconductor layer 2. A second end region 82 of rough surface region 20C and a first end region 81 of rough surface region 20D may be located at a corner connecting side surface 5C and side surface 5D in SiC semiconductor layer 2.

[0274] Rough surface region 20C and rough surface region 20D may be continuous with each other at a corner portion connecting side surface 5C and side surface 5D of SiC semiconductor layer 2, or may be formed with a gap between them.

[0275] A first end region 81 of rough surface region 20D and a first end region 81 of rough surface region 20A may be located at a corner connecting side surface 5D and side surface 5A in SiC semiconductor layer 2. A second end region 82 of rough surface region 20D and a second end region 82 of rough surface region 20A may be located at a corner connecting side surface 5D and side surface 5A in SiC semiconductor layer 2.

[0276] A first end region 81 of rough surface region 20D and a second end region 82 of rough surface region 20A may be located at a corner connecting side surface 5D and side surface 5A in SiC semiconductor layer 2. A second end region 82 of rough surface region 20D and a first end region 81 of rough surface region 20A may be located at a corner connecting side surface 5D and side surface 5A in SiC semiconductor layer 2.

[0277] Rough surface region 20D and rough surface region 20A may be continuous with each other at a corner portion connecting side surface 5D and side surface 5A of SiC semiconductor layer 2, or may be formed with a gap between them.

[0278] In this embodiment, smooth surface regions 21A-21D are formed on side surfaces 5A-5D in regions on the second main surface 4 side as well as in regions on the first main surface 3 side. Smooth surface regions 21A-21D on the second main surface 4 side are formed from the second main surface 4 to a thickness-wise midpoint of the SiC semiconductor layer 2. Smooth surface regions 21A-21D on the second main surface 4 side are formed on SiC semiconductor substrate 6.

[0279] The rough surface regions 20A to 20D according to the fourth embodiment are formed by adjusting the focusing portion (focus) of the laser light in the process of forming the modified lines 70 (rough surface regions 20A to 20D) (also see FIG. 10K).

[0280] As described above, even when the rough surface regions 20A-20D and smooth surface regions 21A-21D of the fourth embodiment are formed, the same effects can be achieved as when the rough surface regions 20A-20D and smooth surface regions 21A-21D of the first and second embodiments are formed.

[0281] In particular, according to the modified line 70 that is the base of the rough surface regions 20A-20D in the fourth embodiment, cleavage origins can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). This allows the SiC semiconductor wafer structure 61 to be appropriately cleaved even when the modified line 70 (rough surface regions 20A-20D) made of one layer is formed.

[0282] Fig. 13D is a perspective view showing the SiC semiconductor device 1 shown in Fig. 3, and is a perspective view showing a fifth embodiment of the rough surface regions 20A-20D and the smooth surface regions 21A-21D. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0283] The rough surface regions 20A-20D according to the first embodiment are formed in stripes extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, the rough surface regions 20A-20D according to the fifth embodiment are formed in stripes extending in a curved (curved) manner and sloping downward from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2.

[0284] In this embodiment, rough surface regions 20A-20D are formed at intervals from second main surface 4 to first main surface 3 of SiC semiconductor layer 2. Rough surface regions 20A-20D expose surface portions of second main surface 4 of SiC semiconductor layer 2 from side surfaces 5A-5D.

[0285] In this embodiment, the rough surface regions 20A-20D are formed, each including one layer of the modified lines 22A-22D. The modified lines 22A-22D are formed one by one in a one-to-one correspondence in the middle of the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A-5D.

[0286] More specifically, the rough surface regions 20A-20D according to the fifth embodiment each include a first end region 84, a second end region 85, and a curved region 86. The first end region 84 is located on the first main surface 3 side of the SiC semiconductor layer 2 in the vicinity of a corner of the SiC semiconductor layer 2. The second end region 85 is located on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the first end region 84 in the vicinity of the corner of the SiC semiconductor layer 2.

[0287] The curved region 86 slopes downward in a concave curve from the first main surface 3 toward the second main surface 4, and connects the first end region 84 and the second end region 85. The curved region 86 may also slope downward in a convex curve from the first main surface 3 toward the second main surface 4.

[0288] A first end region 84 of rough surface region 20A and a first end region 84 of rough surface region 20B may be located at a corner connecting side surface 5A and side surface 5B in SiC semiconductor layer 2. A second end region 85 of rough surface region 20A and a second end region 85 of rough surface region 20B may be located at a corner connecting side surface 5A and side surface 5B in SiC semiconductor layer 2.

[0289] A first end region 84 of rough surface region 20A and a second end region 85 of rough surface region 20B may be located at a corner connecting side surface 5A and side surface 5B in SiC semiconductor layer 2. A second end region 85 of rough surface region 20A and a first end region 84 of rough surface region 20B may be located at a corner connecting side surface 5A and side surface 5B in SiC semiconductor layer 2.

[0290] Rough surface region 20A and rough surface region 20B may be continuous with each other at a corner portion connecting side surface 5A and side surface 5B of SiC semiconductor layer 2, or may be formed with a gap between them.

[0291] A first end region 84 of rough surface region 20B and a first end region 84 of rough surface region 20C may be located at a corner connecting side surface 5B and side surface 5C in SiC semiconductor layer 2. A second end region 85 of rough surface region 20B and a second end region 85 of rough surface region 20C may be located at a corner connecting side surface 5B and side surface 5C in SiC semiconductor layer 2.

[0292] A first end region 84 of rough surface region 20B and a second end region 85 of rough surface region 20C may be located at a corner connecting side surface 5B and side surface 5C in SiC semiconductor layer 2. A second end region 85 of rough surface region 20B and a first end region 84 of rough surface region 20C may be located at a corner connecting side surface 5B and side surface 5C in SiC semiconductor layer 2.

[0293] Rough surface region 20B and rough surface region 20C may be continuous with each other at a corner portion connecting side surface 5B and side surface 5C of SiC semiconductor layer 2, or may be formed with a gap between them.

[0294] A first end region 84 of rough surface region 20C and a first end region 84 of rough surface region 20D may be located at a corner connecting side surface 5C and side surface 5D in SiC semiconductor layer 2. A second end region 85 of rough surface region 20C and a second end region 85 of rough surface region 20D may be located at a corner connecting side surface 5C and side surface 5D in SiC semiconductor layer 2.

[0295] A first end region 84 of rough surface region 20C and a second end region 85 of rough surface region 20D may be located at a corner connecting side surface 5C and side surface 5D in SiC semiconductor layer 2. A second end region 85 of rough surface region 20C and a first end region 84 of rough surface region 20D may be located at a corner connecting side surface 5C and side surface 5D in SiC semiconductor layer 2.

[0296] Rough surface region 20C and rough surface region 20D may be continuous with each other at a corner portion connecting side surface 5C and side surface 5D of SiC semiconductor layer 2, or may be formed with a gap between them.

[0297] A first end region 84 of rough surface region 20D and a first end region 84 of rough surface region 20A may be located at a corner connecting side surface 5D and side surface 5A in SiC semiconductor layer 2. A second end region 85 of rough surface region 20D and a second end region 85 of rough surface region 20A may be located at a corner connecting side surface 5D and side surface 5A in SiC semiconductor layer 2.

[0298] A first end region 84 of rough surface region 20D and a second end region 85 of rough surface region 20A may be located at a corner connecting side surface 5D and side surface 5A in SiC semiconductor layer 2. A second end region 85 of rough surface region 20D and a first end region 84 of rough surface region 20A may be located at a corner connecting side surface 5D and side surface 5A in SiC semiconductor layer 2.

[0299] Rough surface region 20D and rough surface region 20A may be continuous with each other at a corner portion connecting side surface 5D and side surface 5A of SiC semiconductor layer 2, or may be formed with a gap between them.

[0300] In this embodiment, smooth surface regions 21A-21D are formed on side surfaces 5A-5D in regions on the second main surface 4 side as well as in regions on the first main surface 3 side. Smooth surface regions 21A-21D on the second main surface 4 side are formed from the second main surface 4 to a thickness-wise midpoint of the SiC semiconductor layer 2. Smooth surface regions 21A-21D on the second main surface 4 side are formed on SiC semiconductor substrate 6.

[0301] The rough surface regions 20A to 20D according to the fifth embodiment are formed by adjusting the focusing portion (focus) of the laser light in the process of forming the modified lines 70 (rough surface regions 20A to 20D) (also see FIG. 10K).

[0302] As described above, even when the rough surface regions 20A-20D and smooth surface regions 21A-21D of the fifth embodiment are formed, the same effects can be achieved as when the rough surface regions 20A-20D and smooth surface regions 21A-21D of the first and second embodiments are formed.

[0303] In particular, according to the modified line 70 that is the base of the rough surface regions 20A-20D in the fifth embodiment, cleavage origins can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). This allows the SiC semiconductor wafer structure 61 to be appropriately cleaved even when the modified line 70 (rough surface regions 20A-20D) made of one layer is formed.

[0304] Fig. 13E is a perspective view showing the SiC semiconductor device 1 shown in Fig. 3, and is a perspective view showing a sixth embodiment of the rough surface regions 20A-20D and the smooth surface regions 21A-21D. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals and will not be described.

[0305] The rough surface regions 20A-20D according to the first embodiment are formed in strips extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, the rough surface regions 20A-20D according to the sixth embodiment are formed in strips extending in a meandering curved (curved) shape toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2.

[0306] In this embodiment, rough surface regions 20A-20D are formed at intervals from second main surface 4 to first main surface 3 of SiC semiconductor layer 2. Rough surface regions 20A-20D expose surface portions of second main surface 4 of SiC semiconductor layer 2 from side surfaces 5A-5D.

[0307] In this embodiment, the rough surface regions 20A-20D are formed, each including one layer of the modified lines 22A-22D. The modified lines 22A-22D are formed one by one in a one-to-one correspondence in the middle of the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A-5D.

[0308] More specifically, each of rough surface regions 20A-20D includes a plurality of first regions 87, a plurality of second regions 88, and a plurality of connection regions 89. The plurality of first regions 87 are located in a region on the first main surface 3 side of SiC semiconductor layer 2. The plurality of second regions 88 are located in a region on the second main surface 4 side of SiC semiconductor layer 2 with respect to the plurality of first regions 87. The plurality of curved regions 86 connect the corresponding first regions 87 and second regions 88, respectively.

[0309] Rough surface region 20A and rough surface region 20B may be continuous with each other at a corner portion connecting side surface 5A and side surface 5B of SiC semiconductor layer 2, or may be formed with a gap between them.

[0310] Rough surface region 20B and rough surface region 20C may be continuous with each other at a corner portion connecting side surface 5B and side surface 5C of SiC semiconductor layer 2, or may be formed with a gap between them.

[0311] Rough surface region 20C and rough surface region 20D may be continuous with each other at a corner portion connecting side surface 5C and side surface 5D of SiC semiconductor layer 2, or may be formed with a gap between them.

[0312] Rough surface region 20D and rough surface region 20A may be continuous with each other at a corner portion connecting side surface 5D and side surface 5A of SiC semiconductor layer 2, or may be formed with a gap between them.

[0313] In this embodiment, smooth surface regions 21A-21D are formed on side surfaces 5A-5D in regions on the second main surface 4 side as well as in regions on the first main surface 3 side. Smooth surface regions 21A-21D on the second main surface 4 side are formed from the second main surface 4 to a thickness-wise midpoint of the SiC semiconductor layer 2. Smooth surface regions 21A-21D on the second main surface 4 side are formed on SiC semiconductor substrate 6.

[0314] The meandering period of rough surface regions 20A-20D is arbitrary. Rough surface regions 20A-20D may each be formed in a band shape extending in a concave curve from first main surface 3 toward second main surface 4. In this case, rough surface regions 20A-20D may each include two first regions 87, one second region 88, and two connection regions 89.

[0315] Furthermore, rough surface regions 20A-20D may each be formed in a belt shape extending in a convex curve from second main surface 4 toward first main surface 3. In this case, rough surface regions 20A-20D may each include one first region 87, two second regions 88, and two connection regions 89.

[0316] The rough surface regions 20A to 20D according to the sixth embodiment are formed by adjusting the focusing portion (focus) of the laser light in the process of forming the modified lines 70 (rough surface regions 20A to 20D) (also see FIG. 10K).

[0317] As described above, even when the rough surface regions 20A-20D and smooth surface regions 21A-21D of the sixth embodiment are formed, the same effects can be achieved as when the rough surface regions 20A-20D and smooth surface regions 21A-21D of the first and second embodiments are formed.

[0318] In particular, according to the modified line 70 serving as the base of the rough surface regions 20A-20D in the sixth embodiment, cleavage origins can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). This allows the SiC semiconductor wafer structure 61 to be appropriately cleaved even when the modified line 70 (rough surface regions 20A-20D) made of one layer is formed.

[0319] Fig. 13F is a perspective view showing the SiC semiconductor device 1 shown in Fig. 3, and is a perspective view showing a seventh embodiment of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0320] The rough surface regions 20A-20D according to the first embodiment are formed in the same shape as the side surfaces 5A-5D of the SiC semiconductor layer 2. In contrast, the rough surface regions 20A-20D according to the seventh embodiment are formed with different exclusive ratios RA, RB, RC, and RD on the side surfaces 5A-5D of the SiC semiconductor layer 2. The exclusive ratios RA-RD are the ratios that the rough surface regions 20A-20D occupy of the side surfaces 5A-5D.

[0321] In this embodiment, rough surface regions 20A-20D are formed at intervals from second main surface 4 to first main surface 3 of SiC semiconductor layer 2. Rough surface regions 20A-20D expose surface portions of second main surface 4 of SiC semiconductor layer 2 from side surfaces 5A-5D.

[0322] In this embodiment, the rough surface regions 20A, 20C including two layers of modified lines 22A, 22C are formed, and the rough surface regions 20B, 20D including one layer of modified lines 22B, 22D are formed. The modified lines 22A to 22D may be formed one by one in a one-to-one correspondence in the middle of the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A to 5D.

[0323] More specifically, the exclusive ratios RA to RD differ depending on the crystal plane of the SiC single crystal. The exclusive ratios RB, RD of the rough surface regions 20B, 20D formed on the m-plane of the SiC single crystal are equal to or less than the exclusive ratios RA, RC of the rough surface regions 20A, 20C formed on the a-plane of the SiC single crystal (RB, RD≦RA, RC). More specifically, the exclusive ratios RB, RD are less than the exclusive ratios RA, RC (RB, RD <RA,RC)である。

[0324] The ratios RA and RC of the rough surface regions 20A and 20C may be equal to each other or different from each other. The ratios RB and RD of the rough surface regions 20B and 20D may be equal to each other or different from each other.

[0325] In this embodiment, the surface areas of the roughened regions 20B and 20D on the sides 5B and 5D are less than the surface areas of the roughened regions 20A and 20C on the sides 5A and 5C, respectively. In this embodiment, the thicknesses TR of the roughened regions 20B and 20D are less than the thicknesses TR of the roughened regions 20A and 20C, respectively.

[0326] In this embodiment, smooth surface regions 21A-21D are formed on side surfaces 5A-5D in regions on the second main surface 4 side as well as in regions on the first main surface 3 side. Smooth surface regions 21A-21D on the second main surface 4 side are formed from the second main surface 4 to a thickness-wise midpoint of the SiC semiconductor layer 2. Smooth surface regions 21A-21D on the second main surface 4 side are formed on SiC semiconductor substrate 6.

[0327] The rough surface regions 20A to 20D according to the seventh embodiment are formed by adjusting the focusing portion (focus) of the laser light in the process of forming the modified lines 70 (rough surface regions 20A to 20D) (also see FIG. 10K).

[0328] As described above, even when the rough surface regions 20A-20D and smooth surface regions 21A-21D of the seventh embodiment are formed, the same effects can be achieved as when the rough surface regions 20A-20D and smooth surface regions 21A-21D of the first and second embodiments are formed.

[0329] In particular, the rough surface regions 20A-20D according to the seventh embodiment are formed with different exclusive ratios RA-RD, respectively, on the side surfaces 5A-5D of the SiC semiconductor layer 2. More specifically, the rough surface regions 20A-20D have different exclusive ratios RA-RD according to the crystal planes of the SiC single crystal.

[0330] The exclusive ratios RB, RD of rough surface regions 20B, 20D formed on the m-plane of the SiC single crystal are equal to or less than the exclusive ratios RA, RC of rough surface regions 20A, 20C formed on the a-plane of the SiC single crystal (RB, RD≦RA, RC).

[0331] SiC single crystals have the physical property that they easily crack along the nearest atomic direction (see also Figures 1 and 2) when viewed from the c-axis of the c-plane (silicon plane), but are difficult to crack along the direction intersecting the nearest atomic direction. The nearest atomic direction is the a-axis direction and its equivalent direction. The direction intersecting the nearest atomic direction is the m-axis direction and its equivalent direction.

[0332] Therefore, in the process of forming the modified lines 70 (rough surface regions 20A-20D), the crystal plane along the nearest neighbor atomic direction of the SiC single crystal has a relatively easy tendency to break, so the SiC single crystal can be appropriately cut (cleaved) without forming the modified lines 70 (rough surface regions 20A-20D) having a relatively large proportion of the surface area (see also FIG. 10L). The crystal plane along the nearest neighbor atomic direction is the m-plane and its equivalent planes.

[0333] In other words, in the process of forming the modified lines 70 (rough surface regions 20A-20D), the occupancy ratio of the modified lines 70 (rough surface regions 20A-20D) along the second lines to cut 55 extending in the a-axis direction can be made smaller than the occupancy ratio of the modified lines 70 (rough surface regions 20A-20D) along the first lines to cut 54 extending in the m-axis direction.

[0334] On the other hand, a modification line 70 having a relatively large proportion of monopoly is formed on the crystal plane along the intersecting direction of the nearest neighbor atomic direction of the SiC single crystal. This makes it possible to suppress inappropriate cutting (cleavage) of the SiC semiconductor wafer structure 61, and therefore to appropriately suppress the occurrence of cracks due to the physical properties of the SiC single crystal. The crystal plane along the intersecting direction of the nearest neighbor atomic direction is the a-plane and its equivalent plane.

[0335] In this way, according to the rough surface regions 20A-20D and the smooth surface regions 21A-21D of the seventh embodiment, the physical properties of the SiC single crystal can be utilized to adjust and reduce the occupation ratios RA-RD of the rough surface regions 20A-20D to the side surfaces 5A-5D.

[0336] In other words, the ratio of the smooth surface regions 21A-21D to the side surfaces 5A-5D can be increased by utilizing the physical properties of the SiC single crystal. As a result, it is possible to appropriately suppress short circuits caused by the wetting and spreading of the conductive bonding material 80. In addition, the time required for the process of forming the modified line 70 can be shortened.

[0337] The exclusive ratios RA to RD may be adjusted by the surface areas of the rough surface regions 20A to 20D relative to the side surfaces 5A to 5D. The exclusive ratios RA to RD may be adjusted by the thicknesses TR of the rough surface regions 20A to 20D. The exclusive ratios RA to RD may be adjusted by the numbers of the modified lines 22A to 22D included in the rough surface regions 20A to 20D.

[0338] Fig. 13G is a perspective view showing the SiC semiconductor device 1 shown in Fig. 3, and is a perspective view showing an eighth embodiment of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0339] In the first embodiment, rough surface regions 20A-20D are formed in the regions of side surfaces 5A-5D on the second main surface 4 side of SiC semiconductor layer 2, and smooth surface regions 21A-21D are formed in the regions of side surfaces 5A-5D on the first main surface 3 side of SiC semiconductor layer 2.

[0340] In contrast, in the eighth embodiment, the rough surface regions 20A-20D are formed in the regions of the side surfaces 5A-5D facing the first main surface 3 of the SiC semiconductor layer 2, and the smooth surface regions 21A-21D are formed in the regions of the side surfaces 5A-5D facing the second main surface 4 of the SiC semiconductor layer 2. In this embodiment, the rough surface regions 20A-20D including two layers of modified lines 22A-22D are formed.

[0341] More specifically, rough surface regions 20A-20D are formed at intervals on side surfaces 5A-5D from second main surface 4 to first main surface 3 of SiC semiconductor layer 2. Rough surface regions 20A-20D expose surface portions of second main surface 4 of SiC semiconductor layer 2 from side surfaces 5A-5D.

[0342] In this embodiment, the rough surface regions 20A-20D are formed in the SiC epitaxial layer 7. More specifically, the rough surface regions 20A-20D are formed in both the SiC epitaxial layer 7 and the SiC semiconductor substrate 6, across the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7.

[0343] Smooth surface regions 21A-21D are formed from second main surface 4 to a thickness-wise middle portion of SiC semiconductor layer 2. Smooth surface regions 21A-21D are formed on SiC semiconductor substrate 6 in regions of side surfaces 5A-5D on the second main surface 4 side.

[0344] In this embodiment, the first main surface 3 of the SiC semiconductor layer 2 is formed as a mounting surface, and the second main surface 4 of the SiC semiconductor layer 2 is formed as a non-mounting surface. That is, the SiC semiconductor layer 2 is mounted face-down on a connection object with the first main surface 3 facing the connection object.

[0345] The rough surface regions 20A to 20D according to the eighth embodiment are formed by adjusting the focusing portion (focus) of the laser light in the process of forming the modified lines 70 (rough surface regions 20A to 20D) (also see FIG. 10K).

[0346] As described above, when the rough surface regions 20A-20D and the smooth surface regions 21A-21D according to the eighth embodiment are formed, it is possible to suppress the conductive bonding material 80 from spreading from the first main surface 3 side toward the second main surface 4 side. Therefore, it is possible to achieve the same effect as when the rough surface regions 20A-20D and the smooth surface regions 21A-21D according to the first embodiment are formed.

[0347] A SiC semiconductor device 1 may be formed that simultaneously includes at least two of the rough surface regions 20A-20D (smooth surface regions 21A-21D) according to the first, second, third, fourth, fifth, sixth, seventh and eighth embodiment examples (hereinafter simply referred to as "the first to eighth embodiment examples").

[0348] Furthermore, the features of the rough surface regions 20A-20D (smooth surface regions 21A-21D) according to the first to eighth embodiment examples can be combined in any manner and in any form. In other words, the rough surface regions 20A-20D (smooth surface regions 21A-21D) having a form in which at least two features of the rough surface regions 20A-20D (smooth surface regions 21A-21D) according to the first to eighth embodiment examples are combined may be employed.

[0349] In the second to seventh embodiment examples, the smooth surface regions 21A to 21D are formed in the regions on the second main surface 4 side of the side surfaces 5A to 5D. Therefore, the SiC semiconductor device 1 shown in the second to seventh embodiment examples may be mounted face-down on a connection object with the SiC semiconductor layer 2 facing the first main surface 3 as in the eighth embodiment example. That is, in the second to seventh embodiment examples, the first main surface 3 of the SiC semiconductor layer 2 may be the mounting surface, and the second main surface 4 may be the non-mounting surface.

[0350] Furthermore, the features of the rough surface regions 20A-20D (smooth surface regions 21A-21D) according to the fourth embodiment may be combined with the features of the rough surface regions 20A-20D (smooth surface regions 21A-21D) according to the sixth embodiment. In this case, strip-shaped rough surface regions 20A-20D are formed that slope downward from the first main surface 3 toward the second main surface 4 of the SiC semiconductor layer 2 and extend in a meandering curved shape (curved shape) toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2.

[0351] 14 is a perspective view showing a SiC semiconductor device 91 according to a second embodiment of the present invention, and showing a structure to which the rough surface regions 20A-20D and smooth surface regions 21A-21D according to the first embodiment are applied. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals and will not be described.

[0352] In this embodiment, the rough surface regions 20A-20D and smooth surface regions 21A-21D according to the first embodiment are applied. However, instead of or in addition to the rough surface regions 20A-20D according to the first embodiment, the rough surface regions 20A-20D and smooth surface regions 21A-21D according to the second, third, fourth, fifth, sixth, seventh, or eighth embodiment may be adopted.

[0353] Furthermore, the rough surface regions 20A to 20D (smooth surface regions 21A to 21D) may have a configuration in which at least two of the features of the rough surface regions 20A to 20D (smooth surface regions 21A to 21D) according to the first to eighth embodiment examples are combined.

[0354] 14, in this embodiment, insulating side surfaces 11A-11D of main surface insulating layer 10 are formed at intervals in an inner region from side surfaces 5A-5D of SiC semiconductor layer 2 in a plan view. Main surface insulating layer 10 exposes a peripheral portion of first main surface 3 of SiC semiconductor layer 2 in a plan view.

[0355] The main surface insulating layer 10, together with the resin layer 16 and the passivation layer 13, exposes the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2. In this embodiment, the insulating side surfaces 11A-11D of the main surface insulating layer 10 are formed flush with the resin side surfaces 17A-17D of the resin layer 16 and the side surfaces 14A-14D of the passivation layer 13. In this embodiment, the insulating side surfaces 11A-11D of the main surface insulating layer 10 also form parts that define the dicing streets.

[0356] This main surface insulating layer 10 is formed by carrying out a step of removing the main surface insulating layer 10 by an etching method after the step of removing the passivation layer 13 in the step of FIG. 10I described above.

[0357] In this case, in the step of FIG. 10K described above, the inside of the SiC semiconductor wafer structure 61 may be directly irradiated with laser light from the first main surface 62 side of the SiC semiconductor wafer structure 61 without passing through the main surface insulating layer 10.

[0358] As described above, the SiC semiconductor device 91 can also achieve the same effects as those described for the SiC semiconductor device 1. However, in terms of improving the insulation between the side surfaces 5A-5D of the SiC semiconductor layer 2 and the first principal surface electrode layer 12, the structure of the SiC semiconductor device 1 according to the first embodiment is preferable.

[0359] Fig. 15 is a perspective view of a SiC semiconductor device 101 according to a third embodiment of the present invention, seen from one angle, showing a structure to which rough surface regions 20A-20D and smooth surface regions 21A-21D according to the first embodiment are applied. Fig. 16 is a perspective view of the SiC semiconductor device 101 shown in Fig. 15, seen from another angle. Fig. 17 is a plan view showing the SiC semiconductor device 101 shown in Fig. 15. Fig. 18 is a plan view of Fig. 17 with resin layer 129 removed.

[0360] In this embodiment, the rough surface regions 20A-20D and the smooth surface regions 21A-21D according to the first embodiment are applied. That is, in the manufacturing process of SiC semiconductor device 101, the same steps as those in the above-described Figures 10A-10M are applied.

[0361] In the SiC semiconductor device 101, rough surface regions 20A-20D and smooth surface regions 21A-21D according to the second, third, fourth, fifth, sixth, seventh or eighth embodiment examples may be adopted instead of or in addition to the rough surface regions 20A-20D according to the first embodiment example.

[0362] Furthermore, the rough surface regions 20A to 20D (smooth surface regions 21A to 21D) may have a configuration in which at least two of the features of the rough surface regions 20A to 20D (smooth surface regions 21A to 21D) according to the first to eighth embodiment examples are combined.

[0363] 15 to 18, a SiC semiconductor device 101 includes a SiC semiconductor layer 102. The SiC semiconductor layer 102 includes a 4H—SiC single crystal as an example of a SiC single crystal made of a hexagonal crystal. The SiC semiconductor layer 102 is formed in the shape of a rectangular parallelepiped chip.

[0364] The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting the first main surface 103 and the second main surface 104. The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0365] The first main surface 103 is an element formation surface on which a semiconductor element is formed. The second main surface 104 of the SiC semiconductor layer 102 is a ground surface having grinding marks. The side surfaces 105A to 105D are each a cleavage plane facing a crystal plane of a SiC single crystal. The side surfaces 105A to 105D do not have grinding marks.

[0366] The thickness TL of the SiC semiconductor layer 102 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less. The thickness TL is preferably 60 μm or more and 150 μm or less.

[0367] In this embodiment, the first main surface 103 and the second main surface 104 face the c-plane of the SiC single crystal. The first main surface 103 faces the (0001) plane (silicon plane). The second main surface 104 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0368] The first main surface 103 and the second main surface 104 have an off angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0369] The off angle θ may be 0° or more and 5.0° or less. The off angle θ may be set in the range of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. The off angle θ is preferably greater than 0°. The off angle θ may be less than 4.0°.

[0370] The off angle θ may be set in the range of 3.0° to 4.5° inclusive. In this case, the off angle θ is preferably set in the range of 3.0° to 3.5° inclusive or 3.5° to 4.0° inclusive.

[0371] The off angle θ may be set in the range of 1.5° to 3.0° inclusive. In this case, the off angle θ is preferably set in the range of 1.5° to 2.0° inclusive or 2.0° to 2.5° inclusive.

[0372] The length of each of the side surfaces 105A to 105D may be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). In this embodiment, the surface area of ​​the side surfaces 105B and 105D exceeds the surface area of ​​the side surfaces 105A and 105C. The first main surface 103 and the second main surface 104 may be formed in a square shape in a plan view. In this case, the surface area of ​​the side surfaces 105A and 105C is equal to that of the side surfaces 105B and 105D.

[0373] In this embodiment, the side surface 105A and the side surface 105C extend along a first direction X and face each other in a second direction Y that intersects with the first direction X. In this embodiment, the side surface 105B and the side surface 105D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is a direction perpendicular to the first direction X.

[0374] In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

[0375] Side 105A and side 105C form the short sides of SiC semiconductor layer 102 in plan view. Side 105A and side 105C are formed by the a-plane of a SiC single crystal and face each other in the a-axis direction. Side 105A is formed by the (-1-120) plane of the SiC single crystal. Side 105C is formed by the (11-20) plane of the SiC single crystal.

[0376] Side 105B and side 105D form the long sides of SiC semiconductor layer 102 in plan view. Side 105B and side 105D are formed by the m-plane of a SiC single crystal and face each other in the m-axis direction. Side 105B is formed by the (-1100) plane of the SiC single crystal. Side 105D is formed by the (1-100) plane of the SiC single crystal.

[0377] Side 105A and side 105C may form an inclined surface that is inclined toward the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal to first main surface 103 of SiC semiconductor layer 102.

[0378] In this case, when the normal to first main surface 103 of SiC semiconductor layer 102 is set to 0°, side surface 105A and side surface 105C may be inclined at an angle corresponding to off angle θ with respect to the normal to first main surface 103 of SiC semiconductor layer 102. The angle corresponding to off angle θ may be equal to off angle θ or may be an angle exceeding 0° and less than off angle θ.

[0379] In this embodiment, the SiC semiconductor layer 102 is +The SiC semiconductor layer 102 has a layered structure including an n-type SiC semiconductor substrate 106 and an n-type SiC epitaxial layer 107. The SiC semiconductor substrate 106 and the SiC epitaxial layer 107 correspond to the SiC semiconductor substrate 6 and the SiC epitaxial layer 7, respectively, according to the first embodiment. The second main surface 104 of the SiC semiconductor layer 102 is formed by the SiC semiconductor substrate 106.

[0380] A first main surface 103 of the SiC semiconductor layer 102 is formed by the SiC epitaxial layer 107. Side surfaces 105A to 105D of the SiC semiconductor layer 102 are formed by the SiC semiconductor substrate 106 and the SiC epitaxial layer 107.

[0381] The thickness TS of the SiC semiconductor substrate 106 may be 40 μm or more and 150 μm or less. The thickness TS may be 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 106, the resistance value can be reduced by shortening the current path.

[0382] The thickness TE of the SiC epitaxial layer 107 may be 1 μm or more and 50 μm or less. The thickness TE may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

[0383] The n-type impurity concentration of the SiC epitaxial layer 107 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 106. More specifically, the n-type impurity concentration of the SiC epitaxial layer 107 is lower than the n-type impurity concentration of the SiC semiconductor substrate 106. The n-type impurity concentration of the SiC semiconductor substrate 106 is 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 107 may be 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 It may be the following.

[0384] In this embodiment, the SiC epitaxial layer 107 has a plurality of regions having different n-type impurity concentrations along the normal direction Z. More specifically, the SiC epitaxial layer 107 includes a high-concentration region 108 having a relatively high n-type impurity concentration, and a low-concentration region 109 having a lower n-type impurity concentration than the high-concentration region 108.

[0385] The high concentration region 108 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102. The low concentration region 109 is formed in a region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the high concentration region 108.

[0386] The n-type impurity concentration of the high concentration region 108 is 1×10 16 cm -3 More than 1×10 18 cm -3 The n-type impurity concentration of the low concentration region 109 may be 1×10 15 cm -3 More than 1×10 16 cm -3 It may be the following.

[0387] The thickness of the high concentration region 108 is equal to or less than the thickness of the low concentration region 109. More specifically, the thickness of the high concentration region 108 is less than the thickness of the low concentration region 109. The thickness of the high concentration region 108 is less than half the total thickness of the SiC epitaxial layer 107.

[0388] The SiC semiconductor layer 102 has an active region 111 and an outer region 112. The active region 111 is a region in which a vertical MISFET (Metal Insulator Field Effect Transistor) as an example of a semiconductor element is formed. The outer region 112 is a region outside the active region 111.

[0389] In plan view, active region 111 is set in the center of SiC semiconductor layer 102 with a gap inward from side surfaces 105A-105D of SiC semiconductor layer 102. Active region 111 is set in a quadrangular shape (rectangular shape in this embodiment) having four sides parallel to side surfaces 105A-105D of SiC semiconductor layer 102 in plan view.

[0390] Outer region 112 is set in a region between side surfaces 105A-105D of SiC semiconductor layer 102 and the periphery of active region 111. Outer region 112 is set in an endless shape (a quadrangular ring shape in this embodiment) surrounding active region 111 in a plan view.

[0391] A main surface insulating layer 113 is formed on the first main surface 103 of the SiC semiconductor layer 102. The main surface insulating layer 113 selectively covers the active region 111 and the outer region 112. The main surface insulating layer 113 may contain silicon oxide (SiO2).

[0392] The main surface insulating layer 113 has insulating side surfaces 114A, 114B, 114C, and 114D exposed from the side surfaces 105A to 105D of the SiC semiconductor layer 102. The insulating side surfaces 114A to 114D are continuous with the side surfaces 105A to 105D. The insulating side surfaces 114A to 114D are formed flush with the side surfaces 105A to 105D, respectively. The insulating side surfaces 114A to 114D are made of cleavage planes.

[0393] The thickness of the main surface insulating layer 113 may be 1 μm or more and 50 μm or less. The thickness of the main surface insulating layer 113 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0394] A main surface gate electrode layer 115 as one of the first main surface electrode layers is formed on the main surface insulating layer 113. The main surface gate electrode layer 115 penetrates the main surface insulating layer 113 and is electrically connected to an arbitrary region of the SiC semiconductor layer 102.

[0395] The main surface gate electrode layer 115 includes a gate pad 116 and gate fingers 117 and 118. The gate pad 116 and the gate fingers 117 and 118 are disposed in the active region 111.

[0396] The gate pad 116 is formed, in a plan view, along the side surface 105A of the SiC semiconductor layer 102. The gate pad 116 is formed, in a plan view, along a central region of the side surface 105A of the SiC semiconductor layer 102.

[0397] The gate pad 116 may be formed, in a plan view, along a corner connecting any two of the side surfaces 105A to 105D of the SiC semiconductor layer 102. The gate pad 116 may be formed in a quadrangular shape in a plan view.

[0398] The gate fingers 117, 118 include an outer gate finger 117 and an inner gate finger 118. The outer gate finger 117 is drawn out from the gate pad 116 and extends in a strip shape along the periphery of the active region 111.

[0399] In this embodiment, the outer gate fingers 117 are formed along the three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions.

[0400] The outer gate finger 117 has a pair of open ends 119, 120. The pair of open ends 119, 120 are formed in a region facing the gate pad 116 with an inner region of the active region 111 in between. In this embodiment, the pair of open ends 119, 120 are formed along the side surface 105C of the SiC semiconductor layer 102.

[0401] The inner gate finger 118 is extended from the gate pad 116 to an inner region of the active region 111. The inner gate finger 118 extends in a strip shape in the inner region of the active region 111. The inner gate finger 118 extends from the gate pad 116 toward the side surface 105C.

[0402] A main surface source electrode layer 121 as one of the first main surface electrode layers is further formed on the main surface insulating layer 113. The main surface source electrode layer 121 penetrates the main surface insulating layer 113 and is electrically connected to an arbitrary region of the SiC semiconductor layer 102. In this embodiment, the main surface source electrode layer 121 includes a source pad 122, a source lead-out wiring 123, and a source connection portion 124.

[0403] The source pad 122 is formed in the active region 111 at a distance from the gate pad 116 and the gate fingers 117, 118. The source pad 122 is formed in a C-shape (an inverted C-shape in FIGS. 17 and 18) in a plan view so as to cover a C-shaped region (an inverted C-shape in FIGS. 17 and 18) defined by the gate pad 116 and the gate fingers 117, 118.

[0404] The source lead-out wiring 123 is formed in the outer region 112. The source lead-out wiring 123 extends in a strip shape along the active region 111. In this embodiment, the source lead-out wiring 123 is formed in an endless shape (a quadrangular ring shape in this embodiment) surrounding the active region 111 in a plan view. The source lead-out wiring 123 is electrically connected to the SiC semiconductor layer 102 in the outer region 112.

[0405] The source connection portion 124 connects the source pad 122 and the source lead-out wiring 123. The source connection portion 124 is provided in a region between a pair of open ends 119, 120 of the outer gate finger 117. The source connection portion 124 crosses the boundary region between the active region 111 and the outer region 112 from the source pad 122 and is connected to the source lead-out wiring 123.

[0406] The MISFET formed in the active region 111 structurally includes an npn-type parasitic bipolar transistor. When an avalanche current generated in the outer region 112 flows into the active region 111, the parasitic bipolar transistor turns on. In this case, there is a possibility that control of the MISFET becomes unstable due to, for example, latch-up.

[0407] Therefore, in the SiC semiconductor device 101, the structure of the main surface source electrode layer 121 is utilized to form an avalanche current absorption structure that absorbs the avalanche current generated in the outer region 112.

[0408] More specifically, the avalanche current generated in the outer region 112 is absorbed by the source lead-out wiring 123 and reaches the source pad 122 via the source connection part 124. When a conductor for external connection (e.g., a bonding wire) is connected to the source pad 122, the avalanche current is taken out by this conductor.

[0409] This makes it possible to prevent the parasitic bipolar transistor from being turned on due to an undesired current generated in the outer region 112. This makes it possible to prevent latch-up, thereby improving the stability of control of the MISFET.

[0410] A gate voltage is applied to the main surface gate electrode layer 115. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the main surface source electrode layer 121. The source voltage may be a reference voltage (for example, a GND voltage).

[0411] A passivation layer 125 (insulating layer) is formed on the main surface insulating layer 113. The passivation layer 125 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer.

[0412] The passivation layer 125 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the passivation layer 125 has a single-layer structure made of a silicon nitride layer.

[0413] Sides 126A, 126B, 126C, and 126D of the passivation layer 125 are formed at intervals inward from side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view. The passivation layer 125 exposes the peripheral portion of the SiC semiconductor layer 102 in a plan view. The passivation layer 125 exposes the main surface insulating layer 113.

[0414] The passivation layer 125 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. A gate subpad opening 127 and a source subpad opening 128 are formed in the passivation layer 125. The gate subpad opening 127 exposes the gate pad 116. The source subpad opening 128 exposes the source pad 122.

[0415] The thickness of the passivation layer 125 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 125 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0416] A resin layer 129 (insulating layer) is formed on the passivation layer 125. The passivation layer 125 and the resin layer 129 form one insulating laminated structure (insulating layer). In Fig. 17, the resin layer 129 is indicated by hatching.

[0417] The resin layer 129 may include a negative type or a positive type photosensitive resin. In this embodiment, the resin layer 129 includes polybenzoxazole as an example of a positive type photosensitive resin. The resin layer 129 may include polyimide as an example of a negative type photosensitive resin.

[0418] The resin layer 129 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. Resin side surfaces 130A, 130B, 130C, and 130D of the resin layer 129 are formed at intervals inward from the side surfaces 105A to 105D of the SiC semiconductor layer 102. The resin layer 129 exposes the main surface insulating layer 113 together with the passivation layer 125. In this embodiment, the resin side surfaces 130A to 130D of the resin layer 129 are formed flush with the side surfaces 126A to 126D of the passivation layer 125.

[0419] Resin side surfaces 130A-130D of resin layer 129 are portions that define dicing streets when cutting out SiC semiconductor device 101 from one SiC semiconductor wafer. In this embodiment, side surfaces 126A-126D of passivation layer 125 are also portions that define dicing streets.

[0420] By exposing the peripheral portion of the SiC semiconductor layer 102 from the resin layer 129 and the passivation layer 125, it is not necessary to physically cut the resin layer 129 and the passivation layer 125. This makes it possible to smoothly cut out the SiC semiconductor device 101 from one SiC semiconductor wafer. Also, the insulation distance from the side surfaces 105A to 105D of the SiC semiconductor layer 102 can be increased.

[0421] The distance between the side surfaces 105A-105D and the resin side surfaces 130A-130D (side surfaces 126A-126D) may be 1 μm or more and 25 μm or less. The distance between the side surfaces 105A-105D and the resin side surfaces 130A-130D (side surfaces 126A-126D) may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. Of course, the side surfaces 126A-126D of the passivation layer 125 may be formed flush with the side surfaces 105A-105D of the SiC semiconductor layer 102.

[0422] A gate pad opening 131 and a source pad opening 132 are formed in the resin layer 129. The gate pad opening 131 exposes the gate pad 116. The source pad opening 132 exposes the source pad 122.

[0423] The gate pad opening 131 of the resin layer 129 communicates with the gate subpad opening 127 of the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the gate subpad opening 127. The inner wall of the gate pad opening 131 may be located inside the inner wall of the gate subpad opening 127. The resin layer 129 may cover the inner wall of the gate subpad opening 127.

[0424] The source pad opening 132 of the resin layer 129 communicates with the source subpad opening 128 of the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the source subpad opening 128. The inner wall of the source pad opening 132 may be located inside the inner wall of the source subpad opening 128. The resin layer 129 may cover the inner wall of the source subpad opening 128.

[0425] The thickness of the resin layer 129 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 129 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0426] A drain electrode layer 133 serving as a second principal surface electrode layer is connected to the second principal surface 104 of the SiC semiconductor layer 102. The maximum voltage that can be applied between the principal surface source electrode layer 121 and the drain electrode layer 133 in the off state may be 1000V or more and 10000V or less.

[0427] The drain electrode layer 133 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The drain electrode layer 133 may have a single layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer.

[0428] The drain electrode layer 133 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in any manner. The drain electrode layer 133 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer laminated in this order from the second main surface 104 of the SiC semiconductor layer 102.

[0429] The SiC semiconductor substrate 106 is formed as a drain region 134 of the MISFET. The SiC epitaxial layer 107 is formed as a drift region 135 of the MISFET.

[0430] Rough surface regions 20A-20D and smooth surface regions 21A-21D according to the first embodiment are formed on side surfaces 105A-105D of SiC semiconductor layer 102. The structures of rough surface regions 20A-20D and smooth surface regions 21A-21D according to the third embodiment are similar to the structures of rough surface regions 20A-20D and smooth surface regions 21A-21D according to the first embodiment, except that they are formed on SiC semiconductor layer 102 instead of SiC semiconductor layer 2.

[0431] The descriptions of rough surface regions 20A-20D and smooth surface regions 21A-21D according to the first embodiment shall apply mutatis mutandis to the descriptions of rough surface regions 20A-20D and smooth surface regions 21A-21D according to the third embodiment, respectively, and specific descriptions of rough surface regions 20A-20D and smooth surface regions 21A-21D according to the third embodiment will be omitted.

[0432] Fig. 19 is an enlarged view of region XIX shown in Fig. 18 and is a view for explaining the structure of first main surface 103 of SiC semiconductor layer 102. Fig. 20 is a cross-sectional view taken along line XX-XX shown in Fig. 19. Fig. 21 is a cross-sectional view taken along line XXI-XXI shown in Fig. 19. Fig. 22 is an enlarged view of region XXII shown in Fig. 20. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII shown in Fig. 18. Fig. 24 is an enlarged view of region XXIV shown in Fig. 23.

[0433] 19 to 23, a p-type body region 141 is formed in a surface layer portion of a first main surface 103 of a SiC semiconductor layer 102 in an active region 111. The body region 141 defines the active region 111.

[0434] In this embodiment, the body region 141 is formed in the entire region in which the active region 111 is formed on the first main surface 103 of the SiC semiconductor layer 102. The p-type impurity concentration of the body region 141 is 1.0×10 17 cm -3 Above 1.0×10 19 cm -3 It may be the following.

[0435] In the active region 111, a plurality of gate trenches 142 are formed in a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The plurality of gate trenches 142 are each formed in a strip shape extending along a first direction X (the m-axis direction of the SiC single crystal) in a plan view, and are formed at intervals along a second direction Y (the a-axis direction of the SiC single crystal).

[0436] In this embodiment, each gate trench 142 extends from the peripheral portion on one side (side surface 105B side) to the peripheral portion on the other side (side surface 105D side) in the active region 111. The multiple gate trenches 142 are formed in a striped pattern as a whole in a plan view.

[0437] Each gate trench 142 crosses an intermediate portion between one side peripheral edge and the other side peripheral edge of the active region 111. One end of each gate trench 142 is located at one side peripheral edge of the active region 111. The other end of each gate trench 142 is located at the other side peripheral edge of the active region 111.

[0438] The length of each gate trench 142 may be 0.5 mm or more. The length of each gate trench 142 is the length from the end of the connection portion between each gate trench 142 and outer gate finger 117 to the opposite end in the cross section shown in FIG.

[0439] In this embodiment, the length of each gate trench 142 is 1 mm to 10 mm (e.g., 2 mm to 5 mm). The total extension of the one or more gate trenches 142 per unit area is 0.5 μm / μm. 2 More than 0.75μm / μm 2 It may be the following.

[0440] Each gate trench 142 integrally includes an active trench portion 143 and a contact trench portion 144. The active trench portion 143 is a portion of the active region 111 that is along the channel of the MISFET.

[0441] The contact trench portion 144 is a portion of the gate trench 142 mainly intended for contact with the outer gate finger 117. The contact trench portion 144 is extended from the active trench portion 143 to the peripheral portion of the active region 111. The contact trench portion 144 is formed in a region directly below the outer gate finger 117. The extension amount of the contact trench portion 144 is arbitrary.

[0442] Each gate trench 142 penetrates the body region 141 and reaches the SiC epitaxial layer 107. Each gate trench 142 includes a sidewall and a bottom wall. The sidewall forming the long side of each gate trench 142 is formed by the a-plane of the SiC single crystal. The sidewall forming the short side of each gate trench 142 is formed by the m-plane of the SiC single crystal.

[0443] The sidewall of each gate trench 142 may extend along the normal direction Z. The sidewall of each gate trench 142 may be formed substantially perpendicular to the first main surface 103 of the SiC semiconductor layer 102.

[0444] In the SiC semiconductor layer 102, the angle that the sidewall of each gate trench 142 forms with the first main surface 103 of the SiC semiconductor layer 102 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). Each gate trench 142 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.

[0445] The bottom wall of each gate trench 142 is located in the SiC epitaxial layer 107. More specifically, the bottom wall of each gate trench 142 is located in a high concentration region 108 of the SiC epitaxial layer 107.

[0446] The bottom wall of each gate trench 142 faces the c-plane of the SiC single crystal. The bottom wall of each gate trench 142 has an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

[0447] The bottom wall of each gate trench 142 may be formed parallel to the first main surface 103 of the SiC semiconductor layer 102. Of course, the bottom wall of each gate trench 142 may be formed in a convex curved shape toward the second main surface 104 of the SiC semiconductor layer 102.

[0448] With respect to the normal direction Z, the depth of each gate trench 142 may be 0.5 μm or more and 3.0 μm or less. The depth of each gate trench 142 may be 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, 1.5 μm or more and 2.0 μm or less, 2.0 μm or more and 2.5 μm or less, or 2.5 μm or more and 3.0 μm or less.

[0449] The width of each gate trench 142 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of each gate trench 142 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0450] 22 , opening edge portion 146 of each gate trench 142 includes an inclined portion 147 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the inside of each gate trench 142. The opening edge portion 146 of each gate trench 142 is a corner portion that connects the first main surface 103 of the SiC semiconductor layer 102 and the sidewall of each gate trench 142.

[0451] In this embodiment, the inclined portion 147 is formed in a concave curved shape directed toward the inside of the SiC semiconductor layer 102. The inclined portion 147 may be formed in a convex curved shape directed toward the inside of each gate trench 142. The inclined portion 147 relieves electric field concentration at the opening edge portion 146 of each gate trench 142.

[0452] A gate insulating layer 148 and a gate electrode layer 149 are formed in each gate trench 142. In FIG. 19, the gate insulating layer 148 and the gate electrode layer 149 are indicated by hatching.

[0453] The gate insulating layer 148 includes at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), or tantalum oxide (Ta2O3).

[0454] The gate insulating layer 148 may have a laminated structure including a SiN layer and a SiO2 layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102. The gate insulating layer 148 may have a laminated structure including a SiO2 layer and a SiN layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102. The gate insulating layer 148 may have a single layer structure made of a SiO2 layer or a SiN layer. In this embodiment, the gate insulating layer 148 has a single layer structure made of a SiO2 layer.

[0455] The gate insulating layer 148 is formed in a film shape along the inner wall surface of the gate trench 142 so as to define a recessed space within the gate trench 142. The gate insulating layer 148 includes a first region 148a, a second region 148b, and a third region 148c.

[0456] The first region 148a is formed along the side wall of the gate trench 142. The second region 148b is formed along the bottom wall of the gate trench 142. The third region 148c is formed along the first main surface 103 of the SiC semiconductor layer 102. The third region 148c of the gate insulating layer 148 forms a part of the main surface insulating layer 113.

[0457] The thickness Ta of the first region 148a is smaller than the thickness Tb of the second region 148b and the thickness Tc of the third region 148c. The ratio Tb / Ta of the thickness Tb of the second region 148b to the thickness Ta of the first region 148a may be greater than or equal to 2 and less than or equal to 5. The ratio T3 / Ta of the thickness Tc of the third region 148c to the thickness Ta of the first region 148a may be greater than or equal to 2 and less than or equal to 5.

[0458] The thickness Ta of the first region 148a may be 0.01 μm or more and 0.2 μm or less. The thickness Tb of the second region 148b may be 0.05 μm or more and 0.5 μm or less. The thickness Tc of the third region 148c may be 0.05 μm or more and 0.5 μm or less.

[0459] By thinning the first region 148a of the gate insulating layer 148, it is possible to suppress an increase in carriers induced in the region near the sidewall of each gate trench 142 in the body region 141. This makes it possible to suppress an increase in channel resistance. By thickening the second region 148b of the gate insulating layer 148, it is possible to alleviate electric field concentration on the bottom wall of each gate trench 142.

[0460] By thickening the third region 148c of the gate insulating layer 148, it is possible to improve the breakdown voltage of the gate insulating layer 148 in the vicinity of the opening edge portion 146 of each gate trench 142. Furthermore, by thickening the third region 148c, it is possible to prevent the third region 148c from disappearing due to an etching method.

[0461] This can prevent the first region 148a from being removed by an etching method due to the disappearance of the third region 148c. As a result, the gate electrode layer 149 can be appropriately opposed to the SiC semiconductor layer 102 (the body region 141) with the gate insulating layer 148 interposed therebetween.

[0462] The gate insulating layer 148 further includes a bulging portion 148d that bulges into each gate trench 142 at an opening edge portion 146 of each gate trench 142. The bulging portion 148d is formed at a corner portion that connects the first region 148a and the third region 148c of the gate insulating layer 148.

[0463] The bulging portion 148d protrudes in a convex curved shape toward the inside of each gate trench 142. The bulging portion 148d narrows the opening of each gate trench 142 at an opening edge portion 146 of each gate trench 142.

[0464] The bulging portion 148d improves the dielectric strength of the gate insulating layer 148 at the opening edge portion 146. Of course, the gate insulating layer 148 may be formed without the bulging portion 148d. Also, the gate insulating layer 148 may be formed to have a uniform thickness.

[0465] The gate electrode layer 149 is embedded in each gate trench 142 with the gate insulating layer 148 therebetween. More specifically, the gate electrode layer 149 is embedded in a concave space defined by the gate insulating layer 148 in each gate trench 142. The gate electrode layer 149 is controlled by a gate voltage.

[0466] The gate electrode layer 149 has an upper end located on the opening side of each gate trench 142. The upper end of the gate electrode layer 149 is formed in a concave curved shape recessed toward the bottom wall of each gate trench 142. The upper end of the gate electrode layer 149 has a constricted portion that is constricted along the bulging portion 148d of the gate insulating layer 148.

[0467] The cross-sectional area of ​​the gate electrode layer 149 (the cross-sectional area perpendicular to the direction in which each gate trench 142 extends) is 0.05 μm 2 More than 0.5μm 2 The cross-sectional area of ​​the gate electrode layer 149 is defined as the product of the depth of the gate electrode layer 149 and the width of the gate electrode layer 149 .

[0468] The depth of the gate electrode layer 149 is the distance from the upper end to the lower end of the gate electrode layer 149. The width of the gate electrode layer 149 is the width of the gate trench 142 at the midpoint between the upper end and the lower end of the gate electrode layer 149. When the upper end is curved (concavely curved in this embodiment), the position of the upper end of the gate electrode layer 149 is the midpoint in the depth direction on the upper surface of the gate electrode layer 149.

[0469] The gate electrode layer 149 includes p-type polysilicon doped with p-type impurities. The p-type impurities of the gate electrode layer 149 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0470] The p-type impurity concentration of the gate electrode layer 149 is equal to or higher than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the gate electrode layer 149 is higher than the p-type impurity concentration of the body region 141.

[0471] The p-type impurity concentration of the gate electrode layer 149 is 1×10 18 cm -3 More than 1×10 22 cm -3 The sheet resistance of the gate electrode layer 149 may be 10 Ω / □ or more and 500 Ω / □ or less (approximately 200 Ω / □ in this embodiment).

[0472] 19 and 21, a gate wiring layer 150 is formed in the active region 111. The gate wiring layer 150 is electrically connected to the gate pad 116 and the gate fingers 117 and 118. In Fig. 21, the gate wiring layer 150 is indicated by hatching.

[0473] The gate wiring layer 150 is formed on the first main surface 103 of the SiC semiconductor layer 102. More specifically, the gate wiring layer 150 is formed on the third region 148c of the gate insulating layer 148.

[0474] In this embodiment, the gate wiring layer 150 is formed along the outer gate finger 117. More specifically, the gate wiring layer 150 is formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition an inner region of the active region 111 from three directions.

[0475] The gate wiring layer 150 is connected to the gate electrode layer 149 exposed from the contact trench portion 144 of each gate trench 142. In this embodiment, the gate wiring layer 150 is formed by an extended portion of the gate electrode layer 149 extended from each gate trench 142 onto the first main surface 103 of the SiC semiconductor layer 102. An upper end portion of the gate wiring layer 150 is connected to an upper end portion of the gate electrode layer 149.

[0476] 19, 20, and 22, a plurality of source trenches 155 are formed in first main surface 103 of SiC semiconductor layer 102 in active region 111. Each source trench 155 is formed in a region between two gate trenches 142 adjacent to each other.

[0477] The multiple source trenches 155 are each formed in a band shape extending along the first direction X (the m-axis direction of the SiC single crystal). The multiple source trenches 155 are formed in a stripe shape as a whole in a plan view. In the second direction Y, the pitch between the centers of adjacent source trenches 155 may be 1.5 μm or more and 3 μm or less.

[0478] Each source trench 155 penetrates the body region 141 and reaches the SiC epitaxial layer 107. Each source trench 155 includes a sidewall and a bottom wall. The sidewall forming the long side of each source trench 155 is formed by the a-plane of the SiC single crystal. The sidewall forming the short side of each source trench 155 is formed by the m-plane of the SiC single crystal.

[0479] The sidewall of each source trench 155 may extend along the normal direction Z. The sidewall of each source trench 155 may be formed substantially perpendicular to the first main surface 103 of the SiC semiconductor layer 102.

[0480] In the SiC semiconductor layer 102, the sidewall of each source trench 155 may form an angle of 90° or more and 95° or less (for example, 91° or more and 93° or less) with respect to the first main surface 103 of the SiC semiconductor layer 102. Each source trench 155 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.

[0481] The bottom wall of each source trench 155 is located in the SiC epitaxial layer 107. More specifically, the bottom wall of each source trench 155 is located in a high concentration region 108 of the SiC epitaxial layer 107. More specifically, the bottom wall of each source trench 155 is located in a region between the bottom wall of each gate trench 142 and the low concentration region 109.

[0482] The bottom wall of each source trench 155 faces the c-plane of the SiC single crystal. The bottom wall of each source trench 155 has an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

[0483] The bottom wall of each source trench 155 may be formed parallel to the first main surface 103 of the SiC semiconductor layer 102. Of course, the bottom wall of each source trench 155 may be formed in a convex curved shape toward the second main surface 104 of the SiC semiconductor layer 102.

[0484] In this embodiment, the depth of each source trench 155 is equal to or greater than the depth of each gate trench 142. More specifically, the depth of each source trench 155 is greater than the depth of each gate trench 142.

[0485] The bottom wall of each source trench 155 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. Of course, the depth of each source trench 155 may be equal to the depth of each gate trench 142.

[0486] In the normal direction Z, the depth of each source trench 155 may be 0.5 μm or more and 10 μm or less (for example, about 2 μm). The ratio of the depth of each source trench 155 to the depth of each gate trench 142 may be 1.5 or more. The ratio of the depth of each source trench 155 to the depth of each gate trench 142 is preferably 2 or more.

[0487] The first direction width of each source trench 155 may be approximately equal to the first direction width of each gate trench 142. The first direction width of each source trench 155 may be equal to or greater than the first direction width of each gate trench 142. The first direction width of each source trench 155 may be equal to or greater than 0.1 μm and equal to or less than 2 μm (for example, approximately 0.5 μm).

[0488] A source insulating layer 156 and a source electrode layer 157 are formed in each source trench 155. The source insulating layer 156 and the source electrode layer 157 are indicated by hatching in FIG.

[0489] The source insulating layer 156 includes at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0490] The source insulating layer 156 may have a laminated structure including a SiN layer and a SiO2 layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102. The source insulating layer 156 may have a laminated structure including a SiO2 layer and a SiN layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102. The source insulating layer 156 may have a single layer structure made of a SiO2 layer or a SiN layer. In this embodiment, the source insulating layer 156 has a single layer structure made of a SiO2 layer.

[0491] The source insulating layer 156 is formed in the form of a film along the inner wall surface of each source trench 155 so as to define a concave space within each source trench 155. The source insulating layer 156 includes a first region 156a and a second region 156b.

[0492] The first region 156a is formed along the sidewall of each source trench 155. The second region 156b is formed along the bottom wall of each source trench 155. The thickness Tsa of the first region 156a is smaller than the thickness Tsb of the second region 156b.

[0493] A ratio Tsb / Tsa of a thickness Tsb of the second region 156b to a thickness Tsa of the first region 156a may be equal to or greater than 2 and equal to or less than 5. The thickness Tsa of the first region 156a may be equal to or greater than 0.01 μm and equal to or less than 0.2 μm. The thickness Tsb of the second region 156b may be equal to or greater than 0.05 μm and equal to or less than 0.5 μm.

[0494] The thickness Tsa of the first region 156a may be approximately equal to the thickness Ta of the first region 156a of the gate insulating layer 148. The thickness Tsb of the second region 156b may be approximately equal to the thickness Tb of the second region 156b of the gate insulating layer 148. Of course, the source insulating layer 156 may be formed to have a uniform thickness.

[0495] The source electrode layer 157 is embedded in each source trench 155 with the source insulating layer 156 sandwiched therebetween. More specifically, the source electrode layer 157 is embedded in a concave space defined by the source insulating layer 156 in each source trench 155. The source electrode layer 157 is controlled by a source voltage.

[0496] The source electrode layer 157 has an upper end located on the opening side of each source trench 155. The upper end of the source electrode layer 157 is formed below the first main surface 103 of the SiC semiconductor layer 102. The upper end of the source electrode layer 157 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0497] An upper end of the source electrode layer 157 is formed in a concave curved shape recessed toward the bottom wall of each source trench 155. The upper end of the source electrode layer 157 may be formed parallel to the first main surface 103 of the SiC semiconductor layer 102.

[0498] An upper end of the source electrode layer 157 may protrude above an upper end of the source insulating layer 156. An upper end of the source electrode layer 157 may be located below an upper end of the source insulating layer 156. The thickness of the source electrode layer 157 may be not less than 0.5 μm and not more than 10 μm (for example, about 1 μm).

[0499] The source electrode layer 157 preferably contains polysilicon having properties similar to those of SiC. This can reduce stress generated in the SiC semiconductor layer 102. In this embodiment, the source electrode layer 157 contains p-type polysilicon doped with p-type impurities. In this case, the source electrode layer 157 can be formed simultaneously with the gate electrode layer 149.

[0500] The p-type impurity concentration of the source electrode layer 157 is equal to or higher than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the source electrode layer 157 is higher than the p-type impurity concentration of the body region 141. The p-type impurity of the source electrode layer 157 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0501] The p-type impurity concentration of the source electrode layer 157 is 1×10 18 cm -3 More than 1×10 22 cm -3 The sheet resistance of the source electrode layer 157 may be 10 Ω / □ or more and 500 Ω / □ or less (approximately 200 Ω / □ in this embodiment).

[0502] The source electrode layer 157 may have a p-type impurity concentration substantially equal to the p-type impurity concentration of the gate electrode layer 149. The source electrode layer 157 may have a sheet resistance substantially equal to the sheet resistance of the gate electrode layer 149.

[0503] The source electrode layer 157 may contain n-type polysilicon instead of or in addition to p-type polysilicon. The source electrode layer 157 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of or in addition to p-type polysilicon.

[0504] Thus, the SiC semiconductor device 101 has a plurality of trench gate structures 161 and a plurality of trench source structures 162. Each trench gate structure 161 includes a gate trench 142, a gate insulating layer 148, and a gate electrode layer 149. Each trench source structure 162 includes a source trench 155, a source insulating layer 156, and a source electrode layer 157.

[0505] In the surface layer portion of the body region 141, the region along the side wall of each gate trench 142 has n + The n-type source region 163 is formed in the n-type impurity region 163. The n-type impurity concentration of the source region 163 is 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The n-type impurity of the source region 163 may be phosphorus (P).

[0506] The source regions 163 are formed along one sidewall and the other sidewall of each gate trench 142. The source regions 163 are each formed in a strip shape extending along the first direction X.

[0507] The source regions 163 are formed in a striped pattern as a whole in a plan view. Each source region 163 is exposed from the sidewall of each gate trench 142 and the sidewall of each source trench 155.

[0508] In this manner, in the surface portion of the first main surface 103 of the SiC semiconductor layer 102 in the region along the side wall of the gate trench 142, the source region 163, the body region 141 and the drift region 135 are formed in this order from the first main surface 103 to the second main surface 104 of the SiC semiconductor layer 102.

[0509] A channel of the MISFET is formed in a region along the sidewall of the gate trench 142 in the body region 141. The channel is formed in a region along the sidewall of the gate trench 142 facing the a-plane of the SiC single crystal. The ON / OFF of the channel is controlled by a gate electrode layer 149.

[0510] In the active region 111, a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 includes a plurality of p + A contact region 164 of a type is formed. Each contact region 164 is formed in a region between two gate trenches 142 adjacent to each other in a plan view. Each contact region 164 is formed in a region on the opposite side of each source region 163 from the gate trench 142.

[0511] Each contact region 164 is formed along the inner wall of each source trench 155. In this embodiment, a plurality of contact regions 164 are formed at intervals along the inner wall of each source trench 155. Each contact region 164 is formed at intervals from each gate trench 142.

[0512] The p-type impurity concentration of each contact region 164 is greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of each contact region 164 is greater than the p-type impurity concentration of the body region 141. 18 cm -3 Above 1.0×10 21 cm -3 The p-type impurity in each contact region 164 may be aluminum (Al).

[0513] Each contact region 164 covers the sidewall and bottom wall of each source trench 155. The bottom of each contact region 164 may be formed parallel to the bottom wall of each source trench 155. More specifically, each contact region 164 integrally includes a first surface region 164a, a second surface region 164b, and an inner wall region 164c.

[0514] The first surface region 164a covers one sidewall of the source trench 155 in the surface portion of the body region 141. The first surface region 164a is electrically connected to the body region 141 and the source region 163.

[0515] The first surface region 164a is located in a region on the first main surface 103 side of the SiC semiconductor layer 102 with respect to the bottom of the source region 163. In this embodiment, the first surface region 164a has a bottom extending parallel to the first main surface 103 of the SiC semiconductor layer 102.

[0516] In this embodiment, the bottom of the first surface region 164a is located in a region between the bottom of the body region 141 and the bottom of the source region 163. The bottom of the first surface region 164a may be located in a region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the body region 141.

[0517] In this embodiment, the first surface region 164a is drawn out from the source trench 155 toward the adjacent gate trench 142. The first surface region 164a may extend to an intermediate region between the gate trench 142 and the source trench 155. The first surface region 164a is formed at an interval from the gate trench 142 toward the source trench 155.

[0518] The second surface region 164b covers the other sidewall of the source trench 155 in the surface portion of the body region 141. The second surface region 164b is electrically connected to the body region 141 and the source region 163.

[0519] The second surface region 164b is located in a region on the first main surface 103 side of the SiC semiconductor layer 102 with respect to the bottom of the source region 163. In this embodiment, the second surface region 164b has a bottom extending parallel to the first main surface 103 of the SiC semiconductor layer 102.

[0520] In this embodiment, the bottom of second surface region 164b is located in a region between the bottom of body region 141 and the bottom of source region 163. The bottom of second surface region 164b may be located in a region between first main surface 103 of SiC semiconductor layer 102 and the bottom of body region 141.

[0521] In this embodiment, the second surface region 164b is drawn out from the other sidewall of the source trench 155 toward the adjacent gate trench 142. The second surface region 164b may extend to an intermediate region between the source trench 155 and the gate trench 142. The second surface region 164b is formed at an interval from the gate trench 142 toward the source trench 155.

[0522] The inner wall region 164c is located in a region on the second main surface 104 side of the SiC semiconductor layer 102 relative to the first surface region 164a and the second surface region 164b (the bottom of the source region 163). The inner wall region 164c is formed in a region along the inner wall of the source trench 155 in the SiC semiconductor layer 102. The inner wall region 164c covers the side wall of the source trench 155.

[0523] The inner wall region 164c covers a corner portion connecting the side wall and the bottom wall of the source trench 155. The inner wall region 164c covers from the side wall of the source trench 155 through the corner portion to the bottom wall of the source trench 155. The bottom of the contact region 164 is formed by the inner wall region 164c.

[0524] A plurality of deep well regions 165 are formed in a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. Each deep well region 165 is also referred to as a withstand voltage adjusting region (withstand voltage holding region) that adjusts the withstand voltage of the SiC semiconductor layer 102 in the active region 111.

[0525] Each deep well region 165 is formed in the SiC epitaxial layer 107. More specifically, each deep well region 165 is formed in the high concentration region 108 of the SiC epitaxial layer 107.

[0526] Each deep well region 165 is formed along the inner wall of each source trench 155 so as to cover each contact region 164. Each deep well region 165 is electrically connected to each contact region 164.

[0527] Each deep well region 165 is formed in a strip shape extending along each source trench 155 in a plan view. Each deep well region 165 covers the sidewall of each source trench 155.

[0528] Each deep well region 165 covers a corner portion connecting the sidewall and the bottom wall of each source trench 155. Each deep well region 165 covers the sidewall of each source trench 155 through the corner portion and the bottom wall of each source trench 155. Each deep well region 165 is continuous with the body region 141 on the sidewall of each source trench 155.

[0529] Each deep well region 165 has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom portion of each deep well region 165 may be formed parallel to the bottom wall of each source trench 155.

[0530] The p-type impurity concentration of each deep well region 165 may be approximately equal to the p-type impurity concentration of the body region 141. The p-type impurity concentration of each deep well region 165 may be greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of each deep well region 165 may be less than the p-type impurity concentration of the body region 141.

[0531] The p-type impurity concentration of each deep well region 165 may be equal to or less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of each deep well region 165 may be less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of each deep well region 165 may be greater than or equal to 1.0×10 17 cm -3 Above 1.0×10 19 cm -3 It may be the following.

[0532] Each deep well region 165 forms a pn junction with the SiC semiconductor layer 102 (high concentration region 108 of the SiC epitaxial layer 107). A depletion layer extends from this pn junction toward a region between adjacent gate trenches 142. This depletion layer extends toward a region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142.

[0533] The depletion layer extending from each deep well region 165 may overlap the bottom wall of each gate trench 142. The depletion layer extending from the bottom of each deep well region 165 may overlap the bottom wall of each gate trench 142.

[0534] 19 and 21, a p-type peripheral deep well region 166 is formed in the peripheral portion of active region 111. Peripheral deep well region 166 is formed in SiC epitaxial layer 107. More specifically, peripheral deep well region 166 is formed in high concentration region 108 of SiC epitaxial layer 107.

[0535] The peripheral deep well region 166 is electrically connected to each of the deep well regions 165. The peripheral deep well region 166 has the same potential as each of the deep well regions 165. In this embodiment, the peripheral deep well region 166 is integrally formed with each of the deep well regions 165.

[0536] More specifically, the peripheral deep well region 166 is formed in a region along the inner wall of the contact trench portion 144 of each gate trench 142 at the periphery of the active region 111 .

[0537] The peripheral deep well region 166 covers the sidewalls of the contact trench portion 144 of each gate trench 142. The peripheral deep well region 166 covers the corners connecting the sidewalls and bottom wall of each contact trench portion 144.

[0538] The peripheral deep well region 166 covers the sidewalls and bottom walls of each contact trench portion 144 via the corners of each contact trench portion 144. Each deep well region 165 is continuous with the body region 141 at the sidewall of each contact trench portion 144. The bottom of the peripheral deep well region 166 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each contact trench portion 144.

[0539] The peripheral deep well region 166 overlaps the gate wiring layer 150 in a plan view. The peripheral deep well region 166 faces the gate wiring layer 150 with the gate insulating layer 148 (third region 148c) therebetween.

[0540] The peripheral deep well region 166 includes an extension portion 166a extended from each contact trench portion 144 to each active trench portion 143. The extension portion 166a is formed in the high concentration region 108 of the SiC epitaxial layer 107. The extension portion 166a extends along the sidewall of each active trench portion 143, passes through the corners, and covers the bottom wall of the active trench portion 143.

[0541] The lead-out portion 166a covers the sidewalls of the active trench portions 143 of each gate trench 142. The lead-out portion 166a covers the corners connecting the sidewalls and bottom walls of each active trench portion 143.

[0542] The drawn-out portion 166a covers the sidewalls and bottom walls of each active trench portion 143 via the corners of each active trench portion 143. The drawn-out portion 166a is continuous with the body region 141 at the sidewalls of each active trench portion 143. The bottom of the drawn-out portion 166a is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom walls of each active trench portion 143.

[0543] The p-type impurity concentration of the peripheral deep well region 166 may be approximately equal to the p-type impurity concentration of the body region 141. The p-type impurity concentration of the peripheral deep well region 166 may be greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of the body region 141.

[0544] The p-type impurity concentration of the peripheral deep well region 166 may be approximately equal to the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the peripheral deep well region 166 may be greater than the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of each deep well region 165.

[0545] The p-type impurity concentration of the peripheral deep well region 166 may be equal to or less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the peripheral deep well region 166 may be greater than or equal to 1.0×10 17 cm -3 Above 1.0×10 19 cm -3 It may be the following.

[0546] In a SiC semiconductor device including only a pn junction diode, since the structure does not include a trench, there is little problem of electric field concentration in the SiC semiconductor layer 102. Each deep well region 165 (peripheral deep well region 166) brings the trench gate type MISFET closer to the structure of a pn junction diode.

[0547] This allows the trench-gate MISFET to reduce the electric field in the SiC semiconductor layer 102. Therefore, narrowing the pitch between the adjacent deep well regions 165 is effective in reducing the electric field concentration.

[0548] Furthermore, each deep well region 165 having a bottom portion on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142 allows the depletion layer to appropriately reduce electric field concentration in each gate trench 142.

[0549] It is preferable that the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 is approximately constant. This makes it possible to suppress variation in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0550] Therefore, the withstand voltage (for example, breakdown resistance) of the SiC semiconductor layer 102 can be prevented from being limited by the form of each deep well region 165, and therefore the withstand voltage can be appropriately improved.

[0551] In this embodiment, a high concentration region 108 of the SiC epitaxial layer 107 is interposed in a region between adjacent deep well regions 165. This makes it possible to reduce JFET (Junction Field Effect Transistor) resistance in the region between adjacent deep well regions 165.

[0552] Furthermore, in this embodiment, the bottom of each deep well region 165 is located within the high concentration region 108 of the SiC epitaxial layer 107. This allows a current path to extend from the bottom of each deep well region 165 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. This allows a current spreading resistance to be reduced. In this structure, the low concentration region 109 of the SiC epitaxial layer 107 increases the breakdown voltage of the SiC semiconductor layer 102.

[0553] By forming the source trenches 155, p-type impurities can be introduced into the inner walls of the source trenches 155. This allows the deep well regions 165 to be formed conformally to the source trenches 155, thereby appropriately suppressing variations in the depth of the deep well regions 165. Furthermore, by using the source trenches 155, the deep well regions 165 can be appropriately formed in relatively deep regions of the SiC semiconductor layer 102.

[0554] 22, a low resistance electrode layer 167 is formed on the gate electrode layer 149. The low resistance electrode layer 167 covers an upper end of the gate electrode layer 149 in each gate trench 142.

[0555] The low resistance electrode layer 167 includes a conductive material having a sheet resistance lower than the sheet resistance of the gate electrode layer 149. The sheet resistance of the low resistance electrode layer 167 may be equal to or greater than 0.01 Ω / □ and equal to or less than 10 Ω / □.

[0556] The low resistance electrode layer 167 is formed in a film shape. The low resistance electrode layer 167 has a connection portion 167a that contacts the upper end of the gate electrode layer 149 and a non-connection portion 167b on the opposite side. The connection portion 167a and the non-connection portion 167b of the low resistance electrode layer 167 may be formed in a concave curved shape following the upper end of the gate electrode layer 149. The connection portion 167a and the non-connection portion 167b of the low resistance electrode layer 167 may take various forms.

[0557] The entirety of connection portion 167a of low-resistance electrode layer 167 may be located above first main surface 103 of SiC semiconductor layer 102. The entirety of connection portion 167a of low-resistance electrode layer 167 may be located below first main surface 103 of SiC semiconductor layer 102.

[0558] The connection portion 167a of the low-resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The connection portion 167a of the low-resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0559] For example, the central portion of the connection portion 167a of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the connection portion 167a of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0560] The entire non-connected portion 167b of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire non-connected portion 167b of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0561] The non-connected portion 167b of the low-resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The non-connected portion 167b of the low-resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0562] For example, the central portion of the non-connected portion 167b of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the non-connected portion 167b of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0563] The low resistance electrode layer 167 has an edge 167c in contact with the gate insulating layer 148. The edge 167c of the low resistance electrode layer 167 is in contact with a corner of the gate insulating layer 148 that connects the first region 148a and the second region 148b.

[0564] An edge portion 167c of the low resistance electrode layer 167 is in contact with the third region 148c of the gate insulating layer 148. More specifically, the edge portion 167c of the low resistance electrode layer 167 is in contact with a bulging portion 148d of the gate insulating layer 148.

[0565] An edge portion 167c of the low-resistance electrode layer 167 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102 relative to the bottom of the source region 163. The edge portion 167c of the low-resistance electrode layer 167 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102 relative to the boundary region between the body region 141 and the source region 163.

[0566] Therefore, the edge 167c of the low resistance electrode layer 167 faces the source region 163 with the gate insulating layer 148 therebetween. The edge 167c of the low resistance electrode layer 167 does not face the body region 141 with the gate insulating layer 148 therebetween.

[0567] This makes it possible to suppress the formation of a current path in the region between the low resistance electrode layer 167 and the body region 141 in the gate insulating layer 148. The current path may be formed by undesired diffusion of the electrode material of the low resistance electrode layer 167 into the gate insulating layer 148.

[0568] In particular, a design in which the edge 167c of the low resistance electrode layer 167 is connected to the third region 148c (corner portion of the gate insulating layer 148) of the relatively thick gate insulating layer 148 is effective in reducing the risk of a current path being formed.

[0569] In the normal direction Z, the thickness Tr of the low-resistance electrode layer 167 is equal to or less than the thickness TG of the gate electrode layer 149 (Tr ≦ TG). Preferably, the thickness Tr of the low-resistance electrode layer 167 is less than the thickness TG of the gate electrode layer 149 (Tr < TG). More specifically, preferably, the thickness Tr of the low-resistance electrode layer 167 is equal to or less than half of the thickness TG of the gate electrode layer 149 (Tr ≦ TG / 2).

[0570] The ratio Tr / TG of the thickness Tr of the low-resistance electrode layer 167 to the thickness TG of the gate electrode layer 149 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 149 may be 0.5 μm or more and 3 μm or less. The thickness Tr of the low-resistance electrode layer 167 may be 0.01 μm or more and 3 μm or less.

[0571] The current supplied into each gate trench 142 flows through the low-resistance electrode layer 167 having a relatively low sheet resistance and is transmitted to the entire gate electrode layer 149. As a result, the entire gate electrode layer 149 (the entire active region 111) can be quickly shifted from the off state to the on state, so that the delay of the switching response can be suppressed.

[0572] In particular, in the case of the gate trench 142 having a length on the order of millimeters (a length of 1 mm or more), it takes time for the current to be transmitted, but according to the low-resistance electrode layer 167, the delay of the switching response can be appropriately suppressed. That is, the low-resistance electrode layer 167 is formed as a current diffusion electrode layer that diffuses the current in each gate trench 142.

[0573] Further, as the cell structure is miniaturized, the width, depth, cross-sectional area, etc. of the gate electrode layer 149 become smaller, so there is concern about the delay of the switching response due to the increase in the electrical resistance in each gate trench 142.

[0574] However, according to the low-resistance electrode layer 167, the entire gate electrode layer 149 can be quickly shifted from the off state to the on state, so that the delay of the switching response due to miniaturization can be appropriately suppressed.

[0575] 21 , in this embodiment, the low-resistance electrode layer 167 also covers the upper end of the gate wiring layer 150. A portion of the low-resistance electrode layer 167 covering the upper end of the gate wiring layer 150 is integrally formed with a portion of the low-resistance electrode layer 167 covering the upper end of the gate electrode layer 149. As a result, the low-resistance electrode layer 167 covers the entire area of ​​the gate electrode layer 149 and the entire area of ​​the gate wiring layer 150.

[0576] Therefore, the current supplied from the gate pad 116 and the gate fingers 117, 118 to the gate wiring layer 150 is transmitted to the entire gate electrode layer 149 and the gate wiring layer 150 via the low resistance electrode layer 167 having a relatively low sheet resistance.

[0577] This allows the entire gate electrode layer 149 (the entire active region 111) to be quickly transitioned from an OFF state to an ON state via the gate wiring layer 150, thereby suppressing delays in switching response.

[0578] In particular, in the case of the gate trench 142 having a length on the order of millimeters, the low resistance electrode layer 167 covering the upper end of the gate wiring layer 150 can appropriately suppress delays in switching response.

[0579] Low resistance electrode layer 167 includes a polycide layer. The polycide layer is formed by silicidating a portion forming a surface layer of gate electrode layer 149 with a metal material. More specifically, the polycide layer is made of a p-type polycide layer containing p-type impurities added to gate electrode layer 149 (p-type polysilicon). The polycide layer preferably has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less.

[0580] The sheet resistance in the gate trench 142 in which the gate electrode layer 149 and the low resistance electrode layer 167 are embedded is equal to or lower than the sheet resistance of the gate electrode layer 149 alone. The sheet resistance in the gate trench 142 is preferably equal to or lower than the sheet resistance of n-type polysilicon doped with n-type impurities.

[0581] The sheet resistance in the gate trench 142 is approximated to the sheet resistance of the low resistance electrode layer 167. That is, the sheet resistance in the gate trench 142 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance in the gate trench 142 is preferably less than 10 Ω / □.

[0582] The low resistance electrode layer 167 may contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Among these materials, NiSi, CoSi2, and TiSi2 are particularly suitable as a polycide layer for forming the low resistance electrode layer 167, since they have relatively small resistivity and temperature dependency.

[0583] In the first main surface 103 of the SiC semiconductor layer 102, a source sub-trenches 168 communicating with each source trench 155 are formed in a region along the upper end of the source electrode layer 157. The source sub-trenches 168 form part of the sidewalls of each source trench 155.

[0584] In this embodiment, the source sub-trench 168 is formed in an endless shape (in this embodiment, a square ring shape) surrounding the upper end portion of the source electrode layer 157 in a plan view. The source sub-trench 168 borders the upper end portion of the source electrode layer 157.

[0585] The source sub-trench 168 is formed by digging down a part of the source insulating layer 156. More specifically, the source sub-trench 168 is formed by digging down from the first main surface 103 of the SiC semiconductor layer 102 to the upper end of the source insulating layer 156 and the upper end of the source electrode layer 157.

[0586] An upper end of the source electrode layer 157 has a shape narrowed inward relative to a lower end of the source electrode layer 157. The lower end of the source electrode layer 157 is a portion of the source electrode layer 157 located on the bottom wall side of each source trench 155. The width in the first direction of the upper end of the source electrode layer 157 may be smaller than the width in the first direction of the lower end of the source electrode layer 157.

[0587] The source sub-trench 168 is formed in a tapered shape in which the bottom area is smaller than the opening area in a cross-sectional view. The bottom wall of the source sub-trench 168 may be formed in a convex curved shape toward the second main surface 104 of the SiC semiconductor layer 102.

[0588] The source region 163, the contact region 164, the source insulating layer 156, and the source electrode layer 157 are exposed from the inner wall of the source sub-trench 168. A first surface layer region 164a and a second surface layer region 164b of the contact region 164 are exposed from the inner wall of the source sub-trench 168.

[0589] At least the first region 156a of the source insulating layer 156 is exposed from the bottom wall of the source sub-trench 168. In the source insulating layer 156, the upper end of the first region 156a is located lower than the first main surface 103 of the SiC semiconductor layer 102.

[0590] The opening edge portion 169 of each source trench 155 includes an inclined portion 170 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the inside of each source trench 155. The opening edge portion 169 of each source trench 155 is a corner that connects the first main surface 103 of the SiC semiconductor layer 102 and the sidewall of each source trench 155. The inclined portion 170 of each source trench 155 is formed by a source sub-trench 168.

[0591] In this embodiment, the inclined portion 170 is formed in a concave curved shape directed toward the inside of the SiC semiconductor layer 102. The inclined portion 170 may be formed in a convex curved shape directed toward the inside of the source sub-trench 168. The inclined portion 170 relieves electric field concentration at the opening edge portion 169 of each source trench 155.

[0592] 23 and 24, active region 111 has an active main surface 171 forming part of first main surface 103 of SiC semiconductor layer 102. Outer region 112 has an outer main surface 172 forming part of first main surface 103 of SiC semiconductor layer 102. In this embodiment, outer main surface 172 is connected to side surfaces 105A-105D of SiC semiconductor layer 102.

[0593] The active principal surface 171 and the outer principal surface 172 each face the c-plane of the SiC single crystal. Furthermore, the active principal surface 171 and the outer principal surface 172 each have an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

[0594] The outer principal surface 172 is located on the second principal surface 104 side of the SiC semiconductor layer 102 with respect to the active principal surface 171. In this embodiment, the outer region 112 is formed by digging down the first principal surface 103 of the SiC semiconductor layer 102 toward the second principal surface 104 side. Therefore, the outer principal surface 172 is formed in a region recessed toward the second principal surface 104 side of the SiC semiconductor layer 102 with respect to the active principal surface 171.

[0595] The outer principal surface 172 may be located on the second principal surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The outer principal surface 172 may be formed at a depth position substantially equal to the bottom wall of each source trench 155. The outer principal surface 172 may be located on substantially the same plane as the bottom wall of each source trench 155.

[0596] The distance between the outer major surface 172 and the second major surface 104 of the SiC semiconductor layer 102 may be approximately equal to the distance between the bottom wall of each source trench 155 and the second major surface 104 of the SiC semiconductor layer 102 .

[0597] Outer principal surface 172 may be located on the second principal surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155. Outer principal surface 172 may be located on the second principal surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155 within a range of 0 μm or more and 1 μm or less.

[0598] SiC epitaxial layer 107 is exposed from outer main surface 172. More specifically, high concentration region 108 of SiC epitaxial layer 107 is exposed from outer main surface 172 of outer region 112. Outer main surface 172 faces low concentration region 109 of SiC epitaxial layer 107 with high concentration region 108 of SiC epitaxial layer 107 sandwiched therebetween.

[0599] In this embodiment, the active region 111 is partitioned into a plateau shape by the outer region 112. The active region 111 is formed as an active plateau 173 that protrudes upward from the outer region 112.

[0600] The active plateau 173 includes an active sidewall 174 connecting the active main surface 171 and the outer main surface 172. The active sidewall 174 defines a boundary region between the active region 111 and the outer region 112. The first main surface 103 of the SiC semiconductor layer 102 is formed by the active main surface 171, the outer main surface 172, and the active sidewall 174.

[0601] In this embodiment, the active sidewall 174 extends along the normal direction Z of the active principal surface 171 (outer principal surface 172). The active sidewall 174 is formed by the m-plane and a-plane of a SiC single crystal.

[0602] The active sidewall 174 may have an inclined surface that slopes downward from the active principal surface 171 toward the outer principal surface 172. The inclination angle of the active sidewall 174 is the angle that the active sidewall 174 forms with the active principal surface 171 within the SiC semiconductor layer 102.

[0603] In this case, the inclination angle of the active sidewall 174 may be greater than 90° and less than or equal to 135°. The inclination angle of the active sidewall 174 may be greater than 90° and less than or equal to 95°, greater than or equal to 95° and less than or equal to 100°, greater than or equal to 100° and less than or equal to 110°, greater than or equal to 110° and less than or equal to 120°, or greater than or equal to 120° and less than or equal to 135°. The inclination angle of the active sidewall 174 is preferably greater than 90° and less than or equal to 95°.

[0604] The SiC epitaxial layer 107 is exposed from the active sidewall 174. More specifically, the high concentration region 108 of the SiC epitaxial layer 107 is exposed from the active sidewall 174.

[0605] At least the body region 141 is exposed from a region of the active sidewall 174 on the active main surface 171 side. 23 and 24 show an example in which the body region 141 and the source region 163 are exposed from the active sidewall 174.

[0606] In the outer region 112, the surface layer portion of the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102 is + In the semiconductor device, a p-type diode region 181 (impurity region), a p-type outer deep well region 182, and a p-type field limit structure 183 are formed.

[0607] The diode region 181 is formed in the outer region 112 in a region between the active sidewall 174 and the side surfaces 105A-105D of the SiC semiconductor layer 102. The diode region 181 is formed at a distance from the active sidewall 174 and the side surfaces 105A-105D.

[0608] The diode region 181 extends in a strip shape along the active region 111 in a plan view. In this embodiment, the diode region 181 is formed in an endless shape (a square ring shape in this embodiment) surrounding the active region 111 in a plan view.

[0609] The diode region 181 overlaps with the source lead-out wiring 123 in a plan view. The diode region 181 is electrically connected to the source lead-out wiring 123. The diode region 181 forms a part of the avalanche current absorption structure.

[0610] The diode region 181 forms a pn junction with the SiC semiconductor layer 102. More specifically, the diode region 181 is located in the SiC epitaxial layer 107. Therefore, the diode region 181 forms a pn junction with the SiC epitaxial layer 107.

[0611] More specifically, the diode region 181 is located in the high concentration region 108 of the SiC epitaxial layer 107. Therefore, the diode region 181 forms a pn junction with the high concentration region 108. As a result, a pn junction diode Dpn is formed in which the diode region 181 serves as an anode and the SiC semiconductor layer 102 serves as a cathode.

[0612] The entire diode region 181 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom walls of each gate trench 142. The bottom of the diode region 181 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom walls of each source trench 155.

[0613] The bottom of the diode region 181 may be formed at a depth position substantially equal to that of the bottom of the contact region 164. The bottom of the diode region 181 may be located on substantially the same plane as the bottom of the contact region 164.

[0614] The p-type impurity concentration of the diode region 181 is approximately equal to the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the diode region 181 is greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of the diode region 181 is 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 It may be the following.

[0615] The outer deep well region 182 is formed in a region between the active sidewall 174 and the diode region 181 in a plan view. In this embodiment, the outer deep well region 182 is formed at an interval from the active sidewall 174 toward the diode region 181. The outer deep well region 182 is also referred to as a breakdown voltage adjusting region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the outer region 112.

[0616] The outer deep well region 182 extends in a strip shape along the active region 111 in a plan view. In this embodiment, the outer deep well region 182 is formed in an endless shape (a square ring shape in this embodiment) surrounding the active region 111 in a plan view.

[0617] The outer deep well region 182 is electrically connected to the source lead-out wiring 123 via the diode region 181. The outer deep well region 182 may form a part of a pn junction diode Dpn. The outer deep well region 182 may form a part of an avalanche current absorption structure.

[0618] The entire outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom walls of each gate trench 142. The bottom of the outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom walls of each source trench 155.

[0619] The bottom of outer deep well region 182 is located on the second main surface 104 side of SiC semiconductor layer 102 relative to the bottom of diode region 181. The bottom of outer deep well region 182 may be formed at a depth position substantially equal to the bottom of each deep well region 165. The bottom of outer deep well region 182 may be located on substantially the same plane as the bottom of each deep well region 165.

[0620] The distance between the bottom of the outer deep well region 182 and the outer major surface 172 may be approximately equal to the distance between the bottom of each deep well region 165 and the bottom wall of each source trench 155 .

[0621] The distance between the bottom of the outer deep well region 182 and the second major surface 104 of the SiC semiconductor layer 102 may be approximately equal to the distance between the bottom of each deep well region 165 and the second major surface 104 of the SiC semiconductor layer 102.

[0622] This makes it possible to suppress variation between the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 and the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0623] Therefore, the withstand voltage (eg, breakdown resistance) of the SiC semiconductor layer 102 can be prevented from being limited by the shape of the outer deep well region 182 and the shape of each deep well region 165, and therefore the withstand voltage can be appropriately improved.

[0624] The bottom of the outer deep well region 182 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of each deep well region 165. The bottom of the outer deep well region 182 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of each deep well region 165 within a range of 0 μm or more and 1 μm or less.

[0625] An inner periphery of the outer deep well region 182 may extend close to the boundary region between the active region 111 and the outer region 112. The outer deep well region 182 may cross the boundary region between the active region 111 and the outer region 112.

[0626] The inner periphery of the outer deep well region 182 may cover a corner connecting the active sidewall 174 and the outer major surface 172. The inner periphery of the outer deep well region 182 may further extend along the active sidewall 174 and connect to the body region 141.

[0627] In this embodiment, the outer peripheral edge of the outer deep well region 182 covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The outer deep well region 182 may overlap with the source lead-out wiring 123 in a plan view. The outer peripheral edge of the outer deep well region 182 may be formed at a distance from the diode region 181 toward the active sidewall 174.

[0628] The p-type impurity concentration of the outer deep well region 182 may be equal to or lower than the p-type impurity concentration of the diode region 181. The p-type impurity concentration of the outer deep well region 182 may be lower than the p-type impurity concentration of the diode region 181.

[0629] The p-type impurity concentration of the outer deep well region 182 may be approximately equal to the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the outer deep well region 182 may be approximately equal to the p-type impurity concentration of the body region 141.

[0630] The p-type impurity concentration of the outer deep well region 182 may be greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of the outer deep well region 182 may be less than the p-type impurity concentration of the body region 141.

[0631] The p-type impurity concentration of the outer deep well region 182 may be equal to or less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the outer deep well region 182 may be less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the outer deep well region 182 may be greater than or equal to 1.0×10 17 cm -3 Above 1.0×10 19 cm -3 It may be the following.

[0632] The field limit structure 183 is formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view. In this embodiment, the field limit structure 183 is formed at an interval from the side surfaces 105A to 105D toward the diode region 181.

[0633] The field limit structure 183 includes one or more (for example, 2 to 20) field limit regions 184. In this embodiment, the field limit structure 183 includes a field limit region group having a plurality (five) of field limit regions 184A, 184B, 184C, 184D, and 184E.

[0634] The field limit regions 184A to 184E are formed in this order at intervals along a direction away from the diode region 181. Each of the field limit regions 184A to 184E extends in a strip shape along the periphery of the active region 111 in a plan view.

[0635] More specifically, the field limit regions 184A to 184E are each formed in an endless shape (a quadrangular ring shape in this embodiment) in a plan view surrounding the active region 111. The field limit regions 184A to 184E are also referred to as FLR (Field Limiting Ring) regions.

[0636] In this embodiment, the bottoms of the field limit regions 184A to 184E are located closer to the second main surface 104 of the SiC semiconductor layer 102 than the bottom of the diode region 181.

[0637] In this embodiment, the innermost field limit region 184A of the field limit regions 184A to 184E covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The field limit region 184A may overlap the above-mentioned source lead-out wiring 123 in a plan view.

[0638] The field limit region 184A is electrically connected to the source lead-out wiring 123 via the diode region 181. The field limit region 184A may form a part of the pn junction diode Dpn. The field limit region 184A may form a part of the avalanche current absorption structure.

[0639] The entire field limit regions 184A-184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom walls of the gate trenches 142. The bottoms of the field limit regions 184A-184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom walls of the source trenches 155.

[0640] The field limit regions 184A-184E may be formed at a depth substantially equal to that of each deep well region 165 (outer deep well region 182). The bottoms of the field limit regions 184A-184E may be located on substantially the same plane as the bottoms of each deep well region 165 (outer deep well region 182).

[0641] The bottoms of the field limit regions 184A-184E may be located on the outer main surface 172 side with respect to the bottoms of the deep well regions 165 (outer deep well regions 182). The bottoms of the field limit regions 184A-184E may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottoms of the deep well regions 165 (outer deep well regions 182).

[0642] The width between adjacent field limit regions 184A-184E may be different from each other. The width between adjacent field limit regions 184A-184E may be larger in a direction away from the active region 111. The width between adjacent field limit regions 184A-184E may be smaller in a direction away from the active region 111.

[0643] The depths of the field limit regions 184A to 184E may be different from one another. The depths of the field limit regions 184A to 184E may decrease in a direction away from the active region 111. The depths of the field limit regions 184A to 184E may increase in a direction away from the active region 111.

[0644] The p-type impurity concentration of the field limit regions 184A to 184E may be equal to or lower than the p-type impurity concentration of the diode region 181. The p-type impurity concentration of the field limit regions 184A to 184E may be lower than the p-type impurity concentration of the diode region 181.

[0645] The p-type impurity concentration of the field limit regions 184A-184E may be equal to or lower than the p-type impurity concentration of the outer deep well region 182. The p-type impurity concentration of the field limit regions 184A-184E may be lower than the p-type impurity concentration of the outer deep well region 182.

[0646] The p-type impurity concentration of the field limit regions 184A-184E may be equal to or higher than the p-type impurity concentration of the outer deep well region 182. The p-type impurity concentration of the field limit regions 184A-184E may be higher than the p-type impurity concentration of the outer deep well region 182.

[0647] The p-type impurity concentration of the field limit regions 184A to 184E is 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 It is preferable that the p-type impurity concentration of the diode region 181>the p-type impurity concentration of the outer deep well region 182>the p-type impurity concentration of the field limit regions 184A to 184E.

[0648] The field limit structure 183 relieves electric field concentration in the outer region 112. The number, width, depth, p-type impurity concentration, etc. of the field limit regions 184 can take various values ​​depending on the electric field to be relieved.

[0649] In this embodiment, an example has been described in which the field limit structure 183 includes one or more field limit regions 184 formed in the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0650] However, the field limit structure 183 may include one or more field limit regions 184 formed in the region between the active sidewall 174 and the diode region 181 in a planar view, instead of the region between the diode region 181 and the side surfaces 105A-105D of the SiC semiconductor layer 102.

[0651] The field limit structure 183 may also include one or more field limit regions 184 formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a planar view, and one or more field limit regions 184 formed in a region between the active sidewall 174 and the diode region 181 in a planar view.

[0652] In the outer region 112, an outer insulating layer 191 is formed on the first main surface 103 of the SiC semiconductor layer 102. The outer insulating layer 191 forms a part of the main surface insulating layer 113. The outer insulating layer 191 forms a part of the insulating side surfaces 114A-114D of the main surface insulating layer 113.

[0653] The outer insulating layer 191 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112. The outer insulating layer 191 is formed in a film shape along the active sidewall 174 and the outer main surface 172. The outer insulating layer 191 is continuous with the gate insulating layer 148 on the active main surface 171. More specifically, the outer insulating layer 191 is continuous with the third region 148c of the gate insulating layer 148.

[0654] The outer insulating layer 191 may include silicon oxide. The outer insulating layer 191 may include other insulating films such as silicon nitride. In this embodiment, the outer insulating layer 191 is formed of the same insulating material type as the gate insulating layer 148.

[0655] The outer insulating layer 191 includes a first region 191a and a second region 191b. The first region 191a of the outer insulating layer 191 covers the active sidewall 174. The second region 191b of the outer insulating layer 191 covers the outer major surface 172.

[0656] The thickness of the second region 191b of the outer insulating layer 191 may be equal to or less than the thickness of the first region 191a of the outer insulating layer 191. The thickness of the second region 191b of the outer insulating layer 191 may be less than the thickness of the first region 191a of the outer insulating layer 191.

[0657] The thickness of the first region 191a of the outer insulating layer 191 may be approximately equal to the thickness of the first region 191a of the gate insulating layer 148. The thickness of the second region 191b of the outer insulating layer 191 may be approximately equal to the thickness of the third region 148c of the gate insulating layer 148. Of course, the outer insulating layer 191 may be formed to have a uniform thickness.

[0658] 23 and 24, the SiC semiconductor device 101 further includes a sidewall 192 covering the active sidewall 174. The sidewall 192 protects and reinforces the active plateau 173 from the outer region 112 side.

[0659] Moreover, the sidewalls 192 form a step reduction structure that reduces the step formed between the active principal surface 171 and the outer principal surface 172. When an upper layer structure (covering layer) is formed to cover the boundary region between the active region 111 and the outer region 112, the upper layer structure covers the sidewalls 192. The sidewalls 192 improve the flatness of the upper layer structure.

[0660] The sidewall 192 may have an inclined portion 193 that slopes downward from the active principal surface 171 toward the outer principal surface 172. The inclined portion 193 can appropriately reduce the step.

[0661] The inclined portion 193 of the sidewall 192 may be formed in a concave curve toward the SiC semiconductor layer 102 side. The inclined portion 193 of the sidewall 192 may be formed in a convex curve toward the opposite side to the SiC semiconductor layer 102.

[0662] The inclined portion 193 of the sidewall 192 may extend in a plane from the active principal surface 171 side toward the outer principal surface 172 side. The inclined portion 193 of the sidewall 192 may extend linearly from the active principal surface 171 side toward the outer principal surface 172 side.

[0663] The inclined portion 193 of the sidewall 192 may be formed in a step-like shape descending from the active principal surface 171 toward the outer principal surface 172. In other words, the inclined portion 193 of the sidewall 192 may have one or more steps recessed toward the outer principal surface 172. The multiple steps increase the surface area of ​​the inclined portion 193 of the sidewall 192, enhancing adhesion to the upper layer structure.

[0664] The inclined portion 193 of the sidewall 192 may include a plurality of ridges that bulge outwardly of the sidewall 192. The plurality of ridges increases the surface area of ​​the inclined portion 193 of the sidewall 192, enhancing adhesion to the upper layer structure.

[0665] The inclined portion 193 of the sidewall 192 may include a plurality of depressions recessed toward the inside of the sidewall 192. The plurality of depressions increases the surface area of ​​the inclined portion 193 of the sidewall 192, and enhances adhesion to an upper layer structure.

[0666] The sidewall 192 is formed in a self-aligned manner with respect to the active main surface 171. More specifically, the sidewall 192 is formed along the active sidewall 174. In this embodiment, the sidewall 192 is formed in an endless shape (a quadrangular ring in this embodiment) surrounding the active region 111 in a plan view.

[0667] The sidewall 192 preferably includes p-type polysilicon doped with p-type impurities. In this case, the sidewall 192 can be formed simultaneously with the gate electrode layer 149 and the source electrode layer 157.

[0668] The p-type impurity concentration of the sidewall 192 is equal to or higher than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the sidewall 192 is higher than the p-type impurity concentration of the body region 141. The p-type impurity of the sidewall 192 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0669] The p-type impurity concentration of the sidewall 192 is 1×10 18 cm -3 More than 1×10 22 cm -3 The sheet resistance of the sidewall 192 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this embodiment).

[0670] The p-type impurity concentration of the sidewall 192 may be approximately equal to the p-type impurity concentration of the gate electrode layer 149. The sheet resistance of the sidewall 192 may be approximately equal to the sheet resistance of the gate electrode layer 149.

[0671] The sidewall 192 may include n-type polysilicon instead of or in addition to p-type polysilicon. The sidewall 192 may include at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of or in addition to p-type polysilicon.

[0672] The sidewalls 192 may include an insulating material, in which case the sidewalls 192 can improve the insulation of the active region 111 from the outer region 112.

[0673] 20 to 24, an interlayer insulating layer 201 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 201 forms a part of the main surface insulating layer 113. The interlayer insulating layer 201 forms a part of the insulating side surfaces 114A to 114D of the main surface insulating layer 113. The main surface insulating layer 113 has a layered structure including the gate insulating layer 148 (outer insulating layer 191) and the interlayer insulating layer 201.

[0674] The interlayer insulating layer 201 selectively covers the active region 111 and the outer region 112. More specifically, the interlayer insulating layer 201 selectively covers the third region 148c of the gate insulating layer 148 and the outer insulating layer 191.

[0675] The interlayer insulating layer 201 is formed in a film shape along the active principal surface 171 and the outer principal surface 172. The interlayer insulating layer 201 selectively covers the trench gate structure 161, the gate wiring layer 150, and the trench source structure 162 in the active region 111. The interlayer insulating layer 201 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112.

[0676] The interlayer insulating layer 201 is formed along the outer surface (the inclined portion 193) of the sidewall 192 in the boundary region between the active region 111 and the outer region 112. The interlayer insulating layer 201 forms part of an upper structure covering the sidewall 192.

[0677] The interlayer insulating layer 201 may include silicon oxide or silicon nitride. The interlayer insulating layer 201 may include PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass), which are examples of silicon oxide.

[0678] The interlayer insulating layer 201 may have a layered structure including a PSG layer and a BPSG layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The interlayer insulating layer 201 may have a layered structure including a BPSG layer and a PSG layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0679] The interlayer insulating layer 201 has a gate contact hole 202, a source contact hole 203, and a diode contact hole 204 formed therein. The interlayer insulating layer 201 also has an anchor hole 205 formed therein.

[0680] The gate contact hole 202 exposes the gate wiring layer 150 in the active region 111. The gate contact hole 202 may be formed in a strip shape along the gate wiring layer 150. An opening edge portion of the gate contact hole 202 is formed in a convex curved shape toward the inside of the gate contact hole 202.

[0681] The source contact hole 203 exposes the source region 163, the contact region 164, and the trench source structure 162 in the active region 111. The source contact hole 203 may be formed in a strip shape along the trench source structure 162, etc. An opening edge portion of the source contact hole 203 is formed in a convex curved shape toward the inside of the source contact hole 203.

[0682] The diode contact hole 204 exposes the diode region 181 in the outer region 112. The diode contact hole 204 may be formed in a strip shape (more specifically, endless shape) extending along the diode region 181.

[0683] The diode contact hole 204 may expose the outer deep well region 182 and / or the field limit structure 183. The opening edge portion of the diode contact hole 204 is formed in a convex curve toward the inside of the diode contact hole 204.

[0684] The anchor holes 205 are formed by digging down the interlayer insulating layer 201 in the outer region 112. The anchor holes 205 are formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a planar view. More specifically, the anchor holes 205 are formed in a region between the field limit structure 183 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a planar view.

[0685] The anchor hole 205 exposes the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102. The opening edge portion of the anchor hole 205 is formed in a convex curved shape facing the inside of the anchor hole 205.

[0686] 18, the anchor holes 205 extend in a strip shape along the active region 111 in a plan view. In this embodiment, the anchor holes 205 are formed in an endless shape (a quadrangular ring shape in this embodiment) surrounding the active region 111 in a plan view.

[0687] In this embodiment, one anchor hole 205 is formed in the portion of the interlayer insulating layer 201 that covers the outer region 112. However, a plurality of anchor holes 205 may be formed in the portion of the interlayer insulating layer 201 that covers the outer region 112.

[0688] A main surface gate electrode layer 115 and a main surface source electrode layer 121 are formed on the interlayer insulating layer 201. The main surface gate electrode layer 115 and the main surface source electrode layer 121 each have a laminated structure including a barrier electrode layer 206 and a main electrode layer 207 laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0689] The barrier electrode layer 206 may have a single layer structure including a titanium layer or a titanium nitride layer, or may have a multilayer structure including a titanium layer and a titanium nitride layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0690] The thickness of the main electrode layer 207 is greater than the thickness of the barrier electrode layer 206. The main electrode layer 207 includes a conductive material having a resistance value less than a resistance value of the barrier electrode layer 206. The main electrode layer 207 may include at least one of aluminum, copper, an aluminum alloy, or a copper alloy.

[0691] The main electrode layer 207 may include at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-copper alloy. In this embodiment, the main electrode layer 207 includes an aluminum-silicon-copper alloy.

[0692] Outer gate fingers 117 of the main surface gate electrode layer 115 extend into the gate contact holes 202 from above the interlayer insulating layer 201. The outer gate fingers 117 are electrically connected to the gate wiring layer 150 in the gate contact holes 202. As a result, an electrical signal from the gate pad 116 is transmitted to the gate electrode layer 149 via the outer gate fingers 117.

[0693] The source pad 122 of the main surface source electrode layer 121 extends from above the interlayer insulating layer 201 into the source contact hole 203 and the source sub-trench 168. The source pad 122 is electrically connected to the source region 163, the contact region 164, and the source electrode layer 157 within the source contact hole 203 and the source sub-trench 168.

[0694] The source electrode layer 157 may be formed by utilizing a partial region of the source pad 122. The source electrode layer 157 may be formed by a portion of the source pad 122 that extends into each source trench 155.

[0695] The source lead-out wiring 123 of the main surface source electrode layer 121 enters the diode contact hole 204 from above the interlayer insulating layer 201. The source lead-out wiring 123 is electrically connected to the diode region 181 in the diode contact hole 204.

[0696] The source connection portion 124 of the main surface source electrode layer 121 is led out from the active region 111 across the sidewall 192 to the outer region 112. The source connection portion 124 forms a part of an upper layer structure covering the sidewall 192.

[0697] The aforementioned passivation layer 125 is formed on the interlayer insulating layer 201. The passivation layer 125 is formed in a film shape along the interlayer insulating layer 201. The passivation layer 125 selectively covers the active region 111 and the outer region 112 via the interlayer insulating layer 201.

[0698] The passivation layer 125 extends from the active region 111 across the sidewalls 192 to the outer region 112. The passivation layer 125 forms part of an upper structure that covers the sidewalls 192.

[0699] 23, in the outer region 112, the passivation layer 125 extends from above the interlayer insulating layer 201 into the anchor hole 205. The passivation layer 125 is connected to the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102 within the anchor hole 205. In a region located above the anchor hole 205 on the outer surface of the passivation layer 125, a recess 211 is formed that is recessed in accordance with the anchor hole 205.

[0700] The above-mentioned resin layer 129 is formed on the passivation layer 125. The resin layer 129 is formed in a film shape along the passivation layer 125. The resin layer 129 selectively covers the active region 111 and the outer region 112, with the passivation layer 125 and the interlayer insulating layer 201 sandwiched between them.

[0701] The resin layer 129 is extended from the active region 111 across the sidewall 192 to the outer region 112. The resin layer 129 forms part of an upper layer structure that covers the sidewall 192.

[0702] 23, resin layer 129 has an anchor portion that enters recess 211 of passivation layer 125 in outer region 112. In this manner, an anchor structure for increasing the connection strength of resin layer 129 is formed in outer region 112.

[0703] The anchor structure includes an uneven structure formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112. More specifically, the uneven structure (anchor structure) includes unevenness formed by utilizing interlayer insulating layer 201 covering outer main surface 172. More specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in interlayer insulating layer 201.

[0704] The resin layer 129 is engaged with the anchor hole 205. In this embodiment, the resin layer 129 is engaged with the anchor hole 205 via the passivation layer 125. This can increase the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102, thereby suppressing peeling of the resin layer 129.

[0705] As described above, the SiC semiconductor device 101 can achieve the same effects as those described for the SiC semiconductor device 1. Furthermore, according to the SiC semiconductor device 101, the depletion layer can be expanded from the boundary region (pn junction) between the SiC semiconductor layer 102 and the deep well region 165 toward the region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the gate trench 142.

[0706] This narrows the current path of the short-circuit current flowing between the main surface source electrode layer 121 and the drain electrode layer 133. In addition, the depletion layer extending from the boundary region between the SiC semiconductor layer 102 and the deep well region 165 reduces the feedback capacitance Crss inversely proportionally. This makes it possible to provide a SiC semiconductor device 101 that can improve the short-circuit resistance and reduce the feedback capacitance Crss.

[0707] The depletion layer extending from the boundary region (pn junction) between the SiC semiconductor layer 102 and the deep well region 165 may overlap the bottom wall of the gate trench 142. In this case, the depletion layer extending from the bottom of the deep well region 165 may overlap the bottom wall of the gate trench 142.

[0708] Moreover, according to the SiC semiconductor device 101, since the region occupied by the depletion layer in the SiC semiconductor layer 102 can be increased, the feedback capacitance Crss can be reduced inversely proportionally. The feedback capacitance Crss is the electrostatic capacitance between the gate electrode layer 149 and the drain electrode layer 133.

[0709] Moreover, according to the SiC semiconductor device 101, the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 is approximately constant. This makes it possible to suppress variation in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0710] Therefore, the withstand voltage (for example, breakdown resistance) of the SiC semiconductor layer 102 can be prevented from being limited by the form of the deep well region 165, and the withstand voltage can be appropriately improved.

[0711] Moreover, according to the SiC semiconductor device 101, a diode region 181 is formed in the outer region 112. This diode region 181 is electrically connected to the main surface source electrode layer 121. This allows an avalanche current generated in the outer region 112 to flow into the main surface source electrode layer 121 via the diode region 181.

[0712] That is, the avalanche current generated in the outer region 112 can be absorbed by the diode region 181 and the main surface source electrode layer 121. As a result, the stability of the operation of the MISFET can be improved.

[0713] Moreover, according to the SiC semiconductor device 101, the outer deep well region 182 is formed in the outer region 112. This makes it possible to adjust the breakdown voltage of the SiC semiconductor layer 102 in the outer region 112.

[0714] In particular, in the SiC semiconductor device 101, the outer deep well region 182 is formed at a depth position substantially equal to that of the deep well region 165. More specifically, the bottom of the outer deep well region 182 is located on substantially the same plane as the bottom of the deep well region 165.

[0715] The distance between the bottom of the outer deep well region 182 and the second major surface 104 of the SiC semiconductor layer 102 is approximately equal to the distance between the bottom of the deep well region 165 and the second major surface 104 of the SiC semiconductor layer 102 .

[0716] This makes it possible to suppress variation between the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 and the distance between the bottom of the deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0717] This makes it possible to prevent the breakdown voltage (for example, breakdown resistance) of the SiC semiconductor layer 102 from being limited by the configuration of the outer deep well region 182 and the configuration of the deep well region 165. As a result, the breakdown voltage can be appropriately improved.

[0718] In particular, in the SiC semiconductor device 101, the outer region 112 is formed in a region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the active region 111. This allows the position of the bottom of the outer deep well region 182 to be appropriately brought close to the position of the bottom of the deep well region 165.

[0719] That is, when forming outer deep well region 182, it is not necessary to introduce p-type impurities into a relatively deep position in the surface layer of first main surface 103 of SiC semiconductor layer 102. Therefore, it is possible to appropriately prevent the position of the bottom of outer deep well region 182 from shifting significantly from the position of the bottom of deep well region 165.

[0720] Moreover, in SiC semiconductor device 101, outer main surface 172 of outer region 112 is located on approximately the same plane as the bottom wall of source trench 155. As a result, when p-type impurities are introduced into the bottom wall of source trench 155 and outer main surface 172 of outer region 112 with equal energy, deep well region 165 and outer deep well region 182 can be formed at approximately the same depth position.

[0721] As a result, the position of the bottom of the outer deep well region 182 can be more appropriately prevented from shifting significantly from the position of the bottom of the deep well region 165.

[0722] Moreover, according to the SiC semiconductor device 101, the field limit structure 183 is formed in the outer region 112. This makes it possible to obtain an electric field relaxation effect by the field limit structure 183 in the outer region 112. As a result, the breakdown resistance of the SiC semiconductor layer 102 can be appropriately improved.

[0723] Moreover, according to the SiC semiconductor device 101, the active region 111 is formed as a plateau-shaped active plateau 173. The active plateau 173 includes an active sidewall 174 connecting the active main surface 171 of the active region 111 and the outer main surface 172 of the outer region 112.

[0724] A step reduction structure is formed in the region between the active principal surface 171 and the outer principal surface 172 to reduce the step between the active principal surface 171 and the outer principal surface 172. The step reduction structure includes a sidewall 192.

[0725] This can appropriately reduce the step between the active principal surface 171 and the outer principal surface 172. This can appropriately improve the flatness of the upper layer structure formed on the sidewall 192. In the SiC semiconductor device 101, an interlayer insulating layer 201, a principal surface source electrode layer 121, a passivation layer 125, and a resin layer 129 are formed as an example of the upper layer structure.

[0726] Moreover, according to SiC semiconductor device 101, an anchor structure for increasing the connection strength of resin layer 129 is formed in outer region 112. The anchor structure includes an uneven structure formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112.

[0727] More specifically, the unevenness structure (anchor structure) includes unevenness formed by utilizing interlayer insulating layer 201 formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112. More specifically, the unevenness structure (anchor structure) includes anchor holes 205 formed in interlayer insulating layer 201.

[0728] The resin layer 129 is engaged with the anchor hole 205. In this embodiment, the resin layer 129 is engaged with the anchor hole 205 via the passivation layer 125. This can increase the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102, thereby appropriately suppressing peeling of the resin layer 129.

[0729] Moreover, according to the SiC semiconductor device 101, a trench gate structure 161 is formed in which a gate electrode layer 149 is embedded in a gate trench 142 with a gate insulating layer 148 sandwiched therebetween. In this trench gate structure 161, the gate electrode layer 149 is covered with a low resistance electrode layer 167 in the limited space of the gate trench 142. According to such a structure, it is possible to achieve the effects described with reference to FIG. 25.

[0730] Fig. 25 is a graph for explaining the sheet resistance in the gate trench 142. In Fig. 25, the vertical axis represents the sheet resistance [Ω / □], and the horizontal axis represents the items. Fig. 25 shows a first bar graph BL1, a second bar graph BL2, and a third bar graph BL3.

[0731] The first bar graph BL1 represents the sheet resistance in the gate trench 142 filled with n-type polysilicon. The second bar graph BL2 represents the sheet resistance in the gate trench 142 filled with p-type polysilicon.

[0732] A third bar graph BL3 represents the sheet resistance in the gate trench 142 in which the gate electrode layer 149 (p-type polysilicon) and the low-resistance electrode layer 167 are embedded. Here, a case will be described in which the low-resistance electrode layer 167 is formed of TiSi2 (p-type titanium silicide) as an example of polycide (silicide).

[0733] With reference to the first bar graph BL1, the sheet resistance in the gate trench 142 filled with n-type polysilicon was 10 Ω / □. With reference to the second bar graph BL2, the sheet resistance in the gate trench 142 filled with p-type polysilicon was 200 Ω / □. With reference to the third bar graph BL3, the sheet resistance in the gate trench 142 filled with the gate electrode layer 149 (p-type polysilicon) and the low resistance electrode layer 167 was 2 Ω / □.

[0734] P-type polysilicon has a work function different from that of n-type polysilicon. According to a structure in which p-type polysilicon is embedded in the gate trench 142, the gate threshold voltage Vth can be increased by about 1V.

[0735] However, p-type polysilicon has a sheet resistance several tens of times (here, 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for gate electrode layer 149, the energy loss increases significantly with an increase in the parasitic resistance in gate trench 142 (hereinafter, simply referred to as "gate resistance").

[0736] In contrast, with a structure having the low resistance electrode layer 167 on the gate electrode layer 149 (p-type polysilicon), the sheet resistance can be reduced to 1 / 100 or less compared to a case where the low resistance electrode layer 167 is not formed. In other words, with a structure having the low resistance electrode layer 167, the sheet resistance can be reduced to 1 / 5 or less compared to the gate electrode layer 149 including n-type polysilicon.

[0737] In this way, the structure having the low resistance electrode layer 167 can reduce the sheet resistance in the gate trench 142 while increasing the gate threshold voltage Vth (for example, by about 1 V). This allows the gate resistance to be reduced, and therefore the current can be efficiently diffused along the trench gate structure 161. As a result, the switching delay can be reduced.

[0738] Furthermore, the structure having the low resistance electrode layer 167 does not require an increase in the p-type impurity concentration of the body region 141 and the p-type impurity concentration of the contact region 164. Therefore, the gate threshold voltage Vth can be appropriately increased while suppressing an increase in the channel resistance.

[0739] The low resistance electrode layer 167 may include at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, or WSi2. Among these materials, NiSi, CoSi2, and TiSi2 are particularly suitable as a polycide layer for forming the low resistance electrode layer 167, since they have relatively small resistivity and temperature dependency.

[0740] As a result of further verification by the inventors of the present application, when TiSi2 was used as the material for the low resistance electrode layer 167, an increase in the leakage current between the gate and source was observed when a low electric field was applied. In contrast, when CoSi2 was used, no increase in the leakage current between the gate and source was observed when a low electric field was applied. Considering this point, it is considered that CoSi2 is most preferable as the polycide layer forming the low resistance electrode layer 167.

[0741] Furthermore, in the SiC semiconductor device 101, the gate wiring layer 150 is covered with the low resistance electrode layer 167. This makes it possible to reduce the gate resistance in the gate wiring layer 150.

[0742] In particular, in a structure in which the gate electrode layer 149 and the gate wiring layer 150 are covered with the low resistance electrode layer 167, the current can be efficiently diffused along the trench gate structure 161. Therefore, the switching delay can be appropriately reduced.

[0743] Fig. 26 is an enlarged view of a region corresponding to Fig. 19, showing a SiC semiconductor device 221 according to a fourth embodiment of the present invention. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII shown in Fig. 26. In the following, structures corresponding to those described for SiC semiconductor device 101 are given the same reference symbols and will not be described.

[0744] 26 and 27, a SiC semiconductor device 221 includes an outer gate trench 222 formed in a first main surface 103 of a SiC semiconductor layer 102 in an active region 111. The outer gate trench 222 extends in a strip shape along the periphery of the active region 111.

[0745] The outer gate trench 222 is formed in a region directly below the outer gate finger 117 on the first main surface 103 of the SiC semiconductor layer 102. The outer gate trench 222 extends along the outer gate finger 117.

[0746] More specifically, the outer gate trench 222 is formed along three side surfaces 105A, 105B, 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions. The outer gate trench 222 may be formed in an endless shape (for example, a rectangular ring shape) surrounding the inner region of the active region 111.

[0747] The outer gate trench 222 communicates with the contact trench portion 144 of each gate trench 142. As a result, the outer gate trench 222 and the gate trench 142 are formed by a single trench.

[0748] A gate wiring layer 150 is buried in the outer gate trench 222. The gate wiring layer 150 is connected to the gate electrode layer 149 at a communicating portion between the gate trench 142 and the outer gate trench 222.

[0749] A low resistance electrode layer 167 covering the gate wiring layer 150 is formed in the outer gate trench 222. In this case, the low resistance electrode layer 167 covering the gate electrode layer 149 and the low resistance electrode layer 167 covering the gate wiring layer 150 are located within one trench.

[0750] As described above, the SiC semiconductor device 221 can achieve the same effects as those described for the SiC semiconductor device 101. Moreover, according to the SiC semiconductor device 221, it is not necessary to extend the gate wiring layer 150 onto the first main surface 103 of the SiC semiconductor layer 102.

[0751] This makes it possible to prevent the gate wiring layer 150 from facing the SiC semiconductor layer 102 across the gate insulating layer 148 at the opening edge 146 of the gate trench 142 (outer gate trench 222). As a result, it is possible to prevent electric field concentration at the opening edge 146 of the gate trench 142 (outer gate trench 222).

[0752] Fig. 28 is an enlarged view of a region corresponding to Fig. 22, showing a SiC semiconductor device 231 according to a fifth embodiment of the present invention. In the following, structures corresponding to those described with respect to the SiC semiconductor device 101 are given the same reference numerals and descriptions thereof will be omitted.

[0753] 28, the SiC epitaxial layer 107 in this embodiment includes a high concentration region 108, a low concentration region 109, and a concentration gradient region 232 interposed between the high concentration region 108 and the low concentration region 109.

[0754] In the SiC epitaxial layer 107, the concentration gradient region 232 is formed in the outer region 112 in addition to the active region 111. The concentration gradient region 232 is formed throughout the entire SiC epitaxial layer 107.

[0755] The concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually decreases from the high concentration region 108 to the low concentration region 109. In other words, the concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually increases from the low concentration region 109 to the high concentration region 108. The concentration gradient region 232 suppresses abrupt fluctuations in the n-type impurity concentration in the region between the high concentration region 108 and the low concentration region 109.

[0756] When SiC epitaxial layer 107 includes concentration gradient region 232, the n-type impurity concentration of high concentration region 108 is preferably 1.5 to 5 times the n-type impurity concentration of low concentration region 109. The n-type impurity concentration of high concentration region 108 may be 3 to 5 times the n-type impurity concentration of low concentration region 109.

[0757] The thickness of the concentration gradient region 232 may be 0.5 μm or more and 2.0 μm or less. The thickness of the concentration gradient region 232 may be 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2.0 μm or less.

[0758] Although a detailed description will be omitted, the above-mentioned gate trench 142, source trench 155, deep well region 165, outer deep well region 182, etc. are formed in the high concentration region .

[0759] In other words, the aforementioned gate trench 142, source trench 155, deep well region 165, outer deep well region 182, etc. are formed in the region of the SiC semiconductor layer 102 on the first main surface 103 side relative to the boundary region between the high concentration region 108 and the concentration gradient region 232.

[0760] As described above, SiC semiconductor device 231 can also achieve the same effects as those described for SiC semiconductor device 101.

[0761] Fig. 29 is an enlarged view of a region corresponding to Fig. 19, showing a SiC semiconductor device 241 according to a sixth embodiment of the present invention. In the following, structures corresponding to those described with respect to the SiC semiconductor device 101 are given the same reference numerals and descriptions thereof will be omitted.

[0762] 29, in this embodiment, the gate trench 142 is formed in a lattice shape in a plan view. More specifically, the gate trench 142 includes a plurality of first gate trenches 242 and a plurality of second gate trenches 243. The plurality of first gate trenches 242 and the plurality of second gate trenches 243 form an active trench portion 143.

[0763] The multiple first gate trenches 242 are formed at intervals in the second direction Y, and are each formed in a band shape extending along the first direction X. The multiple first gate trenches 242 are formed in a striped shape as a whole in a plan view.

[0764] The sidewalls forming the long sides of each of the first gate trenches 242 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each of the first gate trenches 242 are formed by the m-plane of the SiC single crystal.

[0765] The multiple second gate trenches 243 are formed at intervals in the first direction X, and are each formed in a band shape extending along the second direction Y. The multiple second gate trenches 243 are formed in a stripe shape as a whole in a plan view.

[0766] The sidewalls forming the long sides of each second gate trench 243 are formed by the m-plane of the SiC single crystal. The sidewalls forming the short sides of each second gate trench 243 are formed by the a-plane of the SiC single crystal.

[0767] The first gate trenches 242 and the second gate trenches 243 intersect with each other. This forms one gate trench 142 having a lattice shape in plan view. In the area surrounded by the gate trench 142, a plurality of cell regions 244 are defined.

[0768] The multiple cell regions 244 are arranged in a matrix at intervals in the first direction X and the second direction Y in a plan view. The multiple cell regions 244 are formed in a quadrangular shape in a plan view. In each cell region 244, the body region 141 is exposed from a sidewall of the gate trench 142. The body region 141 is exposed from a sidewall of the gate trench 142 formed by the m-plane and a-plane of the SiC single crystal.

[0769] Of course, the gate trench 142 may be formed in a honeycomb shape as one aspect of a lattice shape in a plan view. In this case, the multiple cell regions 244 may be arranged in a staggered manner at intervals in the first direction X and the second direction Y. Also, in this case, the multiple cell regions 244 may be formed in a hexagonal shape in a plan view.

[0770] Each source trench 155 is formed in the center of each cell region 244 in a plan view. Each source trench 155 is formed in a pattern that appears one by one on a cut surface that appears when each cell region 244 is cut along the first direction X. Also, each source trench 155 is formed in a pattern that appears one by one on a cut surface that appears when each cell region 244 is cut along the second direction Y.

[0771] More specifically, each source trench 155 is formed in a quadrangular shape in a plan view. The four side walls of each source trench 155 are formed by the m-plane and the a-plane of the SiC single crystal.

[0772] The planar shape of each source trench 155 is arbitrary. Each source trench 155 may be formed in a polygonal shape such as a triangular shape, a pentagonal shape, or a hexagonal shape, or in a circular shape or an elliptical shape in a planar view.

[0773] The cross-sectional view taken along line XX-XX in Fig. 29 corresponds to the cross-sectional view shown in Fig. 20. The cross-sectional view taken along line XXI-XXI in Fig. 29 corresponds to the cross-sectional view shown in Fig. 21.

[0774] As described above, the SiC semiconductor device 241 can also achieve the same effects as those described for the SiC semiconductor device 101.

[0775] Although the embodiment of the present invention has been described above, the embodiment of the present invention can be embodied in various other forms.

[0776] In each of the above-described embodiments, the side surfaces 5A, 105A and 5C, 105C of the SiC semiconductor layers 2, 102 face the a-plane of the SiC single crystal, and the side surfaces 5B, 105B and 5D, 105D face the m-plane of the SiC single crystal. However, a configuration in which the side surfaces 5A, 105A and 5C, 105C face the m-plane of the SiC single crystal, and the side surfaces 5B, 105B and 5D, 105D face the a-plane of the SiC single crystal may be adopted.

[0777] In each of the above-described embodiments, examples have been described in which the reforming lines 22A-22D are formed in a continuously extending band shape. However, in each of the above-described embodiments, the reforming lines 22A-22D may be formed in a broken line band shape (dashed line shape). That is, the reforming lines 22A-22D may be formed in a band shape that extends intermittently. In this case, one, two or three of the reforming lines 22A-22D may be formed in a broken line band shape, and the remaining may be formed in a band shape.

[0778] In the above third to sixth embodiments, an example was described in which a plurality of gate trenches 142 (first gate trenches 242) were formed, extending along the m-axis direction ([1-100] direction) of the SiC single crystal.

[0779] However, a plurality of gate trenches 142 (first gate trenches 242) extending along the a-axis direction ([11-20] direction) of the SiC single crystal may be formed. In this case, a plurality of source trenches 155 extending along the a-axis direction ([11-20] direction) of the SiC single crystal are formed.

[0780] In the third to sixth embodiments described above, the source electrode layer 157 is embedded in the source trench 155 with the source insulating layer 156 sandwiched therebetween. However, the source electrode layer 157 may be embedded directly in the source trench 155 without the source insulating layer 156 therebetween.

[0781] In the above-described third to sixth embodiments, the examples in which the source insulating layer 156 is formed along the sidewalls and bottom wall of the source trench 155 have been described.

[0782] However, the source insulating layer 156 may be formed along the sidewalls of the source trench 155 so as to expose the bottom wall of the source trench 155. The source insulating layer 156 may be formed along the sidewalls and bottom wall of the source trench 155 so as to expose a portion of the bottom wall of the source trench 155.

[0783] In addition, source insulating layer 156 may be formed along the bottom wall of source trench 155 so as to expose the side wall of source trench 155. Source insulating layer 156 may be formed along the side wall and bottom wall of source trench 155 so as to expose a portion of the side wall of source trench 155.

[0784] In the above third to sixth embodiments, examples have been described in which the gate electrode layer 149 and the gate wiring layer 150 contain p-type polysilicon doped with p-type impurities. However, when an increase in the gate threshold voltage Vth is not important, the gate electrode layer 149 and the gate wiring layer 150 may contain n-type polysilicon doped with n-type impurities instead of or in addition to p-type polysilicon.

[0785] In this case, the low resistance electrode layer 167 may be formed by silicidating a portion of the gate electrode layer 149 (n-type polysilicon) that forms a surface layer with a metal material. That is, the low resistance electrode layer 167 may include n-type polycide. With such a structure, it is possible to reduce the gate resistance.

[0786] In the third to sixth embodiments described above, n + Instead of the SiC semiconductor substrate 106 of the type + Alternatively, a SiC semiconductor substrate (106) of the type may be adopted. With this structure, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of the MISFET. In this case, in each of the above-mentioned embodiments, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT.

[0787] In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted, that is, a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0788] The above-described embodiments can also be applied to a semiconductor device using a semiconductor material other than SiC. The semiconductor material other than SiC may be a compound semiconductor material. The compound semiconductor material may be either or both of gallium nitride (GaN) and gallium oxide (Ga2O3).

[0789] For example, the third to sixth embodiments may be a compound semiconductor device including a vertical compound semiconductor MISFET in which a compound semiconductor material is used instead of SiC. In the compound semiconductor, magnesium may be used as a p-type impurity (acceptor). Germanium (Ge), oxygen (O) or silicon (Si) may be used as an n-type impurity (donor).

[0790] Below are examples of features extracted from this specification and the drawings.

[0791] [A1] A SiC semiconductor device comprising: a SiC semiconductor layer including a SiC single crystal, the SiC semiconductor layer having a first main surface as an element formation surface, a second main surface opposite the first main surface, and a side surface connecting the first main surface and the second main surface; a roughened surface region formed on the side surface of the SiC semiconductor layer; and a smooth surface region formed in an area of ​​the side surface of the SiC semiconductor layer different from the roughened surface region.

[0792] In this SiC semiconductor device, the smooth surface region can suppress the capillary phenomenon that occurs in the rough surface region, thereby suppressing the conductive bonding material from spreading over the side surfaces of the SiC semiconductor layer.

[0793] [A2] The SiC semiconductor device described in A1, wherein the rough surface region is formed in a region on the second main surface side of the SiC semiconductor layer, and the smooth surface region is formed in a region on the first main surface side of the SiC semiconductor layer relative to the rough surface region.

[0794] [A3] The SiC semiconductor device described in A1 or A2, wherein the rough surface region extends in a band-like manner on the side surface along a tangent direction of the first main surface, and the smooth surface region extends in a band-like manner on the side surface along the tangent direction of the first main surface.

[0795] [A4] A SiC semiconductor device according to any one of A1 to A3, wherein the rough surface region extends in a ring shape surrounding the SiC semiconductor layer at the side surface, and the smooth surface region extends in a ring shape surrounding the SiC semiconductor layer at the side surface.

[0796] [A5] A SiC semiconductor device according to any one of A1 to A4, wherein the rough surface region includes a modified layer modified to have properties different from those of the SiC single crystal, and the smooth surface region is made of a cleavage surface of the SiC single crystal.

[0797] [A6] The SiC semiconductor device described in A5, wherein the modified layer includes a plurality of modified portions each extending in a normal direction of the first main surface of the SiC semiconductor layer and facing each other in a tangential direction of the first main surface of the SiC semiconductor layer.

[0798] [A7] The SiC semiconductor device according to any one of A1 to A6, wherein the SiC semiconductor layer has a thickness of 40 μm or more and 200 μm or less.

[0799] [A8] The SiC semiconductor device according to any one of A1 to A7, wherein the SiC semiconductor layer has a laminated structure including a SiC semiconductor substrate and a SiC epitaxial layer, and the first main surface is formed by the SiC epitaxial layer, the rough surface region is formed in the SiC semiconductor substrate, and the smooth surface region is formed in the SiC epitaxial layer.

[0800] [A9] The SiC semiconductor device according to A8, wherein the smooth surface region is formed in the SiC semiconductor substrate and the SiC epitaxial layer across the boundary between the SiC semiconductor substrate and the SiC epitaxial layer.

[0801] [A10] The SiC semiconductor device according to A8 or A9, wherein the rough surface region is formed in a region on the second main surface side of the SiC semiconductor layer with respect to a boundary between the SiC semiconductor substrate and the SiC epitaxial layer.

[0802] [A11] The SiC semiconductor device according to any one of A8 to A10, wherein the SiC epitaxial layer has a thickness equal to or less than a thickness of the SiC semiconductor substrate.

[0803] [A12] The SiC semiconductor device according to any one of A8 to A11, wherein the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

[0804] [A13] The SiC semiconductor device according to any one of A1 to A12, wherein the SiC single crystal is made of a hexagonal crystal.

[0805] [A14] The SiC semiconductor device according to A13, wherein the SiC single crystal is made of a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal or a 6H-SiC single crystal.

[0806] [A15] The SiC semiconductor device according to A13 or A14, wherein the first main surface of the SiC semiconductor layer faces a c-plane of the SiC single crystal.

[0807] [A16] The SiC semiconductor device according to any one of A13 to A15, wherein the first main surface of the SiC semiconductor layer has an off angle inclined at an angle of 0° or more and 10° or less with respect to a c-plane of the SiC single crystal.

[0808] [A17] The SiC semiconductor device according to A16, wherein the off angle is an angle of 5° or less.

[0809] [A18] The SiC semiconductor device according to A16 or A17, wherein the off angle is an angle exceeding 0° and less than 4°.

[0810] [B1] A SiC semiconductor device comprising a SiC single crystal, comprising: a mounting surface, a non-mounting surface opposite the mounting surface, and a SiC semiconductor layer connecting the mounting surface and the non-mounting surface and having a side including a roughened surface region formed in an area on the mounting surface side and a smooth surface region formed in an area on the non-mounting surface side relative to the roughened surface region.

[0811] According to this SiC semiconductor device, the smooth surface region can suppress the capillary phenomenon occurring in the rough surface region. Therefore, the conductive bonding material can be prevented from spreading over the side surface of the SiC semiconductor layer. In particular, the smooth surface region formed in the non-mounting surface region of the SiC semiconductor layer can appropriately suppress the conductive bonding material from spreading over the non-mounting surface. Therefore, short circuits caused by the conductive bonding material spreading over the side surface can be appropriately suppressed.

[0812] [C1] A SiC semiconductor device comprising: a SiC semiconductor layer including a SiC single crystal and having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a side surface connecting the first main surface and the second main surface; an insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface formed flush with the side surface of the SiC semiconductor layer; a roughened surface region formed on the side surface of the SiC semiconductor layer; a smooth surface region formed in a region of the side surface of the SiC semiconductor layer different from the roughened surface region; an electrode formed on the insulating layer; and a modified layer formed on the side surface of the SiC semiconductor layer and modified to have properties different from those of the SiC single crystal.

[0813] According to this SiC semiconductor device, the smooth surface region can suppress the capillary phenomenon occurring in the rough surface region. Therefore, the wet spreading of the conductive bonding material on the side surface of the SiC semiconductor layer can be suppressed. Moreover, an insulating layer having an insulating side surface formed flush with the side surface of the SiC semiconductor layer is formed on the first main surface of the SiC semiconductor layer. This makes it possible to increase the insulation between the side surface of the SiC semiconductor layer and the electrode by the insulating layer while suppressing the wet spreading of the conductive bonding material. This makes it possible to appropriately suppress short circuits caused by the wet spreading of the conductive bonding material.

[0814] [C2] A SiC semiconductor device comprising: a SiC semiconductor layer including a SiC single crystal and having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a side surface connecting the first main surface and the second main surface; an insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface formed flush with the side surface of the SiC semiconductor layer; a roughened surface region formed on the side surface of the SiC semiconductor layer in a region on the second main surface side of the SiC semiconductor layer; a smooth surface region formed on the side surface of the SiC semiconductor layer ...

Claims

1. a SiC chip having a laminated structure including a SiC substrate and a SiC epitaxial layer, the SiC chip including a first main surface on the SiC epitaxial layer side, a second main surface on the SiC substrate side, and a side surface; a first rough surface region formed on a portion of the side surface that is made of the SiC substrate; a second rough surface region formed in a portion of the side surface that is made of the SiC epitaxial layer; The SiC chip is a SiC semiconductor device made of 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal or 6H-SiC single crystal.

2. The SiC semiconductor device according to claim 1 , wherein the first main surface is formed by a silicon surface of a SiC single crystal.

3. 3. The SiC semiconductor device according to claim 1, wherein the first main surface has an off-angle inclined toward an a-axis of the SiC single crystal.

4. 4. The SiC semiconductor device according to claim 1, wherein the SiC epitaxial layer has an impurity concentration different from an impurity concentration of the SiC substrate.

5. The SiC semiconductor device according to any one of claims 1 to 4, wherein the SiC epitaxial layer has a thickness less than a thickness of the SiC substrate.

6. The SiC semiconductor device according to any one of claims 1 to 5, further comprising a smooth surface region formed on the portion of the side surface made of the SiC substrate.

7. The SiC semiconductor device according to claim 1 , further comprising an insulating layer covering the first main surface.

8. The SiC semiconductor device according to claim 1 , further comprising a first electrode disposed on the first main surface.

9. The SiC semiconductor device according to claim 8 , wherein the first electrode is disposed on the first main surface at a distance from the side surface.

10. The SiC semiconductor device according to any one of claims 1 to 9, further comprising a resin layer covering the first main surface.

11. The SiC semiconductor device according to claim 10 , wherein the resin layer is disposed on the first main surface with a space therebetween from the side surface.

12. The SiC semiconductor device according to any one of claims 1 to 11, further comprising a second electrode covering the second main surface.

13. The SiC semiconductor device according to any one of claims 1 to 12, further comprising a semiconductor element formed on the first main surface.

14. The SiC semiconductor device according to claim 13 , wherein the semiconductor element includes a diode.

15. The SiC semiconductor device according to claim 13 , wherein the semiconductor element includes a field effect transistor.

16. The SiC semiconductor device according to any one of claims 1 to 15, wherein the first rough surface region is formed in a band shape extending along the first main surface.

Images