Method for testing stress robustness of semiconductor substrates - Patents.com

Abstract

A method for testing the stress robustness of a semiconductor substrate includes forming a nitride layer on a surface of the semiconductor substrate, patterning the nitride layer into a patterned nitride by photolithography including reactive ion etching with ions generated from a gas containing hydrogen and / or a hydrogen compound, treating the patterned nitride and semiconductor substrate at a temperature between 800°C and 1300°C to induce formation of dislocations at an interface between the patterned nitride and the semiconductor substrate, and evaluating at least one characteristic associated with the formed dislocations.

Description

[Technical field]

[0001] The present invention relates to a method for testing the stress robustness of a semiconductor substrate. [Background technology]

[0002] Conventional technology / challenges Advanced device processing can impose greater stresses on semiconductor substrates. 3D structures such as FinFETs as well as extreme thermal processing can cause localized stress fields and induce mechanical damage such as plastic deformation in the substrate. Plastic deformation can consequently affect device pattern overlay and electrical device performance. It is therefore important to know how the substrate behaves in the device fabrication process, both in terms of mechanical robustness and overlay performance. Reliable testing that reduces the complexity and simulates the device fabrication process will enable the development of robust semiconductor substrates. Existing tests such as indenter testing cause significant mechanical damage that penetrates the substrate by several microns.

[0003] EP2959500B1 refers to a stress test that involves mechanical damage of the substrate wafer by an indenter tool and subsequent heat treatment. The drawback of this test is that it introduces deep crystal lattice damage and plastic deformation that is not typical in semiconductor device processing. In addition, the indentation only provides very localized information about the properties of the substrate, not the entire semiconductor wafer. Summary of the Invention [Problem to be solved by the invention]

[0004] The objective of the claimed invention is to provide an alternative method that avoids the need to create mechanical impressions in the substrate wafer. An advantage of the claimed invention is that it is very similar to device processes that rely on pure film-induced mechanical near-surface stresses and is capable of revealing robustness information about the entire wafer surface. [Means for solving the problem]

[0005] Description of the invention The object of the present invention is to provide a method for testing the stress robustness of a semiconductor substrate, comprising: forming a nitride layer over a surface of a semiconductor substrate; patterning the nitride layer into a patterned nitride by photolithography including a step of reactive ion etching with ions generated from a gas containing hydrogen and / or a hydrogen compound; treating the patterned nitride and the semiconductor substrate at a temperature between 800° C. and 1300° C. to induce the formation of dislocations at the interface between the patterned nitride and the semiconductor substrate; and evaluating at least one property associated with the formed dislocations.

[0006] The present invention provides a test that targets the near-surface region where the devices are located without inducing mechanical damage as a source of stress. This test allows for a simple simulation of the device manufacturing process that targets the mechanical robustness of the semiconductor substrate with respect to dislocation formation. Semiconductor substrates with reduced dislocation formation rate or dislocation propagation in the test structures function with higher yields in the device manufacturing process. This test allows for the development and manufacture of semiconductor substrates with improved mechanical robustness, since it is closer to the actual device manufacturing process and does not induce significant mechanical damage as a source of stress.

[0007] This method allows for a more realistic picture of the stress robustness of the semiconductor substrate since it lacks mechanical indentation and targets the near-surface region where the electronic devices are formed. This test targets the near-surface region where the electronic devices are located and allows for the identification of semiconductor substrates with improved stress robustness. Dislocation defects in device processing can often only be detected in-line or at the back-end when the devices are being tested for electrical performance. This test allows for simulating the most critical device processes during the development of the semiconductor substrate before the devices are processed on wafers in mass production.

[0008] The method induces the formation of dislocations in a near-surface region and uses at least one property associated with the dislocations to quantify stress robustness of the semiconductor substrate.

[0009] Dislocations are induced by a heat treatment at an interface between a surface of a substrate and a patterned nitride formed on the surface. After heat treatment of the semiconductor substrate and the patterned nitride, the patterned nitride may be removed and at least one property associated with the formed dislocations is examined.

[0010] Prior to forming the patterned nitride, a nitride layer, for example a silicon nitride layer, is formed directly on the surface of the semiconductor substrate without any further intervening layers, such as oxide layers. However, as an exception, a native oxide layer may be present between the nitride layer and the semiconductor substrate. Preferably, the nitride layer has a uniform thickness. Direct formation of the nitride layer results in significant mechanical stress between the nitride layer and the substrate material, caused by different thermal expansion coefficients between the substrate and the nitride layer during cooling after forming the nitride layer. The nitride layer may be formed at high temperatures, for example 700°C to 800°C, by LPCVD (Low Pressure Chemical Vapor Deposition). The thickness of the nitride layer may be 150 nm to 400 nm. Prior to the formation of the nitride layer, the semiconductor substrate may be subjected to a thermal pretreatment, for example in conditions specific to the electronic device manufacturing process.

[0011] Following the formation of the nitride layer, the nitride layer is converted into a patterned nitride by photolithography, which includes forming a patterned photoresist on the nitride layer and removing the nitride where there is no photoresist by RIE (reactive ion etching). The patterned nitride may include nitride structures having shapes such as lines, circles, squares and rectangles. The lines, squares and rectangles may extend laterally over a distance of 100 μm to several mm. The circles may have an outer diameter of 100 μm to 5000 μm. The line width of the nitride structures is preferably 5 μm to 1000 μm. Adjacent nitride structures may be separated from each other by a distance ranging from 10 μm to several mm. A gas containing hydrogen or a hydrogen compound or both, for example a mixture of CHF3, CF4 and argon or oxygen, is used to generate a plasma with ions for the RIE. The presence of hydrogen may cause subsurface damage that leads to the formation of dislocations during subsequent heat treatment.

[0012] After formation of the patterned nitride, the photoresist is removed and the semiconductor substrate and patterned nitride undergo a subsequent heat treatment, which may be performed in either an RTP (rapid thermal processing) tool or a batch furnace. The heat treatment may be performed in a nitrogen atmosphere, which causes the formation of dislocations, which begin at the edge position of the interface between the semiconductor substrate and the patterned nitride. The temperature of the heat treatment may range from 800°C to 1300°C, which affects the kinetics of dislocation propagation. If RTP is used, the ramp rate may be from 10°C / sec to 100°C / sec, and the semiconductor substrate and patterned nitride may be annealed at the target temperature for a period of 1 min to 10 min or more. The heat treatment in a batch furnace may last from 15 min to 3 h or more.

[0013] The patterned nitride may then be removed from the semiconductor substrate and at least one property associated with the formed dislocations is evaluated. The at least one property may be, for example, a density of dislocations at a location on the surface of the semiconductor substrate that was buried under the nitride during the thermal treatment. The higher the mechanical robustness of the semiconductor material, the lower the dislocation density. The dislocation density is highest at a location that was an edge location during the thermal treatment and decreases with distance from the nitride edge. Due to the higher dislocation density at the previous edge location, the dislocation density may be evaluated at a location that is at least 1 μm displaced from the previous edge location. The at least one property associated with the formed dislocations may be, for example, a dislocation propagation length. This indicates the distance to the closest previous edge location where the dislocation density has dropped to a low threshold near or below zero. The higher the mechanical robustness of the semiconductor material, the lower the dislocation propagation length.

[0014] The at least one property associated with the formed dislocations can be evaluated with or without prior removal of the patterned nitride. The patterned nitride may be removed and the semiconductor substrate may be etched for delineation of the dislocations. This defect etch may be performed, for example, with a Wright etchant, followed by evaluation using optical or scanning electron microscopy. For example, a microscopic image may be taken from the etched front side of the semiconductor substrate, and evaluation software may be used to automatically count the defects and calculate the respective dislocation-related properties. Alternatively, the removal of the patterned nitride and the subsequent etching may be omitted, and XRT (x-ray topography) or PL (photoluminescence analysis) may be used for evaluation of the at least one property associated with the formed dislocations. The PL mapper may also evaluate the penetration depth of the dislocations into the bulk of the semiconductor substrate.

[0015] The semiconductor substrate may be, for example, a polished silicon wafer made from a single crystal, or an epitaxial wafer comprising such a silicon wafer and a silicon epitaxial layer formed thereon, or an SOI (silicon-on-insulator) wafer. In the case of a (100) oriented silicon single crystal lattice, the induced dislocations also propagate within the crystal bulk, i.e., along the (111) oriented planes that intersect the (100) oriented surface at an angle of about 55°.

[0016] The invention is further disclosed with reference to the drawings. [Brief description of the drawings]

[0017] [Figure 1] FIG. 2 shows a schematic diagram of a possible flow of the individual steps of the claimed method. [Diagram 2] FIG. 1 illustrates some shapes that the nitride pattern may take. [Diagram 3] FIG. 2 shows an example of the evaluation of properties related to dislocations during step e) of FIG. 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] 1, the claimed method may start with an optional step a) in which the semiconductor substrate is subjected to a thermal pretreatment, for example by heating the semiconductor substrate under conditions dictated by device manufacturing process conditions.

[0019] The first essential step b) of the claimed method comprises forming a nitride layer 2 on a surface 5 of a semiconductor substrate. Surface 2 is the top edge of the area of ​​the substrate wafer in which electronic devices are intended to be integrated. Typically, surface 5 is the surface of a semiconductor substrate 1.

[0020] During step c), a patterned nitride 3 is formed by a lithographic process, in which the nitride layer 2 is partially removed by RIE to leave a patterned nitride 3. As a source of plasma a gas containing hydrogen or containing a hydrogen compound or both is used.

[0021] The next step d) involves a heat treatment of the semiconductor substrate 1 and the patterned nitride 3 at a temperature in the range of 800° C. to 1300° C. in a furnace, e.g. a batch furnace, or in an RTP tool. The heat treatment associated with mechanical stresses between the material of the substrate 1 and the material of the patterned nitride 3 induces the formation of dislocations 4 under the patterned nitride 3. The dislocations 4 propagate laterally under the patterned nitride 3, starting from an edge position 6, i.e. from the lateral boundary of the patterned nitride 3, and extending to a certain depth in the semiconductor substrate 1.

[0022] Subsequently, during step e), the patterned nitride 3 may be removed from the surface 5 of the semiconductor substrate 1 and at least one property related to the formed dislocations 4 of the areas covered by the nitride structure 3 during the thermal treatment is evaluated.

[0023] 2, the patterned nitride 3 can have a shape such as a square, a circle, a straight line, or a slanted line, with a line width d. During thermal treatment, dislocations form at the edge locations 6 and propagate laterally under the patterned nitride 3.

[0024] Working Example The central part of Fig. 3 shows an optical microscope image of the surrounding area of ​​the square nitride structure after removing the patterned nitride from the silicon single crystal wafer used as the semiconductor substrate and after treating the silicon wafer with Wright etchant. The highest dislocation density is located at and near the edge position 6. The left part of Fig. 3 represents an enlarged view of the area marked with a hatched rectangle in the central part. This area was evaluated for dislocation-related properties, i.e., dislocation density and dislocation propagation length.

[0025] The right part of Fig. 3 plots the calculated dislocation density as a function of distance from the edge position, with an offset to exclude the relatively high dislocation density at and near the edge position. The maximum density was observed at a distance of about 1 μm, and the dislocation propagation length was about 75 μm.

[0026] Various semiconductor substrates were tested according to steps b) to e) in FIG. 1, and the test results are summarized in the following table. The patterned nitride formed during step c) had a square shape and a thickness of 250 nm. The heat treatment during step d) was performed at a temperature of 1000° C. as RTP, and the dislocation density (dd) and dislocation propagation length (dpl) were evaluated during step e). As the semiconductor substrate, p-doped (p - ), or p-doped with a low resistivity of less than 10 m ohm cm (p + ), a polished silicon single crystal wafer of 300 mm diameter, or such a wafer with a p-doped silicon epitaxial layer formed thereon (pp - Wafer and pp + The effect of the concentration of interstitial oxygen (Oi) was examined by using a low Oi (1.8 × 10 17 atoms / cm 3 , new ASTM F121) and high Oi (5.8×10 17 atoms / cm 3 ) and the oxygen concentration was varied.

[0027] [Table 1]

[0028] Higher bulk oxygen levels indicate higher mechanical robustness, which is manifested in a reduction in dislocation propagation length. Similarly, the concentration of p-type dopants can also be used to control the mechanical robustness. It was also found that the dislocation density and dislocation propagation length increase when the temperature during heat treatment increases from 900°C to 1000°C. Similarly, the dislocation density and dislocation propagation length also increase when the thickness of the nitride structure increases from 250nm to 320nm. Finally, the reproducibility of the tests could be confirmed for both dislocation density and dislocation propagation length. [Explanation of symbols]

[0029] List of reference numbers used 1. Semiconductor substrate 2. Nitride layer 3. Patterned Nitride 4. Dislocations 5 surface 6 Edge Position

Claims

1. A method for testing the stress robustness of a semiconductor substrate (1), the method comprising the steps of: forming a nitride layer (2) on a surface (5) of the semiconductor substrate (1), the nitride layer (2) being formed either directly on the surface (5) of the semiconductor substrate (1) or on an intervening native oxide layer; cooling the semiconductor substrate (1) and the nitride layer (2); patterning said nitride layer into a patterned nitride (3) by photolithography including a step of reactive ion etching with ions generated from a gas containing hydrogen and / or a hydrogen compound; treating the patterned nitride (3) and the semiconductor substrate (1) in a nitrogen atmosphere at a temperature between 800° C. and 1300° C. to induce the formation of dislocations (4) at the interface between the patterned nitride (3) and the semiconductor substrate (1); and evaluating at least one property associated with the formed dislocation (4).

2. The gas is CHF ３ , C.F. ４ and argon.

3. The method of claim 1, wherein the gas consists of CHF 3 , CF 4 and oxygen.

4. The method according to any one of claims 1 to 3, comprising using x-ray topography or photoluminescence analysis to evaluate the at least one property related to the formed dislocations (4).

5. A step of evaluating the at least one characteristic associated with the formed dislocations (4) by optical microscopy or scanning electron microscopy; The method according to any one of claims 1 to 3, comprising the steps of removing the patterned nitride (3) from the substrate (1) and performing a contour etch prior to the step of evaluating the at least one property related to the formed dislocations (4).

6. The method of any one of claims 1 to 5, comprising using rapid thermal processing or batch furnace processing to process the patterned nitride (3) and the semiconductor substrate (1).

7. The method according to any one of claims 1 to 6, wherein the at least one property related to the formed dislocations (4) is a dislocation density and / or a dislocation propagation length.

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