Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of improving connection reliability, and a method for manufacturing the semiconductor device.SOLUTION: A semiconductor device comprises: a first substrate having a first principal surface and including a first conductive pad on the first principal surface; a second substrate having a second principal surface facing the first principal surface and including a second conductive pad on the second principal surface; a semiconductor element arranged between the first substrate and the second substrate and mounted on the first principal surface of the first substrate; and a conductive core ball in contact with the first and second conductive pads. A maximum dimension of the conductive core ball in a first direction perpendicular to the first principal surface is smaller than a maximum diameter in a plane parallel to the first principal surface of the conductive core ball. The conductive core ball includes a first contact surface directly in contact with the first conductive pad and a second contact surface directly in contact with the second conductive pad.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] A semiconductor package has been disclosed in which an upper substrate and a lower substrate are connected using copper-core balls as spacer members (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-9782 A Summary of the Invention [Problem to be solved by the invention]

[0004] Although the semiconductor package described in Patent Document 1 achieves the intended purpose, higher connection reliability between the copper core balls and the lower and upper substrates is desired.

[0005] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device that can improve connection reliability. [Means for solving the problem]

[0006] According to one embodiment of the present disclosure, there is provided a first substrate having a first main surface and a first conductive pad on the first main surface, a second substrate having a second main surface opposite to the first main surface and a second conductive pad on the second main surface, a semiconductor element disposed between the first substrate and the second substrate and mounted on the first main surface of the first substrate, and a conductive core ball made of copper in contact with the first conductive pad and the second conductive pad, wherein a maximum dimension of the conductive core ball in a first direction perpendicular to the first main surface is smaller than a maximum diameter of the conductive core ball in a plane parallel to the first main surface, and the maximum dimension is 85.0% to 95.0% of the maximum diameter,A compressive stress parallel to the first direction is applied to the conductive core ball, The conductive core ball has a first contact surface that directly contacts the first conductive pad and a second contact surface that directly contacts the second conductive pad. Effect of the Invention

[0007] According to the disclosed technique, connection reliability can be improved. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing a copper core ball in an embodiment. [Diagram 3] 1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 5A to 5C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment. [Diagram 5] 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment. [Figure 6] 4A to 4C are cross-sectional views showing the method for manufacturing a semiconductor device according to an embodiment; [Figure 7] 5A to 5C are cross-sectional views showing the method for manufacturing a semiconductor device according to an embodiment; [Figure 8] 6 is a cross-sectional view (part 6) showing the method for manufacturing a semiconductor device according to an embodiment. [Figure 9] FIG. 2 is a cross-sectional view showing a copper core ball in a reference example. [Figure 10] FIG. 11 is a cross-sectional view showing a copper core ball in a modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant description. In this disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is described as an XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is described as a YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is described as a ZX plane. For convenience, the Z1-Z2 direction is defined as the up-down direction, the Z1 side is defined as the upper side, and the Z2 side is defined as the lower side. In addition, a planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of an object viewed from the Z1 side. However, the semiconductor device can be used upside down or can be arranged at any angle.

[0010] The present embodiment relates to a semiconductor device and a manufacturing method thereof. Fig. 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0011] The semiconductor device 10 according to the embodiment has a lower substrate 100, an upper substrate 200, and a semiconductor element 300. The lower substrate 100 has an upper surface 101 substantially parallel to the XY plane, and the upper substrate 200 has a lower surface 201 substantially parallel to the XY plane. The upper substrate 200 is disposed on the upper side (Z1 side) of the lower substrate 100. The lower substrate 200 has a lower surface 201 opposed to the upper substrate 101 of the lower substrate 100. The lower substrate 100 is an example of a first substrate, and the upper substrate 200 is an example of a second substrate. The upper substrate 101 of the lower substrate 100 is an example of a first main surface, and the lower substrate 201 of the upper substrate 200 is an example of a second main surface.

[0012] The lower substrate 100 has, for example, a core layer 110, a build-up layer 120 provided on an upper surface of the core layer 110, and a build-up layer 130 provided on a lower surface of the core layer 110. The lower substrate 100 may be a coreless substrate that does not include a core layer.

[0013] The core layer 110 has an insulating base material 111 in which a through hole 114 is formed, a through conductive via 112 formed on the inner wall surface of the through hole 114, and a filler 113 filled inside the through conductive via 112. For example, the material of the core layer 110 is glass epoxy or the like, and the material of the through conductive via 112 is copper or the like.

[0014] The build-up layer 120 has an insulating layer 121, a wiring layer 122, and a solder resist layer 123. The solder resist layer 123 has an opening 123A for connection with the upper substrate 200 and an opening 123B for mounting the semiconductor element 300. The wiring layer 122 includes, on the uppermost surface of the insulating layer 121, a conductive pad 124A for connection with the upper substrate 200 and a conductive pad 124B for mounting the semiconductor element 300. The conductive pad 124A is exposed from the opening 123A, and the conductive pad 124B is exposed from the opening 123B. The material of the wiring layer 122 is a conductor such as copper. The conductive pad 124A is an example of a first conductive pad.

[0015] The build-up layer 130 includes an insulating layer 131, a wiring layer 132, and a solder resist layer 133. The solder resist layer 133 has an opening 133A for external connection. The wiring layer 132 includes a conductive pad 134 on the bottom surface of the insulating layer 131. The conductive pad 134 is exposed from the opening 133A. The material of the wiring layer 132 is a conductor such as copper. Solder balls 135 are provided on the conductive pads 134.

[0016] The conductive pads 124A, 124B, and 134 are electrically connected to each other via the wiring layer 122, the through-hole conductive vias 112, and the wiring layer 132. The number of insulating layers 121 and wiring layers 122 included in the build-up layer 120, and the number of insulating layers 131 and wiring layers 132 included in the build-up layer 130 are not particularly limited.

[0017] The semiconductor element 300 is flip-chip mounted on the upper surface 101 of the lower substrate 100. That is, the bumps 301 of the semiconductor element 300 are electrically connected to the conductive pads 124B of the lower substrate 100 via the bonding material 310. The bonding material 310 is made of, for example, solder. An underfill material 320 is filled between the semiconductor element 300 and the lower substrate 100.

[0018] The upper substrate 200 includes, for example, a core layer 210 , a conductive pad 211 , a conductive pad 212 , a solder resist layer 214 , and a solder resist layer 215 .

[0019] The conductive pad 211 is provided on the lower surface of the core layer 210, and the conductive pad 212 is provided on the upper surface of the core layer 210. The conductive pad 212 is connected to the conductive pad 211 through a via hole 213 formed in the core layer 210. The material of the conductive pads 211 and 212 is a conductor such as copper. The conductive pad 211 is an example of a second conductive pad.

[0020] A solder resist layer 214 covers the lower surface of the core layer 210. An opening 214A for connection to the lower substrate 100 is formed in the solder resist layer 214. The conductive pad 211 is exposed from the opening 214A. A solder resist layer 215 covers the upper surface of the core layer 210. An opening 215A for external connection is formed in the solder resist layer 215. The conductive pad 212 is exposed from the opening 215A. The conductive pad 212 is used to mount electronic components such as semiconductor elements, passive elements, or other wiring boards on the upper substrate 200.

[0021] The semiconductor device 10 has a copper (Cu) core ball 20 that contacts the conductive pad 124A of the lower substrate 100 and the conductive pad 211 of the upper substrate 200. Here, the copper core ball 20 will be described in detail. FIG. 2 is a cross-sectional view showing the copper core ball 20.

[0022] The conductive pad 124A of the lower substrate 100 and the conductive pad 211 of the upper substrate 200 face each other. The copper core ball 20 contacts both the conductive pad 124A and the conductive pad 211. The copper core ball 20 has a first contact surface 21 that directly contacts the conductive pad 124A and a second contact surface 22 that directly contacts the conductive pad 211. The copper core ball 20 has a maximum dimension D1 in a first direction perpendicular to the upper surface 101 of the lower substrate 100, i.e., in the Z1-Z2 direction, and a maximum diameter D2 in a plane parallel to the upper surface 101, i.e., in a plane parallel to the XY plane, and the maximum dimension D1 is smaller than the maximum diameter D2. The maximum dimension D1 is the maximum value of the dimension of the copper core ball 20 in the Z1-Z2 direction. The maximum dimension D1 is, so to speak, the height of the copper core ball 20. The maximum diameter D2 is the maximum value of the diameter of the copper core ball 20 in a plane parallel to the XY plane. For example, the maximum dimension D1 is about 90% of the maximum diameter D2. The copper core ball 20 may have a Ni layer formed on its surface.

[0023] The shape of the copper core ball 20 may be ellipsoidal. In the present disclosure, ellipsoidal does not mean a strict ellipsoid defined mathematically. When the copper core ball 20 is ellipsoidal, the maximum dimension D1 corresponds to the minor axis of the ellipsoid, and the maximum diameter D2 corresponds to the major axis of the ellipsoid. The first contact surface 21 and the second contact surface 22 may be flat surfaces or may be curved surfaces that are convex from the center of the copper core ball 20 outward.

[0024] The first contact surface 21 and the second contact surface 22 have a circular planar shape. The first diameter of the first contact surface 21 and the second diameter of the second contact surface 22 are about 10% of the maximum diameter D2. The first area of ​​the first contact surface 21 and the second area of ​​the second contact surface 22 are about 1% of the maximum cross-sectional area (maximum cross-sectional area) of the cross-sectional areas of the copper core ball 20 parallel to the XY plane.

[0025] The side surface of the copper core ball 20 is covered with a solder layer 30. The solder layer 30 may be in contact with both the conductive pad 124A and the conductive pad 211. The material of the solder layer 30 is, for example, a Sn (tin), Sn-Ag (silver)-based, Sn-Cu-based, or Sn-Ag-Cu-based Pb (lead)-free solder.

[0026] A molding resin 40 is filled between the upper substrate 200 and the lower substrate 100, and the upper substrate 200 is fixed to the lower substrate 100. The distance between the upper substrate 200 and the lower substrate 100 is maintained by the copper core balls 20.

[0027] Next, a method for manufacturing the semiconductor device 10 according to the embodiment will be described. Figures 3 to 8 are cross-sectional views showing a method for manufacturing the semiconductor device 10 according to the embodiment.

[0028] First, the lower substrate 100 is prepared as shown in Fig. 3. As described above, the lower substrate 100 has the conductive pad 124A, the conductive pad 124B, etc. Next, for example, the bonding material 310 is formed on the conductive pad 124B. The bonding material 310 can be formed by electrolytic plating or the like.

[0029] 4, the semiconductor element 300 on which the bumps 301 are formed is flip-chip mounted on the lower substrate 100. That is, the bumps 301 are electrically connected to the conductive pads 124B of the lower substrate 100 via the bonding material 310. Next, an underfill material 320 is filled between the semiconductor element 300 and the lower substrate 100.

[0030] 5, an upper substrate 200 is prepared. As described above, the upper substrate 200 has the conductive pads 211 and the like. Next, the copper-cored solder balls 24 are mounted on the conductive pads 211. The copper-cored solder balls 24 have a spherical copper-cored ball 23 and a solder layer 30 provided on the outer periphery of the copper-cored ball 23. In this disclosure, the term "spherical" does not mean a mathematically defined sphere. A Ni layer may be formed on the surface of the copper-cored ball 23.

[0031] Filling the gap between the semiconductor element 300 and the lower substrate 100 with underfill material 320 and mounting the copper core solder balls 24. Posted 6, the upper substrate 200 is placed on the lower substrate 100 with the copper core solder balls 24 in contact with the conductive pads 124A while providing a molding resin 40 between the lower substrate 100 and the upper substrate 200. The semiconductor element 300 is disposed between the lower substrate 100 and the upper substrate 200.

[0032] Next, the solder layer 30 is reflowed while compressing the laminated structure including the lower substrate 100 and the upper substrate 200 shown in Fig. 6 in the Z1-Z2 direction. As a result, as shown in Fig. 7, the spherical copper core balls 23 are compressed in the Z1-Z2 direction to form ellipsoidal copper core balls 20. In addition, an alloy layer (not shown) is formed from a component of the solder layer 30 (e.g., tin), a component of the conductive pad 124A (e.g., copper), and a component of the conductive pad 211 (e.g., copper). The reflow temperature is, for example, about 260°C.

[0033] Next, as shown in FIG. 8, solder balls 135 are formed on the conductive pads 134.

[0034] In this manner, the semiconductor device 10 according to the embodiment can be manufactured.

[0035] It is also possible to provide the molding resin 40 after the ellipsoidal copper core balls 20 are formed without providing the molding resin 40 when placing the upper substrate 200 on the lower substrate 100. Also, it is also possible to provide the molding resin 40 without providing the molding resin 40 when placing the upper substrate 200 on the lower substrate 100, and to provide the molding resin 40 when compressing the laminated structure including the lower substrate 100 and the upper substrate 200 shown in FIG. 6 in the Z1-Z2 direction.

[0036] Here, the effects of this embodiment will be described in comparison with a reference example. Fig. 9 is a cross-sectional view showing a copper core ball in the reference example.

[0037] In the reference example, as shown in Fig. 9, a spherical copper core ball 25 is provided instead of the copper core ball 20. Since the copper core ball 25 is spherical, the maximum dimension D3 of the copper core ball 25 in the Z1-Z2 direction is equal to the maximum diameter D4 of the copper core ball 25 in a plane parallel to the XY plane. The copper core ball 25 has a first contact point 26 that contacts the conductive pad 124A and a second contact point 27 that contacts the conductive pad 211. The other configurations are the same as those of this embodiment.

[0038] In the semiconductor device 10 of this embodiment, the maximum dimension D1 of the copper core ball 20 in the Z1-Z2 direction is smaller than the maximum diameter D2 of the copper core ball 20 in a plane parallel to the XY plane, and the copper core ball 20 has a first contact surface 21 that contacts the conductive pad 124A and a second contact surface 22 that contacts the conductive pad 211.

[0039] Thus, in the reference example, the copper-core ball 25 contacts the conductive pad 124A and the conductive pad 211 at a point, whereas in this embodiment, the copper-core ball 20 contacts the conductive pad 124A and the conductive pad 211 at a surface. Therefore, according to this embodiment, higher connection reliability can be obtained between the copper-core ball 20 and the lower substrate 100 and the upper substrate 200, compared to the reference example.

[0040] As described above, an alloy layer is formed during reflow of the solder layer 30. The volume of the solder layer 30 decreases with the formation of the alloy layer, but according to the present embodiment, even if the volume of the solder layer 30 decreases, excellent connection reliability can be obtained.

[0041] In addition, in this embodiment, when the spherical copper core ball 23 is compressed to form the ellipsoidal copper core ball 20, the solder layer 30 spreads over the conductive pad 124A and the conductive pad 211. That is, the solder layer 30 widely contacts the conductive pad 124A and the conductive pad 211. Therefore, even if the volume of the solder layer 30 decreases with the formation of the alloy layer, the connection between the lower substrate 100 and the upper substrate 200 can be firmly maintained.

[0042] Furthermore, due to warping of the lower substrate 100 and the upper substrate 200, the distance between the conductive pad 124A and the conductive pad 211 may vary before the reflow of the solder layer 30. In this case, in the reference example, the copper core ball 25 may not be able to contact the conductive pad 124A or the conductive pad 211. On the other hand, in this embodiment, the copper core ball 23 is sandwiched between the conductive pad 124A and the conductive pad 211, and the copper core ball 23 is compressed to form the copper core ball 20, so that the copper core ball 20 can be more reliably contacted with the conductive pad 124A and the conductive pad 211. Furthermore, if the copper core ball 23 and the copper core ball 25 have the same size, in this embodiment, the height (dimension in the Z1-Z2 direction) of the semiconductor device 10 can be reduced.

[0043] The conductive pad 124A and the conductive pad 211 may also be deformed when the copper-core ball 23 is compressed. The copper-core ball 20 may be embedded in the conductive pad 124A and the conductive pad 211. When the copper-core ball 20 is embedded in the conductive pad 124A and the conductive pad 211, the first contact surface 21 and the second contact surface 22 tend to be curved, and it is easier to ensure a large area for the first contact surface 21 and the second contact surface 22 compared to when the first contact surface 21 and the second contact surface 22 are flat.

[0044] For example, as shown in Fig. 10, the first contact surface 21 and the second contact surface 22 of the copper-core ball 20 may be curved. Furthermore, the conductive pad 124A may have a first curved portion 124X curved along the shape of the first contact surface 21, and the conductive pad 211 may have a second curved portion 211X curved along the shape of the second contact surface 22. Fig. 10 is a cross-sectional view showing a copper-core ball in a modified example of the embodiment.

[0045] The maximum dimension D1 is preferably 80.0% to 99.9% of the maximum diameter D2, and more preferably 85.0% to 95.0%. The smaller the ratio of the maximum dimension D1 to the maximum diameter D2, the easier it is to ensure a large area for the first contact surface 21 and the second contact surface 22. On the other hand, if the ratio of the maximum dimension D1 to the maximum diameter D2 is too small, it may be difficult to suppress short circuits between the copper core balls 20 while ensuring an appropriate distance between the lower substrate 100 and the upper substrate 200.

[0046] The first diameter of the first contact surface 21 and the second diameter of the second contact surface 22 are preferably 0.1% to 20.0%, more preferably 5.0% to 15.0% of the maximum diameter D2. The larger the ratio of the first diameter and the second diameter to the maximum diameter D2, the easier it is to ensure a large area for the first contact surface 21 and the second contact surface 22. On the other hand, in order to increase the ratio of the first diameter and the second diameter to the maximum diameter D2, it is necessary to compress the copper core ball 23 with a stronger force, which may make processing difficult. If at least one of the first diameter of the first contact surface 21 and the second diameter of the second contact surface 22 is within the above-mentioned preferred range, the connection reliability is easily improved, and if at least one of them is within the above-mentioned more preferred range, the connection reliability is easily improved.

[0047] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0048] 10 Semiconductor device 20 Copper core balls 21 1st contact surface 22 Second contact surface 100 Lower board 101 Top surface 124A, 124B Conductive pads 200 Upper board 201 Bottom surface 211 Conductive Pad 300 Semiconductor elements

Claims

1. a first substrate having a first major surface and a first conductive pad on the first major surface; a second substrate having a second main surface opposite to the first main surface and having a second conductive pad on the second main surface; a semiconductor element disposed between the first substrate and the second substrate and mounted on the first main surface of the first substrate; a copper conductive core ball in contact with the first conductive pad and the second conductive pad; having a maximum dimension of the conductive core ball in a first direction perpendicular to the first main surface is smaller than a maximum diameter of the conductive core ball in a plane parallel to the first main surface; the maximum dimension is between 85.0% and 95.0% of the maximum diameter; A compressive stress parallel to the first direction is applied to the conductive core ball, The conductive core ball is a first contact surface in direct contact with the first conductive pad; a second contact surface in direct contact with the second conductive pad; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the conductive core ball has an ellipsoidal shape.

3. 3. The semiconductor device according to claim 1, further comprising a solder layer covering a side surface of the conductive core ball.

4. The material of the first conductive pad and the second conductive pad is copper, the solder layer contains tin; 4. The semiconductor device according to claim 3, wherein an alloy layer containing tin and copper is present between the first conductive pad and the solder layer and between the second conductive pad and the solder layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that a first diameter of the first contact surface and a second diameter of the second contact surface are 5.0% to 15.0% of the maximum diameter of the conductive core ball.

6. 6. The semiconductor device according to claim 1, wherein the first conductive pad has a first curved portion curved along a shape of the first contact surface of the conductive core ball.

7. 7. The semiconductor device according to claim 1, wherein the second conductive pad has a second curved portion curved along a shape of the second contact surface of the conductive core ball.

8. a step of mounting a semiconductor element on a first main surface of a first substrate having a first main surface and a first conductive pad on the first main surface; a step of mounting a spherical copper conductive core ball on a second conductive pad of a second substrate having a second main surface and a second conductive pad on the second main surface; a step of bonding the conductive core ball to the first conductive pad and the second conductive pad while facing the second main surface to the first main surface; having the step of joining the conductive core ball to the first conductive pad and the second conductive pad includes a step of compressing the conductive core ball in a first direction perpendicular to the first main surface to make a maximum dimension of the conductive core ball in the first direction smaller than a maximum diameter of the conductive core ball in a plane parallel to the first main surface; After the step of reducing the maximum dimension to less than the maximum diameter, the maximum dimension is between 85.0% and 95.0% of the maximum diameter; A method for manufacturing a semiconductor device, comprising the steps of: applying a compressive stress parallel to the first direction to the conductive core ball.

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