Semiconductor Device

Abstract

This semiconductor device comprises a base plate, a substrate, a circuit pattern, a plate-shaped first electrode, a plate-shaped second electrode, a plate-shaped third electrode, a first semiconductor chip, a second semiconductor chip, and a frame body 14 that is attached to the base plate and includes a side wall portion surrounding the outer periphery of the substrate. At least two among the first electrode, the second electrode, and the third electrode include portions arranged in parallel. The frame body includes insulating ribs protruding from an inner wall surface of the side wall portion. The ribs include penetrating portions that penetrate between the portions arranged in parallel and ensure a creepage distance between the electrodes arranged in parallel.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device.

[0002] This application claims priority to Japanese Application No. 2021-8836 filed on January 22, 2021, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0003] A semiconductor device in which a semiconductor element is disposed on a substrate is known (see, for example, Patent Document 1). The semiconductor device disclosed in Patent Document 1 is a power semiconductor module, and includes a positive power supply terminal, a negative power supply terminal, and an output terminal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-98921 A Summary of the Invention

[0005] A semiconductor device according to the present disclosure includes a base plate, a substrate arranged on the base plate and including a first main surface, a first circuit plate, a second circuit plate, a third circuit plate, and a fourth circuit plate located apart from each other, a circuit pattern arranged on the first main surface, a plate-shaped first electrode arranged on the circuit pattern and connected to the first circuit plate, a plate-shaped second electrode arranged on the circuit pattern and connected to the second circuit plate and the third circuit plate, a plate-shaped third electrode arranged on the circuit pattern and connected to the fourth circuit plate, a first semiconductor chip arranged on the first circuit plate, a second semiconductor chip arranged on the third circuit plate, a first conductive member electrically connecting the first semiconductor chip and the second circuit plate, a second conductive member electrically connecting the second semiconductor chip and the fourth circuit plate, and a frame attached to the base plate and including a side wall portion surrounding the outer periphery of the substrate. At least two of the first electrode, the second electrode, and the third electrode include portions arranged in parallel. The frame includes an insulating rib protruding from an inner wall surface of the side wall portion. The rib includes an intrusion portion that intrudes between the portions arranged in parallel and ensures a creepage distance between the electrodes arranged in parallel. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic perspective view of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a schematic cross-sectional view of the semiconductor device shown in FIG. 1 taken along line II-II in FIG. [Diagram 3] 3 is a schematic cross-sectional view of the semiconductor device shown in FIG. 1 taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic perspective view of the semiconductor device shown in FIG. 1 in which a lid portion, which will be described later, is omitted. [Diagram 5] FIG. 5 is a schematic perspective view of the semiconductor device shown in FIG. 1, in which a lid, a sealing material, and a frame, which will be described later, are omitted. [Figure 6] FIG. 6 is a schematic side view of the semiconductor device shown in FIG. [Figure 7] 7 is a schematic cross-sectional view of the semiconductor device shown in FIG. 6 taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of the semiconductor device shown in FIG. 7, in which a first electrode, a second electrode, and a third electrode, which will be described later, are omitted. [Figure 9] FIG. 9 is a schematic cross-sectional view of the semiconductor device shown in FIG. 7, illustrating only the first electrode, the second electrode, and the third electrode. [Figure 10] FIG. 10 is a diagram that roughly illustrates a part of the circuit diagram of the semiconductor device shown in FIG. [Figure 11] 11 is a schematic perspective view of a frame included in the semiconductor device shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a part of the semiconductor device shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a part of the semiconductor device shown in FIG. [Figure 14] FIG. 14 is an enlarged view of a region R indicated by a dashed line in FIG. [Figure 15] FIG. 15 is a schematic perspective view showing a state in which a substrate is bonded to a base plate, and a first electrode, a second electrode, a third electrode, and each semiconductor chip such as a first semiconductor chip are bonded to a circuit pattern. [Figure 16] FIG. 16 is a schematic perspective view showing a state in which the frame is attached to a base plate and the first conductive member and the like are joined. [Figure 17] FIG. 17 is a schematic perspective view showing a state in which the lid is attached to the frame. [Figure 18] FIG. 18 is a schematic perspective view showing a part of the semiconductor device in the second embodiment. [Figure 19] FIG. 19 is a schematic side view of the semiconductor device shown in FIG. [Figure 20] 20 is a schematic cross-sectional view of the semiconductor device shown in FIG. 19 taken along the line XX-XX in FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view of the semiconductor device shown in FIG. 20 in which the first electrode, the second electrode, and the third electrode are not shown. [Figure 22]FIG. 22 is a schematic cross-sectional view of the semiconductor device shown in FIG. 20, illustrating only the first electrode, the second electrode, and the third electrode. [Figure 23] FIG. 23 is a schematic cross-sectional view showing a part of a semiconductor device in the third embodiment. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a part of a semiconductor device in the fourth embodiment. [Diagram 25] FIG. 25 is a schematic cross-sectional view showing a part of a semiconductor device in the fifth embodiment. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a part of a semiconductor device in the sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] [Problem that this disclosure aims to solve] High insulation between terminals (electrodes) is required in semiconductor devices such as the power semiconductor module disclosed in Patent Document 1. It is desirable to ensure high insulation easily without going through complicated manufacturing processes.

[0008] Therefore, an object of the present invention is to provide a semiconductor device in which high insulation between electrodes can be easily ensured.

[0009] [Effects of this disclosure] According to the semiconductor device, high insulation between the electrodes can be easily ensured.

[0010] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be described. The semiconductor device according to the present disclosure includes a base plate, a substrate arranged on the base plate and including a first main surface, a first circuit plate, a second circuit plate, a third circuit plate, and a fourth circuit plate located separately from each other, a circuit pattern arranged on the first main surface, a plate-shaped first electrode arranged on the circuit pattern and connected to the first circuit plate, a plate-shaped second electrode arranged on the circuit pattern and connected to the second circuit plate and the third circuit plate, a plate-shaped third electrode arranged on the circuit pattern and connected to the fourth circuit plate, a first semiconductor chip arranged on the first circuit plate, a second semiconductor chip arranged on the third circuit plate, a first conductive member electrically connecting the first semiconductor chip and the second circuit plate, a second conductive member electrically connecting the second semiconductor chip and the fourth circuit plate, and a frame body attached to the base plate and including a side wall portion surrounding the outer periphery of the substrate. At least two of the first electrode, the second electrode, and the third electrode include portions arranged in parallel. The frame includes an insulating rib protruding from an inner wall surface of the side wall portion. The rib includes an intrusion portion that intrudes between the parallel arranged portions to ensure a creepage distance between the parallel arranged electrodes.

[0011] When a current flows in the semiconductor device, the current path is the first electrode, the first circuit board, the first semiconductor chip, the first conductive member, the second circuit board, and the second electrode. Further, the current path is the second electrode, the third circuit board, the second semiconductor chip, the second conductive member, the fourth circuit board, and the third electrode. According to the semiconductor device of the present disclosure, at least two of the first electrode, the second electrode, and the third electrode include portions arranged in parallel. And the frame includes an insulating rib protruding from the inner wall surface of the side wall portion. The rib includes an entry portion that enters between the portions arranged in parallel and ensures a creepage distance between the electrodes arranged in parallel. Therefore, in at least two of the first electrode, the second electrode, and the third electrode including the portions arranged in parallel, the insulation between the portions arranged in parallel can be increased by the entry portion. In this case, since the rib protruding from the inner wall surface is included in the frame, the rib can be arranged when the frame is attached to the base plate. Therefore, high insulation between the electrodes can be easily ensured. Regarding the parallelism, there is no need to have a strict geometric parallel relationship, and for example, one may be inclined relative to the other by a few degrees, specifically within a range of 30 degrees.

[0012] In the semiconductor device, the third electrode may include a first flat plate portion and a second flat plate portion that are arranged in parallel with each other and spaced apart. The second electrode may include a third flat plate portion that is arranged between the first flat plate portion and the second flat plate portion and spaced apart from each of the first flat plate portion and the second flat plate portion. The entry portion may enter at least one of between the first flat plate portion and the third flat plate portion and between the second flat plate portion and the third flat plate portion. In this manner, the entry portion enters at least one of between the first flat plate portion and the third flat plate portion and between the second flat plate portion and the third flat plate portion, so that high insulation between the electrodes can be easily ensured at least one of between the first flat plate portion and the third flat plate portion and between the second flat plate portion and the third flat plate portion.

[0013] In the semiconductor device, the first flat plate portion, the second flat plate portion, and the third flat plate portion may be perpendicular to the first main surface. In this way, when the frame body is attached to the base plate, the entry portion can be easily arranged at least one of between the first flat plate portion and the third flat plate portion and between the second flat plate portion and the third flat plate portion. Therefore, high insulation between the electrodes can be more easily ensured. Here, the perpendicularity does not have to have a strict geometric perpendicular relationship, and for example, one side may be inclined with respect to the other side by a few degrees with respect to 90 degrees, specifically within a range of 30 degrees.

[0014] In the above semiconductor device, the first electrode may include a seventh plate portion. The third electrode may include an eighth plate portion arranged parallel to the seventh plate portion. The entry portion may be arranged between the seventh plate portion and the eighth plate portion. In this manner, the entry portion that enters between the seventh plate portion of the first electrode and the eighth plate portion of the third electrode that are arranged in parallel can be easily arranged. Therefore, high insulation between the first electrode and the third electrode can be easily ensured.

[0015] In the semiconductor device, the seventh plate portion and the eighth plate portion may be perpendicular to the first main surface. This makes it easier to arrange the entrance portion between the seventh plate portion and the eighth plate portion when attaching the frame body to the base plate. This makes it easier to ensure high insulation between the electrodes.

[0016] In the semiconductor device, the rib may be detachable from the sidewall. In this way, the rib and the sidewall can be manufactured separately, and materials with different comparative tracking indexes (CTIs) can be used depending on the creepage distance. This makes it easy to change the materials.

[0017] In the semiconductor device, the rib may be integral with the side wall. In this way, it is possible to prevent the rib from moving due to buoyancy when the sealing material is filled in. This makes it possible to ensure insulation. In addition, since it can be molded using a single mold, it can be constructed at low cost.

[0018] In the semiconductor device, the rib may be made of a thermoplastic resin, which makes it easier to manufacture the rib.

[0019] The semiconductor device may further include a sealant that insulates a space above the base plate in the region surrounded by the frame. The entry portion may be in contact with the sealant. In this way, a sufficient creepage distance can be ensured, and insulation between the electrodes can be more reliably achieved.

[0020] The semiconductor device may further include insulating paper arranged between the parallel portions. By using insulating paper with a higher CTI than the rib, the minimum creepage distance can be reduced. Therefore, by doing so, it is possible to improve insulation even when it is difficult to ensure a sufficient creepage distance by using a resin rib.

[0021] In the present disclosure, the positions of the circuit boards and semiconductor chips on the circuit pattern and the positions of the conductive members are not necessarily limited to the above-mentioned cases. For example, the following embodiment may be used. The semiconductor device of the present disclosure includes a base plate, a substrate arranged on the base plate and including a first main surface, and a plurality of circuit boards located separately from each other, and includes a circuit pattern arranged on the first main surface, a plate-shaped first electrode arranged on the circuit pattern and connected to one of the circuit boards, a plate-shaped second electrode arranged on the circuit pattern and connected to two of the circuit boards, a plate-shaped third electrode arranged on the circuit pattern and connected to one of the circuit boards, a first semiconductor chip arranged on the circuit board, a second semiconductor chip arranged on the circuit board, and a frame body attached to the base plate and including a side wall portion surrounding the outer periphery of the substrate. At least two of the first electrode, the second electrode, and the third electrode include portions arranged in parallel. The frame body includes an insulating rib protruding from the inner wall surface of the side wall portion. The rib includes an entry portion that enters between the portions arranged in parallel and ensures a creepage distance between the electrodes arranged in parallel.

[0022] [Details of the embodiment of the present disclosure] Next, an embodiment of a semiconductor device according to the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference characters and their description will not be repeated.

[0023] (Embodiment 1) The configuration of the semiconductor device in the first embodiment of the present disclosure will be described. FIG. 1 is a schematic perspective view of the semiconductor device in the first embodiment. FIG. 2 is a schematic cross-sectional view of the semiconductor device shown in FIG. 1 cut along II-II in FIG. 1. FIG. 3 is a schematic cross-sectional view of the semiconductor device shown in FIG. 1 cut along III-III in FIG. 1. FIG. 4 is a schematic perspective view of the semiconductor device shown in FIG. 1 without illustrating a lid portion described later. Note that a nut described later is illustrated in FIG. 4 from the viewpoint of facilitating understanding. FIG. 5 is a schematic perspective view of the semiconductor device shown in FIG. 1 without illustrating a lid portion, a sealing material, and a frame body described later. FIG. 6 is a schematic side view of the semiconductor device shown in FIG. 5. FIG. 7 is a schematic cross-sectional view of the semiconductor device shown in FIG. 6 cut along VII-VII in FIG. 6. FIG. 7 is a view seen in the thickness direction of a substrate described later. Note that FIG. 7 illustrates a case where the semiconductor device is cut along a cross section in a region where a sealing material described later is not located. FIG. 8 is a schematic cross-sectional view of the semiconductor device shown in FIG. 7 without illustrating a first electrode, a second electrode, and a third electrode described later. FIG. 2 corresponds to a cross section cut along a plane including a dashed line in FIG. 7. FIG. 3 corresponds to a cross section cut along a plane including a dashed line in FIG. 7. FIG. 9 is a schematic cross-sectional view of the semiconductor device shown in FIG. 7, showing only the first electrode, the second electrode, and the third electrode. FIG. 10 is a diagram showing a part of the circuit diagram of the semiconductor device shown in FIG. 1. In addition, in FIG. 10, in order to facilitate understanding, a capacitor connected in parallel with the first semiconductor chip and the second semiconductor chip described later and having a configuration not included in the semiconductor device of the present disclosure is also shown. FIG. 11 is a schematic perspective view of a frame body included in the semiconductor device shown in FIG. 1. FIG. 12 is a schematic cross-sectional view showing a part of the semiconductor device shown in FIG. 1. FIG. 13 is a schematic cross-sectional view showing a part of the semiconductor device shown in FIG. 1. FIG. 12 shows a cross-section cut along the XY plane, and FIG. 13 shows a cross-section cut along the XZ plane.

[0024] 1 to 13, semiconductor device 10a in the first embodiment includes a plate-shaped base plate 11a serving as a base portion, a substrate 12a, a circuit pattern 13a, a frame 14a, a sealing material 15a, a lid portion 16a, a first electrode 17a, a second electrode 18a, a third electrode 19a, first semiconductor chips 21a, 21b, 21c, and 21d, second semiconductor chips 22a, 22b, 22c, and 22d, third semiconductor chips 23a, 23b, 23c, and 23d, and fourth semiconductor chips 24a, 24b, 24c, and 24d. , fifth semiconductor chips 21e, 21f, sixth semiconductor chips 22e, 22f, seventh semiconductor chips 23e, 23f, eighth semiconductor chips 24e, 24f, a first control terminal 25a, a second control terminal 25b, a third control terminal 25c, a fourth control terminal 25d, first conductive members 26a, 26b, 26c, 26d, second conductive members 27a, 27b, 27c, 27d, third conductive members 26e, 26f, fourth conductive members 27e, 27f, and wires 28a, 28b, 28c, 28d, 28e.

[0025] In this embodiment, the base plate 11a is rectangular in the thickness direction (Z direction) with the length in the X direction being longer than the length in the Y direction. The base plate 11a is made of, for example, metal. The base plate 11a includes a first main surface 11b located on one side in the thickness direction and a second main surface 11c located on the other side in the thickness direction. Through holes 11d, 11e, 11f, and 11g are formed in the portions near the four corners of the base plate 11a, respectively penetrating in the thickness direction. The through holes 11d, 11e, 11f, and 11g are effectively used together with through holes 14h, 14i, 14j, and 14k described later when mounting the semiconductor device 10a at a predetermined installation location.

[0026] The substrate 12a is disposed on the first main surface 11b. In this embodiment, the substrate 12a is rectangular in shape, with the length in the X direction longer than the length in the Y direction, as viewed in the thickness direction (Z direction). The substrate 12a has insulating properties. The substrate 12a is made of, for example, ceramic. The substrate 12a includes a first main surface 12b located on one side in the thickness direction and a second main surface 12c located on the other side in the thickness direction. The second main surface 12c of the substrate 12a is bonded to the first main surface 11b of the base plate 11a by a bonding material.

[0027] A circuit pattern 13a is disposed on the first main surface 12b of the substrate 12a. The circuit pattern 13a is made of a conductive material, specifically, for example, a copper plate. The circuit pattern 13a includes a circuit board (first circuit board) 13b, a circuit board (second circuit board) 13c, a circuit board (third circuit board) 13d, and a circuit board (fourth circuit board) 13e, which are positioned apart from each other. The circuit pattern 13a further includes a circuit board (fifth circuit board) 13f, a circuit board (sixth circuit board) 13g, a circuit board (seventh circuit board) 13h, a circuit board (eighth circuit board) 13i, a circuit board (ninth circuit board) 13j, a circuit board (tenth circuit board) 13k, a circuit board (eleventh circuit board) 13l, and a circuit board (twelfth circuit board) 13m, which are positioned apart from each other. The circuit boards 13b and 13e are disposed separately from each other in the Y direction. Circuit board 13c is disposed between the separated circuit boards 13b in the Y direction. Of circuit boards 13b, 13c, 13d, and 13e, circuit boards 13b and 13e are divided into a plurality of circuit boards that are electrically connected, specifically, into two circuit boards (see FIG. 8 in particular). Circuit boards 13f and 13h are also divided into a plurality of circuit boards that are electrically connected, specifically, into two circuit boards. In this embodiment, circuit boards 13f and 13h are disposed separated in the Y direction.

[0028] The region in which circuit boards 13b and 13c are arranged, the region in which circuit boards 13d and 13e are arranged, and the region in which circuit boards 13f, 13g, and 13h are arranged are arranged side by side in the X direction. Specifically, in the X direction, the region in which circuit boards 13b and 13c are arranged is arranged at a position close to first control terminal 25a, followed by the region in which circuit boards 13f, 13g, and 13h are arranged, followed by the region in which circuit boards 13d and 13e are arranged. That is, in the X direction, the region in which circuit boards 13f, 13g, and 13h are arranged is arranged between the region in which circuit boards 13b and 13c are arranged and the region in which circuit boards 13d and 13e are arranged.

[0029] During operation of semiconductor device 10a, circuit boards 13b, 13c, 13d, 13e, 13f, 13g, and 13h form a current path together with first electrode 17a, second electrode 18a, and third electrode 19a. Circuit boards 13i, 13j, 13k, 13l, and 13m are used to control first semiconductor chip 21a and the like by first control terminal 25a, second control terminal 25b, third control terminal 25c, and fourth control terminal 25d.

[0030] The frame body 14a is attached to the base plate 11a. Specifically, the frame body 14a is attached to the first main surface 11b of the base plate 11a by an adhesive (not shown). In this embodiment, the frame body 14a is rectangular in shape with a length in the X direction longer than a length in the Y direction when viewed in the thickness direction of the substrate 12a. The frame body 14a includes four side walls 14b, 14c, 14d, and 14e surrounding the outer periphery of the substrate 12a. The side walls 14b, 14c, 14d, and 14e are arranged such that an inner wall surface 14l of the side wall portion 14b faces an inner wall surface 14m of the side wall portion 14c, and an inner wall surface 14n of the side wall portion 14d faces an inner wall surface 14o of the side wall portion 14e. The substrate 12a is arranged in a space 14f surrounded by the four side walls 14b, 14c, 14d, and 14e of the frame body 14a. Four through holes 14h, 14i, 14j, and 14k penetrating in the Z direction are formed in the portions near the four corners of the frame body 14a. The through holes 14h, 14i, 14j, and 14k are arranged so as to align with the four through holes 11d, 11e, 11f, and 11g of the base plate 11a when the frame body 14a is attached to the base plate 11a. The first control terminal 25a, the second control terminal 25b, the third control terminal 25c, and the fourth control terminal 25d are inserted into the side wall portion 14d of the frame body 14a.

[0031] The frame 14a is made of a material having high insulating properties and strength, specifically, for example, PPS (Polyphenylenesulfide) resin. Such resin is a thermoplastic resin with good moldability, excellent insulating properties, moisture resistance, and heat resistance, and has high strength. Alternatively, PBT (Polybutylene Terephtalate) resin may be used as the material of the frame 14a. The frame 14a includes ribs 41a. The specific configuration of the frame 14a will be described in detail later.

[0032] The sealing material 15a covers the substrate 12a. The sealing material 15a fills a part of the space 14f in the frame 14a. The sealing material 15a is disposed at a distance from the lid 16a. The sealing material 15a contacts the side surface of the substrate 12a and a part of the first main surface 12b. Specifically, the sealing material 15a contacts the side surface of the substrate 12a and the first main surface 12b in a portion where the semiconductor chip 21a and the like are not disposed. The sealing material 15a electrically insulates the space on the side surface of the substrate 12a and the space above the substrate 12a in the region surrounded by the frame 14a. A portion of electrode 17a, a portion of electrode 18a, a portion of electrode 19a, and conductive members 26a, 26b, 26c, and 26d, conductive members 27a, 27b, 27c, and 27d, conductive members 26e and 26f, and conductive members 27e and 27f are covered with sealing material 15a. Specifically, the sealing material 15a is used to seal the components arranged on the substrate 12a, more specifically, the first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the third semiconductor chips 23a, 23b, 23c, 23d, the fourth semiconductor chips 24a, 24b, 24c, 24d, the fifth semiconductor chips 21e, 21f, the sixth semiconductor chips 22e, 22f, the seventh semiconductor chips 23e, 23f, the eighth semiconductor chips 24e, 24f, the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, the fourth conductive members 27e, 27f, and the wires 28a, 28b, 28c, 28d, 28e. The members on the base plate 11a are fixed by the sealing material 15a. For example, a resin having high insulating properties and heat resistance is used as the material of the sealing material 15a. Specifically, a thermosetting resin such as an epoxy resin, a phenol resin, or a silicone resin is used as the sealing material 15a.

[0033] The lid portion 16a is plate-shaped. In this embodiment, the lid portion 16a is rectangular in shape with a length in the X direction longer than a length in the Y direction when viewed in the thickness direction of the substrate 12a, and has four notches provided near the four corners. The lid portion 16a is attached to the frame body 14a by an adhesive (not shown). The lid portion 16a is arranged so as to cover the opening 14g of the frame body 14a described above. The lid portion 16a is formed with three terminal blocks 16b, 16c, and 16d arranged at intervals in the longitudinal direction. The terminal blocks 16b, 16c, and 16d are arranged at intervals in the X direction. The lid portion 16a is also formed with three through holes 16e, 16f, and 16g penetrating in the thickness direction (Z direction). The three through holes 16e, 16f, and 16g are formed at the positions where the three terminal blocks 16b, 16c, and 16d are provided. The three through holes 16e, 16f, 16g are arranged at positions through which the first electrode 17a, the second electrode 18a, and the third electrode 19a, which are in a state in which the third regions 17d, 18d, and 19d, which will be described later, are not bent, penetrate, respectively, when the lid portion 16a is attached to the frame body 14a. Nuts 16h, 16i, and 16j are outsert or press-fitted into the positions of the lid portion 16a where the terminal blocks 16b, 16c, and 16d are provided, as fastening members used to electrically connect the first electrode 17a, the second electrode 18a, and the third electrode 19a to external electrodes (not shown). Note that the nuts 16h, 16i, and 16j are illustrated in FIG. 4 for ease of understanding. The material of the lid portion 16a is, for example, the same material as that of the frame body 14a, specifically, PPS resin or PBT resin.

[0034] The first semiconductor chip 21a, 21b, 21c, 21d, the second semiconductor chip 22a, 22b, 22c, 22d, the third semiconductor chip 23a, 23b, 23c, 23d, the fourth semiconductor chip 24a, 24b, 24c, 24d, the fifth semiconductor chip 21e, 21f, the sixth semiconductor chip 22e, 22f, the seventh semiconductor chip 23e, 23f and the eighth semiconductor chip 24e, 24f are each a wide bandgap semiconductor chip. Specifically, the first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the third semiconductor chips 23a, 23b, 23c, 23d, the fourth semiconductor chips 24a, 24b, 24c, 24d, the fifth semiconductor chips 21e, 21f, the sixth semiconductor chips 22e, 22f, the seventh semiconductor chips 23e, 23f, and the eighth semiconductor chips 24e, 24f each include a semiconductor layer made of SiC (silicon carbide). Note that the semiconductor layer may be made of, for example, Si (silicon) or GaN (gallium nitride).

[0035] The first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the fifth semiconductor chips 21e, 21f, and the sixth semiconductor chips 22e, 22f are metal-oxide-semiconductor field effect transistors (MOSFETs). In this embodiment, the first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the fifth semiconductor chips 21e, 21f, and the sixth semiconductor chips 22e, 22f are vertical transistor chips. That is, the first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the fifth semiconductor chips 21e, 21f, and the sixth semiconductor chips 22e, 22f are transistor chips in which a current flows in the thickness direction (Z direction). The first semiconductor chips 21a, 21b, 21c, and 21d, the second semiconductor chips 22a, 22b, 22c, and 22d, the fifth semiconductor chips 21e and 21f, and the sixth semiconductor chips 22e and 22f are each a switching element.

[0036] The first semiconductor chips 21a, 21b, 21c, and 21d are disposed on the circuit board 13b. Specifically, the first semiconductor chips 21a and 21b are disposed on the circuit board 13b closer to the side wall portion 14b among the divided circuit boards 13b. The first semiconductor chips 21c and 21d are disposed on the circuit board 13b closer to the side wall portion 14c among the divided circuit boards 13b. The first semiconductor chips 21a and 21b are disposed at intervals in the X direction. The first semiconductor chips 21c and 21d are disposed at intervals in the X direction. The first semiconductor chips 21a and 21c are disposed at intervals in the Y direction. The first semiconductor chips 21b and 21d are disposed at intervals in the Y direction. The first semiconductor chips 21a, 21b, 21c, and 21d are joined to the circuit board 13b by a conductive bonding material (not shown), thereby electrically connecting the drain electrode pads of each of the first semiconductor chips 21a, 21b, 21c, and 21d to the circuit board 13b.

[0037] The second semiconductor chips 22a, 22b, 22c, and 22d are disposed on the circuit board 13d. Specifically, the second semiconductor chips 22a and 22b are disposed on the circuit board 13d at a position close to the side wall portion 14b. The second semiconductor chips 22c and 22d are disposed on the circuit board 13d at a position close to the side wall portion 14c. The second semiconductor chips 22a and 22b are disposed at an interval in the X direction. The second semiconductor chips 22c and 22d are disposed at an interval in the X direction. The second semiconductor chips 22a and 22c are disposed at an interval in the Y direction. The second semiconductor chips 22b and 22d are disposed at an interval in the Y direction. The second semiconductor chips 22a, 22b, 22c, and 22d are joined to the circuit board 13d by a conductive bonding material (not shown), thereby electrically connecting the drain electrode pads of each of the second semiconductor chips 22a, 22b, 22c, and 22d to the circuit board 13d.

[0038] The fifth semiconductor chips 21e, 21f are disposed on the circuit board 13f. Specifically, the fifth semiconductor chip 21e is disposed on the circuit board 13f closer to the side wall portion 14b among the divided circuit boards 13f. The fifth semiconductor chip 21f is disposed on the circuit board 13f closer to the side wall portion 14c among the divided circuit boards 13f. The fifth semiconductor chips 21e, 21f are disposed at intervals in the Y direction. The fifth semiconductor chips 21e, 21f are bonded to the circuit board 13f by a conductive bonding material (not shown), so that the drain electrode pads of the fifth semiconductor chips 21e, 21f are electrically connected to the circuit board 13f. The sixth semiconductor chips 22e, 22f are disposed on the circuit board 13g. Specifically, the sixth semiconductor chip 22e is disposed on the circuit board 13g at a position closer to the side wall portion 14b. The sixth semiconductor chip 22f is disposed at a position on the circuit board 13g close to the side wall portion 14c. The sixth semiconductor chips 22e, 22f are disposed at an interval in the Y direction. The sixth semiconductor chips 22e, 22f are bonded to the circuit board 13g by a conductive bonding material (not shown), whereby the drain electrode pads of the sixth semiconductor chips 22e, 22f are electrically connected to the circuit board 13g.

[0039] The third semiconductor chips 23a, 23b, 23c, 23d, the fourth semiconductor chips 24a, 24b, 24c, 24d, the seventh semiconductor chips 23e, 23f, and the eighth semiconductor chips 24e, 24f are Schottky barrier diodes (SBDs). In this embodiment, the third semiconductor chips 23a, 23b, 23c, 23d, the fourth semiconductor chips 24a, 24b, 24c, 24d, the seventh semiconductor chips 23e, 23f, and the eighth semiconductor chips 24e, 24f are diode chips in which a current flows in the thickness direction (Z direction).

[0040] The third semiconductor chips 23a, 23b, 23c, and 23d are disposed on the circuit board 13b. Specifically, the third semiconductor chips 23a and 23b are disposed on the circuit board 13b closer to the side wall portion 14b among the divided circuit boards 13b. The third semiconductor chips 23c and 23d are disposed on the circuit board 13b closer to the side wall portion 14c among the divided circuit boards 13b. The third semiconductor chips 23a and 23b are disposed between the side wall portion 14b and the first semiconductor chips 21a and 21b in the Y direction, respectively. The third semiconductor chips 23c and 23d are disposed between the side wall portion 14c and the first semiconductor chips 21c and 21d in the Y direction, respectively. The third semiconductor chips 23a and 23b are disposed at an interval in the X direction. The third semiconductor chips 23c and 23d are disposed at an interval in the X direction. The third semiconductor chips 23a, 23c are arranged at intervals in the Y direction. The third semiconductor chips 23b, 23d are arranged at intervals in the Y direction. The third semiconductor chips 23a, 23b, 23c, 23d are joined to the circuit board 13b by a conductive joining material (not shown), so that the cathode electrode pads of the third semiconductor chips 23a, 23b, 23c, 23d are electrically connected to the circuit board 13b.

[0041] The fourth semiconductor chips 24a, 24b, 24c, and 24d are disposed on the circuit board 13d. Specifically, the fourth semiconductor chips 24a and 24b are disposed on the circuit board 13d at positions close to the side wall portion 14b. The fourth semiconductor chips 24c and 24d are disposed on the circuit board 13d at positions close to the side wall portion 14c. The fourth semiconductor chips 24a and 24b are disposed between the side wall portion 14b and the second semiconductor chips 22a and 22b in the Y direction. The fourth semiconductor chips 24c and 24d are disposed between the side wall portion 14c and the second semiconductor chips 22c and 22d in the Y direction. The fourth semiconductor chips 24a and 24b are disposed at intervals in the X direction. The fourth semiconductor chips 24c and 24d are disposed at intervals in the X direction. The fourth semiconductor chips 24a and 24c are disposed at intervals in the Y direction. The fourth semiconductor chips 24b and 24d are arranged with an interval in the Y direction. The fourth semiconductor chips 24a, 24b, 24c, and 24d are joined to the circuit board 13d by a conductive joining material (not shown), so that the cathode electrode pads of the fourth semiconductor chips 24a, 24b, 24c, and 24d are electrically connected to the circuit board 13d.

[0042] The seventh semiconductor chips 23e, 23f are disposed on the circuit board 13f. Specifically, the seventh semiconductor chip 23e is disposed on the circuit board 13f closer to the side wall portion 14b among the divided circuit boards 13f. The seventh semiconductor chip 23f is disposed on the circuit board 13f closer to the side wall portion 14c among the divided circuit boards 13f. The seventh semiconductor chip 23e is disposed between the side wall portion 14b and the fifth semiconductor chip 21e in the Y direction. The seventh semiconductor chip 23f is disposed between the side wall portion 14c and the fifth semiconductor chip 21f in the Y direction. The seventh semiconductor chips 23e, 23f are disposed at intervals in the Y direction. The seventh semiconductor chips 23e, 23f are bonded to the circuit board 13f by a conductive bonding material (not shown), so that the cathode electrode pads of the seventh semiconductor chips 23e, 23f are electrically connected to the circuit board 13f. The eighth semiconductor chips 24e and 24f are disposed on the circuit board 13g. Specifically, the eighth semiconductor chip 24e is disposed on the circuit board 13g at a position close to the side wall portion 14b. The eighth semiconductor chip 24f is disposed on the circuit board 13g at a position close to the side wall portion 14c. The eighth semiconductor chip 24e is disposed between the side wall portion 14b and the sixth semiconductor chip 22e in the Y direction. The eighth semiconductor chip 24f is disposed between the side wall portion 14c and the sixth semiconductor chip 22f in the Y direction. The eighth semiconductor chips 24e and 24f are disposed at intervals in the Y direction. The eighth semiconductor chips 24e and 24f are bonded to the circuit board 13g by a conductive bonding material (not shown), so that the cathode electrode pads of the eighth semiconductor chips 24e and 24f are electrically connected to the circuit board 13g.

[0043] In this embodiment, the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f are solid cylindrical wires made of conductive aluminum. The first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, the fourth conductive members 27e, 27f, and the wires 28a, 28b, 28c, 28d, 28e are bonded to the respective members by wire bonding using a bonding tool. The first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f may be conductive copper wires or plate-shaped conductive members made of aluminum or copper. The aluminum and copper may be pure aluminum or pure copper, or may be an aluminum alloy or a copper alloy. In the case of plate-shaped members, they are joined by solder, for example.

[0044] The first conductive members 26a, 26b, 26c, and 26d electrically connect the first semiconductor chips 21a, 21b, 21c, and 21d to the circuit board 13c. Specifically, the first conductive members 26a, 26b, 26c, and 26d electrically connect the source electrode pads of the first semiconductor chips 21a, 21b, 21c, and 21d to the circuit board 13c. The first conductive members 26a, 26b, 26c, and 26d electrically connect the source electrode pads of the first semiconductor chips 21a, 21b, 21c, and 21d to the anode electrode pads of the third semiconductor chips 23a, 23b, 23c, and 23d.

[0045] The second conductive members 27a, 27b, 27c, and 27d electrically connect the second semiconductor chips 22a, 22b, 22c, and 22d to the circuit board 13e. Specifically, the second conductive members 27a, 27b, 27c, and 27d electrically connect the source electrode pads of the second semiconductor chips 22a, 22b, 22c, and 22d to the circuit board 13e. The second conductive members 27a, 27b, 27c, and 27d electrically connect the source electrode pads of the second semiconductor chips 22a, 22b, 22c, and 22d to the anode electrode pads of the fourth semiconductor chips 24a, 24b, 24c, and 24d.

[0046] The third conductive members 26e, 26f electrically connect the fifth semiconductor chips 21e, 21f and the circuit board 13g. Specifically, the third conductive members 26e, 26f electrically connect the source electrode pads of the fifth semiconductor chips 21e, 21f and the circuit board 13g. The third conductive members 26e, 26f electrically connect the source electrode pads of the fifth semiconductor chips 21e, 21f and the anode electrode pads of the seventh semiconductor chips 23e, 23f. The fourth conductive members 27e, 27f electrically connect the sixth semiconductor chips 22e, 22f and the circuit board 13h. Specifically, the fourth conductive members 27e, 27f electrically connect the source electrode pads of the sixth semiconductor chips 22e, 22f and the circuit board 13h. The fourth conductive members 27e and 27f electrically connect the source electrode pads of the sixth semiconductor chips 22e and 22f and the anode electrode pads of the eighth semiconductor chips 24e and 24f.

[0047] Moreover, the first control terminal 25a and the circuit board 13i are connected by a wire 28a. The second control terminal 25b and the circuit board 13j are connected by a wire 28b. The third control terminal 25c and the circuit board 13k are connected by a wire 28c. The fourth control terminal 25d and the circuit board 13l are connected by a wire 28d. The circuit board 13l and the circuit board 13m are connected by a wire 28e.

[0048] The gate electrode pads of the first semiconductor chips 21a, 21b, 21c, 21d and the fifth semiconductor chips 21e, 21f are electrically connected to the circuit board 13i by wires. The source electrode pads of the first semiconductor chips 21a, 21b, 21c, 21d and the fifth semiconductor chips 21e, 21f are electrically connected to the circuit board 13j by wires. The gate electrode pads of the second semiconductor chips 22a, 22b, 22c, 22d and the sixth semiconductor chips 22e, 22f are electrically connected to the circuit board 13k by wires. The source electrode pads of the second semiconductor chips 22a, 22b, 22c, 22d and the sixth semiconductor chips 22e, 22f are electrically connected to the circuit board 13l or the circuit board 13m by wires.

[0049] Next, the configuration of the first electrode 17a, the second electrode 18a, and the third electrode 19a will be described. The first electrode 17a, the second electrode 18a, and the third electrode 19a are each plate-shaped. The first electrode 17a, the second electrode 18a, and the third electrode 19a are conductive. In this embodiment, the first electrode 17a, the second electrode 18a, and the third electrode 19a are each made of a folded copper plate. The first electrode 17a, the second electrode 18a, and the third electrode 19a are each disposed on the circuit pattern 13a. In this embodiment, the first electrode 17a, the second electrode 18a, and the third electrode 19a are each disposed away from the side walls 14b, 14c, 14d, and 14e that constitute the frame body 14a. The first electrode 17a, the second electrode 18a, and the third electrode 19a have through holes 17e, 18e, and 19e that penetrate in the thickness direction in the portions exposed from the lid portion 16a, respectively. In this embodiment, the first electrode 17a is a so-called P terminal, the second electrode 18a is a so-called O terminal, and the third electrode 19a is a so-called N terminal.

[0050] The first electrode 17a is connected to the circuit board 13b of the circuit pattern 13a. The first electrode 17a includes a first region 17b connected to the circuit board 13b, a second region 17c connected to the first region 17b and extending in a direction intersecting the first main surface 12b, which is the Z direction in this embodiment, and a third region 17d connected to the second region 17c and extending in a direction intersecting the extension direction of the second region 17c, and exposed from the sealing material 15a. In this embodiment, the third region 17d includes a portion extending in the X direction. The first region 17b is joined to the circuit board 13b by a conductive bonding material, for example, solder. Parts of the first region 17b and the second region 17c are located inside the sealing material 15a. The third region 17d includes a region exposed to the outside, that is, a region exposed from the lid portion 16a. The third region 17d has the above-mentioned through hole 17e formed therein. The first electrode 17a is also connected to the circuit board 13f. In this manner, the first electrode 17a is electrically connected to the circuit boards 13b and 13f.

[0051] The second electrode 18a is connected to the circuit board 13c and the circuit board 13d of the circuit pattern 13a. The second electrode 18a includes a first region 18b connected to the circuit board 13c and the circuit board 13d, a second region 18c connected to the first region 18b and extending in a direction intersecting the first main surface 12b, which is the Z direction in this embodiment, and a third region 18d connected to the second region 18c and extending in a direction intersecting the extension direction of the second region 18c, and exposed from the sealing material 15a. In this embodiment, the third region 18d includes a portion extending in the X direction. The first region 18b is bonded to each of the circuit board 13c and the circuit board 13d by a conductive bonding material, for example, solder. A part of the first region 18b and the second region 18c is located inside the sealing material 15a. The third region 18d includes a region exposed to the outside, that is, a region exposed from the lid portion 16a. The third region 18d has the above-mentioned through hole 18e formed therein. The second electrode 18a is also connected to the circuit board 13g. In this manner, the second electrode 18a is electrically connected to the circuit boards 13c, 13d, and 13g.

[0052] Here, circuit board 13c and circuit board 13d are electrically connected by plate-shaped second electrode 18a. Therefore, in the electrical path between circuit board 13c and circuit board 13d, it is possible to realize a reduction in wiring resistance compared to the case where circuit board 13c and circuit board 13d are connected by wiring such as wire or circuit pattern 13a.

[0053] The third electrode 19a is connected to the circuit board 13e of the circuit pattern 13a. The third electrode 19a includes a first region 19b connected to the circuit board 13e, a second region 19c connected to the first region 19b and extending in a direction intersecting the first main surface 12b, which is the Z direction in this embodiment, and a third region 19d connected to the second region 19c and extending in a direction intersecting the extension direction of the second region 19c, and exposed from the sealing material 15a. In this embodiment, the third region 19d includes a portion extending in the X direction. The first region 19b is joined to the circuit board 13e by a conductive bonding material, for example, solder. Parts of the first region 19b and the second region 19c are located inside the sealing material 15a. The third region 19d includes a region exposed to the outside, that is, a region exposed from the lid portion 16a. The third region 19d has the above-mentioned through hole 19e formed therein. The third electrode 19a is also connected to the circuit board 13h. In this manner, the third electrode 19a is electrically connected to the circuit boards 13e and 13h.

[0054] Here, specific configurations of the first electrode 17a, the second electrode 18a, and the third electrode 19a will be described (particularly with reference to FIGS. 6 to 9).

[0055] The third electrode 19a includes a first plate portion 19f and a second plate portion 19g that are arranged parallel to each other with a gap therebetween. The first plate portion 19f and the second plate portion 19g are provided with a gap therebetween in the Y direction. The first plate portion 19f and the second plate portion 19g are perpendicular to the first main surface 12b. The first plate portion 19f and the second plate portion 19g are each parallel to the XZ plane.

[0056] The second electrode 18a includes a third plate portion 18f. The third plate portion 18f is perpendicular to the first main surface 12b. The third plate portion 18f is parallel to the XZ plane. The third plate portion 18f is disposed between the first plate portion 19f and the second plate portion 19g and spaced apart from each of the first plate portion 19f and the second plate portion 19g. That is, the first plate portion 19f, the second plate portion 19g, and the third plate portion 18f form parallel plates.

[0057] The second electrode 18a includes a first portion 18g that is disposed in parallel to and spaced apart from the third electrode 19a. In this embodiment, the first portion 18g is a third flat plate portion 18f.

[0058] The first electrode 17a also includes a seventh plate portion 17f (see FIG. 6 in particular). The seventh plate portion 17f is perpendicular to the first main surface 12b. The seventh plate portion 17f is parallel to the YZ plane.

[0059] The third electrode 19a includes an eighth plate portion 19h. The eighth plate portion 19h is perpendicular to the first main surface 12b. In this embodiment, the eighth plate portion 19h is parallel to the YZ plane. That is, the seventh plate portion 17f and the eighth plate portion 19h form a parallel plate.

[0060] The first electrode 17a includes a third portion 17g that is disposed in parallel to and spaced apart from the third electrode 19a. In this embodiment, the third portion 17g is a seventh plate portion 17f.

[0061] The second electrode 18a includes a ninth plate portion 18h. The ninth plate portion 18h is perpendicular to the first principal surface 12b. The ninth plate portion 18h is parallel to the YZ plane.

[0062] Next, the arrangement of the first conductive member 26a and the like will be described. There are gaps between the electrodes located inside the sealing material 15a when viewed in the thickness direction of the substrate 12a, here the first electrode 17a, the second electrode 18a, and the third electrode 19a, and the conductive members, here the first conductive members 26a, 26b, 26c, and 26d, the second conductive members 27a, 27b, 27c, and 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f. That is, as shown in FIG. 7, when viewed in the thickness direction of the substrate 12a, the first electrode 17a, the second electrode 18a, and the third electrode 19a do not have overlapping areas with the first conductive members 26a, 26b, 26c, and 26d, the second conductive members 27a, 27b, 27c, and 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f, and are arranged with a gap therebetween.

[0063] 14 is an enlarged view of a region R indicated by a broken line in FIG. 7. Referring to FIG. 14, when viewed in the thickness direction of the substrate 12a, there is a gap 29a between the electrode 19a covered by the sealing material 15a and the conductive member 27b. Specifically, the gap 29a between the first region 19b of the third electrode 19a and the second conductive member 27b, more specifically, the gap 29a between the Y-direction end 29b of the second conductive member 27b and the Y-direction end 29c of the first region 19b, is indicated by D1 in FIG. 14. In this embodiment, the gap D1 is 1 mm or more. Alternatively, the gap D1 is 5 mm or more.

[0064] Next, a specific configuration of the frame body 14a will be described (see especially FIG. 11 and FIG. 12). The frame body 14a includes a rib 41a. The rib 41a protrudes from the inner wall surfaces 14n, 14o of the side wall portions 14d, 14e. Specifically, the rib 41a is provided so as to extend in the X direction from the inner wall surface 14n of the side wall portion 14d toward the opposing inner wall surface 14o. The rib 41a is provided from the side wall portion 14d to the side wall portion 14e. That is, the rib 41a is provided in the frame body 14a so as to be a beam-like shape connecting the side wall portion 14d and the side wall portion 14e. By providing such a beam-like rib 41a, the frame body 14a is configured to be less likely to vibrate, and vibration resistance can be improved. In this embodiment, the rib 41a is integral with the side wall portions 14d, 14e. The rib 41a is also made of the above-mentioned thermoplastic resin. In this way, the ribs 41a can be easily manufactured. Also, since the frame body 14a can be molded using a single mold, the frame body 14a can be constructed at low cost.

[0065] The rib 41a includes a first protrusion 42a connected to the inner wall surface 14n of the side wall portion 14d and extending straight in the X direction, a second protrusion 43a connected to the inner wall surface 14o of the side wall portion 14e and extending straight in the X direction, and a central portion 44a connected to each of the first protrusion 42a and the second protrusion 43a. The central portion 44a is not in contact with each of the inner wall surface 14l of the side wall portion 14b and the inner wall surface 14m of the side wall portion 14c. The central portion 44a includes a first support portion 45a that supports the first electrode 17a and the third electrode 19a, and a second support portion 46a that supports the second electrode 18a and the third electrode 19a. The first support portion 45a is connected to the first protrusion 42a. The second support portion 46a is connected to the second protrusion 43a. The first support portion 45a and the second support portion 46a are arranged side by side in the X direction.

[0066] The first support portion 45a is formed with a first guide hole 47a and a second guide hole 48a. The first guide hole 47a and the second guide hole 48a each penetrate in the thickness direction (Z direction) of the substrate 12a. The first guide hole 47a and the second guide hole 48a are arranged with an interval in the X direction. The wall surfaces constituting the first guide hole 47a and the second guide hole 48a are each rectangular along the outer shapes of the first electrode 17a and the third electrode 19a, respectively, when viewed in the thickness direction of the substrate 12a. The first guide hole 47a is configured to be able to penetrate the third region 17d of the first electrode 17a before bending. The second guide hole 48a is configured to be able to penetrate the third region 19d of the third electrode 19a before bending. A portion located between the first guide hole 47a and the second guide hole 48a becomes an entry portion 49a that enters between the first electrode 17a and the third electrode 19a.

[0067] The second support portion 46a is formed with a first guide groove 51a and a second guide groove 52a. The first guide groove 51a is formed so as to be recessed in the Z direction. The second support portion 46a includes an eleventh flat plate portion 53a, a twelfth flat plate portion 54a, and a first connecting portion 55a. The eleventh flat plate portion 53a and the twelfth flat plate portion 54a are arranged in parallel with a gap in the Y direction. The first connecting portion 55a is provided so as to connect the Z direction end of the eleventh flat plate portion 53a and the Z direction end of the twelfth flat plate portion 54a. The first guide groove 51a is formed between the eleventh flat plate portion 53a and the twelfth flat plate portion 54a arranged with a gap in the Y direction. A part of the third flat plate portion 18f of the second electrode 18a is arranged in the first guide groove 51a. The first flat plate portion 19f of the third electrode 19a is disposed on the opposing surface 56a of the eleventh flat plate portion 53a, which faces the inner wall surface 14m of the side wall portion 14c. The eleventh flat plate portion 53a serves as an entry portion 58a that enters between the second electrode 18a and the third electrode 19a. The second flat plate portion 19g of the third electrode 19a is disposed on the opposing surface 57a of the twelfth flat plate portion 54a, which faces the inner wall surface 14l of the side wall portion 14b. The twelfth flat plate portion 54a serves as an entry portion 59a that enters between the second electrode 18a and the third electrode 19a.

[0068] The second guide groove 52a is formed to be recessed in the Y direction. The second support portion 46a includes a thirteenth flat plate portion 61a, a fourteenth flat plate portion 62a, and a second connecting portion 63a. The thirteenth flat plate portion 61a and the fourteenth flat plate portion 62a are arranged in parallel with a gap in the X direction. The second connecting portion 63a is provided to connect the Y direction end of the thirteenth flat plate portion 61a and the Y direction end of the fourteenth flat plate portion 62a. The second guide groove 52a is formed between the thirteenth flat plate portion 61a and the fourteenth flat plate portion 62a that are arranged with a gap in the X direction. A part of the ninth flat plate portion 18h is arranged in the second guide groove 52a.

[0069] In this embodiment, the entrance portions 49a, 58a, and 59a included in the rib 41a are configured to reach the positions where the sealant 15a is disposed, that is, the entrance portions 49a, 58a, and 59a are in contact with the sealant 15a, as shown in FIG.

[0070] Next, the current path that flows during operation of the semiconductor device 10a will be described. The current path when a current flows in the semiconductor device 10a runs from the first electrode 17a to the circuit board 13b, the first semiconductor chips 21a, 21b, 21c, 21d, the first conductive members 26a, 26b, 26c, 26d, the circuit board 13c, and the second electrode 18a. It also runs through the second electrode 18a, the circuit board 13d, the second semiconductor chips 22a, 22b, 22c, 22d, the second conductive members 27a, 27b, 27c, 27d, the circuit board 13e, and the third electrode 19a. In addition, there is also a current path that runs from the first electrode 17a to the circuit board 13f, the fifth semiconductor chips 21e, 21f, the third conductive members 26e, 26f, the circuit board 13g, the second electrode 18a, and further to the second electrode 18a, the circuit board 13h, the fourth conductive members 27e, 27f, the sixth semiconductor chips 22e, 22f, the circuit board 13g, and the third electrode 19a.

[0071] Here, let us consider the current path from the first electrode 17a to the third electrode 19a. In the semiconductor device 10a, a capacitor 101, such as a smoothing capacitor, may be connected in parallel to the first semiconductor chips 21a, 21b, 21c, and 21d and the second semiconductor chips 22a, 22b, 22c, and 22d, as shown in Fig. 10. In this case, a closed circuit is formed between the capacitor 101 and the first semiconductor chips 21a, 21b, 21c, and 21d and the second semiconductor chips 22a, 22b, 22c, and 22d. In the semiconductor device 10a, the path of this closed circuit is from the first electrode 17a to the circuit board 13b, the first semiconductor chips 21a, 21b, 21c, 21d, the first conductive members 26a, 26b, 26c, 26d, the circuit board 13c, the second electrode 18a, the circuit board 13d, the second semiconductor chips 22a, 22b, 22c, 22d, the second conductive members 27a, 27b, 27c, 27d, the circuit board 13e, and the third electrode 19a. In this closed circuit, a high di / dt occurs when switching. In the case of a surge voltage, if the inductance is large, a high surge voltage occurs when a high di / dt occurs, and is applied to the first semiconductor chips 21a, 21b, 21c, 21d and the second semiconductor chips 22a, 22b, 22c, 22d. Such a state may cause damage to the first semiconductor chips 21a, 21b, 21c, and 21d and the second semiconductor chips 22a, 22b, 22c, and 22d. Therefore, it is necessary to suppress the surge voltage. If the inductance can be reduced in the current path from the first electrode 17a to the third electrode 19a, the surge voltage can be suppressed.

[0072] 10, fifth semiconductor chips 21e and 21f can be arranged in parallel with the first semiconductor chips 21a, 21b, 21c, and 21d. Also, sixth semiconductor chips 22e and 22f can be arranged in parallel with the second semiconductor chips 22a, 22b, 22c, and 22d.

[0073] Here, in the second electrode 18a, a current flows from the first region 18b through the second region 18c to the third region 18d. As shown in Fig. 9, in the third plate portion 18f, which is the first portion 18g in the second region 18c, a current flows in the direction of the arrow X as indicated by the arrow V1. Meanwhile, in the third electrode 19a, a current flows from the first region 19b through the second region 19c to the third region 19d. In the first plate portion 19f and the second plate portion 19g in the second region 19c, a current flows in the opposite direction to the arrow X as indicated by the arrow V2.

[0074] In the first electrode 17a, the current flows from the third region 17d to the first region 17b via the second region 17c. In the second region 17c, the current flows in the direction opposite to the direction of the arrow Z as indicated by the arrow V3. Meanwhile, in the third electrode 19a, the current flows from the first region 19b to the third region 19d via the second region 19c. In the eighth plate portion 19h of the second region 19c, the current flows in the direction of the arrow Z as indicated by the arrow V4.

[0075] In the semiconductor device 10a of the present disclosure, the second electrode 18a includes a first portion 18g that is arranged parallel to the third electrode 19a with a gap therebetween. Therefore, in this parallel portion, the direction of the current flowing through the third electrode 19a is opposite to the direction of the current flowing through the second electrode 18a, thereby canceling out the magnetic flux generated when the current flows through the second electrode 18a and the third electrode 19a, and the inductance of the current path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device 10a can be reduced.

[0076] In this embodiment, the third electrode 19a includes a first plate portion 19f and a second plate portion 19g that are arranged in parallel with a gap between them. The second electrode 18a includes a third plate portion 18f that is arranged between the first plate portion 19f and the second plate portion 19g with a gap between them. In this embodiment, the third plate portion 18f is the first portion 18g. Therefore, between the third plate portion 18f and the first plate portion 19f and the second plate portion 19g that are arranged in parallel with each other, the direction of the current flowing through the third electrode 19a is opposite to the direction of the current flowing through the second electrode 18a, thereby canceling out the magnetic flux that occurs when the current flows through the third electrode 19a and the second electrode 18a, and the inductance of the path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device 10a can be further reduced.

[0077] In this embodiment, the first electrode 17a includes a third portion 17g that is arranged in parallel with the third electrode 19a at a distance. Therefore, in the parallel portion, the direction of the current flowing through the first electrode 17a and the direction of the current flowing through the third electrode 19a are opposite to each other, thereby canceling out the magnetic flux generated when the current flows through the first electrode 17a and the third electrode 19a, and the mutual inductance subtracts the inductance of the path. Therefore, the inductance of the semiconductor device 10a can be further reduced.

[0078] In this embodiment, the first electrode 17a includes a seventh plate portion 17f. The third electrode 19a includes an eighth plate portion 19h arranged in parallel to the seventh plate portion 17f. In this embodiment, the seventh plate portion 17f is the third portion 17g. Therefore, between the seventh plate portion 17f and the eighth plate portion 19h arranged in parallel, the direction of the current flowing through the first electrode 17a and the direction of the current flowing through the third electrode 19a are opposite to each other, so that the magnetic flux generated when the current flows through the first electrode 17a and the third electrode 19a is cancelled, and the inductance of the path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device 10a can be further reduced.

[0079] In the semiconductor device 10a of the present disclosure, the frame body 14a includes insulating ribs 41a protruding from the inner wall surfaces 14n, 14o of the sidewalls 14d, 14e. The ribs 41a include parallel arranged portions, specifically, entrance portions 58a, 59a that enter between the second electrode 18a and the third electrode 19a and ensure a creeping distance between the parallel arranged second electrode 18a and the third electrode 19a. The ribs 41a also include an entrance portion 49a that enters between the first electrode 17a and the third electrode 19a and ensures a creeping distance between the parallel arranged first electrode 17a and the third electrode 19a. Therefore, the insulation between the parallel arranged portions can be improved by the entrance portions 49a, 58a, 59a. In this case, the ribs 41a protruding from the inner wall surfaces 14l, 14o are included in the frame body 14a, so that the ribs 41a can be arranged when the frame body 14a is attached to the base plate 11a. Therefore, high insulation between the electrodes can be easily ensured.

[0080] In this embodiment, the penetration portions 58a, 59a penetrate between the first flat plate portion 19f and the third flat plate portion 18f and between the second flat plate portion 19g and the third flat plate portion 18f. Therefore, the penetration portions 58a, 59a can easily ensure high insulation between the second electrode 18a and the third electrode 19a between the first flat plate portion 19f and the third flat plate portion 18f and between the second flat plate portion 19g and the third flat plate portion 18f.

[0081] In this embodiment, the entry portion 49a is disposed between the seventh plate portion 17f and the eighth plate portion 19h. Therefore, the entry portion 49a that enters between the seventh plate portion 17f of the first electrode 17a and the eighth plate portion 19h of the third electrode 19a, which are disposed in parallel, can be easily disposed. Therefore, high insulation between the first electrode 17a and the third electrode 19a can be easily ensured.

[0082] Next, a manufacturing method of the semiconductor device 10a having the above configuration will be briefly described. First, the base plate 11a is prepared. Next, the substrate 12a is bonded to the base plate 11a using a conductive bonding material such as plate solder or paste solder, and the first electrode 17a, the second electrode 18a, the third electrode 19a, and the first semiconductor chip 21a are bonded to the circuit pattern 13a. Here, the first electrode 17a, the second electrode 18a, and the third electrode 19a are used in a state in which the third regions 17d, 18d, and 19d are not bent. FIG. 15 is a schematic perspective view showing a state in which the substrate 12a is bonded to the base plate 11a and the first electrode 17a, the second electrode 18a, the third electrode 19a, and the first semiconductor chip 21a are bonded to the circuit pattern 13a.

[0083] Thereafter, the frame body 14a is attached to the base plate 11a using an adhesive. The first control terminal 25a, the second control terminal 25b, the third control terminal 25c, and the fourth control terminal 25d are attached to the frame body 14a in advance. The frame body 14a is attached to the base plate 11a such that the seventh flat plate portion 17f of the first electrode 17a is accommodated in the first guide hole 47a, the eighth flat plate portion 19h of the third electrode 19a is accommodated in the second guide hole 48a, the third flat plate portion 18f of the second electrode is accommodated in the first guide groove 51a, and the ninth flat plate portion 18h of the second electrode is accommodated in the second guide groove 52a. At this time, the opposing surface 56a is arranged to face the first flat plate portion 19f of the third electrode 19a, and the opposing surface 57a is arranged to face the second flat plate portion 19g of the third electrode 19a.

[0084] In this embodiment, the first flat plate portion 19f, the second flat plate portion 19g, and the third flat plate portion 18f are perpendicular to the first main surface 12b. Therefore, when the frame body 14a is attached to the base plate 11a, the entrance portions 58a, 59a can be easily arranged between the first flat plate portion 19f and the third flat plate portion 18f and between the second flat plate portion 19g and the third flat plate portion 18f. Therefore, high insulation between the second electrode 18a and the third electrode 19a can be more easily ensured.

[0085] In this embodiment, the seventh plate portion 17f and the eighth plate portion 19h are perpendicular to the first main surface 12b. Therefore, when the frame body 14a is attached to the base plate 11a, the entrance portion 49a can be easily disposed between the seventh plate portion 17f and the eighth plate portion 19h. Therefore, high insulation between the first electrode 17a and the third electrode 19a can be more easily ensured.

[0086] Next, the components are electrically connected by the first conductive member 26a etc. In this case, a bonding tool is used to connect the components by wire bonding. Fig. 16 is a schematic perspective view showing a state in which the frame body 14a is attached to the base plate 11a and the first conductive member 26a etc. are joined.

[0087] Here, according to the semiconductor device 10a of the present disclosure, there is a gap 29a between the first electrode 17a, the second electrode 18a, and the third electrode 19a covered by the sealing material 15a and the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f, as viewed in the thickness direction of the substrate 12a. In this semiconductor device 10a, the first electrode 17a, the second electrode 18a, and the third electrode 19a covered by the sealing material 15a do not overlap with the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f, as viewed in the thickness direction of the substrate 12a. Therefore, bonding between the circuit pattern 13a and the first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the third semiconductor chips 23a, 23b, 23c, 23d, the fourth semiconductor chips 24a, 24b, 24c, 24d, the fifth semiconductor chips 21e, 21f, the sixth semiconductor chips 22e, 22f, the seventh semiconductor chips 23e, 23f, and the eighth semiconductor chips 24e, 24f, and bonding between the circuit pattern 13a and the first electrode 17a, the second electrode 18a, and the third electrode 19a can be performed simultaneously. Furthermore, in the semiconductor device 10a having such a configuration, when wiring is performed using a bonding tool with the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f, the risk of the bonding tool interfering with the first electrode 17a, the second electrode 18a, and the third electrode 19a can be reduced, thereby improving productivity.

[0088] Thereafter, liquid sealant 15a is filled into space 14f surrounded by frame 14a from opening 14g side. Sealant 15a is filled so that sealant 15a and entrance portions 49a, 58a, and 59a are in contact with each other even after sealant 15a is cured.

[0089] In this embodiment, the rib 41a is integral with the side walls 14d and 14e. Therefore, when the sealing material 15a is filled, the rib 41a can be prevented from moving due to buoyancy. As a result, reliable insulation can be achieved.

[0090] In this embodiment, the first flat plate portion 19f, the second flat plate portion 19g, and the third flat plate portion 18f are perpendicular to the first main surface 12b. Therefore, it is possible to prevent air bubbles trapped in the sealing material 15a when filling the sealing material 15a from accumulating in the lower regions of the first flat plate portion 19f, the second flat plate portion 19g, and the third flat plate portion 18f. Therefore, it is possible to prevent air bubbles from accumulating in the sealing material 15a, suppress a decrease in insulation performance, and improve the reliability of the semiconductor device 10a.

[0091] In this embodiment, the seventh flat plate portion 17f and the eighth flat plate portion 19h are perpendicular to the first main surface 12b. Therefore, when the sealing material 15a is filled, it is possible to prevent voids trapped during the filling of the sealing material 15a from accumulating in the lower regions of the seventh flat plate portion 17f and the eighth flat plate portion 19h. Therefore, it is possible to prevent the voids from accumulating in the sealing material 15a, suppress the deterioration of the insulating performance, and improve the reliability of the semiconductor device 10a.

[0092] After the filled sealant 15a is cured, the lid portion 16a is attached to the frame body 14a. Fig. 17 is a schematic perspective view showing a state in which the lid portion 16a is attached to the frame body 14a. Referring to Fig. 17, the lid portion 16a is attached to the frame body 14a such that the first electrode 17a, the second electrode 18a, and the third electrode 19a, specifically, the unfolded third region 17d of the first electrode 17a, the unfolded third region 18d of the second electrode 18a, and the unfolded third region 19d of the third electrode 19a, respectively, penetrate the through holes 16e, 16f, and 16g of the lid portion 16a.

[0093] Then, the exposed portions of the first electrode 17a, the second electrode 18a, and the third electrode 19a from the cover portion 16a are bent 90 degrees in the X direction. In this manner, the exposed portions of the first electrode 17a, the second electrode 18a, and the third electrode 19a are configured to conform to the outer shapes of the terminal blocks 16b, 16c, and 16d, and the openings of the through holes 17e, 18e, and 19e are aligned with the screw holes of the nuts 16h, 16i, and 16j, respectively. In this manner, the semiconductor device 10a shown in FIG. 1 is manufactured.

[0094] (Embodiment 2) Next, a second embodiment, which is another embodiment, will be described. FIG. 18 is a schematic perspective view showing a part of a semiconductor device in the second embodiment. In the semiconductor device shown in FIG. 18, the illustration of the lid, the sealing material, and the frame body is omitted. FIG. 19 is a schematic side view of the semiconductor device shown in FIG. 18. FIG. 20 is a schematic cross-sectional view of the semiconductor device shown in FIG. 19 cut along XX-XX in FIG. 19. FIG. 21 is a schematic cross-sectional view of the semiconductor device shown in FIG. 20, in which the illustration of the first electrode, the second electrode, and the third electrode is omitted. FIG. 22 is a schematic cross-sectional view of the semiconductor device shown in FIG. 20, in which only the first electrode, the second electrode, and the third electrode are illustrated. The semiconductor device of the second embodiment is different from the first embodiment in that the configurations of the first electrode, the second electrode, and the third electrode are different. In the second embodiment, the circuit board 13e and the circuit board 13h are not divided.

[0095] 18 to 22, a semiconductor device 10b according to the second embodiment includes a first electrode 17j, a second electrode 18j, and a third electrode 19j.

[0096] The first electrode 17j includes a fourth plate portion 17k and a fifth plate portion 17l that are arranged parallel to each other with a gap therebetween. The fourth plate portion 17k and the fifth plate portion 17l are provided with a gap in the Y direction. The fourth plate portion 17k and the fifth plate portion 17l are perpendicular to the first main surface 12b. The fourth plate portion 17k and the fifth plate portion 17l are each parallel to the XZ plane.

[0097] The second electrode 18j includes a sixth plate portion 18k. The sixth plate portion 18k is perpendicular to the first main surface 12b. The sixth plate portion 18k is parallel to the XZ plane. The sixth plate portion 18k is disposed between the fourth plate portion 17k and the fifth plate portion 17l, and is spaced apart from each of the fourth plate portion 17k and the fifth plate portion 17l. That is, the fourth plate portion 17k, the fifth plate portion 17l, and the sixth plate portion 18k form parallel plates.

[0098] The second electrode 18j includes a second portion 18l disposed parallel to and spaced apart from the first electrode 17j. In this embodiment, the second portion 18l is a sixth plate portion 18k.

[0099] The first electrode 17j also includes a seventh plate portion 17m (see FIG. 19 in particular). The seventh plate portion 17m is perpendicular to the first principal surface 12b. The seventh plate portion 17m is parallel to the YZ plane.

[0100] The third electrode 19j includes an eighth plate portion 19k. The eighth plate portion 19k is perpendicular to the first main surface 12b. In this embodiment, the eighth plate portion 19k is parallel to the YZ plane. That is, the seventh plate portion 17m and the eighth plate portion 19k form a parallel plate.

[0101] The first electrode 17j includes a third portion 17n disposed in parallel to and spaced apart from the third electrode 19j. In this embodiment, the third portion 17n is a seventh plate portion 17m.

[0102] The second electrode 18j includes a ninth plate portion 18m. The ninth plate portion 18m is perpendicular to the first principal surface 12b. The ninth plate portion 18m is parallel to the YZ plane.

[0103] In addition, with regard to the frame body 14a included in the semiconductor device 10b in this embodiment, a frame body 14a including a rib having a first guide hole, a second guide hole, a first guide groove, and a second guide groove is used depending on the configurations of the first electrode 17j, the second electrode 18j, and the third electrode 19j.

[0104] In this embodiment, the second electrode 18j includes a second portion 18l that is arranged parallel to the first electrode 17j with a gap therebetween. Therefore, in this parallel portion, the direction of the current flowing through the third electrode 19j is opposite to the direction of the current flowing through the second electrode 18j, thereby canceling out the magnetic flux generated when the current flows through the second electrode 18j and the third electrode 19j, and the inductance of the current path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device 10b can be reduced.

[0105] In this embodiment, the first electrode 17j includes a fourth plate portion 17k and a fifth plate portion 17l that are arranged in parallel with a gap between them. The second electrode 18j includes a sixth plate portion 18k that is arranged between the fourth plate portion 17k and the fifth plate portion 17l and that is arranged in a gap between the fourth plate portion 17k and the fifth plate portion 17l. In this embodiment, the sixth plate portion 18k is the second portion 18l. Therefore, between the sixth plate portion 18k and the fourth plate portion 17k and the fifth plate portion 17l that are arranged in parallel with each other, the magnetic flux that occurs when a current flows through the second electrode 18j and the first electrode 17j is canceled, and the inductance of the path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device 10b can be further reduced.

[0106] In this embodiment, the fourth plate portion 17k, the fifth plate portion 17l, and the sixth plate portion 18k are perpendicular to the first main surface 12b. Therefore, it is possible to prevent air bubbles trapped in the sealing material 15a when filling the sealing material 15a from accumulating in the lower regions of the fourth plate portion 17k, the fifth plate portion 17l, and the sixth plate portion 18k. Therefore, it is possible to prevent air bubbles from accumulating in the sealing material 15a, suppress deterioration of insulation performance, and improve the reliability of the semiconductor device 10b. In addition, when the frame body 14a is attached to the base plate 11a, the entrance portions 58a and 59a can be easily arranged between the fourth plate portion 17k and the sixth plate portion 18k and between the fifth plate portion 17l and the sixth plate portion 18k. Therefore, it is possible to more easily ensure high insulation between the second electrode 18j and the third electrode 19j.

[0107] In this embodiment, the first electrode 17j includes a seventh plate portion 17m. The third electrode 19j includes an eighth plate portion 19k arranged parallel to the seventh plate portion 17m. Therefore, by making the direction of the current flowing through the first electrode 17j and the direction of the current flowing through the third electrode 19j opposite between the seventh plate portion 17m and the eighth plate portion 19k arranged in parallel, the magnetic flux generated when the current flows through the first electrode 17j and the third electrode 19j is cancelled, and the inductance of the path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device 10b can be further reduced.

[0108] In this embodiment, the seventh plate portion 17m and the eighth plate portion 19k are perpendicular to the first main surface 12b. Therefore, it is possible to prevent air bubbles trapped in the sealing material 15a when filling the sealing material 15a from accumulating in the lower regions of the seventh plate portion 17m and the eighth plate portion 19k. Therefore, it is possible to prevent air bubbles from accumulating in the sealing material 15a and suppress deterioration of the insulating performance, thereby improving the reliability of the semiconductor device 10b. In addition, when attaching the frame body 14a to the base plate 11a, it is possible to easily arrange the entrance portion 49a between the seventh plate portion 17m and the eighth plate portion 19k. Therefore, it is possible to more easily ensure high insulation between the first electrode 17j and the third electrode 19j.

[0109] (Embodiment 3) Next, a third embodiment, which is yet another embodiment, will be described. Fig. 23 is a schematic cross-sectional view showing a part of a semiconductor device in the third embodiment. Fig. 23 is a cross-section including a frame body, a first electrode, a second electrode, and a third electrode. The semiconductor device in the third embodiment differs from the first embodiment in that the configuration of the frame body is different.

[0110] 23, in the frame 14p included in the semiconductor device of this embodiment, the rib 41b is detachable from the sidewalls 14d and 14e. That is, the rib 41b is a separate member from the sidewalls 14b, 14c, 14d, and 14e. The sidewalls 14d and 14e are formed with notches 14q and 14r into which the rib 41b is fitted, respectively. The first protrusion 42a and the second protrusion 43a of the rib 41b are each formed longer in the X direction than in the case shown in the first embodiment. The rib 41b is attached to the sidewalls 14d and 14e by fitting the ends of the first protrusion 42a and the second protrusion 43a into the notches 14q and 14r.

[0111] In this way, the rib 41b and the side walls 14b, 14c, 14d, and 14e can be manufactured separately, and materials with different comparative tracking indexes (CTIs) can be used depending on the creepage distance. This makes it easy to change the materials of the side walls 14b, 14c, 14d, and 14e and the rib 41b.

[0112] In this embodiment, the materials of the side wall portions 14b, 14c, 14d, 14e and the rib 41b do not need to be changed, and the frame body 14p may be configured by providing recesses on the inner wall surfaces 14n, 14o of the side wall portions 14d, 14e, respectively, and fitting the first protrusion portion 42a and the second protrusion portion 43a of the rib 41b into these recesses.

[0113] (Embodiment 4) Next, a fourth embodiment, which is yet another embodiment, will be described. Fig. 24 is a schematic cross-sectional view showing a part of a semiconductor device in the fourth embodiment. Fig. 24 is a cross-section including a frame body, a first electrode, a second electrode, and a third electrode. The semiconductor device in the fourth embodiment differs from the first embodiment in that the first electrode, the second electrode, and the third electrode are integrated with the frame body.

[0114] 24, in the frame 14s included in the semiconductor device of this embodiment, the rib 41a is integrally molded with the first electrode 17a, the second electrode 18a, and the third electrode 19a. The first support portion 45a of the rib 41a is formed with a first housing portion 47b for housing the first electrode 17a and a second housing portion 48b for housing the third electrode 19a. The second support portion 46a of the rib 41a is formed with a third housing portion 51b for housing the second electrode 18a, and a first fitting portion 56b and a second fitting portion 57b into which the third electrode 19a, specifically, the first flat plate portion 19f and the second flat plate portion 19g of the third electrode 19a, are respectively fitted.

[0115] By doing so, the frame body 14s can be integrated with the first electrode 17a, the second electrode 18a, and the third electrode 19a, thereby reducing the number of parts and ensuring reliable insulation between the electrodes.

[0116] (Embodiment 5) Next, a fifth embodiment, which is yet another embodiment, will be described. Fig. 25 is a schematic cross-sectional view showing a part of a semiconductor device in the fifth embodiment. Fig. 25 shows a cross-section including a frame body, a first electrode, a second electrode, and a third electrode. The semiconductor device in the fifth embodiment differs from the first embodiment in that the frame body includes insulating paper.

[0117] 25, the frame 14t included in the semiconductor device in this embodiment includes insulating papers 64a, 65a, and 66a arranged between the portions where at least any two of the first electrode 17a, the second electrode 18a, and the third electrode 19a are arranged in parallel. The insulating paper 64a is arranged so as to be attached to the wall surface of the first guide hole 47a on the side where the entrance portion 49a is located. That is, the insulating paper 64a is arranged between the first electrode 17a and the entrance portion 49a in the X direction. The insulating paper 65a is arranged so as to be attached to the opposing surface 56a. That is, the insulating paper 65a is arranged between the first flat plate portion 19f of the third electrode 19a and the opposing surface 56a in the Y direction. The insulating paper 66a is arranged so as to be attached to the opposing surface 57a. That is, the insulating paper 66a is arranged between the second flat plate portion 19g of the third electrode 19a and the opposing surface 57a in the Y direction. The insulating papers 64a, 65a, and 66a are attached by, for example, adhering with an adhesive.

[0118] In this way, the minimum creepage distance can be reduced by using the insulating papers 64a, 65a, and 66a, which have a higher CTI than the rib 41a. Therefore, by doing so, even if it is difficult to ensure a sufficient creepage distance by using the rib 41a as a resin member, it is possible to improve the insulation.

[0119] (Embodiment 6) Next, a sixth embodiment, which is yet another embodiment, will be described. Fig. 26 is a schematic cross-sectional view showing a part of a semiconductor device in the sixth embodiment. Fig. 26 is a cross-section including a frame body, a first electrode, a second electrode, and a third electrode. The semiconductor device in the sixth embodiment differs from the fifth embodiment in that the frame body including an insulating paper is integrated with the first electrode, etc.

[0120] 26, the frame 14u included in the semiconductor device in this embodiment includes insulating papers 64a, 65a, and 66a arranged between the portions where at least any two of the first electrode 17a, the second electrode 18a, and the third electrode 19a are arranged in parallel. In the frame 14u included in the semiconductor device in this embodiment, the rib 41a is integrally molded with the first electrode 17a, the second electrode 18a, and the third electrode 19a, and further the insulating papers 64a, 65a, and 66a. In the first support portion 45a of the rib 41a, the insulating paper 64a is arranged between the first housing portion 47b that houses the first electrode 17a and the second housing portion 48b that houses the third electrode 19a. That is, the insulating paper 64a is configured to be embedded in the entrance portion 49a. In the second support portion 46a of the rib 41a, insulating paper 65a is disposed between the third housing portion 51b that houses the second electrode 18a and the opposing surface 56a. That is, the insulating paper 65a is embedded in the entrance portion 58a. In addition, in the second support portion 46a of the rib 41a, insulating paper 66a is disposed between the third housing portion 51b that houses the second electrode 18a and the opposing surface 57a. That is, the insulating paper 66a is embedded in the entrance portion 59a.

[0121] In this way, the frame body 14u, the first electrode 17a, the second electrode 18a, and the third electrode 19a, as well as the insulating papers 64a, 65a, and 66a, can be integrated together, thereby reducing the number of parts and ensuring reliable insulation between the electrodes. In addition, even when it is difficult to ensure a sufficient creepage distance by making the rib 41a a resin member, the insulation properties can be improved.

[0122] In the fifth and sixth embodiments, the insulating papers 64a, 65a, and 66a may be configured such that, for example, only one of them is provided as necessary.

[0123] (Other embodiments) In the above embodiment, the ribs are made of thermoplastic resin, but this is not limited thereto. The ribs may be made of a material other than thermoplastic resin, for example, at least a portion of the ribs may be made of thermosetting resin, or a portion of the ribs may be made of an insulating material, for example, ceramic.

[0124] In the above embodiment, the portions of the first, second and third electrodes exposed from the lid are folded 90 degrees in the third region, but the present invention is not limited to this. The portions exposed from the lid may be left as they are, for example, extending in a direction perpendicular to the first main surface, without being folded. In addition, the first electrode, etc. may be formed by attaching other members to the third region by welding or the like.

[0125] In the above embodiment, at least one of circuit boards 13b, 13c, 13d, and 13e may be divided into a plurality of electrically connected circuit boards, thereby increasing the degree of freedom in designing the shape of circuit pattern 13a.

[0126] In the present disclosure, the positions of the circuit boards and semiconductor chips on the circuit pattern and the positions of the conductive members are not necessarily limited to the above-mentioned cases. For example, the following embodiment may be used. The semiconductor device of the present disclosure includes a base plate, a substrate arranged on the base plate and including a first main surface, and a plurality of circuit boards located separately from each other, and includes a circuit pattern arranged on the first main surface, a plate-shaped first electrode arranged on the circuit pattern and connected to one of the circuit boards, a plate-shaped second electrode arranged on the circuit pattern and connected to two of the circuit boards, a plate-shaped third electrode arranged on the circuit pattern and connected to one of the circuit boards, a first semiconductor chip arranged on the circuit board, a second semiconductor chip arranged on the circuit board, and a frame body attached to the base plate and including a side wall portion surrounding the outer periphery of the substrate. At least two of the first electrode, the second electrode, and the third electrode include portions arranged in parallel. The frame body includes an insulating rib protruding from the inner wall surface of the side wall portion. The rib includes an entry portion that enters between the portions arranged in parallel and ensures a creepage distance between the electrodes arranged in parallel.

[0127] It should be understood that the embodiments disclosed herein are illustrative in all respects and are not limiting in any respect. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0128] Reference Signs List 10a, 10b semiconductor device, 11a base plate, 11b, 12b first main surface, 11c, 12c second main surface, 11d, 11e, 11f, 11g, 14h, 14i, 14j, 14k, 16e, 16f, 16g, 17e, 18e, 19e through hole, 12a substrate, 13a circuit pattern, 13b circuit board (first circuit board), 13c circuit board (second circuit board), 13d circuit board (third circuit board), 13e circuit board (fourth circuit board), 13f circuit board (fifth circuit board), 13g circuit board (sixth circuit board), 13h circuit board (seventh circuit board), 13i circuit board (eighth circuit board), 13j circuit board (ninth circuit board), 13k Circuit board (tenth circuit board), 13l circuit board (eleventh circuit board), 13m circuit board (twelfth circuit board), 14a, 14p, 14s, 14t, 14u frame, 14b, 14c, 14d, 14e side wall, 14f space, 14g opening, 14l, 14m, 14n, 14o inner wall, 14q, 14r notch, 15a sealing material, 16a cover, 16b, 16c, 16d terminal block, 16h, 16i, 16j nuts, 17a, 17j first electrode, 17b, 18b, 19b first region, 17c, 18c, 19c second region, 17d, 18d, 19d third region, 17f, 17m seventh plate portion, 17g, 17n Third portion, 17k Fourth plate portion, 17l Fifth plate portion, 18a, 18j Second electrode, 18f Third plate portion, 18g First portion, 18h Ninth plate portion, 18k Sixth plate portion, 18l Second portion, 19a, 19j Third electrode, 19f First plate portion, 19g Second plate portion, 19h, 19k Eighth plate portion, 21a, 21b, 21c, 21d First semiconductor chip, 21e, 21f Fifth semiconductor chip, 22a, 22b, 22c, 22d Second semiconductor chip, 22e, 22f Sixth semiconductor chip, 23a, 23b, 23c, 23d Third semiconductor chip, 23e, 23f Seventh semiconductor chip, 24a, 24b, 24c, 24d Fourth semiconductor chip, 24e, 24f 8th semiconductor chip, 25a first control terminal, 25b second control terminal, 25c third control terminal, 25d fourth control terminal, 26a, 26b, 26c, 26d first conductive member, 26e, 26f third conductive member, 27a, 27b, 27c, 27d second conductive member, 27e, 27f fourth conductive member, 28a, 28b, 28c, 28d, 28e wire, 29a, gap, 29b,29c end portion, 41a, 41b rib, 42a first protruding portion, 43a second protruding portion, 44a central portion, 45a first support portion, 46a second support portion, 47a first guide hole, 47b first housing portion, 48a second guide hole, 48b second housing portion, 49a, 58a, 59a entrance portion, 51a first guide groove, 51b third housing portion, 52a second guide groove, 53a 11th flat portion, 54a 12th flat portion, 55a first connection portion, 56a, 57a opposing surface, 56b first fitting portion, 57b second fitting portion, 61a 13th flat portion, 62a 14th flat portion, 63a second connection portion, 64a, 65a, 66a insulating paper, 101 capacitor, D1 gap, R area, V1,V2,V3,V4 arrow,

Claims

1. A base plate and a substrate disposed on the base plate and including a first main surface; a circuit pattern disposed on the first major surface, the circuit pattern including a first circuit board, a second circuit board, a third circuit board, and a fourth circuit board spaced apart from one another; a plate-shaped first electrode disposed on the circuit pattern and connected to the first circuit plate; a plate-shaped second electrode disposed on the circuit pattern and connected to the second circuit plate and the third circuit plate; a plate-shaped third electrode disposed on the circuit pattern and connected to the fourth circuit plate; a first semiconductor chip disposed on the first circuit board; a second semiconductor chip disposed on the third circuit board; a first conductive member electrically connecting the first semiconductor chip and the second circuit board; a second conductive member electrically connecting the second semiconductor chip and the fourth circuit board; a frame body attached to the base plate and including a side wall portion surrounding an outer periphery of the substrate; At least two of the first electrode, the second electrode, and the third electrode include portions that are arranged in parallel; The frame includes an insulating rib protruding from an inner wall surface of the side wall portion, The rib includes an entry portion that enters between the portions arranged in parallel and ensures a creepage distance between the electrodes arranged in parallel.

2. A base plate and a substrate disposed on the base plate and including a first main surface; a circuit pattern disposed on the first major surface, the circuit pattern including a plurality of spaced apart circuit boards; a plate-shaped first electrode disposed on the circuit pattern and connected to one of the circuit plates; A plate-shaped second electrode is disposed on the circuit pattern and connected to two of the circuit plates; a plate-shaped third electrode disposed on the circuit pattern and connected to one of the circuit plates; a first semiconductor chip disposed on the circuit board; a second semiconductor chip disposed on the circuit board; a frame body attached to the base plate and including a side wall portion surrounding an outer periphery of the substrate; At least two of the first electrode, the second electrode, and the third electrode include portions that are arranged in parallel; The frame includes an insulating rib protruding from an inner wall surface of the side wall portion, The rib includes an entry portion that enters between the portions arranged in parallel and ensures a creepage distance between the electrodes arranged in parallel.

3. the third electrode includes a first flat plate portion and a second flat plate portion arranged parallel to each other with a gap therebetween; the second electrode includes a third plate portion disposed between the first plate portion and the second plate portion and spaced apart from each of the first plate portion and the second plate portion, 3 . The semiconductor device according to claim 1 , wherein the penetration portion penetrates into at least one of a gap between the first flat plate portion and the third flat plate portion and a gap between the second flat plate portion and the third flat plate portion. 4 .

4. The semiconductor device according to claim 3 , wherein the first flat plate portion, the second flat plate portion and the third flat plate portion are perpendicular to the first main surface.

5. the first electrode includes a seventh plate portion, the third electrode includes an eighth plate portion disposed parallel to the seventh plate portion, The semiconductor device according to claim 1 , wherein the entrance portion is disposed between the seventh flat plate portion and the eighth flat plate portion.

6. The semiconductor device according to claim 5 , wherein the seventh plate portion and the eighth plate portion are perpendicular to the first main surface.

7. The semiconductor device according to claim 1 , wherein the rib is detachable from the side wall portion.

8. The semiconductor device according to claim 1 , wherein the rib is integral with the side wall portion.

9. 9. The semiconductor device according to claim 1, wherein the rib is made of a thermoplastic resin.

10. a sealing material that insulates a space above the base plate in the region surrounded by the frame, The semiconductor device according to claim 1 , wherein the entrance portion is in contact with the sealing material.

11. The semiconductor device according to claim 1 , further comprising an insulating paper disposed between the portions that are arranged in parallel.

Images