Semiconductor device and its manufacturing method

Abstract

An objective of the present disclosure is to provide a semiconductor device and a method for manufacturing the same, in which material of a metal layer is not diffused into a semiconductor substrate. A semiconductor device according to the present disclosure includes a semiconductor substrate formed from GaAs, a first barrier layer formed on the semiconductor substrate from an alloy containing Ni, a second barrier layer formed on the first barrier layer from Co or an alloy containing Co, and a metal layer formed on the second barrier layer. The Ni concentration of the first barrier layer is at most 80 at.%.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a technique for providing a barrier layer between a semiconductor substrate and a metal layer. The barrier layer is provided to prevent the material of the metal layer from diffusing into the semiconductor substrate. A Co alloy film is also disclosed as a barrier layer with high diffusion prevention performance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2015-145815 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the Co alloy film is kept in a high-temperature environment of 200°C or higher for a long time, some of the Co diffuses into the semiconductor substrate, forming voids in the Co alloy film, which results in deterioration of the Co alloy film and a decrease in its ability to prevent the diffusion of the metal layer into the semiconductor substrate.

[0005] The present disclosure has been made to solve the above problems, and has a first object to provide a semiconductor device in which the material of the metal layer is not diffused into the semiconductor substrate, and a second object to provide a method for manufacturing a semiconductor device in which the material of the metal layer is not diffused into the semiconductor substrate. [Means for solving the problem]

[0006] A first aspect of the present disclosure is a semiconductor substrate formed of GaAs, Made of Ni-PA first barrier layer formed of an alloy, a second barrier layer formed of an alloy containing Co or Co on the first barrier layer, and a metal layer formed on the second barrier layer, teeth Ni concentration is 80at% or less Crystalline film of It is preferable that the semiconductor device is one in which

[0007] A second aspect of the present disclosure includes a step of forming a deposition layer by depositing a catalytically active metal on a semiconductor substrate formed of GaAs, and a step of depositing a catalytically active metal on the deposition layer. Made of Ni-P The method for manufacturing a semiconductor device preferably includes the steps of: forming a first barrier layer made of an alloy by a plating method; forming a second barrier layer made of Co or an alloy containing Co by a plating method on the first barrier layer; forming a metal layer on the second barrier layer; and performing a heat treatment until the Ni concentration in the first barrier layer becomes 80 at% or less. Effect of the Invention

[0008] According to the first and second aspects of the present disclosure, a semiconductor device can be provided in which the material of the metal layer is not diffused into the semiconductor substrate. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] 1A and 1B are cross-sectional views of a sample with a Co alloy film before and after a long-term heat treatment. [Diagram 3] 1A and 1B are cross-sectional views of a sample with a Ni alloy film before and after a long-term heat treatment. [Figure 4] FIG. 2 is a cross-sectional view of a sample having a Ni alloy film after heat treatment. [Diagram 5] FIG. 2 is a cross-sectional view of a sample having a Co alloy film after heat treatment. [Figure 6] 1A and 1B are cross-sectional views of Ni alloy films and Co alloy films stacked on a Si substrate before and after they are maintained in a usage environment. [Figure 7]1A and 1B are cross-sectional views of a Ni alloy film and a Co alloy film stacked on a GaAs substrate before and after heat treatment. [Figure 8] 1 is a cross-sectional view of a via structure having a Cu diffusion barrier film formed by PVD. [Figure 9] 1 is a cross-sectional view of a via structure having a Cu diffusion barrier layer formed by plating. [Figure 10] 10A to 10C are cross-sectional views showing a process for producing a surface side element for producing the structure shown in FIG. [Figure 11] 10 is a cross-sectional view showing a supporting substrate attachment step for producing the structure shown in FIG. [Figure 12] 10A to 10C are cross-sectional views showing a process of thinning a substrate to produce the structure shown in FIG. [Figure 13] 10 is a cross-sectional view showing a via processing step for producing the structure shown in FIG. [Figure 14] 10A to 10C are cross-sectional views showing a step of forming a Ni alloy film for producing the structure shown in FIG. [Figure 15] 10A to 10C are cross-sectional views showing a step of forming a Co alloy film for producing the structure shown in FIG. [Figure 16] 10A to 10C are cross-sectional views showing a Cu film formation step for producing the structure shown in FIG. [Figure 17] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment of the present disclosure. [Figure 18] FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment of the present disclosure. [Figure 19] FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 20] FIG. 1 is a cross-sectional view showing a pinhole in a Ni plating film. [Figure 21] FIG. 11 is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 22] FIG. 13 is a cross-sectional view showing the pinhole repair effect of a Ni plating film according to a fifth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] First embodiment FIG. 1 is a cross-sectional view of a semiconductor device 10 according to a first embodiment of the present disclosure. The semiconductor device 10 includes a semiconductor substrate 12 made of GaAs. A Ni barrier layer 14 is formed on the semiconductor substrate 12. The Ni barrier layer 14 is made of Ni or an alloy containing Ni. The alloy containing Ni is, for example, Ni-P. Here, Ni-P indicates an alloy of Ni and P, and hyphens will be used hereinafter to represent the alloy. A Co barrier layer 16 is formed on the Ni barrier layer 14. The Co barrier layer 16 is made of Co or an alloy containing Co. A metal layer 18 made of Cu is formed on the Co barrier layer 16.

[0011] FIG. 2 is a cross-sectional view of a sample having a Co alloy film before and after a long-term heat treatment. The left diagram of FIG. 2 is a cross-sectional view of a sample in which a Co barrier layer 16 made of an alloy containing Co is provided between a semiconductor substrate 12 made of GaAs and a metal layer 18 made of Cu. The right diagram of FIG. 2 is a cross-sectional view of the sample after heat treatment at 270° C. for 1000 hours. From the right diagram of FIG. 2, it can be seen that the semiconductor substrate 12 and the Co barrier layer 16 react with each other when heat treatment is performed, and a Co diffusion layer 20 is formed between the two layers. At this time, voids are formed in the Co barrier layer 16. That is, Co in the Co barrier layer 16 is diffused to the semiconductor substrate 12 side. At the same time, the amount of Co that has been diffused is reduced, causing the Co barrier layer to become voided, and the diffusion path of Cu is increased. As a result, the diffusion barrier property of the Co barrier layer 16 is reduced.

[0012] FIG. 3 is a cross-sectional view of a sample having a Ni alloy film before and after a long-term heat treatment. The left diagram of FIG. 3 is a cross-sectional view of a sample in which a Ni barrier layer 14 made of an alloy containing Ni is provided between a semiconductor substrate 12 made of GaAs and a metal layer 18 made of Cu. The right diagram of FIG. 3 is a cross-sectional view of the sample after heat treatment at 270° C. for 1000 hours. From the right diagram of FIG. 3, it can be seen that the semiconductor substrate 12 and the Ni barrier layer 14 react with each other when heat treatment is performed, and a Ni diffusion layer 22 is formed between the two layers. However, unlike the Co barrier layer 16 in the right diagram of FIG. 2, no voids are formed in the Ni barrier layer 14. In other words, when Ni in the Ni barrier layer 14 diffuses to the semiconductor substrate 12 side, the Ni barrier layer does not become voided, and the diffusion path of Cu does not increase. As a result, the diffusion barrier property of the Ni barrier layer 14 does not decrease.

[0013] 4 is a cross-sectional view of a sample with a Ni alloy film after heat treatment. Here, the sample is shown in a state after heat treatment at 270° C. for 3 hours, in which a barrier layer 24 made of Ni-P is provided between a semiconductor substrate 12 made of GaAs and a metal layer 18 made of Cu. At this time, it can be seen that a Ni-Ga-As film 26 is formed at the interface between the barrier layer 24 and the semiconductor substrate 12.

[0014] Fig. 5 is a cross-sectional view of a sample having a Co alloy film after heat treatment. This shows a state after heat treatment at 270°C for 3 hours for a sample having a barrier layer 28 made of Co-WP between a semiconductor substrate 12 made of GaAs and a metal layer 18 made of Cu. It can be seen that no clear reaction layer is formed at the interface between the barrier layer 28 and the semiconductor substrate 12. Comparing Fig. 4 and Fig. 5, it can be seen that Ni has a higher reactivity with the semiconductor substrate than Co, i.e., it has better adhesion.

[0015] In the semiconductor device 10, a Ni barrier layer 14 is formed on a semiconductor substrate 12, and a Co barrier layer 16 is further formed thereon. When the semiconductor device 10 is heat-treated, the Ni barrier layer 14 in contact with the semiconductor substrate 12 does not form voids. Moreover, the Co barrier layer 16 does not form voids either, since it is not in contact with the semiconductor substrate 12. Since the Co barrier layer does not deteriorate and the Ni barrier layer itself has a Cu diffusion barrier effect, it is possible to provide a semiconductor device that does not allow the material of the metal layer to diffuse into the semiconductor substrate. Furthermore, since the interface with the semiconductor substrate 12 is the Ni barrier layer 14, it is expected that the adhesion of the electrode will be improved.

[0016] Fig. 6 is a cross-sectional view of a Ni alloy film and a Co alloy film laminated on a Si substrate before and after they are maintained in a usage environment. In the left diagram of Fig. 6, a barrier layer 24 made of Ni-P is formed on a semiconductor substrate 40 made of Si. A Co alloy layer 42 made of Co-P is formed on the barrier layer 24. A metal layer 18 made of Cu is formed on the Co alloy layer 42. The barrier layer 24 and the Co alloy layer 42 are formed by, for example, electroless plating.

[0017] The right diagram in Fig. 6 shows the state after the sample in the left diagram in Fig. 6 was maintained in a usage environment. At this time, the barrier layer 24 and the Co alloy layer 42 mutually diffuse at the interface, forming a diffusion layer 44 made of Ni-Co-P. That is, the Co alloy layer 42, which has a high diffusion barrier effect, is reduced, and the barrier properties of Cu are reduced.

[0018] The operating environment referred to here is, for example, an environment of about 100 to 200°C. A semiconductor chip having a transistor element amplifies a signal and passes a current proportional to the signal through a minute area. As a result, the temperature rises to about 100 to 200°C during operation. Furthermore, such a semiconductor chip is generally required to have a life of about 10E5 to 10E7 hours. Therefore, the barrier layer 24 and other components that constitute it are also required to have properties that are not easily deteriorated in this environment.

[0019] Fig. 7 is a cross-sectional view of a Ni alloy film and a Co alloy film laminated on a GaAs substrate before and after heat treatment. In the left diagram of Fig. 7, a barrier layer 24 made of Ni-P is formed on a semiconductor substrate 12 made of GaAs. A Co alloy layer 42 made of Co-P is formed on the barrier layer 24. A metal layer 18 made of Cu is formed on the Co alloy layer 42. The barrier layer 24 and the Co alloy layer 42 are formed by, for example, electroless plating.

[0020] The right diagram of Fig. 7 shows the state after heat treatment of the sample in the left diagram of Fig. 7. At this time, Ni of the barrier layer 24 diffuses toward the semiconductor substrate 12, and a Ni-Ga-As film 26 is formed.

[0021] The formation of the Ni-Ga-As film 26 reduces Ni, and therefore the P concentration of the barrier layer 24 increases. The barrier layer 24 formed by plating is amorphous, but when the Ni concentration is 80 at % or less, this composition change causes it to change into a crystalline film. More specifically, 12 P5, Ni7P3, Ni3P, etc. are crystallized and become more stable. As a result, interdiffusion between the barrier layer 24 and the Co alloy layer 42 is suppressed. That is, the Co alloy layer 42, which has a high diffusion barrier effect, is not reduced, so the barrier properties of Cu are maintained.

[0022] The barrier layer 24 is formed with a P concentration of, for example, 2 at % to 16 at %. In this case, the P concentration of the barrier layer 24 after the heat treatment increases from 20 at % to 40 at %.

[0023] This heat treatment is, for example, an aging treatment. In the manufacturing process of semiconductor chips, an aging treatment may be performed at 100° C. or higher for several minutes to several hours to stabilize the transistor characteristics or the adhesion of formed electrodes. When the semiconductor substrate is made of GaAs, the barrier properties of Cu can be maintained even by a relatively short-term treatment such as an aging treatment.

[0024] As described above, when the semiconductor substrate is made of GaAs, the barrier properties of Cu can be maintained by stacking a Ni alloy film and a Co alloy film on the GaAs semiconductor substrate. In other words, the configuration of the semiconductor device 10 can provide a semiconductor device that does not allow the material of the metal layer to diffuse into the semiconductor substrate.

[0025] Hereinafter, a method for manufacturing the semiconductor device 10 will be described taking as an example a case where a Cu electrode is used as the back electrode serving as the ground of a GaAs semiconductor device. This device is used, for example, in a microwave monolithic IC or the like.

[0026] Prior to the description of the manufacturing method, the existing problems when forming a film on a via structure will be described as a comparison. FIG. 8 is a cross-sectional view of a case where a Cu diffusion barrier film is formed on a via structure by the PVD method. The via structure is a through electrode structure for electrically connecting the front and back surfaces of a semiconductor substrate. The PVD method is known as a method for forming a diffusion barrier film on this via structure. Due to the mechanism of the PVD method, the amount of film formed on a flat portion differs from that on a vertical portion perpendicular to the flat portion. Specifically, the amount of film formed on the vertical portion is thinned to about 1 / 10 of the amount of film formed on the flat portion. In other words, the barrier layer 30 formed on the via structure by the PVD method is partially thinned, increasing the risk that Cu will diffuse from there into the semiconductor substrate.

[0027] Therefore, in order to ensure sufficient coverage of the via structure, there is a technique for forming a diffusion barrier film by electroless plating instead of PVD. Fig. 9 is a cross-sectional view of a case where a Cu diffusion barrier layer is formed on a via structure by plating. By forming the Ni barrier layer 14 and the Co barrier layer 16 by electroless plating, a layer of uniform thickness can be formed from the flat portion to the vertical portion, thereby reducing the risk of Cu diffusion. Therefore, in this embodiment, a manufacturing method using this plating method will be described.

[0028] First, an electric circuit is formed on one side of the GaAs single crystal semiconductor substrate 12 as the surface. Fig. 10 is a cross-sectional view showing the process of creating the surface side elements to produce the structure shown in Fig. 9. Although not shown, the wafer process for forming this electric circuit involves repeating epitaxial growth, metal film formation, insulating film formation, transfer patterning, etc. During the formation of the circuit on the surface, the opposing electrode 32 of the through electrode portion is formed. The GaAs single crystal semiconductor substrate 12 is subjected to the wafer process while it is in the shape of a disk having a diameter of 4 to 8 inches and a thickness of 0.5 to 0.6 mm.

[0029] Next, a support substrate is attached. Fig. 11 is a cross-sectional view showing a support substrate attachment step for fabricating the structure shown in Fig. 9. Here, after the wafer process on the substrate surface is completed, the surface side of the substrate is attached to a support substrate 36 with a wax material 34. Note that a tape material may be used instead of the wax material 34. The thickness of the wax material 34 is, for example, 20 microns.

[0030] Next, the substrate is thinned. Fig. 12 is a cross-sectional view showing the process of thinning the substrate to produce the structure shown in Fig. 9. Here, the semiconductor substrate 12 is attached to a support substrate 36 and then ground and polished to reduce the thickness of the semiconductor substrate 12. The thickness of the thinned semiconductor substrate 12 is set to, for example, 100 microns. By thinning the semiconductor substrate 12 in this way, the heat dissipation and high frequency characteristics of the device are improved.

[0031] Next, via processing is performed. FIG. 13 is a cross-sectional view showing a via processing process for producing the structure shown in FIG. 9. Here, in order to form an electrode penetrating the semiconductor substrate 12, a resist material is first applied to the wafer by a spin coater. Next, the resist is removed only from the processed portion by transfer and development patterning. Next, vias 38 are formed by substrate etching processing using ICP dry etching. Instead of dry etching, wet etching using a mixture of sulfuric acid and hydrogen peroxide may be used. Next, the semiconductor substrate 12 is immersed in a stripping solution to remove the resist, thereby obtaining a semiconductor substrate 12 with an exposed back surface. It should be noted that a smaller via is more advantageous in terms of the degree of freedom of layout, but if it is too small, etching does not proceed and the substrate cannot be penetrated. Therefore, the via is formed, for example, in a cylindrical shape with a diameter of 50 microns.

[0032] Next, a Ni alloy film is formed by electroless plating. Fig. 14 is a cross-sectional view showing the process of forming a Ni alloy film to produce the structure shown in Fig. 9. First, hydrophilization and activator treatment are performed as pretreatment. For example, oxygen plasma treatment or ozone treatment is performed on the wafer to modify the inner surfaces of the semiconductor substrate 12 and the vias of the counter electrode 32 to be hydrophilic. Next, when the wafer is immersed in an activated solution for electroless plating reaction containing Pd ions, the surface of the semiconductor substrate 12 dissolves due to the effect of galvanic corrosion, and Pd precipitates.

[0033] For example, the Pd ion concentration should be 10 ppm to 100 ppm, the liquid temperature should be 0°C to 50°C, and the immersion time should be 1 to 5 minutes. If the amount of Pd deposited is too small, the Ni plating film that is subsequently formed will not be formed, and if it is too large, the adhesion between the films will deteriorate. However, since the ease of Pd deposition differs depending on the type of semiconductor, it is necessary to adjust the amount within the above range depending on the type of substrate.

[0034] After the pretreatment is completed, the plate is immersed in an electroless Ni plating solution containing hypophosphorous acid as the main component. For example, the solution temperature is set to 70°C to 90°C. The plating reaction can be stabilized by circulating, filtering, and shaking the solution, and the plating film can be formed smoothly. As a result, Ni ions are precipitated as Ni by the catalytic action of Pd, and at the same time, P, a component of the solution, is co-precipitated, forming a Ni-P alloy film. Here, Pd is used as an example of the catalytic metal, but any metal that has catalytic activity for electroless plating deposition, such as Au, Ag, Pt, Ni, Sn, or Ru, can be used to obtain a Ni alloy film in the same way.

[0035] Although the Ni alloy film is formed by plating here, it may be formed by other means such as PVD or vapor deposition, in which case the pretreatment step of precipitating a catalytically active metal such as Pd is not required.

[0036] Next, a Co alloy film is formed by electroless plating. FIG. 15 is a cross-sectional view showing the process of forming a Co alloy film to produce the structure shown in FIG. 9. Here, the wafer is taken out of the electroless Ni plating solution, washed with water, and then immersed in the electroless Co plating solution while still wet. This forms a Co barrier layer 16 in succession to the Ni barrier layer 14. For example, the electroless Co plating solution containing hypophosphorous acid as the main component is used, and the solution temperature is set to 70° C. to 90° C. The plating reaction can be stabilized by circulating, filtering, and rocking the solution, so that the plating film can be formed smoothly.

[0037] If the surface is dried through a spin drying process after the formation of the Ni barrier layer 14, the surface hydrophilicity is lost, so a hydrophilization treatment is performed before immersion in the plating solution. If the Co deposition reaction is difficult to initiate, it can be stabilized by adding an activator treatment before electroless Co plating.

[0038] Next, Cu plating is performed by electroplating. FIG. 16 is a cross-sectional view showing the process of forming a Cu film to produce the structure shown in FIG. 9. The wafer and the Cu plate are immersed in a Cu sulfate plating solution, and electricity is passed through the wafer periphery as the cathode and the Cu plate as the anode, so that a metal layer 18 proportional to the amount of electricity supplied can be formed. The solution temperature is set to, for example, 30° C. Also, by selectively growing a film in the via 38 by adjusting the additive, it is possible to manufacture a via 38 whose inside is filled with Cu. This can improve the heat dissipation and electrical characteristics of the semiconductor device.

[0039] In addition, when forming the Cu plating, electroless plating may be used instead of electroplating. In the case of electroless plating, it is also possible to manufacture Cu-filled vias 38 by adjusting the additives. In addition, in order to prevent the surface oxidation of the Cu plating, electroless plating may be performed as a post-treatment, or Ni plating, Pd plating, and Au plating may be performed in sequence by electroplating. This improves the adhesion of die bonding and wire bonding.

[0040] The thickness may be, for example, 0.5 microns for the Ni barrier layer 14, 0.5 microns for the Co barrier layer 16, and 3 microns for the metal layer 18. In electroless Ni plating and electroless Co plating, the start of the plating reaction may vary across the surface, and a thin film may cause poor film formation, so the film is formed to a thickness of at least 0.2 microns. In addition, if the total thickness of the Ni barrier layer 14 and the Co barrier layer 16 exceeds 2 microns, the interface will peel off due to residual stress, so the film is formed so that the total thickness is less than 2 microns. The thickness of the metal layer 18 needs to be designed according to the maximum current flowing through the via.

[0041] Finally, the support substrate 36 is removed. First, the support substrate 36 and the semiconductor device are heated on a hot plate at 100°C for at least one minute to melt the wax material 34. Then, they are slid parallel to the substrate surface, and the support substrate 36 is removed. After that, the substrate is immersed in acetone heated to 50°C for 10 minutes to remove the wax material 34 on the surface. At this time, the longer the temperature and the immersion time, the higher the removability.

[0042] The semiconductor substrate 12 in this embodiment is made of GaAs, but since the interaction due to the thermal history after the metal film formation is similar to that of a single crystal semiconductor substrate, it may be made of other semiconductor materials. The other materials include, for example, compound semiconductors such as InP, GaN, SiC, and SiGe, and Si. This can also be applied to the semiconductor device and the manufacturing method of the semiconductor device according to the following embodiments. In addition, the present disclosure is not limited to the use of the back electrode of an IC device, etc., but is effective for the general technology of forming a metal film on a semiconductor substrate. The semiconductor device and the manufacturing method according to the following embodiments will be described focusing on the differences from the first embodiment.

[0043] Embodiment 2 17 is a cross-sectional view of a semiconductor device according to a second embodiment of the present disclosure. A semiconductor device 50 differs from the first embodiment in that a diffusion prevention layer 52 including Pd is formed between the Ni barrier layer 14 and the Co barrier layer 16. When a Co alloy and a Ni alloy are continuously grown, depending on the usage environment, Ni and Co may interdiffuse with each other, resulting in a decrease in barrier properties. Therefore, the diffusion prevention layer 52 is formed between them to prevent interdiffusion.

[0044] The diffusion prevention layer 52 including Pd is formed by, for example, electroless plating. After removing the wafer from the electroless Ni plating solution and rinsing it with water, the wafer is immersed in an electroless Pd plating solution while still wet, to form a Pd plating film.

[0045] The thickness of the diffusion prevention layer 52 is, for example, 0.01 microns. If it is thicker than 0.1 microns, peeling occurs at the boundary with the Ni barrier layer 14, so it is designed to be 0.1 microns or less. If it is thinner than 0.01 microns, precipitation is not stable, so it is designed to be 0.01 microns or more.

[0046] The diffusion prevention layer 52 is made of Pd, but other materials may be used as long as they can prevent interdiffusion. For example, metals that have catalytic activity for electroless plating deposition, such as Au, Ag, Pt, Sn, and Ru, may be used.

[0047] Third embodiment 18 is a cross-sectional view of a semiconductor device according to a third embodiment of the present disclosure. The semiconductor device 100 differs from the first embodiment in that a precipitate layer 102 is formed by precipitating Pd on a semiconductor substrate 12, and that a Ni alloy film and a Co alloy film are formed by electroless plating. That is, the semiconductor device 100 forms a Ni-plated barrier layer 104 on the precipitate layer 102. Furthermore, a Co-plated barrier layer 106 is formed on the Ni-plated barrier layer 104. By using the electroless plating method, a uniform barrier layer can be formed even on an uneven shape such as a via structure.

[0048] Here, the deposition layer 102 is an essential step in forming the Ni plating barrier layer 104. The deposition layer 102 is made of Pd, but other materials may be used as long as they are metals with catalytic activity. This embodiment can be manufactured by the method shown in Figs. 10 to 16.

[0049] Fourth embodiment 19 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present disclosure. The semiconductor device 150 includes a diffusion prevention layer 52 including Pd in ​​addition to the configuration of the semiconductor device 100. The diffusion prevention layer 52 is formed between the Ni plating barrier layer 104 and the Co plating barrier layer 106 in order to prevent interdiffusion of Ni and Co. The diffusion prevention layer 52 may be made of a material other than Pd as long as it can prevent interdiffusion. For example, a metal having catalytic activity for electroless plating deposition, such as Au, Ag, Pt, Sn, or Ru, may be used.

[0050] Fifth embodiment Prior to describing the fifth embodiment, a manufacturing process when pinholes are formed, which is an existing problem, will be described for comparison. FIG. 20 is a cross-sectional view showing a pinhole in a Ni plating film. If a formation defect occurs due to foreign matter, dirt, or the like, a pinhole 204 may be formed as shown in FIG. 20 when the Ni plating barrier layer 104 is formed. If the Co plating barrier layer 106 is subsequently formed in this state, a film cannot be formed in the pinhole portion because there is no nucleus for film growth. As a result, the pinhole remains unrepaired even when the metal layer 18 is formed. This embodiment solves the above-mentioned problems.

[0051] 21 is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present disclosure. In the semiconductor device 200, a diffusion prevention layer 202 including Pd is formed by deposition or sputtering in addition to the configuration of the semiconductor device 100. The diffusion prevention layer 202 is formed between the Ni plating barrier layer 104 and the Co plating barrier layer 106 in order to prevent interdiffusion of Ni and Co. The diffusion prevention layer 202 may be made of a material other than Pd as long as it can prevent interdiffusion. For example, a metal having catalytic activity for electroless plating deposition, such as Au, Ag, Pt, Sn, or Ru, may be used.

[0052] FIG. 22 is a cross-sectional view showing the pinhole repair effect of the Ni plating film according to the fifth embodiment of the present disclosure. Here, following the Ni plating barrier layer 104 in which the pinhole 204 is formed, the diffusion prevention layer 202 is formed by deposition or sputtering. Unlike plating, deposition and sputtering form a film without relying on an underlayer, so that the diffusion prevention layer 202 is also formed on the pinhole 204. If the Co plating barrier layer 106 is subsequently formed, a film can be formed in the pinhole portion because there is a nucleus for film growth. As a result, no pinhole remains in the metal layer 18, and any pinhole that may have formed in the barrier layer is repaired. That is, the deterioration of the barrier properties of the barrier layer can also be prevented. [Explanation of symbols]

[0053] 10, 50, 100, 150, 200 Semiconductor device 12, 40 Semiconductor substrate 18 Metal Layer 24, 28, 30 Barrier layer 52, 202 Diffusion prevention layer 102 Precipitated layer 104, 106 Barrier layer

Claims

1. A semiconductor substrate made of GaAs; a first barrier layer formed of an alloy of Ni--P on the semiconductor substrate; a second barrier layer formed of an alloy containing Co or Co on the first barrier layer; a metal layer formed on the second barrier layer; Equipped with The semiconductor device, wherein the first barrier layer is a crystalline film having a Ni concentration of 80 at % or less.

2. Between the first barrier layer and the second barrier layer, 2. The semiconductor device according to claim 1, further comprising a diffusion barrier layer containing a catalytically active metal.

3. Between the semiconductor substrate and the first barrier layer, 3. The semiconductor device according to claim 1, further comprising a deposition layer formed by depositing a metal having catalytic activity.

4. forming a deposition layer by depositing a catalytically active metal on a semiconductor substrate made of GaAs; forming a first barrier layer made of an alloy of Ni-P on the deposition layer by a plating method; forming a second barrier layer made of Co or an alloy containing Co on the first barrier layer by a plating method; forming a metal layer on the second barrier layer; performing a heat treatment until the Ni concentration of the first barrier layer becomes 80 at % or less; A method for manufacturing a semiconductor device comprising the steps of:

5. Between the first barrier layer and the second barrier layer, 5. The method for manufacturing a semiconductor device according to claim 4, further comprising the step of forming a diffusion prevention layer containing a metal having catalytic activity.

6. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the diffusion prevention layer is formed by a vapor deposition method or a sputtering method.

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