Variable Resistance Memory Element

Abstract

To provide a variable resistance memory device.SOLUTION: A variable resistance memory device includes: a variable resistance layer which includes a first layer formed of a first material and a second layer located on the first layer, the second layer being formed of a second material having a different valence than a valence of the first material; and a first conductive element and a second conductive element which are located on the variable resistance layer to be spaced apart from each other, so as to form a current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a non-volatile memory device utilizing a variable resistance material. [Background technology]

[0002] As a semiconductor memory device, a non-volatile memory device is a memory device in which stored data does not disappear even if the power supply is interrupted. Examples of such a memory device include a programmable read only memory (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), and a flash memory device.

[0003] In recent years, due to the demand for technology that has high integration and low power consumption characteristics and allows random access to memory cells, next-generation semiconductor memory devices such as magnetic random access memory (MRAM) and phase-change random access memory (PRAM) have been developed.

[0004] Such next-generation semiconductor memory devices employ variable resistance elements whose resistance value changes depending on an applied current or voltage and whose changed resistance value is maintained even when the supply of the current or voltage is interrupted. In order to realize high integration and low power consumption, it is preferable that the variable resistance element has a resistance change characteristic that occurs at a low applied voltage and has a wide resistance change range. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention provides a variable resistance memory element with improved variable resistance performance. [Means for solving the problem]

[0006] According to one type, there is provided a variable resistance memory element including: a first layer made of a first material; a second layer arranged on the first layer and made of a second material having a different valence from the first material; and a first conductive element and a second conductive element arranged on the variable resistance layer to be spaced apart from each other so as to form a current path in the variable resistance layer in a direction perpendicular to a stacking direction of the first layer and the second layer.

[0007] The valence difference between the first and second substances may be 1 or more.

[0008] The density difference between the first and second substances is 1g / cm 3 It may be larger than.

[0009] The variable resistance layer may further include a third layer disposed on the second layer and made of a third material having a valence different from the valence of the second material.

[0010] The first and third layers may be made of the same material.

[0011] The resistance variable layer may further include a fourth layer disposed on the third layer and made of a fourth material having a valence different from a valence of the third material.

[0012] The first and third substances may be the same substance.

[0013] The second substance and the fourth substance may be the same substance.

[0014] The first and second materials may be oxides having a band gap energy of 2 eV or more.

[0015] The first and second substances are Rb 2 O,TiO 2 ,BaO,ZrO 2 ,CaO,HfO 2 ,SrO,Sc 2 O 3 ,MgO,Li 2 O,Al 2 O 3,SiO 2 ,BeO,Sc 2 O 3 ,Nb 2 O 5 ,NiO,Ta 2 O 5 ,WO 3 ,V 2 O 5 ,La 2 O 3 ,Gd 2 O 3 ,CuO,MoO 3 ,Cr 2 O 3 and MnO 2 It may be any one of the above.

[0016] According to another type, there is provided a variable resistance memory element including: a support layer made of an insulating material; a variable resistance layer disposed on the support layer, the variable resistance layer including a first layer made of a first material, and a second layer disposed on the first layer and made of a second material having a different valence from the first material; a channel layer disposed on the variable resistance layer; a gate insulating layer formed on the channel layer; and a plurality of gate electrodes disposed spaced apart from each other on the gate insulating layer.

[0017] The valence difference between the first and second substances may be 1 or more.

[0018] The density difference between the first and second substances is 1g / cm 3 It may be larger than.

[0019] The variable resistance layer may further include a third layer disposed on the second layer and made of a third material having a valence different from the valence of the second material.

[0020] The first and third layers may be made of the same material.

[0021] The resistance variable layer may further include a fourth layer disposed on the third layer and made of a fourth material having a valence different from a valence of the third material.

[0022] The first and third substances may be the same substance.

[0023] The second substance and the fourth substance may be the same substance.

[0024] The first and second layers may each have a thickness of 10 nm or less.

[0025] The first and second materials may be oxides having a band gap energy of 2 eV or more.

[0026] The first and second substances are Rb 2 O,TiO 2 ,BaO,ZrO 2 ,CaO,HfO 2 ,SrO,Sc 2 O 3 ,MgO,Li 2 O,Al 2 O 3 ,SiO 2 ,BeO,Sc 2 O 3 ,Nb 2 O 5 ,NiO,Ta 2 O 5 ,WO 3 ,V 2 O 5 ,La 2 O 3 ,Gd 2 O 3 ,CuO,MoO 3 ,Cr 2 O 3 and MnO 2 It may be any one of the above.

[0027] According to yet another type, there is provided a variable resistance memory element including: a first layer made of a first material; a second layer disposed on the first layer and made of a second material having a different valence from the first material; a variable resistance layer located between the first layer and the second layer and including an interface including a plurality of oxygen vacancies; a first conductive element coupled to a first region of the variable resistance layer; and a second conductive element coupled to a second region of the variable resistance layer and spaced apart from the first conductive element. Effect of the Invention

[0028] The resistance variable memory element described above can change in resistance under a low applied voltage.

[0029] The above-described variable resistance memory element can exhibit a wide variable resistance range.

[0030] The above-described variable resistance memory device can be easily implemented with low power consumption and high integration. [Brief description of the drawings]

[0031] [Figure 1] 1 is a cross-sectional view illustrating a schematic structure of a variable resistance memory element according to an embodiment; [Diagram 2] 2 is a conceptual diagram illustrating the principle of variable resistance occurring in a variable resistance layer provided in the variable resistance memory element of FIG. 1. FIG. [Diagram 3] 11 is a cross-sectional view showing a schematic configuration of a variable resistance memory element according to another embodiment. [Figure 4] 4 is a conceptual diagram for explaining the principle of variable resistance occurring in a variable resistance layer provided in the variable resistance memory element of FIG. 3. FIG. [Diagram 5] 11 is a cross-sectional view showing a schematic configuration of a variable resistance memory element according to still another embodiment. [Figure 6] 1 is a cross-sectional view showing a schematic configuration of a sample fabricated for experimenting variable resistance performance in a configuration in which variable resistance materials having different atomic valences are adjacently stacked. FIG. [Figure 7] 1 is a cross-sectional view showing a schematic configuration of a sample fabricated for experimenting variable resistance performance in a configuration in which variable resistance materials having different atomic valences are adjacently stacked. FIG. [Figure 8] 11 is a cross-sectional view showing a schematic configuration of a variable resistance memory element according to still another embodiment. [Figure 9] 9 is an equivalent circuit diagram of the variable resistance memory element of FIG. 8. [Figure 10] 9 is a conceptual diagram for illustrating an example of the operation of the variable resistance memory element of FIG. 8. FIG. [Figure 11] 11 is a cross-sectional view illustrating a schematic structure of a variable resistance memory device according to yet another embodiment. [Figure 12] 11 is a cross-sectional view illustrating a schematic structure of a variable resistance memory device according to yet another embodiment. [Figure 13] 11 is a cross-sectional view illustrating a schematic structure of a variable resistance memory device according to yet another embodiment. [Figure 14] 14 is a perspective view showing a schematic structure of a memory string included in the variable resistance memory element of FIG. 13. FIG. [Figure 15] FIG. 14 is an equivalent circuit diagram of the variable resistance memory element of FIG. [Figure 16] 1 is a block diagram illustrating a memory system according to an embodiment. [Figure 17] FIG. 2 is a block diagram illustrating a neuromorphic device and an external device coupled thereto according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. The described embodiments are merely exemplary, and various modifications are possible from these embodiments. In the following drawings, the same reference numerals refer to the same components, and the size of each component may be exaggerated in the drawings for clarity and convenience of explanation.

[0033] Hereinafter, the terms "upper" and "above" include not only those that are directly above in contact with one another, but also those that are above without contacting one another.

[0034] The terms first, second, etc., are used to describe various components, but are used only to distinguish one component from another, and are not intended to limit the components to being different in material or structure.

[0035] The singular expression includes the plural expression unless otherwise clearly indicated in the context. Furthermore, when a part "comprises" a certain element, it does not mean excluding other elements, but further includes other elements, unless otherwise specified to the contrary.

[0036] In addition, terms such as "unit" and "module" used in the specification refer to a unit that processes at least one function or operation, and may be realized by hardware or software, or a combination of hardware and software.

[0037] Use of the term "said" and similar referents refers to both the singular and the plural.

[0038] The steps constituting the method may be performed in any suitable order unless there is an explicit citation that they should be performed in the order described. Furthermore, the use of all exemplary terms (e.g., etc.) is merely for the purpose of illustrating technical concepts in detail, and is not intended to limit the scope of the invention unless and until the scope of the claims is limited by such terms.

[0039] FIG. 1 is a cross-sectional view showing a schematic structure of a variable resistance memory element according to an embodiment, and FIG. 2 is a conceptual diagram explaining the principle of variable resistance occurring in a variable resistance layer provided in the variable resistance element of FIG.

[0040] Referring to FIG. 1, a variable resistance memory element 100 includes a variable resistance layer 130 having a first layer 11 and a second layer 12, and a first conductive element E1 and a second conductive element E2 for applying a voltage to the variable resistance layer 130.

[0041] The variable resistance layer 130 includes a first layer 11 made of a first substance and a second layer 12 disposed on the first layer 11 and made of a second substance having a different valence from the first substance. The first layer 11 may be a layer having a higher valence than the second layer 12, and the second layer 12 may be a layer having a higher valence than the first layer 11.

[0042] The first conductive element E1 and the second conductive element E2 are disposed on both ends of the variable resistance layer 130, and are disposed so as to form a current path in a horizontal direction within the variable resistance layer 130, i.e., in a direction perpendicular to the direction in which the first layer 11 and the second layer 12 are stacked, when a voltage is applied. The first conductive element E1 and the second conductive element E2 are formed so as to contact both ends of the second layer 12. However, this is merely an example, and the first conductive element E1 and the second conductive element E2 may also be formed so as to contact both ends of the first layer 11.

[0043] The variable resistance layer 130 is a layer that exhibits different resistance characteristics depending on the applied voltage. The resistance characteristics of the variable resistance layer 130 depend on whether or not a conductive filament is formed due to the behavior of oxygen that occurs in the variable resistance layer 130 in response to a voltage applied to the first conductive element E1 and the second conductive element E2 formed on the variable resistance layer 130. Depending on whether or not a conductive filament is formed, the variable resistance layer 130 exhibits a low resistance state or a high resistance state, thereby recording information '1' or '0'. The applied voltage that changes the variable resistance layer 130 from a high resistance state to a low resistance state is called a set voltage V set The applied voltage that changes the low resistance state to the high resistance state is the reset voltage V reset The resistance variable memory element 100 according to the embodiment provides a configuration of the resistance variable layer 130 capable of implementing a low set voltage.

[0044] In the embodiment, when the variable resistance layer 130 is formed of a plurality of layers in which the first layer 11 and the second layer 12 made of materials having different valences are arranged adjacent to each other, as shown in FIG. 4, oxygen vacancies V o is formed.

[0045] For example, the first substance contained in the first layer 11 is HfO 2 and the second substance contained in the second layer 12 is Al having a valence of 3. 2 O 3 In this case, Al occupies the Hf site and oxygen vacancies are formed at the interface between the first layer 11 and the second layer 12. Such atomic behavior is expressed by the following equation.

[0046] [ka]

[0047] In the formula, Al Hf ’ Al 2 O 3 In the structure, some of the Al is HfO 2 This means that the Hf position is occupied by V. O ·· is a structure in which the O position is vacant, and O O x means a structure in which O is located at the O position.

[0048] The oxygen vacancy V thus formed o gather together to form conductive filaments, which cause the resistance of the variable resistance layer 130 to become lower.

[0049] Even at a low applied voltage, the conductive filament is sufficiently formed, and the larger the difference in resistance between the low resistance state and the high resistance state caused by the applied voltage, the better the variable resistance performance. For this reason, the variable resistance layer 130 employs a structure in which oxides with different valences are arranged adjacent to each other, and oxygen vacancies V o The valence difference between the first layer 11 and the second layer 12 may be 1 or more so that the above is sufficiently formed.

[0050] When the variable resistance layer 130 is configured as in the embodiment, a desired resistance change range can be realized with a smaller thickness than an existing charge trap based variable resistance element or a variable resistance element using a phase change material. The first layer 11 and the second layer 12 constituting the variable resistance layer 130 may each have a thickness of, for example, 10 nm or less.

[0051] The first and second materials included in the variable resistance layer 130 may be made of various oxides. For example, the first and second materials include an oxide of at least one element selected from the group including zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), praseodymium (Pr), rubidium (Rb), barium (Ba), magnesium (Mg), beryllium (Be), niobium (Nb), vanadium (V), gadolinium (Gd), scandium (Sc) and silicon (Si). As the first and second materials, an oxide having a band gap energy of 2 eV or more is used, for example, Rb 2 O,TiO 2 ,BaO,ZrO 2 ,CaO,HfO 2 ,SrO,Sc 2 O 3 ,MgO,Li 2 O,Al 2 O 3 ,SiO 2 ,BeO,Sc 2 O 3 ,Nb 2 O 5 ,NiO,Ta 2 O 5 ,WO 3 ,V 2 O 5 ,La 2 O 3 ,Gd 2 O 3 ,CuO,MoO 3 ,Cr 2 O 3 and MnO 2 Any one of them may be used.

[0052] If we look at the atomic valence of substances, we see the following Table 1.

[0053] [Table 1]

[0054] With reference to Table 1, two substances having different valences can be selected and applied to the first layer 11 and the second layer 12. The valence difference between the first layer 11 and the second layer 12 can be set so that sufficient interatomic replacement due to the valence difference occurs, thereby forming sufficient oxygen vacancies. For example, the substances of the first layer 11 and the second layer 12 may be set so that the valence difference between the first layer 11 and the second layer 12 is 1 or more. For example, the first layer 11 is made of HfO, which has a valence of 4. 2 The second layer 12 includes Al having a valence of 3. 2 O 3 In addition, the following combinations may be adopted:

[0055] [Table 2]

[0056] In each of the illustrated combinations, the first and second materials are selected from among materials with a valence difference of 1. However, this is exemplary and other combinations with a valence difference of 2, 3, 4, etc. may be selected.

[0057] Even if the valence difference between the first and second materials is constant, the greater the density difference, the smoother the formation of oxygen vacancies. Since the lower density oxide has more space between atoms than the higher density oxide, the oxygen ions (O 2- In consideration of this, the density difference between the materials of the first layer 11 and the second layer 12 is set to, for example, 1 g / cm 3 The first and second substances can be selected so that the above is satisfied. 2 O 3 / HfO 2 It is estimated that the density difference is the largest and oxygen vacancies are formed more smoothly in the combination of the above. However, the present invention is not limited to this combination.

[0058] Fig. 3 is a cross-sectional view showing a schematic configuration of a variable resistance memory element 101 according to another embodiment. Fig. 4 is a conceptual diagram explaining the principle of variable resistance occurring in a variable resistance layer provided in the variable resistance element of Fig. 3.

[0059] The variable resistance layer 131 of the variable resistance memory element 101 according to this embodiment includes a first layer 11, a second layer 12 and a third layer 13, and a first conductive element E1 and a second conductive element E2 are arranged on the third layer 13 so as to contact both ends thereof.

[0060] The resistance variable layer 131 has a structure in which two or more substances with different valences are laminated, and any two adjacent layers among the first layer 11, the second layer 12, and the third layer 13 may each contain a substance with a different valence. That is, the first substance of the first layer 11 and the second substance of the second layer 12 have different valences, and the second substance of the second layer 12 and the third substance of the third layer 13 have different valences. The first substance and the third substance may be the same or different.

[0061] The valence difference between the first material of the first layer 11 and the second material of the second layer 12 may be 1 or more. The valence difference between the second material of the second layer 12 and the third material of the third layer 13 may be 1 or more.

[0062] The second material of the second layer 12 located in the middle of the resistance variable layer 131 is a material having a different valence from the first material and the third material, and is not particularly limited thereto. For example, the valences of the first layer 11, the second layer 12, and the third layer 13 may be arranged to be successively higher or lower, and the valence of the second material of the second layer 12 may be the lowest or highest.

[0063] The materials are selected so that oxygen vacancies caused by the difference in atomic valence are generated sufficiently at each interface between the first layer 11, the second layer 12, and the third layer 13. The first layer 11 and the third layer 13 are made of HfO 2 and the second layer 12 comprises Al 2 O 3The first layer 11 and the third layer 13 may contain a first substance, and the second layer 12 may contain a second substance. For example, a combination of the first substance and the second substance as shown in Table 2 may be selected. In addition, among them, a combination of the first substance and the second substance with a density difference of 1 g / cm 3 A material having a density difference of 1 g / cm may be selected among the combinations of different valences. 3 may be selected as the first material and the second material.

[0064] The first layer 11, the second layer 12, and the third layer 13 may each have a thickness of 10 nm or less. The second layer 12 may have the smallest thickness, for example, a thickness of 2 nm or less.

[0065] In this embodiment, the resistance variable layer 131 is configured with a three-layer structure in which materials with different valences are adjacent to each other, so that there are more interfaces where oxygen vacancies occur due to the difference in valences. As shown in FIG. 4, oxygen vacancies V o and interstitial oxygen ions (O 2- When the oxygen vacancies V are formed, an exchange of atoms occurs at two interfaces where materials with different atomic valences are in contact, that is, at the interface between the first layer 11 and the second layer 12 and the interface between the second layer 12 and the third layer 13. o is sufficiently formed, and oxygen vacancies V o For example, the conductive filaments can be formed more easily than in the structure of FIG.

[0066] FIG. 5 is a cross-sectional view showing a schematic configuration of a variable resistance memory element 102 according to still another embodiment.

[0067] In the variable resistance memory element 102 according to this embodiment, the variable resistance layer 132 includes a first layer 11, a second layer 12, a third layer 13 and a fourth layer 14.

[0068] At least two of the first, second, third and fourth substances contained in the first layer 11, the second layer 12, the third layer 13 and the fourth layer 14 respectively have different valences. In addition, adjacent layers are made of substances having different valences. That is, the first and second substances have different valences, the second and third substances have different valences, and the third and fourth substances have different valences. The first and third substances may be the same substance. The second and fourth substances may be the same substance. For example, the first and third layers 11 and 13 may contain the first substance, and the second and fourth layers 12 and 14 may contain the second substance. A combination of the first and second substances as shown in Table 2 may be selected. In addition, among them, a density difference of 1 g / cm 3 A material having a density difference of 1 g / cm may be selected among the combinations of different valences. 3 may be selected as the first and second materials, but is not limited thereto.

[0069] The materials of the first layer 11, the second layer 12, the third layer 13, and the fourth layer 14 constituting the variable resistance layer 132 are selected so that the materials at adjacent positions have different valences, and are not particularly limited thereto. For example, the valences of the first layer 11, the second layer 12, the third layer 13, and the fourth layer 14 may be arranged to be sequentially higher or lower, and the second layer 12 or the third layer 13 may be made of a material with the highest or lowest valence.

[0070] The first material, the second material, the third material, and the fourth material are set so that the valence difference between each layer is 1 or more, and is determined so that oxygen vacancies generated due to the valence difference are more sufficiently generated at the interface between each layer.

[0071] Various oxides having a band gap energy of 2 eV or more are used as the materials for the first layer 11, the second layer 12, the third layer 13, and the fourth layer 14, and as described above, each material is set so that the valence difference at the interface between adjacent layers is as large as possible.

[0072] Such a material configuration allows the valence difference at the interface between the layers to be expressed as large as possible, and the formation of oxygen vacancies by atomic exchange is more easily achieved.

[0073] The variable resistance layer 132 has a structure in which interfaces of materials with different valences are further added, and the number of interfaces where conductive filaments are formed by oxygen vacancies increases, so that the resistance change range becomes larger.

[0074] 6 and 7 are cross-sectional views showing a schematic configuration of a sample fabricated for testing variable resistance performance in a structure in which variable resistance materials having different atomic valences are adjacently laminated.

[0075] As shown in Figure 6, a 100 nm SiO 2 , 400 nm N-type Si, 10 nm SiO 2 and a 50 nm N-type Si layer were sequentially deposited, followed by patterning and etching to form a N-Si(50 nm) / SiO 2 We created a cylindrical element of N-Si (10 nm) / N-Si (400 nm). The side of the cylindrical element was coated with HfO 2 By depositing 10 nm of HfO on the n-Si upper electrode and applying a voltage between the n-Si lower electrode and the N-Si lower electrode, HfO 2 / SiO 2 Current flows along the layer. In order to improve the contact resistance between the N-Si upper electrode and the probe station terminal, Ti (10 nm) / Pt (40 nm) are evaporated onto the N-Si upper electrode.

[0076] FIG. 7 shows the structure of FIG. 6 with HfO 2 The layer is then made 2 nm thick and then coated with Al 2 O 3 2nm and HfO 2 When a voltage is applied between the upper electrode N-Si and the lower electrode N-Si, SiO 2 / HfO 2 / Al 2 O3 A current flows along the layer.

[0077] The structures of Figures 6 and 7 are intended to replicate the variable resistance performance of a multi-layer structure in which materials of different valences are adjacent.

[0078] In both structures, the set voltage V set The average set voltage V for 35 samples was measured as shown in Figure 6. set is 12.36V, the average set voltage V for 56 samples as shown in Figure 7. set was measured at 6.85V.

[0079] Such a set voltage V set is the set voltage V, which is usually expressed as 15 V or more in variable resistance elements that use existing charge trapping layers. set , it can be seen that the set voltage is reduced in the structure in which two layers having different valences are adjacently arranged.

[0080] In the above-described embodiments, the variable resistance layers 130, 131, and 132 are exemplified as having a two-layer, three-layer, or four-layer structure, but are not limited thereto, and may be changed to a structure of five or more layers in which interfaces with different valences are further added.

[0081] Fig. 8 is a cross-sectional view showing a schematic configuration of a variable resistance memory element according to yet another embodiment, and Fig. 9 shows an equivalent circuit of the variable resistance memory element of Fig. 8. Fig. 10 is a conceptual diagram exemplarily explaining the operation of the variable resistance memory element of Fig. 8.

[0082] 8, the variable resistance memory element 200 includes an insulating layer 210, a variable resistance layer 230 disposed on the insulating layer 210, a channel layer 240 disposed on the variable resistance layer 230, a gate insulating layer 250 disposed on the channel layer 240, and a plurality of gate electrodes 260 formed on the gate insulating layer 250. Spaces between the plurality of gate electrodes 260 are filled with an insulating layer 270. However, this is merely exemplary, and the insulating layer 270 may be omitted.

[0083] The resistance variable layer 230 includes a first layer 11 made of a first material and a second layer 12 made of a second material having a different valence from the first material. The second layer 12 may have a higher valence than the first layer 11. The materials and characteristics of the resistance variable layer 230 are substantially similar to those described for the resistance variable layer 130 of FIG. 1. When materials having different valences are mixed, atomic exchange occurs, and oxygen vacancies are generated. In other words, oxygen vacancies V o occurs sufficiently to form a conductive filament.

[0084] In the variable resistance layer 230, the second layer 12 having a high valence is shown disposed on the first layer 11 having a low valence, but the present invention is not limited thereto, and the stacking order of the first layer 11 and the second layer 12 may be changed. That is, the first layer 11 having a low valence may be formed on the second layer 12 having a high valence, and the first layer 11 may be in contact with the channel layer 240.

[0085] The channel layer 240 may be made of a semiconductor material, for example, poly-Si. A source electrode S and a drain electrode D may be connected to both ends of the channel layer 240.

[0086] The gate insulating layer 250 may be made of various kinds of insulating materials. For example, silicon oxide, silicon nitride, or silicon oxynitride may be used for the gate insulating layer 250.

[0087] A voltage for turning on / off the channel layer 240 may be selectively applied to each of the multiple gate electrodes 260 .

[0088] The variable resistance memory element 200 has a structure in which a plurality of memory cells MC are arrayed, and each memory cell MC has a configuration in which a transistor and a variable resistor are connected in parallel, as shown in the equivalent circuit of Fig. 9. Each variable resistor is set by a voltage applied to a gate electrode and a voltage between a source electrode S and a drain electrode D, and has a value corresponding to information of 1 or 0.

[0089] The operation of the variable resistance memory device 200 will be described with reference to FIG.

[0090] When a memory cell to be recorded is selected, the gate voltage value of the selected cell is adjusted so that a channel is not formed in the selected cell, i.e., the channel is turned off, and the gate voltage values ​​of the unselected cells are adjusted so that the channels are turned on.

[0091] 10 shows a case where a gate voltage is applied to the gate electrode 260 of each cell so that the middle memory cell MC2 is turned off and the two memory cells MC1 and MC3 on either side are turned on. When a voltage is applied between the source electrode S and the drain electrode D, a conduction path is formed as shown by the arrow A. When the applied voltage is a set voltage V set or reset voltage V reset The desired information, 1 or 0, is recorded in the memory cell MC2 selected as the value of .

[0092] Similarly, in a read operation, a selected cell is read. That is, the gate voltage applied to each gate electrode 260 is adjusted so that the selected memory cell MC2 is in a channel-off state and the unselected memory cells MC1 and MC2 are in a channel-on state, and then the applied voltage V between the source electrode S and the drain electrode D is adjusted. read By measuring the current flowing through the cell MC2, the cell state (1 or 0) can be confirmed.

[0093] FIG. 11 is a cross-sectional view showing a schematic structure of a variable resistance memory element according to still another embodiment.

[0094] The variable resistance memory element 201 according to this embodiment differs from the variable resistance memory element 200 of FIG. 8 in that the variable resistance layer 231 includes a first layer 11, a second layer 12 and a third layer 13, but the remaining configuration is substantially similar to that of the variable resistance memory element 200 of FIG. 8.

[0095] The resistance variable layer 231 includes a first layer 11, a second layer 12, and a third layer 13. The second layer 12 located in the middle of the resistance variable layer 231 may include a material having the highest atomic valence compared to the first layer 11 and the third layer 13. Alternatively, the second layer 12 may include a material having the lowest atomic valence compared to the first layer 11 and the third layer 13. The first layer 11 and the third layer 13 may be made of the same material. However, without being limited thereto, the first layer 11 and the third layer 13 may be made of different materials.

[0096] In the variable resistance layer 231 of the variable resistance memory element 201 according to the present embodiment, the materials of the first layer 11, the second layer 12, and the third layer 13 are set so that a plurality of interfaces between materials with different valences are generated, and the valence difference at each interface is as large as possible, similar to the variable resistance layer 131 described in FIG. 3. In the variable resistance layer 231, the first material, the second material, and the third material may be set so that the valence of the second material of the second layer 12, which is the intermediate position, is the lowest or highest. This allows the replacement of atoms to occur more smoothly, and oxygen vacancies are sufficiently generated in the interface region, so that the conductive filament can be sufficiently formed. The variable resistance memory element 201 according to the present embodiment may have a low set voltage, for example, a set voltage lower than that of the variable resistance memory element 200 of FIG. 8.

[0097] FIG. 12 is a cross-sectional view showing a schematic structure of a variable resistance memory element 202 according to yet another embodiment.

[0098] The variable resistance memory element 202 according to this embodiment differs from the variable resistance memory element 201 of FIG. 11 in that the variable resistance layer 232 has a four-layer structure including a first layer 11, a second layer 12, a third layer 13 and a fourth layer 14, but the remaining configuration is substantially similar.

[0099] Two or more of the first substance, second substance, third substance, and fourth substance contained in the first layer 11, the second layer 12, the third layer 13, and the fourth layer 14, respectively, have different valences. In addition, adjacent layers are made of substances having different valences. That is, the first substance and the second substance have different valences, the second substance and the third substance have different valences, and the third substance and the fourth substance have different valences. The first substance and the third substance may be the same substance. The second substance and the fourth substance may be the same substance.

[0100] The variable resistance layer 232 of the variable resistance memory element 202 according to this embodiment, like the variable resistance layer 132 described in FIG. 5, is configured such that multiple interfaces between materials with different valences are generated, and the materials of the first layer 11, second layer 12, third layer 13, and fourth layer 14 are set so that the valence difference at each interface is as large as possible.

[0101] By setting up such a material, the valence difference at the interface between the layers is expressed as large as possible, and oxygen vacancies can be formed more smoothly by atomic replacement.

[0102] The variable resistance layer 232 has a structure in which interfaces of materials with different valences are further added, and the number of interfaces where conductive filaments are formed by oxygen vacancies increases, so that the resistance change range becomes larger.

[0103] Fig. 13 is a cross-sectional view showing a schematic structure of a variable resistance memory element according to yet another embodiment, and Fig. 14 is a perspective view showing a schematic structure of a memory string included in the variable resistance memory element of Fig. 13. Fig. 15 is an equivalent circuit diagram of the variable resistance memory element of Fig. 13.

[0104] The variable resistance memory device 500 according to the present embodiment is a vertical NAND (VNAND) memory in which a plurality of memory cells MC having a variable resistance material are vertically arrayed.

[0105] A detailed configuration of the variable resistance memory device 500 will be described with reference to FIGS.

[0106] First, referring to FIG. 13, a plurality of cell strings CS are formed on a substrate 520 .

[0107] The substrate 520 may include a silicon material doped with a first type impurity. For example, the substrate 520 may include a silicon material doped with a p-type impurity. For example, the substrate 520 may be a p-type well (e.g., a pocket p-well). In the following, it is assumed that the substrate 520 is p-type silicon. However, the substrate 520 is not limited to p-type silicon.

[0108] A doping region 525 is provided on the substrate 520. For example, the doping region 525 may have a second type different from the substrate 520. For example, the doping region 525 may have an n-type. In the following, it is assumed that the doping region 525 is an n-type. However, the doping region 525 is not limited to an n-type. Such a doping region 525 may be connected to a common source line CSL.

[0109] The cell strings CS may be arranged in a matrix of k*n cells, and may be named CSij (1≦i≦k, 1≦j≦n) according to the position of each row and column, as shown in the circuit diagram of Fig. 15. Each cell string CSij is connected to a bit line BL, a string selection line SSL, a word line WL, and a common source line CSL.

[0110] Each cell string CSij includes a memory cell MC and a string selection transistor SST. The memory cells MC and the string selection transistor SST of each cell string CSij may be stacked in the height direction.

[0111] A row of a plurality of cell strings CS is connected to different string selection lines SSL1 to SSLk, respectively. For example, the string selection transistors SSTs of the cell strings CS11 to CS1n are commonly connected to the string selection line SSL1. The string selection transistors SSTs of the cell strings CSk1 to CSkn are commonly connected to the string selection line SSLk.

[0112] A column of a plurality of cell strings CS is connected to different bit lines BL1 to BLn, respectively. For example, the memory cells and string selection transistors SST of the cell strings CS11 to CSk1 are commonly connected to the bit line BL1, and the memory cells MC and string selection transistors SST of the cell strings CS1n to CSkn are commonly connected to the bit line BLn.

[0113] The rows of the cell strings CS are respectively connected to different common source lines CSL1 to CSLk, for example, the string selection transistors SST of the cell strings CS11 to CS1n are commonly connected to the common source line CSL1, and the string selection transistors SST of the cell strings CSk1 to CSkn are commonly connected to the common source line CSLk.

[0114] The memory cells MC located at the same height from the substrate 520 or the string selection transistor SST are commonly connected to one word line WL, and the memory cells MC located at different heights are respectively connected to different word lines WL1 to WLm.

[0115] The circuit structure shown in FIG. 15 is illustrative. For example, the number of rows of cell strings CS is increased or decreased. As the number of rows of cell strings CS is changed, the number of string selection lines connected to the rows of cell strings CS and the number of cell strings CS connected to one bit line are also changed. As the number of rows of cell strings CS is changed, the number of common source lines connected to the rows of cell strings CS is also changed.

[0116] The number of columns of the cell strings CS may also be increased or decreased. As the number of columns of the cell strings CS is changed, the number of bit lines connected to the columns of the cell strings CS and the number of cell strings CS connected to one string selection line are also changed.

[0117] The height of the cell strings CS may also be increased or decreased. For example, the number of memory cells MC stacked in each cell string CS may be increased or decreased. As the number of memory cells MC stacked in each cell string CS is changed, the number of word lines WL may also be changed. For example, the number of string selection transistors provided in each cell string CS may be increased. As the number of string selection transistors provided in each cell string CS is changed, the number of string selection lines or common source lines may also be changed. If the number of string selection transistors is increased, the string selection transistors may be stacked in the same form as the memory cells MC.

[0118] Exemplarily, writing and reading may be performed in units of rows of cell strings CS. The cell strings CS may be selected in units of rows by the common source line CSL, and the cell strings CS may be selected in units of rows by the string selection line SSL. Furthermore, a voltage may be applied to at least two common source lines as a unit to the common source line CSL. A voltage may be applied to the entire common source line CSL as a unit.

[0119] In a selected row of the cell string CS, writing and reading may be performed in units of a page. A page is also a row of memory cells connected to one word line WL. In a selected row of the cell string CS, memory cells may be selected in units of a page by the word line WL.

[0120] 13, the cell string CS includes a cylindrical pillar PL, and a plurality of gates 560 and a plurality of insulators 570 surrounding the cylindrical pillar PL in a ring shape. The plurality of gates 560 and the plurality of insulators 570 may be stacked to cross each other along the vertical direction (Z direction).

[0121] The gates 560 may be made of a metal material or a highly doped silicon material, and each gate 560 is connected to one of a word line WL and a string select line SSL.

[0122] Insulator 570 may be made of a variety of insulating materials, such as silicon oxide, silicon nitride, and the like.

[0123] The pillar PL may be composed of multiple layers. The outermost layer of the pillar PL may be a gate insulating layer 550. For example, the gate insulating layer 550 may be made of various insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The gate insulating layer 550 is conformally deposited on the pillar PL.

[0124] A channel layer 540 is conformally deposited along the inner surface of the gate insulating layer 550. The channel layer 540 may include a semiconductor material doped to a first type. The channel layer 540 may include a silicon material doped to the same type as the substrate 520, for example, if the substrate 520 includes a silicon material doped to a p-type, the channel layer 540 also includes a silicon material doped to a p-type. Alternatively, the channel layer 540 may include a material such as Ge, IGZO, GaAs, etc.

[0125] The variable resistance layer 530 is disposed along the inner surface of the channel layer 540. The variable resistance layer 530 is disposed in contact with the channel layer 540 and is conformally deposited on the channel layer 540.

[0126] The variable resistance layer 530 is a layer that changes to a high resistance state or a low resistance state depending on an applied voltage, and includes a first layer 11, a second layer 12, and a third layer 13 made of oxides having different valences.

[0127] The first layer 11, the second layer 12, and the third layer 13 of the variable resistance layer 530 include an oxide of at least one element selected from the group including zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), praseodymium (Pr), and silicon (Si). An oxide having a band gap energy of 2 eV or more is used as the material of each of the first layer 11, the second layer 12, and the third layer 13. For example, Rb 2 O,TiO 2 ,BaO,ZrO 2 ,CaO,HfO 2 ,SrO,Sc 2 O 3 ,MgO,Li 2 O,Al 2 O 3 ,SiO 2 and BeO may be used.

[0128] The resistance variable layer 530 has a structure in which two or more materials having different valences are laminated, and adjacent two layers among the first layer 11, the second layer 12, and the third layer 13 may each include a material having a different valence. As described in the resistance variable layer 131 of Fig. 3 and the resistance variable layer 231 of Fig. 11, the first material of the first layer 11, the second material of the second layer 12, and the third material of the third layer 13 are set in the resistance variable layer 530 so that oxygen vacancies are sufficiently generated by atomic replacement at each interface. As a result, the resistance variable memory element 500 can have low set voltage and reset voltage characteristics.

[0129] Although the variable resistance layer 530 is illustrated as having a three-layer structure, it is not limited thereto, and may be formed of two or more layers in which layers having a predetermined valence difference are arranged adjacent to each other so that one or more interfaces with different valences are generated.

[0130] The channel layer 540 and the variable resistance layer 530 are in contact with a doped region 525, a common source region.

[0131] A drain 580 is provided on the pillar PL. The drain 580 may comprise a silicon material doped to a second type. For example, the drain 580 may comprise a silicon material doped to an n-type.

[0132] A bit line 590 is provided on the drain 580. The drain 580 and the bit line 590 may be connected via a contact plug.

[0133] Each gate 560 and the gate insulating layer 550, channel layer 540, and variable resistance layer 530 at a position facing the gate 560 in the horizontal direction (X direction) constitute a memory cell MC. That is, the memory cell MC has a circuit structure in which a transistor including the gate 560, gate insulating layer 550, and channel layer 540 and a variable resistance formed by the variable resistance layer 530 are connected in parallel.

[0134] Such parallel connection structures are continuously arranged in the vertical direction (Z direction) to form a cell string CS. Furthermore, both ends of the cell string CS are connected to a common source line CSL and a bit line BL as shown in the circuit diagram of Figure 15. When voltages are applied to the common source line CSL and the bit line BL, a program, read, and erase process is performed on a plurality of memory cells MC.

[0135] For example, when a memory cell MC to be recorded is selected, the gate voltage value of the selected cell is adjusted so that a channel is not formed in the selected cell, i.e., the channel is turned off, and the gate voltage value of the unselected cells is adjusted so that the channel is turned on. As a result, a current path due to the voltage applied to the common source line CSL and the bit line BL passes through the region of the variable resistance layer 530 of the selected memory cell MC, and at this time, the applied voltage is set to the set voltage V set or reset voltage V reset , creating a low resistance state or a high resistance state, and a desired piece of information, 1 or 0, can be recorded in the selected memory cell MC.

[0136] Similarly, in a read operation, a selected cell is read. That is, the gate voltage applied to each gate electrode 560 is adjusted so that the selected memory cell MC is in a channel-off state and the unselected memory cell is in a channel-on state, and then the applied voltage V between the common source line CSL and the bit line BL is adjusted. read By measuring the current flowing through the cell MC, the cell state (1 or 0) can be confirmed.

[0137] As described above, the variable resistance memory device 500 according to the present embodiment uses the variable resistance layer 530 having a structure in which a conductive filament is easily formed by oxygen vacancies to form memory cells MC, and then arrays the memory cells to implement a memory device, so that the variable resistance layer 530 can be formed thinner and have a lower operating voltage than memory devices having existing structures, for example, a phase-change material-based or charge trap-based memory device. Such a variable resistance memory device 500 can increase integration density and implement low power by solving the scaling issue between memory cells in next-generation VNAND.

[0138] The variable resistance memory device 500 according to the present disclosure may be implemented as a memory system and / or a memory block in the form of a chip, and may be used as a neuromorphic computing platform or may be used to configure a neural network.

[0139] FIG. 16 is a block diagram illustrating a memory system according to an embodiment.

[0140] 16, memory system 1600 includes a memory controller 1601 and a memory device 1602. Memory controller 1601 performs control operations on memory device 1602, for example, memory controller 1601 provides address ADD to memory device 1602 and commands CMD for performing programming (or write), read and / or erase operations on memory device 1602. Data for programming operations and read data may also be transferred between memory controller 1601 and memory device 1602.

[0141] The memory device 1602 includes a memory cell array 1610 and a voltage generator 1620. The memory cell array 1610 includes a plurality of memory cells arranged at the intersections of a plurality of word lines and a plurality of bit lines. The memory cell array 1610 includes non-volatile memory cells according to the embodiments of Figures 1 to 5 and 8 to 15.

[0142] The memory controller 1601 includes a processing circuit, such as hardware including logic circuits; a combination of hardware / software, such as a processor running software; or a combination thereof. For example, the processing circuit may be, more specifically, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc., but is not limited thereto. The memory controller 1601 is operable in response to a request from a host (not shown) and configured to access the memory device 1602 and control the control operations described above (e.g., for the write / read operations of FIG. 10 ) to convert the memory controller 1601 into a special-purpose controller. The memory controller 1601 generates addresses ADD and commands CMD for performing programming / read / erase operations on the memory cell array 1610. Also, in response to instructions from the memory controller 1601, a voltage generator 1620 (e.g., a power circuit) generates voltage control signals to control the voltage levels of the word lines in the memory cell array 1610 for data programming or data reading.

[0143] The memory controller 1601 also performs a decision operation on data read from the non-volatile memory device 1602. For example, the number of ON cells and / or the number of OFF cells are determined from the data read from the memory cells. The memory device 1602 provides a pass / fail signal P / F to the memory controller 1601 according to the read result of the read data. The memory controller 1601 controls the write and read operations of the memory cell array 1610 by referring to the pass / fail signal P / F.

[0144] FIG. 17 is a block diagram illustrating a neuromorphic device and an external device coupled thereto according to an embodiment.

[0145] 17, a neuromorphic device 1700 includes a processing circuit 1710 and / or a memory 1720. The neuromorphic device 1700 includes a memory based on the embodiments of FIGS.

[0146] In some exemplary embodiments, the processing circuitry 1710 may be configured to control functions for driving the neuromorphic device 1700. For example, the processing circuitry 1710 may be configured to control the neuromorphic device 1700 by executing a program stored in the memory 1720. In some exemplary embodiments, the processing circuitry 1710 may include hardware, such as logic circuits, a combination of hardware / software, such as a processor executing software, or a combination thereof. For example, a processor may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1700, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, an FPGA, a SoC, a programmable logic unit, a microprocessor, an ASIC, etc. In some exemplary embodiments, the processing circuitry 1710 may be configured to read / write various data from / to the external device 1730 and / or execute the neuromorphic device 1700 using the data read / written. In some embodiments, the external device 1730 may include an external memory and / or a sensor array having an image sensor (eg, a CMOS image sensor circuit).

[0147] In some embodiments, the neuromorphic device of Figure 17 is applied to a machine learning system, which can utilize various artificial neural network structures and processing models, such as a convolutional neural network (CNN), a deconvolutional neural network, a recurrent neural network (RNN) optionally including a long short-term memory (LSTM) unit and / or a gated recurrent unit (GRU), a stacked neural network (SNN), a state-space dynamic neural network (SSDNN), a deep faith network (DBN), a generative adversarial network (GAN), and / or a restricted Boltzmann machine (RBM).

[0148] Alternatively or additionally, such machine learning systems may include other forms of machine learning models, e.g., linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, expert systems, and / or combinations thereof including ensembles such as random forests. Such machine learning models may be used to provide various services and / or applications performed by the electronic device, e.g., image classification services, user authentication services based on biometric or biometric data, Advanced Driver Assistance System (ADAS) services, voice assistant services, automatic speech recognition (ASR) services, etc.

[0149] The variable resistance memory device described above has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and those skilled in the art will appreciate that various modifications and equivalent embodiments are possible therefrom. Although many specific details are described in the above description, they should be construed as examples of specific embodiments rather than limiting the scope of the invention. Therefore, the scope of the present invention should be determined not by the described embodiments, but by the technical ideas described in the claims. [Industrial Applicability]

[0150] The present invention is applicable, for example, to technical fields related to memory systems. [Explanation of symbols]

[0151] 11 1st layer 12 2nd layer 100,101,102,200,201,202,500 Variable resistance memory element 130,131,132,230,231,232,530 Variable resistance layer 210,510,270,570 Insulating layer 240,540 Channel Layer 250,550 Gate insulation layer 260,560 Gates CS Cell String E1 First conductive element E2 Second conductive element MC memory cell V o Oxygen vacancy

Claims

1. a variable resistance layer including a first layer made of a first material, a second layer disposed on the first layer and made of a second material having a valence different from that of the first material, and a third layer disposed on the second layer and made of a third material having a valence different from that of the second material; a first conductive element and a second conductive element are disposed in the variable resistance layer, the first conductive element and the second conductive element being spaced apart from each other and in contact with the third layer to form a current path in a direction perpendicular to a stacking direction of the first layer and the second layer; The first material and the third material include hafnium oxide, and the second material includes aluminum oxide.

2. The resistance variable memory element of claim 1 , wherein a valence difference between the first material and the second material is 1 or more.

3. The density difference between the first material and the second material is 1 g / cm ３ The variable resistance memory element according to claim 2 , wherein

4. 2. The variable resistance memory element of claim 1, wherein the variable resistance layer further includes a fourth layer made of a fourth material having a valence different from a valence of the third material, and the third layer, the second layer, the first layer, and the fourth layer are stacked in this order.

5. The resistance variable memory element of claim 4 , wherein the second material and the fourth material are the same material.

6. The variable resistance memory element of claim 1 , wherein the first material and the second material are oxides having a band gap energy of 2 eV or more.

7. A support layer made of an insulating material; disposed on the support layer, a variable resistance layer including a first layer made of a first material and a second layer disposed on the first layer and made of a second material having a different valence than the first material; a channel layer disposed on the variable resistance layer; a gate insulating layer formed on the channel layer; a plurality of gate electrodes spaced apart from each other and disposed on the gate insulating layer.

8. The resistance variable memory element of claim 7 , wherein a valence difference between the first material and the second material is 1 or more.

9. The density difference between the first material and the second material is 1 g / cm ３ The variable resistance memory element of claim 8 .

10. The variable resistance layer is The resistance variable memory element of claim 7 , further comprising a third layer disposed on the second layer and made of a third material having a valence different from a valence of the second material.

11. The resistance variable memory element of claim 10 , wherein the first layer and the third layer are made of the same material.

12. The variable resistance layer is The resistance variable memory element of claim 10 , further comprising a fourth layer disposed on the third layer and made of a fourth material having a valence different from a valence of the third material.

13. The resistance variable memory element of claim 12, wherein the first material and the third material are the same material.

14. The resistance variable memory element of claim 12, wherein the second material and the fourth material are the same material.

15. The variable resistance memory element according to claim 7 , wherein the first layer and the second layer each have a thickness of 10 nm or less.

16. The variable resistance memory element of claim 7 , wherein the first material and the second material are oxides having a band gap energy of 2 eV or more.

17. The first substance and the second substance are each Rb ２ O, TiO ２ , BaO, ZrO ２ , CaO, HfO ２ , SrO, Sc ２ O ３ , MgO, Li ２ O, Al ２ O ３ , SiO ２ , BeO, Sc ２ O ３ , Nb ２ O ５ , NiO, Ta ２ O ５ , W.O. ３ , V ２ O ５ , La ２ O ３ , Gd ２ O ３ , CuO, MoO ３ , Cr ２ O ３ and MnO ２ 8. The variable resistance memory device of claim 7, wherein the variable resistance memory device is any one of:

18. a variable resistance layer including a first layer made of a first material, a second layer made of a second material having a valence different from that of the first material, an interface between the first layer and the second layer, the interface including a plurality of oxygen vacancies, and a third layer made of a third material having a valence different from that of the second material, the first layer, the second layer, and the third layer being stacked in this order; a first conductive element in contact with the first layer and coupled to a first region of the variable resistance layer; a second conductive element in contact with the first layer, coupled to a second region of the variable resistance layer, and spaced apart from the first conductive element; The first material and the third material include hafnium oxide, and the second material includes aluminum oxide.

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