Semiconductor Device

Abstract

To provide a semiconductor device in which accuracy of alignment between a semiconductor chip and a mounting pad can be improved.SOLUTION: A semiconductor device comprises: a semiconductor chip; and a metal plate. The semiconductor chip has a first surface, a second surface at an opposite side of the first surface, four side surfaces connecting between the first surface and the second surface, corners in which two of the four side surfaces contact with each other, and four sides in which the four side surfaces contact with the second surface. The semiconductor chip has a first electrode and a second electrode at the first surface side, and controls electric current flowing between the first electrode and the second electrode through a conductive layer provided on the second surface. The metal plate is connected to the second surface side of the semiconductor chip, and has a third surface connected to the second surface and a fourth surface at an opposite side of the third surface. The metal plate has a through-hole or a notch that is connected to the third surface from the fourth surface.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] In so-called flip chip bonding, in which electrodes provided on the front side of a semiconductor chip are connected to mounting pads on a mounting substrate, the semiconductor chip is aligned on the mounting pads of the mounting substrate with the back side of the semiconductor chip as a reference. However, in a semiconductor device having a structure in which a metal plate is connected to the back side of the semiconductor chip, it becomes difficult to align the semiconductor chip with the mounting pads of the mounting substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-112153 A Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device capable of improving the alignment accuracy between a semiconductor chip and a mounting pad. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a semiconductor chip and a metal plate. The semiconductor chip has a first surface, a second surface opposite to the first surface, four side surfaces connecting the first surface and the second surface, a corner where two of the four side surfaces meet, and four sides where the four side surfaces meet the second surface. The semiconductor chip has first and second electrodes provided on the first surface side and a conductive layer provided on the second surface, and controls a current flowing between the first electrode and the second electrode via the conductive layer. The metal plate is connected to the second surface side of the semiconductor chip, and has a third surface connected to the second surface of the semiconductor chip, and a fourth surface opposite to the third surface. The metal plate has a through hole or a notch connecting the fourth surface to the third surface. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment; [Diagram 2] 1A to 1C are schematic plan views showing a manufacturing process of a semiconductor device according to an embodiment. [Diagram 3] 5A to 5C are schematic cross-sectional views showing a mounting process of the semiconductor device according to the embodiment. [Figure 4] 1 is a schematic plan view showing a semiconductor device according to an embodiment; [Diagram 5] FIG. 11 is a schematic plan view showing a semiconductor device according to a modified example of the embodiment. [Figure 6] FIG. 11 is another schematic plan view showing a semiconductor device according to a modified example of the embodiment. [Figure 7] FIG. 11 is a schematic diagram showing a semiconductor device according to a second modified example of the embodiment. [Figure 8] FIG. 13 is a schematic plan view showing a semiconductor device according to a third modified example of the embodiment. [Figure 9] FIG. 13 is a schematic plan view showing a semiconductor device according to a fourth modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. The same parts in the drawings are given the same numbers, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones. Even when the same parts are shown, the dimensions and ratios of each part may be different depending on the drawing.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be described as upward and the opposite direction as downward.

[0009] 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment of the present invention, in which the semiconductor device 1 is mounted on a circuit board 30. As shown in FIG.

[0010] The semiconductor device 1 includes a semiconductor chip 10 and a metal plate 20. The semiconductor chip 10 has a first surface 1s and a second surface 2s. The second surface 2s is located opposite the first surface 1s. The metal plate 20 is connected to the second surface 2s of the semiconductor chip 10. The metal plate 20 includes, for example, copper.

[0011] The semiconductor chip 10 includes a semiconductor portion 11, a conductive layer 13, a first electrode 15a, and a second electrode 15b. The first electrode 15a and the second electrode 15b are provided on the first surface 1s side. The conductive layer 13 is provided on the second surface 2s. The semiconductor portion 11 is, for example, silicon. The conductive layer 13 is, for example, a metal layer containing nickel (Ni), titanium (Ti), or the like. The first electrode 15a and the second electrode 15b include, for example, aluminum (Al), or the like.

[0012] The semiconductor chip 10 further includes MOS gate structures 17a and 17b. The MOS gate structure 17a is provided between the semiconductor portion 11 and the first electrode 15a. The MOS gate structure 17b is provided between the semiconductor portion 11 and the second electrode 15b. The MOS gate structures 17a and 17b control a current flowing between the first electrode 15a and the second electrode 15b through the semiconductor portion 11 and the conductive layer 13.

[0013] The metal plate 20 includes a third surface 3s and a fourth surface 4s. The third surface 3s is connected to the conductive layer 13 of the semiconductor chip 10 via a connection member 23. The connection member 23 is, for example, a solder material or a conductive paste. The fourth surface 4s is located on the opposite side to the third surface 3s. The metal plate 20 further has a through hole 25 that communicates from the fourth surface 4s to the third surface 3s.

[0014] In the semiconductor device 1, in order to reduce the on-resistance between the first electrode 15a and the second electrode 15b, it is preferable to reduce the thickness of the semiconductor portion 11 in the direction from the first surface 1s to the second surface 2s (hereinafter, Z direction). This increases the current component flowing through the conductive layer 13, and the on-resistance between the first electrode 15a and the second electrode 15b can be reduced. However, when the thickness of the semiconductor portion 11 is reduced, warping is likely to occur in the semiconductor chip 10. In addition, the mechanical strength of the semiconductor chip 10 is also reduced. For this reason, it is preferable to prevent warping and improve the mechanical strength by connecting a metal plate 20 to the second surface 2s side of the semiconductor chip 10.

[0015] 1, the semiconductor device 1 is mounted such that a first surface 1s of the semiconductor chip 10 faces a circuit board 30. The circuit board 30 has, for example, mounting pads 33a and 33b. The first electrode 15a is connected to the mounting pad 33a via a connecting member 19a. The second electrode 15b is connected to the mounting pad 33b via a connecting member 19b. The connecting members 19a and 19b are, for example, solder materials.

[0016] 2(a) and (b) are schematic plan views showing a manufacturing process of the semiconductor device 1 according to the embodiment.

[0017] As shown in Fig. 2(a), a plurality of semiconductor chips 10 are mounted on a frame 100. The frame 100 includes metal plates 20 interconnected via a plurality of leads. Each of the metal plates 20 has a through hole 25. Each of the semiconductor chips 10 is mounted on the metal plates 20 via a connecting member 23 (see Fig. 1).

[0018] When a solder material is used as the connection member 23, for example, the semiconductor chip 10 is mounted on the metal plate 20 after cream solder material is supplied onto the metal plate 20. The semiconductor chip 10 is placed so as to be in close contact with the metal plate 20 via the solder material. The solder material is then melted in an electric furnace set to a predetermined temperature, and then cooled outside the electric furnace. This connects the semiconductor chip 10 to the metal plate 20.

[0019] Furthermore, when a conductive paste is used as the connection member 23, for example, the semiconductor chip 10 is mounted on the metal plate 20 after the conductive paste is supplied onto the metal plate 20. The semiconductor chip is placed so as to be in close contact with the metal plate 20 via the conductive paste. Thereafter, the conductive paste is hardened in an oven set at a predetermined temperature, and the semiconductor chip 10 is connected to the metal plate 20.

[0020] 2(b), the leads connecting the adjacent metal plates 20 are cut to separate the multiple semiconductor devices 1. The leads of the frame 100 are cut using, for example, a dicing blade.

[0021] 3(a) and (b) are schematic cross-sectional views showing a mounting process of the semiconductor device 1 according to the embodiment. The semiconductor device 1 is flip-chip bonded onto a circuit board 30.

[0022] 3(a), the semiconductor device 1 is aligned above the mounting pads 33a and 33b of the circuit board 30. The circuit board 30 is heated to a predetermined temperature. Meanwhile, the connection members 19a and 19b are provided on the first electrode 15a and the second electrode 15b. The connection members 19a and 19b are provided on the first electrode 15a and the second electrode 15b, respectively, in the final stage of the manufacturing process of the semiconductor chip 10, for example.

[0023] 3(b), the semiconductor device 1 is pressure-bonded to a circuit board 30. The first electrode 15a is connected to a mounting pad 33a via a connecting member 19a. The second electrode 15b is connected to a mounting pad 33b via a connecting member 19b.

[0024] As shown in FIG. 3(a), the size LM of the metal plate 20 in the X direction is larger than the size LC of the semiconductor chip 10 in the X direction. The same is true for the size of the metal plate 20 in the Y direction (see FIG. 2(b)). For example, if the metal plate 20 does not have a through hole 25, the semiconductor chip 10 cannot be seen from the fourth surface 4s side of the metal plate 20. Therefore, the semiconductor device 1 is aligned so that the outer edge of the metal plate 20 coincides with the alignment pattern on the circuit board 30. For this reason, if the accuracy of the relative position between the semiconductor chip 10 and the metal plate 20 is lower than the alignment accuracy required between the first electrode 15a and the mount pad 33a and between the second electrode 15b and the mount pad 33b, there are cases where the first electrode 15a and the second electrode 15b cannot be properly connected to the mount pads 33a and 33b. In other words, a positional deviation of the semiconductor chip 10 with respect to the circuit board 30 occurs.

[0025] 4(a) and (b) are schematic plan views showing the semiconductor device 1 according to the embodiment. 4(a) and (b) show the semiconductor device 1 as viewed from the fourth surface 4s side of the metal plate 20.

[0026] The first surface 1s and the second surface 2s of the semiconductor chip 10 have, for example, a square shape (see FIG. 2(b)). The semiconductor chip 10 has four side surfaces 10s (see FIG. 1) that are connected to the first surface 1s and the second surface 2s. The planar shape of the metal plate 20 is, for example, a square (see FIG. 2(b)).

[0027] As shown in FIG. 4(a), the metal plate 20 has through holes 25 provided at each of the four corners. The semiconductor chip 10 has a corner 10c where two of the four side surfaces 10s are connected. The metal plate 20 is provided so that the corner 10c of the semiconductor chip 10 can be seen from the fourth surface 4s side through the through holes 25. This allows the semiconductor chip 10 to be directly aligned with the circuit board 30 when aligning the semiconductor device 1 above the circuit board 30 (see FIG. 3(a)). This makes it possible to prevent the semiconductor chip 10 from being misaligned with respect to the circuit board 30.

[0028] 4(b), the metal plate 20 has, for example, a notch 27 provided at each of the four corners. In this way, the notch 27 may be provided instead of the through hole 25. The metal plate 20 is provided so that the corners 10c of the semiconductor chip 10 can be visually observed from the fourth surface 4s side through the notch 27. This makes it possible to prevent the semiconductor chip 10 from being misaligned with respect to the circuit board 30.

[0029] 5(a) to 5(d) are schematic plan views showing a semiconductor device 1 according to a modified example of the embodiment, as viewed from the fourth surface 4s side of the metal plate 20.

[0030] 5(a), the metal plate 20 has through holes 25 provided at three of the four corners of the fourth surface 4s. The metal plate 20 is provided so that three of the four corners 10c of the semiconductor chip 10 can be seen from the fourth surface 4s side through the through holes 25.

[0031] 5(b), the metal plate 20 has notches 27 provided in place of the through holes 25 at three of the four corners of the fourth surface 4s. The metal plate 20 is provided so that three of the four corners 10c of the semiconductor chip 10 can be seen from the fourth surface 4s side through the notches 27.

[0032] 5(c), the metal plate 20 has through holes 25 provided at two of the four corners of the fourth surface 4s. The metal plate 20 is provided so that two of the four corners 10c of the semiconductor chip 10 can be seen from the fourth surface 4s side through the through holes 25.

[0033] 5(d), the metal plate 20 has notches 27 provided in place of the through holes 25 at two of the four corners of the fourth surface 4s. The metal plate 20 is provided so that two of the four corners 10c of the semiconductor chip 10 can be seen from the fourth surface 4s side through the notches 27.

[0034] 6(a) and (b) are another schematic plan view showing a semiconductor device 1 according to a modified example of the embodiment. Figures 6(a) and (b) show the semiconductor device 1 as viewed from the fourth surface 4s side of the metal plate 20. Furthermore, a plurality of first electrodes 15a, a plurality of second electrodes 15b, a control pad 18a, and a control pad 18b provided on the first surface 1a side of the semiconductor chip 10 are shown by dashed lines.

[0035] The control pads 18a and 18b are electrically connected to the gate electrodes of the MOS gate structures 17a and 17b, respectively. The semiconductor device 1 controls the current flowing between the first electrode 15a and the second electrode 15b by a gate signal supplied from an external gate control circuit to the MOS gate structures 17a and 17b via the control pads 18a and 18b.

[0036] 6(a), the metal plate 20 has notches 27 provided at three of the four corners of the fourth surface 4s. The metal plate 20 is provided so that three of the four corners 10c of the semiconductor chip 10 can be seen from the fourth surface 4s side through the notches 27. The arrangement of the notches 27 in the metal plate 20 is rotationally asymmetric.

[0037] 6(b) is a plan view showing a state in which the semiconductor device 1 is rotated 90 degrees clockwise in a plane parallel to the fourth surface 4s of the metal plate 20. Since the arrangement of the notches 27 of the metal plate 20 is rotationally asymmetric, by checking the positions of the three notches 27, it can be known that the arrangement direction of the first electrode 15a, the second electrode 15b, the control pad 18a, and the control pad 18b on the first surface 1s side of the semiconductor chip 10 has been rotated 90 degrees.

[0038] 7(a) to (c) are schematic diagrams showing a semiconductor device 2 according to a second modified example of the embodiment. Fig. 7(a) is a plan view showing a third surface 3s of a metal plate 20. Figs. 7(b) and (c) are partial cross-sectional views showing a cross section parallel to the XZ plane.

[0039] As shown in FIG. 7(a), the metal plate 20 has, for example, four through holes 25. The four through holes 25 are provided at the four corners of the third surface 3s, respectively. The metal plate 20 further includes a groove 29 provided on the third surface 3s side. The groove 29 is provided at a position corresponding to the four sides of the semiconductor chip 10. That is, when the semiconductor chip 10 is mounted on the metal plate 20 (see FIG. 2(a)), the groove 29 is provided so as to extend along the outer edge of the semiconductor chip 10. This allows an excess portion of the connection member 23 to be accommodated inside the groove 29, and prevents the connection member 23 from spreading toward the outer periphery. The groove 29 is provided so as to connect to the through hole 25, for example.

[0040] 7(b), the semiconductor chip 10 may include burrs 13p in the conductive layer 13. The conductive layer 13 is preferably provided thick in order to reduce the on-resistance between the first electrode 15a and the second electrode 15b. For this reason, when the semiconductor chip 10 is divided into individual pieces using a dicer, burrs 13p may be formed along the outer edge of the conductive layer 13.

[0041] Such burrs 13p are formed so as to protrude in a direction perpendicular to the second surface 2s of the semiconductor chip 10. For this reason, the semiconductor chip 10 is mounted on the metal plate 20 at an angle, which may cause problems such as the semiconductor chip 10 not being in close contact with the metal plate 20.

[0042] In the semiconductor device 2, the grooves 29 are provided at positions corresponding to the four sides of the semiconductor chip 10, so that the tips of the burrs 13p can be accommodated in the grooves 29, and the semiconductor chip 10 can be prevented from being mounted at an angle. This can improve the adhesion between the semiconductor chip 10 and the metal plate 20 via the connection members 23.

[0043] 7(c), the metal plate 20 can be provided so that the thickness Tm1 of the outer periphery located outside the groove 29 is thinner than the thickness Tm2 in the Z direction of the portion located inside the groove 29. This can prevent the connection member 23 from creeping up to the side surface of the semiconductor chip 10.

[0044] 8(a) to (d) are schematic diagrams showing a semiconductor device 3 according to a third modified example of the embodiment. Fig. 8(a) to (d) show the semiconductor device 3 as viewed from the fourth surface 4s side of the metal plate 20.

[0045] 8(a), the metal plate 20 has four through holes 25, which are provided in positions close to the four sides of the fourth surface 4s. The metal plate 20 is provided so that a portion of each of the four sides of the semiconductor chip 10 can be seen from the fourth surface 4s side through the through holes 25. This allows the semiconductor chip 10 to be directly aligned with the circuit board 30 when aligning the semiconductor device 3 above the circuit board 30. This prevents the semiconductor chip 10 from being misaligned with respect to the circuit board 30.

[0046] 8(b), the metal plate 20 may be provided to have two through holes 25. The through holes 25 are provided at positions close to two of the four sides of the fourth surface 4s. The metal plate 20 is provided so that two of the four sides of the semiconductor chip 10 can be partially seen through the through holes 25. This makes it possible to prevent the semiconductor chip 10 from being misaligned with respect to the circuit board 30.

[0047] 8(c), the metal plate 20 may have four notches 27 instead of the through holes 25. The notches 27 are provided on the four sides of the fourth surface 4s, respectively. The metal plate 20 is provided so that a portion of each of the four sides of the semiconductor chip 10 can be seen from the fourth surface 4s side through the notches 27.

[0048] 8(d), the metal plate 20 may be provided to have two notches 27. The notches 27 are provided on two of the four sides of the fourth surface 4s. The metal plate 20 is provided so that two of the four sides of the semiconductor chip 10 can be partially seen through the notches 27.

[0049] 9(a) and (b) are schematic diagrams showing a semiconductor device 4 according to a fourth modified example of the embodiment. The semiconductor device 1 includes a metal plate 40 instead of the metal plate 20. Figs. 9(a) and (b) show the semiconductor device 4 as viewed from the fourth surface 4s side of the metal plate 40.

[0050] 9(a), the metal plate 40 includes, for example, four through holes 45. The four through holes 45 are provided at the four corners of the fourth surface 4s. The metal plate 40 is provided such that, at each of the through holes 45, one corner 10c of the semiconductor chip 10 and parts of two sides 10sd1 and 10sd2 connected thereto can be visually observed from the fourth surface 4s side.

[0051] The through-holes 45 are provided so as to extend along each of the two sides 10sd1 and 10sd2. In the fourth surface 4s, the through-holes 45 are provided so that the width Lop1 of the exposed portion of each side in a direction perpendicular to each side is narrower than the length Lop2 of the exposed portion in a direction along each side.

[0052] In this example, the outer edge of the semiconductor chip 10 can be seen more clearly on the fourth surface 4s side, which makes it easier to align the semiconductor chip 10 with the circuit board 30.

[0053] 9(b), a metal plate 50 may be used instead of the metal plate 40. The metal plate 50 includes, for example, four notches 57. The four notches 57 are provided at the four corners of the fourth surface 4s. The metal plate 50 is provided so that, in each of the notches 57, one corner 10c of the semiconductor chip 10 and parts of the two sides 10sd1 and 10sd2 connected thereto can be visually observed from the fourth surface 4s side.

[0054] A portion of the semiconductor chip 10 that can be seen through the cutout 57 has, for example, a length Ls1 in a direction along each side and a width Ls2 in a direction perpendicular to each side. The metal plate 50 is provided so that the width Ls2 is narrower than the length Ls1.

[0055] It should be noted that the above embodiment is not limited to the metal plates 40 and 50. For example, it is sufficient that at least one through hole 45 or notch 57 is provided on the fourth surface 4s, and the number is not limited to four.

[0056] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0057] 1, 2, 3, 4...semiconductor device, 1s...first surface, 2s...second surface, 3s...third surface, 4s...fourth surface, 10...semiconductor chip, 10c...corner, 10s...side surface, 10sd1, 10sd2...edge, 11...semiconductor portion, 13...conductive layer, 13p...burr, 15a...first electrode, 15b...second electrode, 17a, 17b...MOS gate structure, 18a, 18b...control pad, 19a, 19b, 23...connection member, 20, 40, 50...metal plate, 25, 45...through hole, 27, 57...notch, 29...groove, 30...circuit board, 33a, 33b...mounting pad, 100...frame

Claims

1. a semiconductor chip having a first surface, a second surface opposite to the first surface, four side surfaces connecting the first surface and the second surface, a corner where two of the four side surfaces meet, and four sides where the four side surfaces and the second surface meet, the semiconductor chip having a first electrode and a second electrode provided on the first surface side and a conductive layer provided on the second surface, the semiconductor chip controlling a current flowing between the first electrode and the second electrode via the conductive layer; a metal plate connected to the second surface side of the semiconductor chip, the metal plate having a third surface connected to the second surface of the semiconductor chip and a fourth surface opposite to the third surface, the metal plate having a through hole or a notch connecting the fourth surface to the third surface; Equipped with A semiconductor device in which the metal plate is configured so that at least two of the corners of the semiconductor chip, or a portion of each of at least two of the four sides, are visible from the fourth surface side through the through hole or the notch.

2. a semiconductor chip having a first surface, a second surface opposite to the first surface, four side surfaces connecting the first surface and the second surface, a corner where two of the four side surfaces meet, and four sides where the four side surfaces and the second surface meet, the semiconductor chip having a first electrode and a second electrode provided on the first surface side and a conductive layer provided on the second surface, the semiconductor chip controlling a current flowing between the first electrode and the second electrode via the conductive layer; a metal plate connected to the second surface side of the semiconductor chip, the metal plate having a third surface connected to the second surface of the semiconductor chip and a fourth surface opposite to the third surface, the metal plate having a through hole or a notch connecting the fourth surface to the third surface; Equipped with A semiconductor device, wherein the metal plate has two of the through holes or two of the notches through which two of the corners of the semiconductor chip can be seen, respectively.

3. a semiconductor chip having a first surface, a second surface opposite to the first surface, four side surfaces connecting the first surface and the second surface, a corner where two of the four side surfaces meet, and four sides where the four side surfaces and the second surface meet, the semiconductor chip having a first electrode and a second electrode provided on the first surface side and a conductive layer provided on the second surface, the semiconductor chip controlling a current flowing between the first electrode and the second electrode via the conductive layer; a metal plate connected to the second surface side of the semiconductor chip, the metal plate having a third surface connected to the second surface of the semiconductor chip and a fourth surface opposite to the third surface, the metal plate having a through hole or a notch connecting the fourth surface to the third surface; Equipped with A semiconductor device, wherein the metal plate has two through holes or two notches through which two of the four sides of the semiconductor chip are partially visible.

4. a semiconductor chip having a first surface, a second surface opposite to the first surface, four side surfaces connecting the first surface and the second surface, a corner where two of the four side surfaces meet, and four sides where the four side surfaces and the second surface meet, the semiconductor chip having a first electrode and a second electrode provided on the first surface side and a conductive layer provided on the second surface, the semiconductor chip controlling a current flowing between the first electrode and the second electrode via the conductive layer; a metal plate connected to the second surface side of the semiconductor chip, the metal plate having a third surface connected to the second surface of the semiconductor chip and a fourth surface opposite to the third surface, the metal plate having a through hole or a notch connecting the fourth surface to the third surface; Equipped with A semiconductor device in which the metal plate is arranged so that at least one corner of the semiconductor chip and two sides connected to at least one corner of the semiconductor chip are visible from the fourth surface side through the through hole or the notch.

5. 5. The semiconductor device according to claim 1, wherein the through holes or the cutouts are arranged in the fourth surface of the metal plate so as to be rotationally asymmetric.

6. 6. The semiconductor device according to claim 1, wherein the metal plate has grooves on the third surface side, the grooves being provided at positions corresponding to the four sides of the semiconductor chip.

Images