Semiconductor Device

Abstract

To easily avoid a decrease in a breakdown voltage due to avalanche breakdown while improving the breakdown voltage of an LDMOS transistor.SOLUTION: A semiconductor device (1) is set such that, in the distance (L1) in a direction along the top surface (2a) of a P-type semiconductor substrate (2) from a first reference position (P1) below the end facing the N-type drain region (8) of a P-type body region (4) to the end of a P-type diffusion region (3) and a distance (L2) in a direction along the upper surface (2a) of the P-type semiconductor substrate (2) from the second reference position (P2) below the end of the N-type drain region (8) on the STI structure (12) side to the end of the P-type diffusion region (3), the intensity of the electric field in a region (A) including the edge (5a) of the N-type drift region (5), and a region (B) between the edge of the P-type diffusion region (3) and the N-type drain region (8) of the P-type diffusion region (3) becomes 0.35 MV / cm or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a high-voltage transistor such as an LDMOS (Laterally Diffused MOS) transistor. [Background technology]

[0002] There are various types of high-voltage Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). For example, LDMOS transistors are devices that achieve both high voltage and low on-resistance, and have features such as fast switching speed and ease of use due to their voltage drive system. For these reasons, LDMOS transistors are used in switching regulators, various drivers, DC-DC converters, etc., taking advantage of these features, and are key devices in the fields of power and high voltage.

[0003] For this reason, LDMOS transistors are required to have low on-resistance to reduce losses when they are conductive, while ensuring a high breakdown voltage (breakdown voltage) when they are off. However, there is generally a trade-off between breakdown voltage and on-resistance, and increasing the breakdown voltage also increases the on-resistance. For this reason, development has been carried out for many years to find a way to achieve both high breakdown voltage and low on-resistance.

[0004] LDMOS transistors have a structure in which the drain region is extended laterally in order to alleviate the concentration of the electric field between the drain and gate and between the source and drain. When LDMOS is used with a large current, a high voltage is applied to the drain region, so the electric field is likely to concentrate at the gate end on the drain side and at the junction between the source and drain. Alleviating such electric field concentration is a useful technology for increasing the breakdown voltage of transistors.

[0005] For example, Patent Document 1 describes that for an N-type LDMOS transistor formed in an N-type diffusion region, a P-type diffusion region is disposed below a P-type body region. This reduces the concentration of the electric field in the region where the gate electrode overlaps the LOCOS oxide film. As a result, the breakdown voltage of the LDMOS transistor can be improved. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2009-059949 A Summary of the Invention [Problem to be solved by the invention]

[0007] In the LDMOS transistor structure disclosed in Patent Document 1, when the P-type diffusion region is extended to below the N-type drift region, the electric field strength between the P-type diffusion region and the N-type drain region becomes strong, which results in a problem of a decrease in breakdown voltage due to avalanche breakdown.

[0008] An object of one aspect of the present invention is to provide a semiconductor device that can easily prevent a decrease in the breakdown voltage caused by avalanche breakdown while improving the breakdown voltage of an LDMOS transistor. [Means for solving the problem]

[0009] In order to solve the above problems, a semiconductor device according to one aspect of the present invention includes a semiconductor substrate of a first conductivity type, a body region of the first conductivity type formed in a surface layer of the semiconductor substrate, a source region of a second conductivity type formed so as to be in contact with the body region, a drain region of the second conductivity type formed at a distance from the body region, a gate electrode formed between the source region and the drain region, a drift region of the second conductivity type formed in the surface layer of the semiconductor substrate so as to be in contact with the drain region and having an end between the body region and the drain region, a buried oxide film overlapping at least an end of the gate electrode on the drain region side and formed so as to be buried from an upper surface of the semiconductor substrate, thereby relieving an electric field, and a semiconductor region of the first conductivity type formed at a position deeper than the body region so as to be in contact with a bottom surface of the body region, the semiconductor region being formed so as to extend in a direction along the upper surface of the semiconductor substrate, The position of an end of the semiconductor region that defines the range in which the semiconductor region extends is a first distance in a direction along the upper surface of the semiconductor substrate from a first reference position below an end of the body region facing the drain region to an end of the semiconductor region, and a second distance in a direction along the upper surface of the semiconductor substrate from a second reference position below an end of the drain region on the buried oxide film side to the end of the semiconductor region; , identified by , The first distance and the second distance are The intensity of the electric field in a first region including an end of the drift region and in a second region between the end of the semiconductor region and the drain region is set to be 0.35 MV / cm or less. Effect of the Invention

[0010] According to one aspect of the present invention, it is possible to easily prevent a decrease in the breakdown voltage due to avalanche breakdown while improving the breakdown voltage of an LDMOS transistor. [Brief description of the drawings]

[0011] [Figure 1] 1 is a vertical cross-sectional view showing a cross-sectional structure of a semiconductor device according to an embodiment of the present invention; [Diagram 2] FIG. 4 is a diagram showing a potential distribution by simulation of the semiconductor device. [Diagram 3] FIG. 2 is an enlarged view of the potential distribution in region A of FIG. [Figure 4] 2 is an enlarged view of the potential distribution in region B of FIG. 1. FIG. [Diagram 5] 4 is a diagram showing the relationship between the maximum electric field value and the breakdown voltage with respect to two distances that define the positions of the ends of the P-type diffusion region in the semiconductor device. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] [Embodiment] (Configuration of Semiconductor Device 1) Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS.

[0013] FIG. 1 is a vertical cross-sectional view showing a cross-sectional structure of a semiconductor device 1 according to this embodiment.

[0014] In this embodiment, an N-channel LDMOS transistor (laterally diffused MOS transistor) with a withstand voltage of 60 V will be described as the semiconductor device 1.

[0015] As shown in FIG. 1, the semiconductor device 1 includes a P-type semiconductor substrate 2 (semiconductor substrate), a P-type diffusion region 3 (semiconductor region), a P-type body region 4 (body region), an N-type drift region 5 (drift region), an N-type source region 6 (source region), a source electrode 6a, a P-type body contact region 7, an N-type drain region 8 (drain region), a drain electrode 8a, a gate electrode 9, a gate insulating film 10, a thick oxide film 11, and an STI (Shallow Trench Isolation) structure 12.

[0016] In FIG. 1, layers containing P-type impurities are marked with "p" and layers containing N-type impurities are marked with "n." Layers containing higher concentrations of P-type impurities than layers marked with "p" are marked with "p + " is written, and "n" is written for layers that contain a higher concentration of N-type impurities than the layers marked with "n". +" is stated.

[0017] The P-type body region 4 is of P-type (first conductivity type). The P-type body region 4 is formed by ion implantation, for example, of boron ions (11B + ) are implanted at different acceleration energies (60-500 keV) several times. The dose of ion implantation is 1.0E12-1.0E13 / cm 2 The P-type body region 4 is formed so that a part of it is exposed on the upper surface 2 a of the P-type semiconductor substrate 2 .

[0018] The P-type diffusion region 3 is of P-type. The P-type diffusion region 3 is disposed at a deep position in the P-type semiconductor substrate 2 such that the upper surface of the P-type diffusion region 3 is in contact with the bottom surface of the P-type body region 4. The P-type diffusion region 3 is formed so as to extend along the upper surface 2a of the P-type semiconductor substrate 2 from below the P-type body region 4 to below any one of a gate insulating film 10, a thick oxide film 11, and an STI structure 12, which will be described later. The P-type diffusion region 3 is formed by implanting boron ions (11B + ) is implanted at an acceleration energy of 500 to 5000 keV. The dose of ion implantation is 5.0E11 to 5.0E12 / cm 2 The range is.

[0019] The N-type source region 6 is of N-type (second conductivity type). The N-type source region 6 is formed on the surface layer of the P-type semiconductor substrate 2 so as to be in contact with the P-type body region 4 and exposed on the upper surface 2a of the P-type semiconductor substrate 2. The N-type source region 6 is formed by, for example, doping phosphorus ions (31P + ) is formed by implantation with an acceleration energy of 35 to 60 KeV.

[0020] The P-type body contact region 7 is of P type. The P-type body contact region 7 is formed on the surface layer of the P-type semiconductor substrate 2 so as to be in contact with the P-type body region 4 and to be exposed on the upper surface 2a of the P-type semiconductor substrate 2. The P-type body contact region 7 is in contact with the N-type source region 6 so as to be adjacent to the N-type source region 6. The P-type body contact region 7 is formed by doping the N-type source region 6 with boron ions (11B + ) is formed by implantation with an acceleration energy of 5 to 30 KeV.

[0021] The source electrode 6 a is formed on the N-type source region 6 and the P-type body contact region 7 .

[0022] The N-type drift region 5 is of N-type. The N-type drift region 5 is disposed in the surface layer of the P-type semiconductor substrate 2, closer to the upper surface 2a of the semiconductor substrate than the P-type diffusion region 3. The N-type drift region 5 is formed so as to contact the N-type drain region 8. The N-type drift region 5 has an end portion 5a located between the P-type body region 4 and the N-type drain region 8. The upper surface of the end portion 5a is exposed to the upper surface 2a of the P-type semiconductor substrate 2. This structure of the N-type drift region 5 makes it possible to prevent the P-type diffusion region 3 and the N-type drift region 5, which are each highly concentrated, from contacting each other.

[0023] The N-type drift region 5 has a lower impurity concentration than the N-type drain region 8. The N-type drift region 5 is doped with, for example, phosphorus ions ( + The ion implantation dose is 7.5E11 to 3.5E12 / cm. 2 The range is.

[0024] In the implantations for forming the N-type drift region 5 and the P-type diffusion region 3, the acceleration energy in each implantation is adjusted so that the N-type drift region 5 does not contact the P-type diffusion region 3 in the depth direction.

[0025] The N-type drain region 8 is of N-type. The N-type drain region 8 is disposed in a surface layer of the P-type semiconductor substrate 2, separated from the P-type body region 4. The N-type drain region 8 is formed at the same time as the N-type source region 6.

[0026] The drain electrode 8 a is formed on the N-type drain region 8 .

[0027] The gate insulating film 10 is formed in a range including the upper surface 2a of the P-type semiconductor substrate 2, the upper surface of the P-type body region 4, and the upper surface of an end of the N-type drift region 5. The gate insulating film 10 is not formed on the upper surfaces of the N-type source region 6, the P-type body contact region 7, the N-type drain region 8, and the STI structure 12.

[0028] The thick oxide film 11 is an oxide film formed thick on the upper surface of the N-type drift region 5 so as to extend from the end of the gate insulating film 10 on the N-type drain region 8 side toward the N-type drain region 8 side. As the thick oxide film 11, for example, a LOCOS (Local Oxidation of Silicon) oxide film formed by thermal oxidation, or an oxide film (HTO (High Temperature Oxidation) film) formed by high temperature oxidation using CVD (Chemical Vapor Deposition) is suitably used. The thick oxide film 11 is provided for the purpose of alleviating an electric field. The thick oxide film 11 is formed thicker than the gate insulating film 10.

[0029] The gate electrode 9 is disposed between the N-type source region 6 and the N-type drain region 8 on the P-type semiconductor substrate 2. The gate electrode 9 is formed on the gate insulating film 10 and the thick oxide film 11. Therefore, the gate electrode 9 is formed such that the upper surfaces of a portion overlapping the thick oxide film 11 and a portion of the gate electrode 9 that is adjacent to the portion overlapping the gate insulating film 10 are higher than the upper surfaces of the other portions. As a result, the gate electrode 9 has a step in the middle portion.

[0030] The STI structure 12 is formed so as to overlap at least the end of the gate electrode 9 on the N-type drain region 8 side in the thickness direction of the P-type semiconductor substrate 2, via the thick oxide film 11. The STI structure 12 is also formed so as to be embedded to a predetermined depth from the upper surface 2a of the P-type semiconductor substrate 2 (more strictly speaking, the upper surface of the N-type drain region 8). The STI structure 12 is also formed in a range from a position slightly shifted toward the N-type drain region 8 side from the boundary between the gate insulating film 10 and the thick oxide film 11 to the end of the N-type drain region 8. The STI structure 12 is provided for the purpose of alleviating the electric field.

[0031] In this embodiment, the P-type body region 4 and the N-type source region 6 are electrically connected to each other by a source electrode 6a so as to have the same potential.

[0032] Here, with regard to P-type diffusion region 3, the positions of the ends of P-type diffusion region 3 that define the range over which it extends are specified by distance L1 (first distance) and distance L2 (second distance).

[0033] Distance L1 is the distance along the upper surface 2a of the P-type semiconductor substrate 2 from a first reference position P1 below the end of the P-type body region 4 facing the N-type drain region 8 to the end of the P-type diffusion region 3. Distance L2 is the distance along the upper surface 2a of the P-type semiconductor substrate 2 from a second reference position P2 below the end of the N-type drain region 8 on the STI structure 12 side to the end of the P-type diffusion region 3. The sum of distance L1 and distance L2 is a specified value.

[0034] (Operation of Semiconductor Device 1) Here, the operation of the semiconductor device 1 will be described.

[0035] By applying a positive potential to the gate electrode 9 with respect to the P-type body region 4, a channel is formed in the P-type body region 4 and the P-type semiconductor substrate 2 directly below the gate electrode 9 between the N-type source region 6 and the N-type drift region 5. As a result, electrons move through the channel in a path from the source electrode 6a to the drain electrode 8a. This causes a current to flow between the source electrode 6a and the drain electrode 8a.

[0036] (Improvement of breakdown voltage of semiconductor device 1) In the semiconductor device 1 assumed to have a withstand voltage of 60 V, a simulation was performed on the potential distribution in a state in which a GND potential was applied to the source electrode 6a and the gate electrode 9, and a voltage of 60 V was applied to the drain electrode 8a. In the following explanation, the sum of the distances L1 and L2 is 3.7 μm.

[0037] Fig. 2 is a diagram showing simulated potential distributions of the semiconductor device 1 when the distance L1 is 1.2 μm and the distance L2 is 2.5 μm. Fig. 3 is a diagram showing an enlarged view of the potential distribution in the above case in region A of Fig. 1. Fig. 4 is a diagram showing an enlarged view of the potential distribution in region B of Fig. 1.

[0038] 2 and 3, when the distance L1 is 1.2 μm and the distance L2 is 2.5 μm, the intervals between the equipotential lines in region A (first region) including the end 5a of the N-type drift region 5 are relatively wide, and it can be seen that the potential distribution in region A is sparse. In contrast, when the distance L1 is −0.3 μm and the distance L2 is 4.0 μm, although not shown, the intervals between the equipotential lines in region A are narrower than in the case of the above-mentioned distance L1=1.2 μm and distance L2=2.5 μm, and the potential distribution is denser.

[0039] As described above, when the distance L1=1.2 μm and the distance L2=2.5 μm, the potential distribution in region A was relatively sparse. This alleviates the concentration of the electric field in region A, and it can be seen that the surface electric field of the semiconductor device 1 is alleviated. This means that the breakdown voltage is improved. Therefore, by lengthening the distance L1 to a certain extent, it is expected that the breakdown voltage in region A will be improved. If this effect of improving the breakdown voltage is sufficient, the breakdown voltage of the semiconductor device 1 is not determined by the breakdown voltage in region A, but is instead limited by the breakdown voltage in region B (second region) between the end of the P-type diffusion region 3 and the N-type drain region 8 shown in FIG. 1.

[0040] Next, when the distance L1 is 1.2 μm and the distance L2 is 2.5 μm, as shown in Figures 2 and 4, it can be seen that the intervals between the equipotential lines in region B are relatively wide, and the potential distribution in region B is sparse. In contrast, when the distance L1 is 3.7 μm and the distance L2 is 0 μm, although not shown, the intervals between the equipotential lines in region B are narrower than in the above case of distance L1 = 1.2 μm and distance L2 = 2.5 μm, and the potential distribution is denser.

[0041] As described above, when the distance L1 = 1.2 μm and the distance L2 = 2.5 μm, the potential distribution in region B was relatively sparse. This shows that the concentration of the electric field in region B is alleviated. This means that the breakdown voltage is improved by increasing the distance L2.

[0042] Considering the effect of improving the withstand voltage in the regions A and B, a desired withstand voltage can be obtained by appropriately setting the distances L1 and L2.

[0043] Next, the effect of improving the breakdown voltage by optimizing the settings of the distances L1 and L2 will be described. Figure 5 is a diagram showing the relationship between the maximum electric field value and the breakdown voltage in regions A and B for the two distances L1 and L2 that define the positions of the ends of the P-type diffusion region 3. In Figure 5, the upper horizontal axis represents the distance L1, the lower horizontal axis represents the distance L2, the left vertical axis represents the maximum electric field value, and the right vertical axis represents the breakdown voltage. The sum of the values ​​of the distances L1 and L2 facing each other on the upper and lower horizontal axes is 3.7 μm.

[0044] As shown by the solid line in Fig. 5, the maximum electric field value decreases as the distance L1 increases from the case where L1 = -0.3 μm, L2 = 4 μm, reaches a minimum when L1 = 1 μm, L2 = 2.7 μm, and then increases as the distance L1 increases. On the other hand, as shown by the dashed line in Fig. 5, the withstand voltage increases as the distance L1 increases from the case where L1 = -0.3 μm, L2 = 4 μm, reaches a maximum when L1 = 1 μm, L2 = 2.7 μm, and then decreases as the distance L1 increases.

[0045] From this relationship between the maximum electric field value and the withstand voltage, the withstand voltage of 60V or more is determined by the combination of distances L1 and L2 where the range of the maximum electric field value in areas A and B is 0.35MV / cm or less. This range is from the combination of L1=-0.2μm, L2=3.9μm to the combination of L1=2.45μm, L2=1.25μm. Of these, the optimal value of the electric field value that maximizes the withstand voltage is obtained with the combination of L1=1μm, L2=2.7μm.

[0046] In this manner, in this embodiment, the combination of distances L1 and L2 is appropriately selected and set so that the electric field strength in regions A and B is 0.35 MV / cm or less. This makes it easy to avoid a decrease in breakdown voltage due to avalanche breakdown in regions A and B, and makes it possible to obtain a breakdown voltage of 60 V or more.

[0047] This embodiment is not limited to the above-mentioned example, and includes various modified examples. For example, the above-mentioned semiconductor device 1 is described in detail to make the present invention easier to understand, and is not necessarily limited to having all the described configurations. For example, the conditions of ion implantation for forming each semiconductor layer are examples, and can be changed as appropriate.

[0048] In this case, the optimum distances L1 and L2 are constant in sum, and vary within a range from a combination in which the distance L1 is the first distance lower limit and the distance L2 is the second distance upper limit to a combination in which the distance L1 is the first distance upper limit and the distance L2 is the second distance lower limit. Specifically, the distances L1 and L2 vary within the range of the above combination as a suitable example, that is, within a range from a combination of L1=-0.2 μm (first distance lower limit) and L2=3.9 μm (second distance upper limit) to a combination of L1=2.45 μm (first distance upper limit) and L2=1.25 μm (second distance lower limit). In this way, the distances L1 and L2 can take any combination of values ​​within the above range, so that the optimum distances L1 and L2 can be selected within the range.

[0049] Also, a part of a certain configuration of an embodiment can be replaced with another configuration of an embodiment, and another configuration of an embodiment can be added to a certain configuration of an embodiment. Also, at least one of addition, deletion, and replacement of another configuration can be performed for a part of the configuration of an embodiment. Such an example is not limited to the semiconductor device 1 of this embodiment, i.e., an N-channel LDMOS transistor, but may be a configuration applied to a P-channel LDMOS transistor. Also, the withstand voltage target of the target device is not particularly limited, and the lateral size of each configuration including the distances L1 and L2 is not limited. Also, the semiconductor device 1 may have an LDD (Lightly Doped Drain) implantation or the like added to the configuration for forming another transistor.

[0050] Furthermore, the semiconductor device 1 (N-channel LDMOS transistor) of this embodiment is formed on a P-type semiconductor substrate 2, but this P-type semiconductor substrate 2 may exist as a P-type semiconductor region formed on an N-type epitaxial buried layer. In that case, it is possible to set the source electrode and the P-type semiconductor region to a potential different from that of the P-type semiconductor substrate via the N-type epitaxial buried layer. This is the case when it is assumed that the semiconductor device 1 is operated as a high-side switch, and in this case, the breakdown voltage is defined as the potential difference between the drain electrode and the source electrode.

[0051] In addition, in this embodiment, it is presumed that the effects of the present invention can also be obtained in an N-channel LDMOS transistor in an N-type diffusion region as described in Patent Document 1.

[0052] Incidentally, the thick oxide film 11 is arranged shifted toward the N-type source region 6 side from the STI structure 12. This changes the electric field distribution in the region A, improving the breakdown voltage.

[0053] 〔summary〕 A semiconductor device 1 according to a first aspect of the present invention includes a semiconductor substrate of a first conductivity type, a body region of the first conductivity type formed in a surface layer of the semiconductor substrate, a source region of a second conductivity type formed so as to be in contact with the body region, a drain region of a second conductivity type formed at a distance from the body region, a gate electrode formed between the source region and the drain region, a drift region of a second conductivity type formed in the surface layer of the semiconductor substrate so as to be in contact with the drain region and having an end between the body region and the drain region, a buried oxide film for mitigating an electric field formed so as to be buried from an upper surface of the semiconductor substrate so as to overlap at least an end of the gate electrode on the drain region side, and a semiconductor region of a first conductivity type formed at a position deeper than the body region so as to be in contact with a bottom surface of the deep region, the semiconductor region being formed to extend in a direction along the upper surface of the semiconductor substrate, a first distance in a direction along the upper surface of the semiconductor substrate from a first reference position below an end of the body region facing the drain region to the end of the semiconductor region, and a second distance in a direction along the upper surface of the semiconductor substrate from a second reference position below an end of the drain region on the buried oxide film side to the end of the semiconductor region are set so that the electric field strength in a first region including an end of the drift region, and in a second region between the end of the semiconductor region and the drain region is 0.35 MV / cm or less.

[0054] According to the above configuration, in a state in which the intensity of the electric field in the first region and the second region is relaxed to 0.35 MV / cm or less, a withstand voltage equal to or higher than a desired voltage can be obtained.

[0055] A second aspect of the present invention relates to a semiconductor device in accordance with the first aspect, wherein the drift region is disposed at a position closer to an upper surface of the semiconductor substrate than the semiconductor region is.

[0056] According to the above-mentioned configuration, it is possible to prevent the semiconductor regions having higher concentrations from contacting the drift region.

[0057] A semiconductor device according to a third aspect of the present invention may be such that, in the first or second aspect, the sum of the first distance and the second distance is constant and can take a value within a range from a combination in which the first distance is a first distance lower limit value and the second distance is a second distance upper limit value to a combination in which the first distance is the first distance upper limit value and the second distance is the second distance lower limit value.

[0058] According to the above configuration, it is possible to select an optimal combination of the first distance and the second distance within the range.

[0059] [Additional Notes] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. In addition, embodiments obtained by appropriately combining the technical means disclosed in each embodiment are also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment. [Explanation of symbols]

[0060] 1. Semiconductor device (laterally diffused MOS transistor) 2 P-type semiconductor substrate (semiconductor substrate) 2a Top side 3 P-type diffusion region (semiconductor region) 4 P-type body region (body region) 5 N-type drift region (drift region) 6 N-type source region (source region) 8 N-type drain region (drain region) 9 Gate electrode 10 Gate insulating film 12 STI structure (buried oxide film) Area A (first area) B area (second area) L1 distance (first distance) L2 Distance (Second Distance) Area A (first area) B area (second area) P1 First reference position P2 Second reference position

Claims

1. a semiconductor substrate of a first conductivity type; a body region of a first conductivity type formed on a surface layer of the semiconductor substrate; a source region of a second conductivity type formed in contact with the body region; a drain region of a second conductivity type formed apart from the body region; a gate electrode formed between the source region and the drain region; a drift region of a second conductivity type formed in a surface layer of the semiconductor substrate so as to be in contact with the drain region and having an end between the body region and the drain region; a buried oxide film that overlaps at least an end of the gate electrode on the drain region side and is formed so as to be buried from an upper surface of the semiconductor substrate, thereby reducing an electric field; a semiconductor region of a first conductivity type formed at a position deeper than the body region so as to be in contact with a bottom surface of the body region; The semiconductor region is formed to extend in a direction along an upper surface of the semiconductor substrate, and a position of an end of the semiconductor region that defines a range in which the semiconductor region extends is a first distance in a direction along the top surface of the semiconductor substrate from a first reference position below an end of the body region facing the drain region to an end of the semiconductor region; a second distance in a direction along the top surface of the semiconductor substrate from a second reference position below an end of the drain region on the buried oxide film side to an end of the semiconductor region; The semiconductor device is characterized in that the first distance and the second distance are set so that the electric field strength in a first region including an end of the drift region, and in a second region between the end of the semiconductor region and the drain region is 0.35 MV / cm or less.

2. 2. The semiconductor device according to claim 1, wherein the drift region is disposed at a position closer to the upper surface of the semiconductor substrate than the semiconductor region.

3. 2. The semiconductor device according to claim 1, wherein the sum of the first distance and the second distance is constant and can take values ​​within a range from a combination in which the first distance is a first distance lower limit value and the second distance is a second distance upper limit value to a combination in which the first distance is the first distance upper limit value and the second distance is a second distance lower limit value.

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