Multistate pulsing to achieve a balance between warpage control and mask selectivity.

Abstract

A multi-state pulsing method for achieving a balance between warpage control and mask selectivity is described. The method includes generating a primary radio frequency (RF) signal. The primary RF signal is pulsed between three states, including a first state, a second state, and a third state. The method further includes generating a secondary RF signal. The secondary RF signal is pulsed between three states. In the first state, a power level of the primary RF signal is greater than a power level of the secondary RF signal. Also, in the second state, a power level of the secondary RF signal is greater than a power level of the primary RF signal. In the third state, the power levels of the primary RF signal and the secondary RF signal are approximately equal.

Description

[Technical field]

[0001] The embodiments described in this disclosure relate to multi-state pulsing systems and methods for achieving a balance between warpage control and mask selectivity. [Background technology]

[0002] The description of the background art provided herein is intended to provide a general background to the present disclosure. The inventors' work within the scope of this description, and aspects of the description that may not otherwise be admitted as prior art at the time of filing, are not admitted, explicitly or implicitly, as prior art to the present disclosure.

[0003] A radio frequency (RF) generator generates an RF signal and supplies the RF signal through a matching network to a plasma reactor. The plasma reactor has a semiconductor wafer, and the semiconductor wafer is etched when the RF signal and an etching gas are supplied to the plasma reactor. However, during etching of the semiconductor wafer, a desired selectivity for the semiconductor wafer is not obtained.

[0004] It is in this context that the embodiments described in this disclosure are provided. Summary of the Invention

[0005] The embodiments of the present disclosure provide a multi-state pulsing apparatus, method, and computer program for achieving a balance between warpage control and mask selectivity. It should be appreciated that the embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, hardware, or a method recorded on a computer readable medium. Several embodiments are described below.

[0006] In one embodiment, a three-state radio frequency (RF) pulsing method is described that overcomes the trade-off between sidewall polymer passivation and mask selectivity, which creates a constraint in achieving pitch to further limit device size. As an example, the three-state RF pulsing method includes synchronously pulsing a low-frequency RF generator and a high-frequency RF generator between three states in a periodic manner.

[0007] In one embodiment, a multi-state pulsing method is described to achieve a balance between warpage control and mask selectivity. The method includes generating a primary RF signal. The primary RF signal is pulsed between three states including a first state, a second state, and a third state. The method further includes generating a secondary RF signal. The secondary RF signal is pulsed between three states. In the first state, a power level of the primary RF signal is greater than a power level of the secondary RF signal. Also, in the second state, a power level of the secondary RF signal is greater than a power level of the primary RF signal. In the third state, the power levels of the primary RF signal and the secondary RF signal are approximately equal.

[0008] In one embodiment, a controller is described. The controller includes a processor that controls a primary RF generator to generate a primary RF signal. The processor controls the primary RF generator to pulse the primary RF signal between three states including a first state, a second state, and a third state. The processor also controls a secondary RF generator to generate a secondary RF signal. The processor controls the secondary RF generator to pulse the secondary RF signal between the three states. In the first state, a power level of the primary RF signal is greater than a power level of the secondary RF signal. In the second state, a power level of the secondary RF signal is greater than a power level of the primary RF signal. In the third state, the power levels of the primary RF signal and the secondary RF signal are approximately equal. The controller includes a memory device coupled to the processor.

[0009] In one embodiment, the processor controls the duty cycle of the first state to be less than the duty cycle of the third state, and the processor controls the duty cycle of the second state to be less than the duty cycle of the third state.

[0010] In one embodiment, the power level of the primary RF signal in the first state is at least six times and up to ten times greater than the power level of the secondary RF signal in the first state.

[0011] In one embodiment, the power level of the primary RF signal in the second state is at least 20 percent and up to less than 100 percent of the power level of the secondary RF signal in the second state.

[0012] In one embodiment, a system is described. The system includes a primary RF generator configured to generate a primary RF signal. The system further includes a secondary RF generator configured to generate a secondary RF signal. The system includes an impedance matching circuit coupled to the primary RF generator via a first RF cable and coupled to the secondary RF generator via a second RF cable. The impedance matching circuit receives the primary RF signal via the first RF cable and the secondary RF signal via the second RF cable and outputs a modified RF signal. The system also includes a plasma chamber coupled to the impedance matching circuit and receiving the modified RF signal. The system includes a computer coupled to the RF generator. The computer controls the primary RF generator to pulse the primary RF signal between three states including a first state, a second state, and a third state. The computer further controls the secondary RF generator to pulse the secondary RF signal between the three states. In the first state, a power level of the primary RF signal is greater than a power level of the secondary RF signal. Also, in the second state, a power level of the secondary RF signal is greater than a power level of the primary RF signal. In a third state, the power levels of the primary RF signal and the secondary RF signal are approximately equal.

[0013] In one embodiment, the computer controls the duty cycle of the first state to be less than the duty cycle of the third state, and the computer controls the duty cycle of the second state to be less than the duty cycle of the third state.

[0014] In one embodiment, the power level of the primary RF signal in the first state is at least six times and up to ten times greater than the power level of the secondary RF signal in the first state.

[0015] In one embodiment, the power level of the primary RF signal in the second state is at least 20 percent and up to less than 100 percent of the power level of the secondary RF signal in the second state.

[0016] In one embodiment, a system is described. The system includes a primary RF generator configured to generate a primary RF signal in a first frequency range. The system further includes a secondary RF generator configured to generate a secondary RF signal in a second frequency range. The system includes an impedance matching circuit coupled to the primary RF generator via a first RF cable and coupled to the secondary RF generator via a second RF cable. The impedance matching circuit receives the primary RF signal via the first RF cable and the secondary RF signal via the second RF cable and outputs a modified RF signal. The system includes a plasma chamber coupled to the impedance matching circuit and receiving the modified RF signal. The system further includes a gas source fluidly connected to the plasma chamber. The gas source includes a tungsten-containing gas source and an etching component gas source. The system includes a computer coupled to the RF generator. The computer controls the tungsten-containing gas source and the etching component gas source. The computer further controls the primary RF generator to pulse the primary RF signal between at least three states including a first state, a second state, and a third state. The computer also controls the secondary RF generator to pulse the secondary RF signal between the at least three states. The power level of the primary RF signal in the second state is less than 80% of the power level of the primary RF signal in the first state. The power level of the primary RF signal in the third state is less than 20% of the power level of the primary RF signal in the second state. The power level of the secondary RF signal in the third state is less than 20% of the power level of the secondary RF signal in the second state. In the first state, the second state, and the third state, gas is flowed from the tungsten-containing gas source and the etching component gas source.

[0017] In one embodiment, the computer controls the duty cycle of the first state to be less than the duty cycle of the third state, and the computer controls the duty cycle of the second state to be less than the duty cycle of the third state.

[0018] In one embodiment, the duty cycle of the first state is in the range of 3 percent to 25 percent of a clock cycle of the clock signal.

[0019] Also, in one embodiment, the duty cycle of the second state is in the range of 3 percent to 50 percent of a clock cycle of the clock signal.

[0020] In one embodiment, the duty cycle of the third state is in the range of 25 percent to 94 percent of a clock cycle of the clock signal, and the sum of the duty cycles of the first, second, and third states is equal to 100 percent of the clock cycle.

[0021] In one embodiment, the first frequency range is from 80 kHz to 14 MHz (inclusive) and the second frequency range is from 15 MHz to 120 MHz (inclusive).

[0022] In one embodiment, the tungsten containing gas is tungsten fluoride.

[0023] In one embodiment, the tungsten containing gas is tungsten hexafluoride.

[0024] In one embodiment, a ratio of the power level of the primary RF signal in the first state to the power level of the secondary RF signal in the first state is greater than 1, and a ratio of the power level of the primary RF signal in the second state to the power level of the secondary RF signal in the second state is less than 1.

[0025] In one embodiment, the computer adjusts the first state, the second state, and the third state to minimize necking and warping using a metal fluoride or tungsten-containing passivation agent.

[0026] Advantages of the three-state RF pulsing method described herein include the ability to reduce the bow in the nitride layer sidewalls by more than about 1.5 nanometers (nm) while increasing the mask selectivity, e.g., by achieving reduced bow, the mask selectivity increases by about 15%-20% compared to the mask selectivity using two-state pulsing.

[0027] A further advantage of the multi-state pulsing system and method described herein is that a balance between warpage control and mask selectivity can be achieved. This balance is achieved by pulsing each of the low-frequency RF generator and the high-frequency RF generator in three states. For example, in a first state, the low-frequency RF generator is pulsed at a much greater power level compared to the power level of the high-frequency RF generator. In a second state, the high-frequency RF generator is pulsed at a greater power level compared to the power level of the low-frequency RF generator. In a third state, the power levels of the low-frequency RF generator and the high-frequency RF generator are approximately zero. By pulsing the low-frequency RF generator and the high-frequency RF generator in this manner, a balance is achieved. Achieving this balance facilitates etching high aspect ratio substrate features.

[0028] Other aspects will become apparent from the following detailed description considered in conjunction with the accompanying drawings. [Brief description of the drawings]

[0029] Various embodiments will be understood by reference to the following description in conjunction with the accompanying drawings.

[0030] [Figure 1] FIG. 1 is a diagram of one embodiment of a system to illustrate tri-state pulsing of multiple radio frequency (RF) signals to achieve a balance between warp control and mask selectivity.

[0031] [Figure 2A] FIG. 2A illustrates one embodiment of a graph of a clock signal.

[0032] [Figure 2B] FIG. 2B is a diagram illustrating an embodiment of a graph to explain an embodiment of a digital pulse signal.

[0033] [Figure 2C] FIG. 2C illustrates an embodiment of a graph to illustrate an embodiment of an RF signal generated by a low frequency RF generator and an embodiment of an RF signal generated by a high frequency RF generator.

[0034] [Figure 2D] FIG. 2D illustrates an embodiment of a graph to illustrate an embodiment of an RF signal generated by a low frequency RF generator and an embodiment of an RF signal generated by a high frequency RF generator.

[0035] [Figure 3A] FIG. 3A shows one embodiment of a graph illustrating an expanded portion of the RF signal of FIG. 2C generated by a low frequency RF generator.

[0036] [Figure 3B] FIG. 3B shows one embodiment of a graph illustrating a magnified portion of the RF signal of FIG. 2C generated by a high frequency RF generator.

[0037] [Figure 4A] FIG. 4A illustrates one embodiment of a graph of the clock signals of FIG. 2A.

[0038] [Figure 4B] FIG. 4B is a diagram showing an embodiment of a graph to explain an embodiment of a digital pulse signal.

[0039] [Figure 4C]FIG. 4C illustrates an embodiment of a graph to illustrate an embodiment of an RF signal generated by a low frequency RF generator and an embodiment of an RF signal generated by a high frequency RF generator.

[0040] [Figure 4D] FIG. 4D illustrates an embodiment of a graph to illustrate an embodiment of an RF signal generated by a low frequency RF generator and an embodiment of an RF signal generated by a high frequency RF generator.

[0041] [Figure 5A] FIG. 5A shows one embodiment of a graph illustrating an expanded portion of the RF signal of FIG. 4C generated by a low frequency RF generator.

[0042] [Figure 5B] FIG. 5B shows one embodiment of a graph illustrating a magnified portion of the RF signal of FIG. 4C generated by a high frequency RF generator.

[0043] [Figure 6] FIG. 6 illustrates one embodiment of a table illustrating the duty cycles associated with three states of the RF signal generated by the low frequency RF generator and the high frequency RF generator.

[0044] [Figure 7A] FIG. 7A illustrates one embodiment of a substrate stack before processing.

[0045] [Figure 7B] FIG. 7B illustrates another embodiment of a substrate stack during processing.

[0046] [Figure 7C] FIG. 7C shows a portion of the substrate stack of FIG. 7B.

[0047] [Figure 7D]FIG. 7D illustrates yet another embodiment of a substrate stack after processing the substrate stack of FIG. 7A.

[0048] [Figure 8] FIG. 8 is a flow chart of another embodiment.

[0049] [Figure 9A] FIG. 9A is a schematic cross-sectional view of a stack processed according to the embodiment shown in FIG.

[0050] [Figure 9B] FIG. 9B is a schematic cross-sectional view of a stack processed according to the embodiment shown in FIG.

[0051] [Figure 10] FIG. 10 is a schematic diagram of a plasma processing system used in one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0052] In the following embodiments, a multi-state pulsing system and method for achieving a balance between warpage control and mask selectivity is described. It will be apparent that the embodiments may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the embodiments.

[0053] 1 is a diagram illustrating an embodiment of a system 100 for illustrating tri-state pulsing of multiple radio frequency (RF) signals to achieve a balance between warpage control and mask selectivity. The system 100 includes an RF generator RFGx, another RF generator RFGy, an impedance matching network IMN, a plasma chamber 106, and a host computer 110.

[0054] Examples of RF generators RFGx include low-frequency RF generators, such as RF generators having an operating frequency of 400 kilohertz (kHz), 2 megahertz (MHz), or 13.56 MHz. Examples of RF generators RFGy include high-frequency RF generators, such as RF generators having an operating frequency of 27 MHz or 60 MHz. Note that the operating frequency of the high-frequency RF generator is greater than the operating frequency of the low-frequency RF generator.

[0055] The impedance matching network IMN is a network of circuit components such as inductors, capacitors, and resistors. For example, the impedance matching network is a circuit including a shunt capacitor and a series capacitor. The shunt capacitor has one end coupled to the series capacitor and the other end coupled to ground potential. The series capacitor is coupled between an input of the impedance matching network IMN (such as an input I2x or an input I2y) and an output O2 of the impedance matching network IMN. As another example, one or more circuit components of the impedance matching network IMN are coupled in series or parallel to one or more circuit components of the impedance matching network IMN. The impedance matching network IMN has a branch including one or more circuit components, which is coupled between the input I2x and the output O2. Similarly, the impedance matching network IMN has another branch including one or more circuit components, which is coupled between the input I2y and the output O2.

[0056] The plasma chamber 106 includes a substrate support 104, such as a chuck. The chuck includes a lower electrode embedded within the chuck, a fixture plate located below the lower electrode, and a ceramic plate located above the lower electrode. The plasma chamber 106 further includes an upper electrode 118 that is coupled to a ground potential. Examples of the host computer 110 include a desktop computer, a laptop computer, a controller, a tablet, and a smartphone.

[0057] The RF generator RFGx includes a digital signal processor (DSP) DSPx, a power controller PWRS1x, another power controller PWRS2x, yet another power controller PWRS0x, an automatic frequency tuner (AFT) AFTx, and a power supply PSx. Examples of DSPs used herein include controllers including a microprocessor, an application specific integrated circuit (ASIC), or a programmable logic device (PLD). The controller of the DSP also includes a memory device capable of fetching multiple data or instructions simultaneously. The memory device of the DSP is coupled to the microprocessor, the ASIC, or the PLD of the DSP. Examples of memory devices used herein include ROM, RAM, flash memory, storage disk arrays, hard disks, etc.

[0058] Examples of power controllers as used herein include microcontrollers. Illustratively, the power controller includes a microprocessor, an ASIC, or a PLD. The power controller further includes a memory device coupled to the microprocessor, ASIC, or PLD of the power controller.

[0059] As used herein, examples of a tuner include a microcontroller. For example, the tuner includes a microprocessor, an ASIC, or a PLD. The tuner further includes a memory device coupled to the tuner's microprocessor, ASIC, or PLD.

[0060] Examples of power sources as used herein include electronic or RF oscillators that generate a periodic oscillating electronic signal (such as a sinusoidal RF signal).

[0061] The digital signal processor DSPx is coupled to the power controllers PWRS1x, PWRS2x, PWRS0x and to the automatic frequency tuner AFTx. Further, each of the power controllers PWRS1x, PWRS2x, PWRS0x is coupled to a power supply PSx. The automatic frequency tuner AFTSx is also coupled to the power supply PSx.

[0062] The RF generator RFGy includes a digital signal processor DSPy, a power controller PWRS1y, another power controller PWRS2y, yet another power controller PWRS0y, an automatic frequency tuner AFTy, and a power supply PSy. The digital signal processor DSPy is coupled to the power controllers PWRS1y, PWRS2y, PWRS0y and the automatic frequency tuner AFTy. Further, each of the power controllers PWRS1y, PWRS2y, PWRS0y is coupled to the power supply PSy. The automatic frequency tuner AFTSy is also coupled to the power supply PSy.

[0063] The host computer includes a processor 112 and a memory device 114. The processor 112 is coupled to the memory device 114. Examples of processors used herein include microprocessors, ASICs, central processing units (CPUs), or PLDs.

[0064] The processor 112 is coupled to the digital signal processor DSPx via a transfer cable 120x and is also coupled to the digital signal processor DSPy via another transfer cable 120y. Examples of transfer cables used herein include parallel transfer cables that facilitate parallel transfer of data between the processor 112 and the DSP, serial transfer cables that facilitate serial transfer of data between the processor 112 and the DSP, and USB transfer cables that facilitate data transfer between the processor 112 and the DSP according to the USB standard.

[0065] The power supply PSx is coupled to the input I2x of the impedance matching network IMN via an RF cable 116x For example, the output O1x of the RF generator RFGx is coupled to the input I2x via an RF cable 116x Further, the power supply Psy is coupled to the input I2y of the impedance matching network IMN via an RF cable 116y For example, the output O1y of the RF generator RFGy is coupled to the input I2y via an RF cable 116y Thereby coupled to the input I2y.

[0066] An output O2 of the impedance matching network IMN is coupled to the bottom electrode of the substrate support pedestal 104 via an RF transmission line 122. An example of the RF transmission line 122 includes a conductor surrounded by an insulator surrounded by an RF sleeve (such as an aluminum solid bar). The insulator can be a dielectric material such as Teflon. Another example of the RF transmission line 122 includes a conductor coupled to an RF cylinder having an inner conductive rod and an outer housing via one or more RF straps. The inner conductive rod of the RF cylinder is coupled to the bottom electrode. As described in the above example, the conductor is surrounded by an insulator surrounded by an RF sleeve. The conductor of the RF transmission line 122 is coupled to the output O2 of the impedance matching network IMN.

[0067] The processor 112 generates a clock signal and a digital pulse signal 108 synchronized with the clock signal. Examples of the clock signal and the digital pulse signal 108 are described below. The digital pulse signal 108 has three states, such as state S1, state S2, and state S0, as described below.

[0068] The processor 112 accesses (e.g., reads or retrieves) from the memory device 114 a power level for state S1 of the RF signal 102x generated by the RF generator RFGx, a power level for state S2 of the RF signal 102x, and a power level for state S0 of the RF signal 102x. Additionally, the processor 112 accesses from the memory device 114a a power level for state S1 of the RF signal 102y generated by the RF generator RFGy, a power level for state S2 of the RF signal 102y, and a power level for state S0 of the RF signal 102y. Each of the RF signals 102x, 102y is a sinusoidal signal.

[0069] It should be noted that in one embodiment, the power level for a state of the RF signal is the power level achieved by the RF signal while in that state. For example, the power level for state S1 of the RF signal is the power level achieved during instances when the digital pulse signal 108 is in state S1, the power level for state S2 of the RF signal is the power level achieved during instances when the digital pulse signal 108 is in state S2, and the power level for state S0 of the RF signal is the power level achieved during instances when the digital pulse signal 108 is in state S0.

[0070] The processor 112 transmits the power levels for the states S1, S2, and S0 of the RF signal 102x to be generated together with the identification information of each of the states S1, S2, and S0 to the digital signal processor DSPx via the transmission cable 120x. When the digital signal processor DSPx receives the power levels for the states S1, S2, and S0 of the RF signal 102x together with the identification information of each state, the digital signal processor DSPx accesses the correspondence (one-to-one mapping, link, one-to-one relationship, etc.) between the identification information of the states S1 to S0 and the power controllers PWRS1x, PWRS2x, and PWRS0x from the memory device of the digital signal processor DSPx. Then, the digital signal processor DSPx transmits the power level for the state S1 to the power controller PWRS1x, the power level for the state S2 to the power controller PWRS2x, and the power level for the state S0 to the power controller PWRS0x. Each power controller PWRS1x, PWRS2x, PWRS0x stores the respective power level received from the digital signal processor DSPx in a memory device of the power controller.

[0071] Similarly, the processor 112 transmits the power levels for the states S1, S2, and S0 of the RF signal 102y to be generated, together with the identification information of each of the states S1, S2, and S0, to the digital signal processor DSPy via the transmission cable 120y. When the digital signal processor DSPy receives the power levels for the states S1, S2, and S0 of the RF signal 102y together with the identification information of each state, the digital signal processor DSPy accesses the correspondence (one-to-one mapping, link, one-to-one relationship, etc.) between the identification information of the states S1, S2, and S0 and the power controllers PWRS1y, PWRS2y, and PWRS0y from the memory device of the digital signal processor DSPy. Then, the processor transmits the power level for the state S1 to the power controller PWRS1y, the power level for the state S2 to the power controller PWRS2y, and the power level for the state S0 to the power controller PWRS0y. Each power controller PWRS1y, PWRS2y, PWRS0y stores the respective power level received from the digital signal processor DSPy in a memory device of the power controller.

[0072] The processor 112 transmits the digital pulse signal 108 to the digital signal processor DSPx via the transmission cable 120x, and simultaneously transmits the digital pulse signal 108 to the digital signal processor DSPy via the transmission cable 120y. Upon receiving the digital pulse signal 108, the digital signal processor DSPx identifies the state of the digital pulse signal 108 from the logic level of the digital pulse signal 108. For example, when the digital signal processor DSPx determines that the logic level of the digital pulse signal 108 is 0, it identifies that the state of the digital pulse signal 108 is S1, when it determines that the logic level of the digital pulse signal 108 is 1, it identifies that the state of the digital pulse signal 108 is S2, and when it determines that the logic level of the digital pulse signal 108 is 2, it identifies that the state of the digital pulse signal 108 is S0.

[0073] When the digital pulse signal 108 is in state S1, upon determining that the state of the digital pulse signal 108 is S1, the digital signal processor DSPx sends a control signal to the power controller PWRS1x. When the digital pulse signal 108 is in state S1 and upon receiving the control signal, the power controller PWRS1x accesses the power level for state S1 from a memory device of the power controller PWRS1x, generates a signal including the power level for state S1, and sends the signal to the power supply PSx. When the digital pulse signal 108 is in state S1 and upon receiving a signal including the power level for state S1 from the power controller PWRS1x, the power supply PSx generates a portion of the RF signal 102x having the power level for state S1.

[0074] Similarly, when the digital pulse signal 108 is in state S2, upon determining that the state of the digital pulse signal 108 is S2, the digital signal processor DSPx sends a control signal to the power controller PWRS2x. Upon receiving the control signal when the digital pulse signal 108 is in state S2, the power controller PWRS2x accesses the power level for state S2 from a memory device of the power controller PWRS2x, generates a signal including the power level for state S2, and sends the signal to the power supply PSx. When the digital pulse signal 108 is in state S2, the power controller PWRS2x receives the control signal, accesses the power level for state S2 from a memory device of the power controller PWRS2x, generates a signal including the power level for state S2, and sends the signal to the power supply PSx. PWRS2x , power supply PSx transitions RF signal 102x from a power level for state S1 to a power level for state S2 and generates a portion of RF signal 102x having a power level for state S2.

[0075] Also, when the digital pulse signal 108 is in state S0, upon determining that the state of the digital pulse signal 108 is S0, the digital signal processor DSPx transmits a control signal to the power controller PWRS0x. When the digital pulse signal 108 is in state S0 and the digital signal processor DSPx receives the control signal, the power controller PWRS0x accesses the power level for state S0 from the memory device of the power controller PWRS0x, generates a signal including the power level for state S0, and transmits the signal to the power supply PSx. When the digital pulse signal 108 is in state S0 and the power supply PSx receives a signal having the power level for state S0 from the power controller PWRS0x, the power supply PSx transitions the RF signal 102x from the power level for state S2 to the power level for state S0 and generates a portion of the RF signal 102x having the power level for state S0.

[0076] Similarly, upon receiving the digital pulse signal 108, the digital signal processor DSPy identifies the state of the digital pulse signal 108 from the logic level of the digital pulse signal 108 in the same manner as the above-mentioned digital signal processor DSPx identifies the state of the digital pulse signal 108. For example, when the digital signal processor DSPy determines that the logic level of the digital pulse signal 108 is 0, it identifies that the state of the digital pulse signal 108 is S1, when it determines that the logic level of the digital pulse signal 108 is 1, it identifies that the state of the digital pulse signal 108 is S2, and when it determines that the logic level of the digital pulse signal 108 is 2, it identifies that the state of the digital pulse signal 108 is S0.

[0077] When the digital pulse signal 108 is in state S1, the digital signal processor DSPy transmits a control signal to the power controller PWRS1y upon determining that the state of the digital pulse signal 108 is S1. Also, when the digital pulse signal 108 receives a control signal when the digital pulse signal 108 is in state S1, the power controller PWRS1y accesses a power level for state S1 from a memory device of the power controller PWRS1y, generates a signal including the power level for state S1, and transmits the signal to the power supply PSy. When the digital pulse signal 108 is in state S1 and receives a signal having a power level for state S1 from the power controller PWRS1y, the power supply PSy generates a portion of the RF signal 102y having a power level for state S1.

[0078] Similarly, the digital pulse signal 108 is in the state S2 When the digital pulse signal 108 is determined to be in the state S2, the digital signal processor DSPy controls the power controller PWRS2y When the digital pulse signal 108 is in state S2, the power controller PWRS2y accesses the power level for state S2 from a memory device of the power controller PWRS2y, generates a signal including the power level for state S2, and transmits the signal to the power supply PSy. When the digital pulse signal 108 is in state S2 and a signal having the power level for state S2 is received from the power controller PWRS1y, the power supply PSy transitions the RF signal 102y from the power level for state S1 to the power level for state S2 and generates a portion of the RF signal 102y having the power level for state S2.

[0079] Also, when the digital pulse signal 108 is in state S0, upon determining that the state of the digital pulse signal 108 is S0, the digital signal processor DSPy transmits a control signal to the power controller PWRS0y. When the digital pulse signal 108 is in state S0 and the digital signal processor DSPy receives the control signal, the power controller PWRS0y accesses the power level for state S0 from the memory device of the power controller PWRS0y, generates a signal including the power level for state S0, and transmits the signal to the power supply PSy. When the digital pulse signal 108 is in state S0 and the power supply PSy receives a signal having the power level for state S0 from the power controller PWRS0y, the power supply PSy transitions the RF signal 102y from the power level for state S2 to the power level for state S0, and generates a portion of the RF signal 102y having the power level for state S0.

[0080] The RF signal 102x is supplied from the power supply PSx via an output O1x and an RF cable 116x to an input I2x of the impedance matching network IMN. The RF signal 102y is supplied from the power supply PSy via an output O1y and an RF cable 116y to an input I2y of the impedance matching network IMN. The impedance matching network IMN receives the RF signal 102x at the input I2x. The RF signal 102x is then forwarded through a branch circuit coupled to the input I2x of the impedance matching network IMN, whereby the impedance of the RF signal RF102x is modified by the branch circuit, and a first modified RF signal is output. Similarly, the impedance matching network IMN receives the RF signal RF102x at the input I2y. 102yThe RF signal 102y is then forwarded through a branch circuit coupled to an input I2y of the impedance matching network IMN, whereby the impedance of the RF signal RF102y is modified by the branch circuit to output a second modified RF signal. The impedances of the RF signals 102x and 102y are modified to match the impedance of a load coupled to the output O2 with the impedance of a source coupled to the inputs I2x and I2y. The load coupled to the output O2 is, for example, an RF transmission line 122 and a plasma chamber 106. The sources coupled to the inputs I2x and I2y are, for example, RF cables 116x and 116y and RF generators RFGx and RFGy. The branch circuit coupled to the input I2x is connected to the branch circuit coupled to the input I2y at the output O2, where the first and second modified RF signals are combined, and a combined modified RF signal 124 is output at the output O2.

[0081] The integrated modified RF signal 124 is transmitted from an output O2 of the impedance matching network IMN through an RF transmission line 122 to the lower electrode of the substrate support pedestal 104. In addition, one or more process gases (such as a fluorine-containing gas, an oxygen-containing gas, or a combination thereof) are provided in a gap between the upper electrode 118 and the substrate support pedestal 104 in the plasma chamber 106. When the integrated modified RF signal 124 and the one or more process gases are simultaneously provided to the plasma chamber 106, a plasma is ignited or sustained in the gap to process the substrate S. Examples of the substrate S include a semiconductor wafer formed on a substrate layer and a substrate stack formed on a substrate layer. Examples of the processing of the substrate S include depositing one or more materials (such as an oxide layer, a nitride layer, a silicon nitride layer, a mask layer, or a combination of two or more thereof) on the substrate layer. Other examples of the substrate processing include etching the substrate S, sputtering the substrate S, or cleaning the substrate S.

[0082] In one embodiment, the bottom electrode of the substrate support pedestal 104 is coupled to ground potential and the top electrode 118 is coupled to the output O2 of the impedance matching network IMN.

[0083] In one embodiment, in addition to RF generators RFGx and RFGy being coupled to the lower electrode of the substrate support pedestal 104 through an impedance matching network IMN, one or more RF generators are coupled to the upper electrode 118 through an impedance matching network.

[0084] In one embodiment, digital signal processors DSPx, power controllers PWRS1x, PWRS2x, PWRS0x, and automatic frequency tuners AFTx The functions or operations described herein as being performed by one or more of the power controllers PWRS1x, PWRS2x, PWRS0x, and the automatic frequency tuner AFTx are performed by a controller or processor of the RF generators RFGx. For example, the functions described herein as being performed by the power controllers PWRS1x, PWRS2x, PWRS0x, and the automatic frequency tuner AFTx are performed by the digital signal processors DSPx.

[0085] Similarly, in one embodiment, a digital signal processor DSPy, a power controller PWRS1y The functions or operations described herein as being performed by one or more of the power controller PWRS2y, the power controller PWRS0y, and the automatic frequency tuner AFTSy are performed by a controller or processor of the RF generator RFGy. For example, the functions described herein as being performed by the power controller PWRS1y, the power controller PWRS2y, the power controller PWRS0y, and the automatic frequency tuner AFTSy are performed by a digital signal processor DSPy.

[0086] In one embodiment, the functions or operations described herein as being performed by one or more of the digital signal processor DSPx, the power controller PWRS1x, the power controller PWRS2x, the power controller PWRS0x, the automatic frequency tuner AFTSx, the digital signal processor DSPy, the power controller PWRS1y, the power controller PWRS2y, the power controller PWRS0y, and the automatic frequency tuner AFTSy are performed by the processor 112.

[0087] In one embodiment, the clock signal is generated by a clock source instead of the processor 112 .

[0088] 2A illustrates one embodiment of a graph 202 of a clock signal 204, which is the clock signal described above. The clock signal 204 is generated by the processor 112. The graph 202 plots logic levels on the y-axis and time t on the x-axis. The y-axis of the graph 202 includes a logic level 0 and a logic level 1. The x-axis of the graph 202 includes a number of times t0, t1, t2, t3, t4, and t5.

[0089] The time interval between any two consecutive times on the x-axis of the graph 202 is the same. For example, the time interval between times t0 and t1 is equal to the time interval between times t1 and t2, and the time interval between times t1 and t2 is equal to the time interval between times t2 and t3. The time interval between times t3 and t4 is equal to the time interval between times t2 and t3, and the time interval between times t4 and t5 is equal to the time interval between times t3 and t4. Time t1 is consecutive to time t0. Similarly, time t2 is consecutive to time t1, time t3 is consecutive to time t2, time t4 is consecutive to time t3, and time t5 is consecutive to time t4.

[0090] Clock signal 204 periodically transitions between logic levels 0 and 1. For example, during the first half of cycle 1 of clock signal 204, clock signal 204 is at logic level 1. At time t1, clock signal 204 transitions from logic level 1 to logic level 0. During the second half of cycle 1 of clock signal 204, clock signal 204 is at logic level 0. At time t2, clock signal 204 transitions from logic level 0 to logic level 1. During the first half of cycle 2 of clock signal 204, clock signal 204 is at logic level 1. At time t3, clock signal 204 transitions from logic level 1 to logic level 0. During the second half of cycle 2 of clock signal 204, the clock signal is at logic level 0. At time t4, clock signal 204 transitions from logic level 0 to logic level 1.

[0091] Cycle 2 of clock signal 204 is consecutive to cycle 1 of clock signal 204. For example, there are no other clock cycles between cycles 1 and 2 of clock signal 204. Cycle 1 occurs from time t0 to time t2, and cycle 2 occurs from time t2 to time t4.

[0092] 2B illustrates an embodiment of a graph 206 to illustrate an embodiment of a digital pulse signal 208. The digital pulse signal 208 is an example of the digital pulse signal 108 of FIG. 1. The graph 206 plots the logic levels of the digital pulse signal 208 on the y-axis and time t on the x-axis. The y-axis of the graph 206 includes logic levels 0, 1, and 2. The x-axis of the graph 206 includes time t0, time t0a, time t0b, time t1, time t2, time t2a, time t2b, time t3, and time t4. Time t0a occurs between time t0 and time t0b, and time t0b occurs between time t0a and time t1. Additionally, time t2a occurs between time t2 and time t2b, and time t2b occurs between time t2a and time t3.

[0093] The digital pulse signal 208 transitions periodically between states S1, S2, and S0. For example, the digital pulse signal 208 has state S1 defined by a logic level 0 from time t0 to time t0a. Illustratively, when the digital pulse signal 208 is in state S1, the digital pulse signal 208 is at logic level 0. At time t0a, the digital pulse signal 208 transitions from logic level 0 to logic level 1. State S2 of the digital pulse signal 208 is defined by a logic level 1. Illustratively, when the digital pulse signal 208 is in state S2, the digital pulse signal 208 is at logic level 1.

[0094] The digital pulse signal 208 is in state S2 from time t0a to time t0b. At time t0b, the digital pulse signal 208 transitions from state S2 to state S0, which is defined by logic level 2. By way of example, when the digital pulse signal 208 is in state S0, the digital pulse signal 208 is at logic level 2. The digital pulse signal 208 is in state S0 from time t0b to time t2. At time t2, the digital pulse signal 208 transitions from state S0 back to state S1.

[0095] The digital pulse signal 208 is in state S1 from time t2 to time t2a. At time t2a, the digital pulse signal 208 transitions from state S1 to state S2. The digital pulse signal 208 is in state S2 from time t2a to time t2b. At time t2b, the digital pulse signal 208 transitions from state S2 to state S0. The digital pulse signal 208 is in state S0 from time t2b to time t4. At time t4, the digital pulse signal 208 transitions from state S0 back to state S1.

[0096] It should be noted that states S1, S2, and S0 of digital pulse signal 208 each occur at multiple instances. For example, a first instance of state S1 of digital pulse signal 208 occurs between times t0 and t0a, and a second instance of state S1 of digital pulse signal 208 occurs between times t2 and t2a. As another example, a first instance of state S2 of digital pulse signal 208 occurs between times t0a and t0b, and a second instance of state S2 of digital pulse signal 208 occurs between times t2a and t2b. As yet another example, a first instance of state S0 of digital pulse signal 208 occurs between times t0b and t2, and a second instance of state S0 of digital pulse signal 208 occurs between times t2a and t2b. t2b and t4. As another example, a first instance of state S2 of digital pulse signal 208 is consecutive to a first instance of state S1 of digital pulse signal 208, and a first instance of state S0 of digital pulse signal 208 is consecutive to a first instance of state S2 of digital pulse signal 208. A second instance of state S1 of digital pulse signal 208 is consecutive to a first instance of state S0 of digital pulse signal 208. Also, a second instance of state S2 of digital pulse signal 208 is consecutive to a second instance of state S1 of digital pulse signal 208, and a second instance of state S0 of digital pulse signal 208 is consecutive to a second instance of state S2 of digital pulse signal 208.

[0097] 2C illustrates an embodiment of a graph 210 to illustrate an embodiment of an RF signal 212 generated by RF generator RFGx (FIG. 1) and an embodiment of an RF signal 214 generated by RF generator RFGy (FIG. 1). RF signal 212 is an example of RF signal 102x (FIG. 1), and RF signal 214 is an example of RF signal 102y (FIG. 1).

[0098] The RF signals 212 and 214 are synchronized with the digital pulse signal 208. For example, each of the RF signals 212 and 214 begins a transition from state S1 to state S2 at time t0a when the digital pulse signal 208 transitions from state S1 to state S2. As another example, each of the RF signals 212 and 214 begins a transition from state S2 to state S0 at time t0b when the digital pulse signal 208 transitions from state S2 to state S0. As yet another example, each of the RF signals 212 and 214 begins a transition from state S0 to state S1 at time t2 when the digital pulse signal 208 transitions from state S0 to state S1.

[0099] Graph 210 plots the power levels of RF signals 212 and 214. For example, the y-axis of graph 210 includes power levels P0, P1, P2, P3, and P4. Power level P1 is greater than power level P0. Power level P2 is greater than power level P1, and power level P3 is greater than power level P2. Power level P4 is greater than power level P3.

[0100] A power level as used herein is an envelope (e.g., peak-to-peak amplitude) of an RF signal. For example, power levels P4, P2, and P0 are the envelope of RF signal 102x, and power levels P1, P3, and P0 are the envelope of RF signal 102y. As another example, a power level includes one or more peak-to-peak power values ​​within a predetermined range from the power level (e.g., greater than or less than the value of the power level). As yet another example, a power level is a statistical value (e.g., average or median) of all peak-to-peak power values ​​of the power level. As yet another example, a power level is the highest value of all peak-to-peak power values ​​of the power level. As yet another example, a power level is the lowest value of all peak-to-peak power values ​​of the power level.

[0101] Also, the first power level is different from the second power level, e.g., one or more power values ​​of power level P0 do not include one or more power values ​​of power level P1, and one or more power values ​​of power level P2 do not include one or more power values ​​of each of power levels P0 and P1.

[0102] Graph 210 also plots time t on the x-axis. For example, the x-axis of graph 210 includes times t0, t0a, t0b, t1, t2, t2a, t2b, t3, and t4.

[0103] RF signal 212 periodically transitions between states S1, S2, and S0 of RF signal 212 in a manner described below. Similarly, RF signal 214 periodically transitions between states S1, S2, and S0 of RF signal 214 in a manner described below.

[0104] The state S1 of the RF signal 212 is defined by a power level P4. For example, when the digital pulse signal 208 or the RF signal 212 is in the state S1, the RF signal 212 is at the power level P4.

[0105] The RF signal 212 transitions from state S1 to state S2 within a time window from time t0a. The state S2 of the RF signal 212 is defined by a power level P2. For example, when the digital pulse signal 208 or the RF signal 212 is in state S2, the RF signal 212 is at power level P2.

[0106] It is noted that the RF signal described herein does not transition from one state to the subsequent state instantaneously. For example, the transition of the RF signal 212 from state S1 to state S2 does not occur instantaneously. For example, the transition of the RF signal 212 from state S1 to state S2 occurs within a time window. As another example, as used herein, the time window of a transition from a time is the period of time that occurs during a state after that time. For example, the time window from time t0a is the period of time that the digital pulse signal 208 occurs during state S2 after time t0a. The period of time after time t0a is the period of time that the digital pulse signal 208 occurs during state S2 from time t0a to a time between times t0a and t0b.

[0107] The RF signal 212 transitions from state S2 to state S0 within a time window from time t0b. The state S0 of the RF signal 212 is defined by a power level P0. For example, when the digital pulse signal 208 or the RF signal 212 is in state S0, the RF signal 212 is at the power level P0.

[0108] The RF signal 212 transitions from state S0 to state S1 within a time window from time t2, from state S1 to state S2 within a time window from time t2a, and from state S2 to state S0 within a time window from time t2b.

[0109] Similarly, when the digital pulse signal 208 is in state S1, the RF signal 214 is at power level P1. The state S1 of the RF signal 214 is defined by the power level P1. For example, when the digital pulse signal 208 or the RF signal 214 is in state S1, the RF signal 214 is at power level P1.

[0110] The RF signal 214 transitions from state S1 to state S2 within a time window from time t0a. The state S2 of the RF signal 214 is defined by a power level P3. For example, when the digital pulse signal 208 or the RF signal 214 is in state S2, the RF signal 214 is at power level P3.

[0111] The RF signal 214 transitions from state S2 to state S0 within a time window from time t0b. The state S0 of the RF signal 214 is defined by a power level P0. For example, when the digital pulse signal 208 or the RF signal 214 is in state S0, the RF signal 214 has a power level P0.

[0112] The RF signal 214 transitions from state S0 to state S1 within a time window from time t2, from state S1 to state S2 within a time window from time t2a, and from state S2 to state S0 within a time window from time t2b.

[0113] The state S1 of the RF signal 212 between times t0 and t0a is a first instance of the state S1 of the RF signal 212, and the state S1 of the RF signal 212 between times t2 and t2a is a second instance of the state S1 of the RF signal 212. Similarly, the state S2 of the RF signal 212 between times t0a and t0b is a first instance of the state S2 of the RF signal 212, and the state S2 of the RF signal 212 between times t2a and t2b is a second instance of the state S2 of the RF signal 212. Also, the state S0 of the RF signal 212 between times t0b and t2 is a first instance of the state S0 of the RF signal 212, and the state S0 of the RF signal 212 between times t2b and t4 is a second instance of the state S0 of the RF signal 212.

[0114] Similarly, state S1 of RF signal 214 between times t0 and t0a is a first instance of state S1 of RF signal 214, and state S1 of RF signal 214 between times t2 and t2a is a second instance of state S1 of RF signal 214. Similarly, state S2 of RF signal 214 between times t0a and t0b is a first instance of state S2 of RF signal 214, and state S2 of RF signal 214 between times t2a and t2b is a second instance of state S2 of RF signal 214. Also, state S0 of RF signal 214 between times t0b and t2 is a first instance of state S0 of RF signal 214, and state S0 of RF signal 214 between times t2b and t4 is a second instance of state S0 of RF signal 214.

[0115] 2D shows an embodiment of a graph 215 to illustrate an embodiment of an RF signal 216 generated by RF generator RFGx (FIG. 1) and an embodiment of an RF signal 218 generated by RF generator RFGy (FIG. 1). RF signal 216 is an example of RF signal 102x (FIG. 1), and RF signal 218 is an example of RF signal 102y (FIG. 1).

[0116] Graph 215 plots the power levels of RF signals 216 and 218. Graph 215 also plots time t on the x-axis. For example, the x-axis of graph 215 may be plotted as follows: t1 , t2, t3, t4. Note that the duty cycles of states S1-S3 of RF signals 216 and 218 are different from the duty cycles of states S1-S3 illustrated in FIG 2C. For example, state S1 of RF signals 216 and 218 has a duty cycle of 25%, state S2 of RF signals 216 and 218 has a duty cycle of 40%, and state S3 of RF signals 216 and 218 has a duty cycle of 35%.

[0117] 3A illustrates one embodiment of a graph 302 to illustrate a close-up of a portion of the RF signal 212. The graph 302 plots the power level of the RF signal 212 versus time t. The RF signal 212 transitions from a power level P4 to a power level P2 within a time window from time t0a. For example, the RF signal 212 transitions from a power level P4 to a power level P2 during a period from time t0a to t0a1. Time t0a1 occurs when the RF signal 212 or the digital pulse signal 208 (FIG. 2B) is in state S2 and occurs between times t0a and t0b. Similarly, the RF signal 212 transitions from a power level P2 to a power level P0 within a time window from time t0b.

[0118] 3B illustrates an embodiment of a graph 304 to illustrate a zoomed-in portion of the RF signal 214. The graph 304 plots the power level of the RF signal 214 versus time t. The RF signal 214 transitions from a power level P1 to a power level P3 within a time window from time t0a. For example, the RF signal 214 transitions from a power level P1 to a power level P3 during a period from time t0a to t0a2. Time t0a2 occurs when the RF signal 214 or the digital pulse signal 208 (FIG. 2B) is in state S2 and occurs between times t0a and t0b. Similarly, the RF signal 214 transitions from a power level P3 to a power level P0 within a time window from time t0b.

[0119] FIG. 4A illustrates one embodiment of a graph 202 of a clock signal 204.

[0120] 4B illustrates an embodiment of a graph 402 to illustrate an embodiment of a digital pulse signal 404. The digital pulse signal 404 is an example of the digital pulse signal 108 of FIG. 1. The graph 402 plots the logic levels of the digital pulse signal 404 on the y-axis and time t on the x-axis. The y-axis of the graph 402 includes logic levels 0, 1, and 2. The x-axis of the graph 402 includes times t0, t0a, t1, t1a, t2, t2a, t3, t3a, and t4. Time t1a occurs between times t1 and t2, and time t3a occurs between times t3 and t4.

[0121] The digital pulse signal 404 periodically transitions between states S1, S0, and S2. For example, the digital pulse signal 404 has state S1 defined by logic level 0 from time t0 to time t0a. Illustratively, when in state S1, the digital pulse signal 208 is at logic level 0. The digital pulse signal 404 transitions from logic level 0 to logic level 2 at time t0a. State S0 of the digital pulse signal 404 is defined by logic level 2. Illustratively, when in state S0, the digital pulse signal 404 is at logic level 2.

[0122] The digital pulse signal 404 is in state S0 from time t0a to time t1a. At time t1a, the digital pulse signal 404 transitions from state S0 to state S2, which is defined by a logic level 1. Illustratively, when in state S2, the digital pulse signal 404 is at logic level 1.

[0123] At time t2, the digital pulse signal 404 transitions from state S2 back to state S1. The digital pulse signal 404 is in state S1 from time t2 to time t2a. The digital pulse signal 404 transitions from state S1 to state S0 at time t2a. The digital pulse signal 404 is in state S0 from time t2a to time t3a. At time t3a, the digital pulse signal 404 transitions from state S0 to state S2. The digital pulse signal 404 is in state S2 from time t3a to time t4. At time t4, the digital pulse signal 404 transitions from state S2 back to state S1.

[0124] It should be noted that each of the states S1, S0, and S2 of the digital pulse signal 404 occurs at multiple instances. For example, a first instance of the state S1 of the digital pulse signal 404 occurs between times t0 and t0a, and a second instance of the state S1 of the digital pulse signal 404 occurs between times t2 and t2a. As another example, a first instance of the state S0 of the digital pulse signal 404 occurs between times t0a and t1a, and a second instance of the state S0 of the digital pulse signal 404 occurs between times t2a and t3a. As yet another example, a first instance of the state S2 of the digital pulse signal 404 occurs between times t1a and t2, and a second instance of the state S2 of the digital pulse signal 404 occurs between times t3a and t4. As another example, a first instance of the state S0 is consecutive to a first instance of the state S1 of the digital pulse signal 404, and a first instance of the state S2 of the digital pulse signal 404 is consecutive to a first instance of the state S0. The second instance of state S1 of the digital pulse signal 404 is successive to a first instance of state S2 of the digital pulse signal 404. Also, the second instance of state S0 of the digital pulse signal 404 is successive to a second instance of state S1 of the digital pulse signal 404, and the second instance of state S2 of the digital pulse signal 404 is successive to a second instance of state S0 of the digital pulse signal 404.

[0125] 4C illustrates an embodiment of a graph 406 to illustrate an embodiment of an RF signal 408 generated by RF generator RFGx (FIG. 1) and an embodiment of an RF signal 410 generated by RF generator RFGy (FIG. 1). RF signal 408 is an example of RF signal 102x (FIG. 1), and RF signal 410 is an example of RF signal 102y (FIG. 1).

[0126] The RF signals 408 and 410 are synchronized with the digital pulse signal 404. For example, each of the RF signals 408 and 410 begins a transition from state S1 to state S0 at the time the digital pulse signal 404 transitions from state S1 to state S0. As another example, each of the RF signals 408 and 410 begins a transition from state S0 to state S2 at the time the digital pulse signal 404 transitions from state S0 to state S2. As yet another example, each of the RF signals 408 and 410 begins a transition from state S2 to state S1 at the time the digital pulse signal 404 transitions from state S2 to state S1.

[0127] Graph 406 plots the power levels of RF signals 408 and 410. For example, the y-axis of graph 406 includes power levels P0, P1, P2, P3, and P4. Graph 406 also plots time t on the x-axis. For example, the x-axis of graph 406 includes times t0, t0a, t1, t1a, t2, t2a, t3, t3a, and t4.

[0128] The RF signal 408 periodically transitions between the RF signal 408 states S1, S0, and S2 in a manner described below. Similarly, the RF signal 410 periodically transitions between the RF signal 410 states S1, S0, and S2 in a manner described below.

[0129] The state S1 of the RF signal 408 is defined by a power level P4. For example, when the digital pulse signal 404 or the RF signal 408 is in the state S1, the RF signal 408 is at the power level P4.

[0130] The RF signal 408 transitions from state S1 to state S0 within a time window from time t0a. The state S0 of the RF signal 408 is defined by a power level P0. For example, when the digital pulse signal 404 or the RF signal 408 is in state S0, the RF signal 408 is at the power level P0.

[0131] The RF signal 408 transitions from state S0 to state S2 within a time window from time t1a. The state S2 of the RF signal 408 is defined by a power level P2. For example, when the digital pulse signal 404 or the RF signal 408 is in state S2, the RF signal 408 is at the power level P2.

[0132] The RF signal 408 transitions from state S2 to state S1 within a time window from time t2, transitions from state S1 to state S0 within a time window from time t2a, and transitions from state S0 to state S2 within a time window from time t3a.

[0133] Similarly, when the digital pulse signal 404 is in state S1, the RF signal 410 is at power level P1. The state S1 of the RF signal 410 is defined by the power level P1. For example, when the digital pulse signal 404 or the RF signal 410 is in state S1, the RF signal 410 is at power level P1.

[0134] The RF signal 410 transitions from state S1 to state S0 within a time window from time t0a. The state S0 of the RF signal 410 is defined by a power level P0. For example, when the digital pulse signal 404 or the RF signal 410 is in state S0, the RF signal 410 is at the power level P0.

[0135] The RF signal 410 transitions from state S0 to state S2 within a time window from time t1a. The state S2 of the RF signal 410 is defined by a power level P3. For example, when the digital pulse signal 404 or the RF signal 410 is in state S2, the RF signal 410 is at power level P3.

[0136] The RF signal 410 transitions from state S2 to state S1 within a time window from time t2, transitions from state S1 to state S0 within a time window from time t2a, and transitions from state S0 to state S2 within a time window from time t3a.

[0137] The state S1 of the RF signal 408 between times t0 and t0a is a first instance of the state S1 of the RF signal 408, and the state S1 of the RF signal 408 between times t2 and t2a is a second instance of the state S1 of the RF signal 408. Similarly, the state S0 of the RF signal 408 between times t0a and t1a is a first instance of the state S0 of the RF signal 408, and the state S0 of the RF signal 408 between times t2a and t3a is a second instance of the state S0 of the RF signal 408. Also, the state S2 of the RF signal 408 between times t1a and t2 is a first instance of the state S2 of the RF signal 408, and the state S2 of the RF signal 408 between times t3a and t4 is a second instance of the state S2 of the RF signal 408.

[0138] Similarly, state S1 of the RF signal 410 between times t0 and t0a is a first instance of state S1 of the RF signal 410, and state S1 of the RF signal 410 between times t2 and t2a is a second instance of state S1 of the RF signal 410. Similarly, state S0 of the RF signal 410 between times t0a and t1a is a first instance of state S0 of the RF signal 410, and state S0 of the RF signal 410 between times t2a and t3a is a second instance of state S0 of the RF signal 410. Also, state S2 of the RF signal 410 between times t1a and t2 is a first instance of state S2 of the RF signal 410, and state S2 of the RF signal 410 between times t3a and t4 is a second instance of state S2 of the RF signal 410.

[0139] 4D illustrates an embodiment of a graph 411 to explain an embodiment of an RF signal 412 generated by RF generator RFGx (FIG. 1) and an embodiment of an RF signal 414 generated by RF generator RFGy (FIG. 1). RF signal 414 is an example of RF signal 102x (FIG. 1), and RF signal 416 is an example of RF signal 102y (FIG. 1).

[0140] Graph 411 plots the power levels of RF signals 414 and 416. Graph 411 also plots time t on the x-axis. For example, the x-axis of graph 411 includes times t0, t2, t2, t3, and t4. Note that the duty cycles of states S1-S3 of RF signals 414 and 416 are different from the duty cycles of states S1-S3 illustrated in FIG. 4C. For example, the duty cycle of state S1 of RF signals 414 and 416 is 25%, the duty cycle of state S2 of RF signals 414 and 416 is 40%, and the duty cycle of state S3 of RF signals 414 and 416 is 35%.

[0141] 5A illustrates one embodiment of a graph 502 to illustrate a zoomed-in portion of the RF signal 408. The graph 502 plots the power level of the RF signal 408 versus time t. The RF signal 408 transitions from a power level P4 to a power level P0 within a time window from time t0a. For example, the RF signal 408 transitions from a power level P4 to a power level P0 during a period from time t0a to time t0a1. Time t0a1 occurs when the RF signal 408 and the digital pulse signal 404 (FIG. 4B) are in state S0 and occurs between times t0a and t1a. Similarly, the RF signal 408 transitions from a power level P0 to a power level P2 within a time window from time t1a.

[0142] 5B illustrates an embodiment of a graph 504 to illustrate a close-up of a portion of the RF signal 410. The graph 504 plots the power level of the RF signal 410 versus time t. The RF signal 410 transitions from a power level P1 to a power level P0 within a time window from time t0a. For example, the RF signal 410 transitions from a power level P1 to a power level P0 during a period from time t0a to time t0a2. Time t0a2 occurs when the RF signal 410 and the digital pulse signal 404 (FIG. 4B) are in state S0 and occurs between times t0a and t1a. Similarly, the RF signal 214 transitions from a power level P0 to a power level P3 within a time window from time t1a.

[0143] FIG. 6 illustrates an embodiment of a table 600 for describing duty cycles associated with states S1, S2, and S0, and power levels in states S1, S2, and S0. As an example, the duty cycle of state S1 of RF signal 102x (FIG. 1) or digital pulse signal 108 (FIG. 1) is in the range of 3% to 25% (inclusive) of the cycle of clock signal 204 (FIG. 2A). By way of example, the duty cycle of state S1 of RF signal 102x or digital pulse signal 108 is in the range of 3% to 5% (inclusive) of the cycle of clock signal 204. As another example, the duty cycle of state S1 of RF signal 102y (FIG. 1) or digital pulse signal 108 is in the range of 3% to 25% (inclusive) of the cycle of clock signal 204 (FIG. 2A). Illustratively, the duty cycle of state S1 of RF signal 102y or digital pulse signal 108 is in the range of 3% to 5% of the cycle of clock signal 204, inclusive.

[0144] As yet another example, the duty cycle of state S2 of RF signal 102x or digital pulse signal 108 is in the range of 3% to 50% (inclusive) of the cycle of clock signal 204. S2The duty cycle of state S2 of RF signal 102y or digital pulse signal 108 is in the range of 3% to 5% (inclusive) of the cycle of clock signal 204. As another example, the duty cycle of state S2 of RF signal 102y or digital pulse signal 108 is in the range of 3% to 50% (inclusive) of the cycle of clock signal 204. By way of illustration, the duty cycle of state S2 of RF signal 102y or digital pulse signal 108 is in the range of 3% to 5% (inclusive) of the cycle of clock signal 204.

[0145] As yet another example, the duty cycle of state S0 of RF signal 102x or digital pulse signal 108 is in the range of 25% to 94% (inclusive) of the cycle of clock signal 204. As another example, the duty cycle of state S2 of RF signal 102y or digital pulse signal 108 is in the range of 25% to 94% (inclusive) of the cycle of clock signal 204.

[0146] As another example, in state S1, the ratio of the power level of the RF signal 102x to the power level of the RF signal 102y is in the range of 6 to 10 (including the boundary). For example, the power level of the RF signal 102x is 10 kilowatts (kW), and the power level of the RF signal 102y is 1 kW. It should be noted that the duty cycle of the RF signals 102x and 102y in state S1, and the power level ratio of the RF signals 102x and 102y in state S1, enhances the mask selection ratio, which will be described further below. As yet another example, in state S2, the ratio of the power level of the RF signal 102x to the power level of the RF signal 102y is in the range of 0.2 to 1 (including the boundary). As another example, in state S2, the ratio of the power level of the RF signal 102x to the power level of the RF signal 102y is in the range of 0.2 to less than 1 (including the boundary). Examples of ratios less than 1 are 0.4, 0.45, 0.5, 0.8, or 0.9. For example, in state S2, the power level of RF signal 102x is 2 kW, and the power level of RF signal 102y is 5 kW. As another example, in state S2, the power level of RF signal 102x is 20% to 100% of the power level of RF signal 102y. As yet another example, in state S2, the power level of RF signal 102x is less than 20% to 100% of the power level of RF signal 102y. As another example, in state S2, the power level of RF signal 102x is not about zero, and the power level of RF signal 102y is not about zero. For further example, the power level of RF signal 102x in state S2 is not in the range of 0 to 300 watts, and the power level of RF signal 102y in state S2 is not in the range of 0 to 300 watts. It should be noted that the duty cycle of RF signals 102x and 102y in state S2 and the power level ratio of RF signals 102x and 102y in state S2 enhance passivation of the warp, as will be further described below.As another example, in state S0, the power level of RF signal 102x is in the range of 0 to 300 watts (inclusive) and the power level of RF signal 102y is in the range of 0 to 300 watts (inclusive).

[0147] It should be noted that when the RF signals 102x and 102y are in state S0, the power levels of the RF signals 102x and 102y are approximately equal. For example, when the RF signals 102x and 102y are in state S0, the power levels of the RF signals 102x and 102y are within a predetermined range from each other. For example, when the RF signal 102x is in state S0, the power level of the RF signal 102x is in a range of 0 to 300 watts, and when the RF signal 102y is in state S0, the power level of the RF signal 102y is in a range of 0 to 300 watts. As another example, when the RF signals 102x and 102y are in state S0, the power levels of the RF signals 102x and 102y are zero.

[0148] Furthermore, the state S1~ of the RF signal 102x S0 The sum or sum of the duty cycles of the clock signals 204 is equal to 100 percent of the clock cycle of the clock signal 204. For example, a first instance of states S1, S2, S0 of each of the RF signals 102x and 102y occupies cycle 1 of the clock signal 204 (FIG. 2A), and a second instance of states S1, S2, S0 of each of the RF signals 102x and 102y occupies cycle 2 of the clock signal 204 (FIG. 2A).

[0149] In one embodiment, the duty cycle of a state of an RF signal is the time period during which the RF signal has a unique power level. For example, the duty cycle of state S1 of RF signal 212 is the time period from time t0 to t0a during which the RF signal 212 has power level P4. As another example, the duty cycle of state S2 of RF signal 212 is the time period from time t0a to t0b during which the RF signal 212 has power level P2. As yet another example, the duty cycle of state S0 of RF signal 212 is the time period from time t0b to t2 during which the RF signal 212 has power level P0. As another example, the duty cycle of state S1 of RF signal 214 is the time period from time t0 to t0a during which the RF signal 214 has power level P1. As yet another example, the duty cycle of state S2 of RF signal 214 is the time period from time t0a to t0b during which the RF signal 214 has power level P3. As yet another example, the duty cycle of state S0 of RF signal 214 is the period from time t0b to t2 during which RF signal 214 has power level P0.

[0150] FIG. 7A is a perspective view of an embodiment of a substrate stack 700. The substrate stack 700 is an example of a substrate S before being processed in the plasma chamber 106 (FIG. 1). The substrate stack 700 includes a substrate layer 714 formed of silicon. The substrate stack 700 further includes a stop layer 712 deposited on the substrate layer 714. An example of the stop layer 712 is an etch stop layer made of a dielectric material such as an oxide or a nitride. An oxide layer 710 is deposited on the stop layer 712. A silicon nitride (SiN) layer 708 is deposited on the oxide layer 710, an oxide layer 706 is deposited on the silicon nitride layer 708, another silicon nitride layer 704 is deposited on the oxide layer 706, and a mask layer 702 is deposited on the silicon nitride layer 704. The mask layer 702 is a photolithography mask that is an opaque plate or film.

[0151] In one embodiment, a nitride layer is used in place of oxide layer 706. Similarly, in one embodiment, a nitride layer is used in place of oxide layer 710.

[0152] 7B illustrates one embodiment of a substrate stack 720 to illustrate the balance between a passivation layer 722 deposited over feature 702B of mask layer 702 (FIG. 7A) and a passivation layer 724 deposited over feature 704B of silicon nitride layer 704 (FIG. 7A). Substrate stack 720 includes features 702A and 702B of mask layer 702, features 704A and 704B of silicon nitride layer 704, features 706A and 706B of oxide layer 706 (FIG. 7A), silicon nitride layer 708, and oxide layer 710. The remaining layers 712 and 714 of substrate stack 720 (FIG. 7A) are omitted from FIG. 7B.

[0153] The substrate stack 720 is fabricated by etching the substrate stack 700 of FIG. 7A in the plasma chamber 106 (FIG. 1). The substrate stack 720 is an example of the substrate S (FIG. 1) after etching a portion of the substrate stack 700. The substrate stack 700 is etched to achieve a balance between the passivation layer 722 and the passivation layer 724 by providing the plasma chamber 106 with an integrated modified RF signal 124 (FIG. 1) generated based on the RF signals 102x and 102y (FIG. 1). For example, the balance between the passivation layer 722 and the passivation layer 724 is achieved by depositing the passivation layers 722 and 724 in a substantially equal manner over the features of the mask layer 702 and the silicon nitride layer 704, respectively. Illustratively, the width of the passivation layer 722 is substantially equal to the width of the passivation layer 724.

[0154] The substantially uniform passivation by the passivation layer 724 controls warpage. For example, the substantially uniform passivation by the passivation layer 724 prevents warpage from forming on the sidewalls of features in the silicon nitride layer 704. As an example, a passivation layer is a layer that is deposited on or around another layer when a modified RF signal 124 is applied to the substrate S. Illustratively, the passivation layers 722 and 724 include a combination of materials that are part of the substrate stack 720 (e.g., silicon nitride and oxide) and a combination of materials from one or more process gases.

[0155] In the case of two-state pulsing, the RF signal periodically switches between a first state and a second state during one clock cycle of the clock signal. In the first state of the two-state pulsing, the mask selectivity is high and the passivation level of the feature 702B is high, but the passivation of the feature 704B is negligible or minimal. In addition, in the first state, the passivation level of the feature 702B is high, but the passivation of the feature 704B is negligible or minimal, resulting in bowing of the feature 704B. This bowing is undesirable. In addition, in the second state of the two-state pulsing, the mask selectivity is low compared to the first state and the passivation level of the feature 704B is high, but the passivation of the feature 702B is minimal or negligible. Thus, in the two-state pulsing, there is an imbalance between the passivation of the feature 702B and the passivation of the feature 704B, resulting in bowing. This imbalance results in a relatively high amount of passivation for feature 702B compared to feature 704B in a first state and a relatively low amount of passivation for feature 702B compared to feature 704B in a second state. 702B This occurs due to a relatively large amount of passivation in feature 704B compared to feature 704. By pulsing RF signals 102x and 102y in the manner described with reference to Figures 2A-2C or 4A-4C, a balance of passivation in features 702B and 704B is achieved, reducing or eliminating bowing.

[0156] Furthermore, pulsing of RF signals 102x and 102y as described with reference to Figures 2A-2C or 4A-4C increases the mask selectivity as compared to two-state pulsing. The mask selectivity is, for example, the ratio of the etch rate of any of layers 704-710 of substrate stack 700 (Figure 7A) to the etch rate of mask layer 702. The higher the mask selectivity, the faster substrate stack 700 (Figure 7A) will be etched, and the lower the mask selectivity, the slower substrate stack 700 will be etched.

[0157] Pulsing of RF signals 102x and 102y as described with reference to FIGS. 2A-2C or 4A-4C facilitates achieving a balance between mask selectivity and warpage control. Warpage control is achieved by passivation of the sidewalls (e.g., sidewall 734) of features in silicon nitride layer 704. For example, mask selectivity is increased by reducing the amount of passivation of mask layer 702 achieved by pulsing RF signals 102x and 102y in the manner described with reference to FIGS. 2A-2C or 4A-4C compared to the amount of passivation achieved by two-state pulsing. Additionally, increasing the amount of passivation of the sidewalls of features formed by etching silicon nitride layer 704 compared to the amount of sidewall passivation achieved by application of two-state pulsing is achieved by using integrated modified RF signal 124 (FIG. 1). Increasing the amount of passivation on the sidewalls of features formed by etching silicon nitride layer 704 reduces or eliminates bowing in the sidewalls of features formed by etching silicon nitride layer 704, and reducing or eliminating bowing increases mask selectivity.

[0158] Pulsing the RF signals 102x and 102y facilitates achieving both warpage control and mask selectivity simultaneously. By managing the pulsing of the RF signals 102x and 102y, an optimal balance can be achieved between achieving both warpage control and mask selectivity while minimizing any trade-offs or compromises associated with two-state pulsing.

[0159] FIG. 7C is an expanded view of a portion 730 of the substrate stack 720 (FIG. 7B). The portion 730 includes a feature 702B of the mask layer 702 (FIG. 7A), a feature 704B of the silicon nitride layer 704 (FIG. 7A), and a feature 706B of the oxide layer 706 (FIG. 7A). Also shown in FIG. 7C is a bow 732 shown in dashed lines. The bow 732 is formed on a sidewall 734 of the feature 704B, which faces the sidewall 726 of the feature 704A (FIG. 7B), and a gap is formed between the sidewalls 726 and 734 when the substrate stack 700 (FIG. 7A) is etched. Note that the bow 732 is formed when a two-state pulse is applied to the substrate S. However, when the pulsing of RF signals 102x and 102y described with reference to Figures 2A-2C or 4A-4C is applied to substrate S via integrated modified RF signal 124 (Figure 1), bow 732 is reduced or does not form. When the pulsing of RF signals 102x and 102y described with reference to Figures 2A-2C or 4A-4C achieves a balance of passivation of features 702B and 704B, bow 732 is reduced or does not form.

[0160] Warpage control is achieved when the warpage 732 is reduced or does not form so as to achieve or maintain a predetermined critical dimension. For example, a predetermined critical dimension (CD) that is a predetermined width between a sidewall 734 in feature 704B of silicon nitride layer 704 and a similar sidewall in feature 704A is achieved with effective warpage control. The predetermined width is less than the width (e.g., horizontal distance) between the warpage 732 and a similar warpage formed in the sidewall of feature 704A.

[0161] Figure 7D illustrates an embodiment of a substrate stack 740 after processing of the substrate stack 700 (Figure 7A) using the method described with reference to Figures 2A-2C or 4A-4C. Substrate stack 740 is an example of a substrate stack S after application of pulses of RF signals 102x and 102y to substrate stack 700 as described with reference to Figures 2A-2C or 4A-4C.

[0162] The substrate stack 740 includes features of the mask layer 702 (FIG. 7A), features of the silicon nitride layer 704 (FIG. 7A), features of the oxide layer 706 (FIG. 7A), features of the silicon nitride layer 708 (FIG. 7A), features of the oxide layer 710 (FIG. 7A), and features of the stop layer 712 (FIG. 7A). A passivation layer 742 including multiple passivation portions, such as passivation layer 722 (FIG. 7C) and passivation layer 724 (FIG. 7C), is deposited over features 702B, 704B, 706B, feature 708B of the silicon nitride layer 708, feature 710B of the oxide layer 710, and feature 712B of the stop layer 712. The passivation layer 742 is deposited when the substrate stack 700 is subjected to a combined modified RF signal 124 that is generated based on the RF signals 102x and 102y described with reference to FIGS. 2A-2C or 4A-4C.

[0163] FIG. 8 is a schematic flow chart of an embodiment. A stack is prepared (step 804). FIG. 9A is a schematic cross-sectional view of a stack 904 processed according to an embodiment. The stack 904 includes a substrate 908. One or more intermediate layers 912, such as an etch stop layer, may be provided above the substrate 908. A first silicon oxide (SiO2) layer 916 is provided above the one or more intermediate layers 912. A first silicon nitride (SiN) layer 920 is provided above the first SiO2 layer 916. A second SiO2 layer 924 is provided above the first SiN layer 920. A second SiN layer 928 is provided above the second SiO2 layer 924. A patterned mask 932 is provided above the second SiN layer 928. In various embodiments, one or more layers may be provided between the patterned mask 932 and the second SiN layer 928. In various embodiments, the stack 904 may further include alternating layers of SiN and SiO2. In other embodiments, the stack 904 may include layers of other materials. In various embodiments, the stack 904 includes a silicon-containing layer. In this embodiment, the patterned mask 932 is a hard mask, such as polysilicon.

[0164] The stack 904 may be placed in a plasma chamber 106. An etching gas is flowed into the plasma chamber 106 (step 808). In this embodiment, the etching gas includes a metal fluoride or tungsten-containing passivation agent and an etching component. In this embodiment, the metal fluoride or tungsten-containing passivation agent is tungsten hexafluoride (WF6). In this embodiment, the etching component includes oxygen (O2) and a fluorocarbon, such as hexafluorobutadiene (C4F6) and / or octafluorocyclobutane (C4F8).

[0165] A multi-state pulsing scheme is performed to generate the etching gas into a plasma, thereby etching the stack 904. (Step 812)In this embodiment, the multi-state pulsing scheme includes generating a primary RF signal in a first frequency range and generating a secondary RF signal in a second frequency range, where the first frequency range is less than the second frequency range. The primary RF signal and the secondary RF signal are pulsed between at least three states including a first state, a second state, and a third state. As an example, the frequency of the primary RF signal is 400 kHz and the frequency of the secondary RF signal is 60 MHz. The first state has a duty cycle of 3% to 20%, a power level of the primary RF signal is 17 kW to 30 kW, and a power level of the secondary RF signal is greater than 5 kW. As a more specific example, the first state has a duty cycle of 3% to 5%, and a power level of the primary RF signal is 29 kW. The second state has a duty cycle of 3% to 40%, a power level of the primary RF signal is greater than 8 kW, and a power level of the secondary RF signal is greater than 3 kW. As a more specific example, the second state has a duty cycle of 3% to 5%, a power level of the primary RF signal is 13 kW, and a power level of the secondary RF signal is 5 kW. The third state has a duty cycle of 40% to 94%, a power level of the primary RF signal is less than 2 kW, and a power level of the secondary RF signal is 1 kW. As a specific example, the third state has a duty cycle of 90% to 94%, a power level of the primary RF signal is 0 kW, and a power level of the secondary RF signal is 0 kW. In one embodiment, a ratio of the power level of the primary RF signal in the first state to the power level of the secondary RF signal in the first state is greater than 1, and a ratio of the power level of the primary RF signal in the second state to the power level of the secondary RF signal in the second state is less than 1.

[0166] FIG. 9B is a schematic cross-sectional view of the stack 904 after etching is completed. A feature 940 has been etched into the stack 904 by the etching process described above with the etching gas flow (step 808) and the multi-state pulsing scheme. In this embodiment, the feature 940 is a contact hole. In this embodiment, a single etch recipe can selectively etch the first and second silicon oxide layers 916, 924 and the first and second silicon nitride layers 920, 928. Without the metal fluoride or tungsten-containing passivation agent, bowing can occur, as shown by the dotted line 948. With the addition of the metal fluoride or tungsten-containing passivation agent alone, necking can occur, as shown by the dotted line 944. The combination of the metal fluoride or tungsten-containing passivation agent with the multi-state pulsing scheme allows tuning to prevent necking and bowing while achieving high etch selectivity. It is believed that the multi-state pulsing scheme of this embodiment having three power levels provides an ion flux and bias energy that can prevent necking while using metal fluorides or tungsten-containing passivation agents. In this embodiment, the etch selectivity ratio for etching the dielectric stack relative to the polysilicon mask is at least 2:1. More specifically, the etch selectivity ratio for etching the dielectric stack relative to the polysilicon mask is between 2:1 and 3:1.

[0167] In another embodiment, the power level of the primary RF signal in the second state is less than 80% of the power level of the primary RF signal in the first state. The power level of the primary RF signal in the third state is less than 20% of the power level of the primary RF signal in the second state. The power level of the secondary RF signal in the third state is less than 20% of the power level of the secondary RF signal in the second state. The first state has a duty cycle between 3% and 25%. The second state has a duty cycle between 3% and 50%. The third state has a duty cycle between 25% and 94%. In some embodiments, the duty cycle of the first state is less than the duty cycle of the third state. The duty cycle of the second state is less than the duty cycle of the third state.

[0168] In various embodiments, the first frequency range may be a frequency range of 80 kHz to 14 MHz. The first frequency range is used to create a bias for ion bombardment. The second frequency range may be a frequency range of 15 MHz to 120 MHz. The second frequency range is used to excite the plasma. The second frequency range may also be used to control the plasma density, ion flux, and degree of dissociation of the plasma. In various embodiments, the metal fluoride or tungsten-containing passivation agent is tungsten fluoride. Tungsten fluoride may include tungsten hexafluoride, tungsten pentafluoride chloride (WClF5), and tungsten tetrafluoride dichloride (WCl2F4). In other embodiments, another tungsten-containing passivation agent is tungsten fluoride WF x Cl y (x+y=4, 5, 6) or WO x F y (2x+y=4, 5, 6). For example, the tungsten-containing passivation agent may be WO2F2, WOF4, or WCl2F4.

[0169] In various embodiments, the stack has at least one silicon oxide layer. The stack includes a silicon-based layer. In various embodiments, the mask is a hard mask, such as polysilicon. In other embodiments, the stack includes alternating silicon oxide and silicon nitride layers. In various embodiments, High Aspect Ratio (HAR) features are provided having a height / width ratio of greater than 20:1.

[0170] In various embodiments, the etching gas has a molar ratio of tungsten-containing passivation material to total etching gas flow of between 1:10 and 1:100.

[0171] 10 is a schematic diagram of an etch reactor that can be used in one embodiment. In one or more embodiments, a plasma processing system 1000 includes a gas distribution plate 1006 that provides a gas inlet into a plasma processing chamber 1049 surrounded by a chamber wall 1052, and an electrostatic chuck (ESC) 1008. In the plasma processing chamber 1049, a stack 1018 is disposed on or above the ESC 1008. The ESC 1008 may provide a bias from an ESC source 1048. A primary RF signal from the ESC source 1048 provides a bias at the ESC 1008. An etching gas source 1010 is connected to the plasma processing chamber 1049 through the gas distribution plate 1006. In this embodiment, the etching gas source 1010 may include a polymer passivation agent source 1012, an etching component gas source 1017, and a WF6 (or tungsten-containing passivation agent) source 1016. An ESC temperature controller 1050 is connected to the cooler 1014. In this embodiment, the cooler 1014 provides coolant to the flow path 1005 in or near the ESC 1008. A radio frequency (RF) source 1030 provides RF power to the lower electrode and / or the upper electrode (in this embodiment, the ESC 1008 and the gas distribution plate 1006). In this embodiment, a secondary RF signal may be provided by the RF source 1030. The secondary RF signal may be used to provide energy to form the plasma. In an exemplary embodiment, 400 kHz, 60 MHz, and optional configurations of 2 MHz, 27 MHz power sources constitute the RF source 1030 and the ESC source 1048. The RF source 1030 and the ESC source 1048 may include RF generators RFGx, RF generators RFGy, and impedance matching network IMN as shown in FIG. 1. In this embodiment, the upper electrode is grounded. In this embodiment, one generator is provided for each frequency. In other embodiments, multiple generators may be provided in separate RF sources, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have an inner electrode and an outer electrode connected to different RF sources. In other embodiments, other configurations of RF sources and electrodes may be used.A controller 1035 is controllably connected to the RF source 1030, the ESC source 1048, the exhaust pump 1020, and the etching gas source 1010. An example of such an etching chamber is the modified Exelan Flex manufactured by Lam Research Corporation (Fremont, Calif.). TM The process chamber may be a Capacitively Coupled Plasma (CCP) reactor or an Inductively Coupled Plasma (ICP) reactor. In other embodiments, other types of plasma processing chambers may be used, such as dielectric and conductive etch chambers or deposition chambers.

[0172] In other embodiments, multiple chambers of different sizes may be provided. These chambers may use different relative powers. For example, a larger chamber may use RF power equal to or greater than 120 kW. In other embodiments, other states may be added. Thus, a fourth or fifth state may exist.

[0173] The embodiments described herein may be practiced with a variety of computer system configurations including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments described herein may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0174] In some embodiments, the controller is part of a system, which may be part of the examples described above. The system includes semiconductor processing equipment including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer pedestal and a gas flow system). The system is integrated with electronics for controlling the operation of the system before, during, and after processing of a semiconductor wafer or substrate. The electronics may also be referred to as a "controller" and may control various components or sub-parts of the system. The controller is programmed to control any of the processes disclosed herein depending on the processing requirements and / or type of system. The processes include supply of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow settings, fluid supply settings, position and motion settings, wafer loading and unloading from the tool, and wafer loading and unloading from other transport tools and / or load locks connected or associated with the system.

[0175] In various embodiments, a controller is broadly defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, sends instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include chips as firmware that store program instructions, DSPs, chips defined as ASICs, PLDs, one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller as various individual settings (or program files) that define operational parameters for performing a process on or for a semiconductor wafer. In some embodiments, the operational parameters are part of a recipe defined by a process engineer to accomplish one or more processing steps in the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0176] In some embodiments, the controller is part of or coupled to a computer, where the computer is integral to the system, coupled to the system, or otherwise networked with the system, or a combination thereof. For example, the controller may reside on the "cloud" or in all or part of a fab host computer system, allowing remote access to wafer processing. The computer enables remote access to the system to monitor the progress of a manufacturing process, examine past manufacturing process history, or examine trends or performance indicators from multiple manufacturing processes, change parameters of a current process, set up processing steps following a current process, or initiate a new process.

[0177] In some embodiments, a process recipe is provided to the system from a remote computer (e.g., a server) over a computer network, where the network includes a local network or the Internet. The remote computer includes a user interface that allows for input or programming of parameters and / or settings. These parameters and / or settings are then communicated from the remote computer to the system. In some examples, the controller receives instructions as settings for processing the wafer. It should be understood that these settings are specific to the type of process to be performed on the wafer and the type of tool the controller interfaces with or controls. Thus, as described above, the controller is distributed, such as by having one or more individual controllers. These individual controllers are networked and operate toward a common goal, such as accomplishing the processes described herein. An example of a distributed controller for such a purpose includes one or more integrated circuits mounted on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of the remote computer). These integrated circuits cooperate to control the process in the chamber.

[0178] In various embodiments, the plasma systems described herein include, by way of non-limiting example, a plasma etch chamber, a deposition chamber, a spin rinse chamber, a metal plating chamber, a cleaning chamber, a bevel edge etch chamber, a physical vapor deposition (PVD) chamber, a chemical vapor deposition (CVD) chamber, an atomic layer deposition (ALD) chamber, an atomic layer etch (ALE) chamber, an ion implantation chamber, a track chamber, or any other semiconductor processing chamber associated with or used in the manufacturing and / or production of semiconductor wafers.

[0179] Additionally, although the above operations are described with reference to a parallel plate plasma chamber (e.g., a capacitively coupled plasma chamber, etc.), in some embodiments, the above operations apply to other types of plasma chambers, such as an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, a plasma chamber including a conductor tool, a dielectric tool, or an electron cyclotron resonance (ECR) reactor. For example, an X MHz RF generator, a Y MHz RF generator, and a Z MHz RF generator are coupled to an inductor in an ICP plasma chamber.

[0180] As described above, depending on the process steps being performed by the tool, the controller communicates with one or more of other tool circuits or tool modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from wafer containers to tool locations and / or load ports within a semiconductor manufacturing factory.

[0181] With the above embodiments in mind, it should be understood that some embodiments employ various computer-implemented operations with data stored in computer systems. These computer-implemented operations manipulate physical quantities.

[0182] Some embodiments also relate to a hardware unit or apparatus for performing these operations. The apparatus is specially configured for a special purpose computer. When defined as a special purpose computer, the computer is operable for a specific purpose, but also performs other processes, program executions, or routines that are not included in the specific purpose.

[0183] In some embodiments, the operations described herein are executed by a selectively activated computer, configured by one or more computer programs stored in a computer memory, or obtained over a computer network. If data is obtained over a computer network, the data may be processed by other computers on the computer network (e.g., a cloud of computing resources).

[0184] One or more embodiments described herein may be manufactured as computer readable code recorded on a non-transitory computer readable medium. The non-transitory computer readable medium is any data storage hardware unit (e.g., memory device, etc.) that stores data. The data is then read by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disk ROM (CD-ROM), CD recordable (CD-R), CD rewriteable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer readable medium includes a tangible computer readable medium distributed over a network-coupled computer system such that the computer readable code is stored and executed in a distributed manner.

[0185] It should be noted that while some of the method steps above are shown in a particular order, in various embodiments, other housekeeping steps may be performed between these method steps, these method steps may be coordinated to occur at slightly different times, these method steps may be distributed in a system that allows these method steps to occur at various intervals, or the method steps may be performed in a different order than that shown above.

[0186] Furthermore, it should be noted that in one embodiment, one or more features of any of the above embodiments may be combined with one or more features of any of the other embodiments without departing from the scope of the various embodiments described in this disclosure.

[0187] Although the above embodiments have been described in some detail for purposes of clarity of understanding, it is apparent that some modifications and variations can be made within the scope of the appended claims. Therefore, the present embodiments should be considered as merely illustrative and not limiting of the present disclosure, and the embodiments are not limited to the details described herein, but may be modified within the scope of the appended claims and their equivalents.

Claims

1. 1. A multi-state pulsing method for achieving a balance between mask selectivity and sidewall bow control of an etched feature, comprising: generating a primary radio frequency (RF) signal pulsed between three states including a first state, a second state, and a third state; generating a secondary RF signal pulsed between the three states, the primary RF signal and the secondary RF signal being generated to form a plasma from an etching gas; In the first state, a power level of the primary RF signal is greater than a power level of the secondary RF signal; In the second state, a power level of the secondary RF signal is greater than a power level of the primary RF signal; In the third state, the power levels of the primary RF signal and the secondary RF signal are equal to one another. method.

2. 2. The method of claim 1 , a duty cycle of the first state is less than a duty cycle of the third state, and a duty cycle of the second state is less than the duty cycle of the third state. method.

3. 2. The method of claim 1 , a duty cycle of the first state ranging from 3 percent to 25 percent of a clock cycle of the clock signal; method.

4. 4. The method of claim 3, the duty cycle of the second state is in the range of 3 percent to 50 percent of the clock cycle of the clock signal. method.

5. 5. The method of claim 4, the third state has a duty cycle, the sum of the duty cycles of the first, second, and third states being equal to 100 percent of the clock cycle. method.

6. 3. The method of claim 2, the power level of the primary RF signal in the first state, the power level of the secondary RF signal in the second state, the duty cycle of the first state, and the duty cycle of the second state facilitate achieving a balance between the warpage control and the mask selectivity. method.

7. 2. The method of claim 1 , providing the primary RF signal to an impedance matching network coupled to an electrode of a plasma chamber; providing the secondary RF signal to the impedance matching network. method.

8. 2. The method of claim 1 , the power level of the primary RF signal in the first state is at least six times and at most ten times greater than the power level of the secondary RF signal in the first state; method.

9. 2. The method of claim 1 , the power level of the primary RF signal in the second state is at least 20 percent and at most less than 100 percent of the power level of the secondary RF signal in the second state; method.

10. 2. The method of claim 1 , the power levels of the primary RF signal and the secondary RF signal in the third state are zero. method.

11. 2. The method of claim 1 , the primary RF signal is pulsed from the power level of the first state to the power level of the second state, from the power level of the second state to the power level of the third state, and from the power level of the third state to the power level of the first state. method.

12. 2. The method of claim 1 , the primary RF signal is pulsed between the three power levels in synchronization with the three states of a digital pulse signal; method.

13. 1. A method for etching a stack under a mask in a plasma processing chamber, comprising: flowing an etching gas containing a metal fluoride or a tungsten-containing passivation agent and an etching component into the plasma processing chamber; and generating the etching gas into a plasma by applying a multi-state pulsing scheme, the generating of the etching gas comprising: generating a primary radio frequency (RF) signal in a first frequency range that is pulsed between at least three states including a first state, a second state, and a third state; generating a secondary RF signal in a second frequency range that is pulsed between the at least three states, the first frequency range being less than the second frequency range; a power level of the primary RF signal in the second state is less than 80% of a power level of the primary RF signal in the first state; a power level of the primary RF signal in the third state is less than 20% of the power level of the primary RF signal in the second state; a power level of the secondary RF signal in the third state is less than 20% of a power level of the secondary RF signal in the second state; In the first state, a power level of the primary RF signal is greater than a power level of the secondary RF signal; In the second state, a power level of the secondary RF signal is greater than a power level of the primary RF signal; In the third state, the power levels of the primary RF signal and the secondary RF signal are equal to one another. method.

14. 14. The method of claim 13, a duty cycle of the first state is less than a duty cycle of the third state, and a duty cycle of the second state is less than the duty cycle of the third state. method.

15. 14. The method of claim 13, a duty cycle of the first state ranging from 3 percent to 25 percent of a clock cycle of the clock signal; method.

16. 16. The method of claim 15, a duty cycle of the second state ranging from 3 percent to 50 percent of the clock cycle of the clock signal. method.

17. 17. The method of claim 16, the third state has a duty cycle, the sum of the duty cycles of the first, second, and third states being equal to 100 percent of the clock cycle. method.

18. 14. The method of claim 13, The first frequency range is 80 kHz to 14 MHz (inclusive) and the second frequency range is 15 MHz to 120 MHz (inclusive); method.

19. 14. The method of claim 13, The metal fluoride or tungsten-containing passivation agent is tungsten fluoride; method.

20. 14. The method of claim 13, The metal fluoride or tungsten-containing passivation agent is tungsten hexafluoride. method.

21. 14. The method of claim 13, the stack comprises silicon; method.

22. 22. The method of claim 21, The mask is a hard mask. method.

23. 23. The method of claim 22, the hard mask comprises polysilicon; method.

24. 24. The method of claim 23, The stack includes at least one silicon oxide-containing layer. method.

25. 14. The method of claim 13, a ratio of the power level of the primary RF signal in the first state to the power level of the secondary RF signal in the first state is greater than 1, and a ratio of the power level of the primary RF signal in the second state to the power level of the secondary RF signal in the second state is less than 1. method.

26. 14. The method of claim 13, the multi-state pulsing regime is tailored to minimize necking and warping of sidewalls of etched features, the necking and warping being minimized using the metal fluoride or tungsten-containing passivation agent; method.

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