Semiconductor Device

Abstract

To improve a tolerated dose of an active clamp.SOLUTION: A semiconductor element comprises a substrate and an electrode pad. The substrate includes a transistor formation region of a shape other than a quadrangle in which a transistor is formed and a control circuit region controlling the transistor. An electrode pad is located on the transistor formation region. A first connection member is connected to the electrode pad at one position. The transistor formation region comprises a first region and a second region. A temperature sensor is arranged in a position adjacent to the transistor formation region. The electrode pad is provided so as to cover a gravity center of each of the first and second regions in the plan view. In the plan view, the connection region in which the first connection member is connected to the electrode pad includes a position of the gravity center of the transistor formation region.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] As an example of a semiconductor device, a vertical MOSFET is known in which a drain electrode is formed on the surface that is mounted on a lead frame, and a source electrode pad and a gate electrode pad are formed on the surface opposite to the surface on which the drain electrode is formed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-23211 A

[0004] [overview] Incidentally, a semiconductor device may be connected to an inductive load and be required to absorb energy released from the inductive load when the semiconductor device is turned off. If the energy given to the semiconductor device from the inductive load exceeds a predetermined value, the semiconductor device may fail due to an increase in temperature. An index of how much energy stored in the inductive load can be absorbed is indicated by the active clamp withstand capability. As the value of the active clamp withstand capability increases, more energy stored in the inductive load can be absorbed. For this reason, a large value of the active clamp withstand capability is preferable.

[0005] A semiconductor device according to one embodiment of the present disclosure comprises a substrate including a transistor formation region having a shape other than a rectangle in which transistors are formed, a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at one point, wherein the electrode pad is arranged to cover the center of gravity of the transistor formation region in a planar view, and a connection region where the first connection member is connected to the electrode pad includes the center of gravity of the transistor formation region in the planar view.

[0006] The present inventors have focused on the connection position of the electrode pad of the first connection member connected to the semiconductor element to the transistor formation region of the semiconductor element in order to improve the active clamp withstand voltage of the semiconductor device. The present inventors have found that the active clamp withstand voltage is improved when the first connection member is connected to the electrode pad at a position corresponding to the center of gravity of the transistor formation region. In view of this, the present semiconductor device is configured such that the connection region where the first connection member is connected to the electrode pad includes the center of gravity of the transistor formation region. Therefore, the active clamp withstand voltage can be improved.

[0007] A semiconductor device according to one embodiment of the present disclosure comprises a substrate including a transistor formation region having a shape other than a rectangle in which transistors are formed, a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at multiple points, wherein the transistor formation region is divided into a plurality of divided regions of equal area according to the number of connection points of the first connection member, the electrode pad is arranged to cover the center of gravity of each of the plurality of divided regions in a planar view, and the connection region where the first connection member is connected to the electrode pad includes the center of gravity of each of the plurality of divided regions in the planar view.

[0008] The present inventors have focused on the connection position of the electrode pad of the first connection member connected to the semiconductor element to the transistor formation region of the semiconductor element in order to improve the active clamp withstand voltage of the semiconductor device. The present inventors have found that when the first connection member is connected to the electrode pad at two points, the active clamp withstand voltage is improved when the first connection member is connected to the electrode pad at positions corresponding to the center positions of two divided regions obtained by dividing the transistor formation region into equal areas. In view of this, the present semiconductor device is configured such that the connection region where the first connection member is connected to the electrode pad includes the center positions of the respective divided regions obtained by dividing the transistor formation region into equal areas. Therefore, the active clamp withstand voltage can be improved.

[0009] A semiconductor device according to one embodiment of the present disclosure comprises a substrate including a transistor formation region having a shape other than a rectangle in which a transistor is formed, a semiconductor element having an electrode pad on the transistor formation region, and a plurality of first connection members connected to the electrode pad, wherein the transistor formation region is divided into a plurality of divided regions of equal area according to the number of the first connection members, the electrode pad is arranged to cover the center of gravity of each of the plurality of divided regions in a planar view, and the connection region in which the plurality of first connection members are respectively connected to the electrode pad includes the center of gravity position of each of the plurality of divided regions in the planar view.

[0010] The present inventors have focused on the connection position of the electrode pad of the first connection member connected to the semiconductor element to the transistor formation region of the semiconductor element in order to improve the active clamp withstand voltage of the semiconductor device. The present inventors have found that when a plurality of first connection members are connected to the electrode pad, the active clamp withstand voltage is improved when the first connection members are connected to the electrode pad at positions corresponding to the center positions of the respective divided regions obtained by dividing the transistor formation region into equal areas according to the number of the first connection members. In view of this, the present semiconductor device is configured such that the connection region where the plurality of first connection members are connected to the electrode pad includes the center positions of the respective divided regions obtained by dividing the transistor formation region into equal areas according to the number of the first connection members. Therefore, the active clamp withstand voltage can be improved.

[0011] A semiconductor device according to one aspect of the present disclosure includes a semiconductor element having a substrate including a transistor formation region having a shape other than a rectangle in which transistors are formed, an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at one point, the electrode pad being provided so as to cover a center of gravity of the transistor formation region in a plan view, a connection region where the first connection member is connected to the electrode pad includes a position of the center of gravity of the transistor formation region in the plan view, and the substrate includes a plurality of trenches and a plurality of functional element-shaped regions including a channel formation region that serves as a current path, the plurality of trenches being arranged along each of the plurality of trenches. a first functional element formation region in which the area of ​​the channel formation region per unit area is relatively small, and a second functional element formation region in which the area of ​​the channel formation region per unit area is relatively large, the first functional element formation region is provided in a region of the plurality of functional element formation regions in which heat generation should be suppressed, a metal layer is formed between the functional element formation region and the electrode pad, and one or more slits are provided in the metal layer at least in a portion facing the electrode pad.

[0012] A semiconductor device according to one embodiment of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle in which transistors are formed, a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at one point, wherein the electrode pad is arranged to cover a center of gravity of the transistor formation region in a planar view, and a connection region where the first connection member is connected to the electrode pad in the planar view includes a center of gravity position of the transistor formation region, and the electrode pad includes a first protective layer covering an interlayer insulating film, a first electrode layer covering the first protective layer, a second protective layer covering the first electrode layer, and a second electrode layer covering the second protective layer, and the Vickers hardness of each of the first protective layer and the second protective layer is greater than the Vickers hardness of each of the first electrode layer and the second electrode layer.

[0013] A semiconductor device according to one embodiment of the present disclosure comprises a semiconductor element having a substrate including a transistor formation region having a shape other than a rectangle in which transistors are formed, an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at one point, wherein the electrode pad is arranged to cover a center of gravity of the transistor formation region in a planar view, a connection region where the first connection member is connected to the electrode pad in the planar view includes a center of gravity position of the transistor formation region, and the first connection member is an aluminum wire wedge bonded to the electrode pad.

[0014] A semiconductor device according to one embodiment of the present disclosure comprises a semiconductor element having a substrate including a transistor formation region having a shape other than a rectangle in which transistors are formed, an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at one point, wherein the electrode pad is arranged to cover a center of gravity of the transistor formation region in a planar view, a connection region where the first connection member is connected to the electrode pad in the planar view includes a center of gravity position of the transistor formation region, and the first connection member is a copper wire wedge bonded to the electrode pad.

[0015] A semiconductor device according to one embodiment of the present disclosure comprises a substrate including a transistor formation region of a shape other than a rectangle in which transistors are formed and a control circuit region in which a circuit for controlling the transistor is provided, a semiconductor element having a temperature sensor provided in the control circuit region and an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad, wherein the transistor formation region has a first region and a second region having an area larger than that of the first region, the temperature sensor is disposed at a position adjacent to the transistor formation region, the electrode pad is provided so as to cover the center of gravity of each of the first region and the second region in a planar view, and a connection region in which the first connection member is connected to the electrode pad includes the center of gravity of the transistor formation region in the planar view. [Brief description of the drawings]

[0016] [Figure 1] 1A is a plan view of a semiconductor device according to a first embodiment, FIG. 1B is a side view of the semiconductor device, and FIG. [Diagram 2] FIG. 2 is a plan view showing the internal structure of the semiconductor device. [Diagram 3] Cross-sectional view of line 3-3 in Figure 1. [Figure 4] Cross-sectional view of line 4-4 in Figure 1. [Diagram 5] FIG. 2 is a plan view showing a semiconductor element of the semiconductor device, and is a schematic diagram showing a layout of the semiconductor element. [Figure 6] FIG. 2 is a circuit diagram showing a circuit configuration of the semiconductor device. [Figure 7] FIG. 2 is a plan view illustrating an active region and a source pad of a semiconductor element. [Figure 8] FIG. 2 is a plan view illustrating an active region and a source pad of a semiconductor element. [Figure 9] FIG. 1 is a cross-sectional view showing a schematic structure of a MISFET constituting a part of a semiconductor element. [Figure 10] FIG. 10 is an enlarged view of one trench gate structure and its surroundings in FIG. [Figure 11] FIG. 2 is a plan view showing a schematic diagram of an epitaxial layer of a MISFET. [Figure 12] 1 is a cross-sectional view showing a schematic structure of a low-voltage CMOSFET constituting a part of a semiconductor element. [Figure 13] FIG. 1 is a cross-sectional view showing a schematic structure of a MOS capacitor constituting a part of a semiconductor element. [Figure 14] FIG. 1 is a cross-sectional view showing a schematic structure of a polysilicon resistor constituting a part of a semiconductor element. [Figure 15] 1 is a cross-sectional view showing a schematic structure of a high-voltage N-channel MOSFET constituting a part of a semiconductor element. [Figure 16] 1 is a cross-sectional view showing a schematic structure of a high-voltage P-channel MOSFET constituting a part of a semiconductor element. [Figure 17] FIG. 1 is a cross-sectional view showing a schematic structure of an NPN transistor that constitutes a part of a semiconductor element. [Figure 18] 1 is a flowchart showing a method for manufacturing a semiconductor device. [Figure 19A] 1A to 1C are diagrams showing a part of a manufacturing process of a semiconductor device. [Figure 19B] A figure showing the next step of Figure 19A. [Figure 19C] A figure showing the next step of Figure 19B. [Figure 19D] A figure showing the next step of Figure 19C. [Figure 19E] A figure showing the next step of Figure 19D. [Figure 19F] A figure showing the next step of Figure 19E. [Figure 20] FIG. 11 is a plan view illustrating a semiconductor device according to a second embodiment, which is a schematic diagram showing an active region and a source pad of a semiconductor element. [Figure 21] FIG. 2 is a plan view showing a schematic view of an active region and a source pad of the semiconductor element. [Figure 22] 22 is a side view of a first wire connected to the source pad of FIG. 21; FIG. [Diagram 23] FIG. 11 is a cross-sectional view showing a schematic structure of a portion of a MISFET of a semiconductor element in a semiconductor device according to a third embodiment. [Figure 24] FIG. 13 is a plan view illustrating a semiconductor device according to a fourth embodiment, which is a schematic diagram showing an active region and a source pad of a semiconductor element. [Diagram 25] FIG. 2 is a plan view showing a schematic view of an active region and a source pad of the semiconductor element. [Figure 26A] FIG. 2 is a plan view showing a schematic diagram of an epitaxial layer of the semiconductor element. [Figure 26B] FIG. 2 is a plan view showing a schematic diagram of an epitaxial layer of the semiconductor element. [Figure 26C] FIG. 2 is a plan view showing a schematic diagram of an epitaxial layer of the semiconductor element. [Figure 27A] 2A to 2C are diagrams showing a part of the manufacturing process for the MISFET of the semiconductor element. [Figure 27B] A figure showing the next step of Figure 27A. [Figure 27C] A figure showing the next step of Figure 27B. [Figure 27D]A figure showing the next step of Figure 27C. [Figure 27E] A figure showing the next step of Figure 27D. [Figure 27F] A figure showing the next step of Figure 27E. [Figure 27G] A figure showing the next step of Figure 27F. [Fig. 27H] A figure showing the next step of Figure 27G. [Figure 27I] A figure showing the next step of Figure 27H. [Figure 27J] A figure showing the next step of Figure 27I. [Figure 27K] A figure showing the next step of Figure 27J. [Figure 28A] FIG. 11 is a plan view illustrating an active region and a source pad of a semiconductor element of a semiconductor device according to a modified example. [Figure 28B] FIG. 2 is a plan view showing a schematic view of an active region and a source pad of the semiconductor element. [Figure 29] FIG. 28C is a side view of a heat dissipation member provided in the semiconductor element of FIGS. 28A and 28B. [Figure 30A] FIG. 11 is a plan view illustrating an active region and a source pad of a semiconductor element of a semiconductor device according to a modified example. [Figure 30B] FIG. 2 is a plan view showing a schematic view of an active region and a source pad of the semiconductor element. [Figure 31A] 30B is a plan view showing a schematic internal structure of a semiconductor device having the semiconductor element of FIG. 30A. [Figure 31B] FIG. 30C is a plan view showing a schematic internal structure of a semiconductor device having the semiconductor element of FIG. 30B. [Figure 31C] FIG. 30C is a plan view showing a schematic internal structure of a semiconductor device having the semiconductor element of FIG. 30B. [Figure 32A] FIG. 11 is a plan view illustrating an active region and a source pad of a semiconductor element of a semiconductor device according to a modified example. [Figure 32B] FIG. 2 is a plan view showing a schematic view of an active region and a source pad of the semiconductor element. [Figure 33A] FIG. 32B is a plan view showing a schematic internal structure of a semiconductor device having the semiconductor element of FIG. 32A. [Figure 33B]FIG. 32C is a plan view showing a schematic internal structure of a semiconductor device having the semiconductor element of FIG. 32B. [Figure 34A] FIG. 11 is a plan view illustrating an active region and a source pad of a semiconductor element of a semiconductor device according to a modified example. [Figure 34B] FIG. 2 is a plan view showing a schematic view of an active region and a source pad of the semiconductor element. [Figure 35A] FIG. 34B is a plan view showing a schematic internal structure of a semiconductor device having the semiconductor element of FIG. 34A. [Figure 35B] FIG. 34C is a plan view showing a schematic internal structure of a semiconductor device having the semiconductor element of FIG. 34B. [Diagram 36] FIG. 13 is a plan view illustrating an internal structure of a semiconductor device according to a modified example. [Figure 37] 37 is a plan view showing a schematic diagram of an active region and a source pad of a semiconductor element of the semiconductor device of FIG. 36. [Figure 38] FIG. 13 is a plan view illustrating an internal structure of a semiconductor device according to a modified example. [Figure 39] FIG. 11 is a cross-sectional view illustrating a schematic structure of a portion of a MISFET of a semiconductor element according to a modified example. [Diagram 40] 13 is a graph showing the relationship between the pad thickness of the source pad and the maximum principal stress. [Diagram 41] 1 is a graph showing the relationship between the pad thickness of a source pad and the TDDB failure time. [Diagram 42] FIG. 1 is an explanatory diagram relating to a first application example of a semiconductor device. [Diagram 43] FIG. 11 is an explanatory diagram relating to a second application example of the semiconductor device. [Diagram 44] FIG. 13 is an explanatory diagram relating to a third application example of the semiconductor device. [Diagram 45] FIG. 13 is an explanatory diagram relating to a fourth application example of the semiconductor device. [Figure 46] FIG. 13 is an explanatory diagram relating to a fifth application example of the semiconductor device.

[0017] [Detailed Description] Hereinafter, embodiments of a semiconductor device will be described with reference to the drawings. The embodiments shown below are merely examples of configurations and methods for embodying technical ideas, and are not intended to limit the materials, shapes, structures, arrangements, dimensions, etc. of each component to those described below. Various modifications can be made to the following embodiments.

[0018] In this specification, "a state in which component A is connected to component B" includes a case in which component A and component B are directly physically connected to each other, as well as a case in which component A and component B are indirectly connected to each other via another component that does not affect the electrical connection state.

[0019] Similarly, "a state in which component C is provided between component A and component B" includes a case in which component A and component C, or component B and component C, are directly connected to each other, as well as a case in which component A and component C, or component B and component C, are indirectly connected to each other via another component that does not affect the electrical connection state.

[0020] (First embodiment) As shown in FIG. 1(a) to FIG. 3, the semiconductor device 1 has a lead frame 10, a semiconductor element 20 mounted on the lead frame 10, and a sealing resin 30 that seals a part of the lead frame 10 and the semiconductor element 20. The semiconductor element 20 includes, for example, a transistor connected to an inductive load, and turns the transistor on and off. In the semiconductor device 1, for example, the on-resistance of the semiconductor element 20 is preferably 30 mΩ or less. An example of the on-resistance of the semiconductor element 20 is 28 mΩ. The semiconductor device 1 is used, for example, in a control circuit of an on-vehicle electrical device. Examples of the on-vehicle electrical device include an engine, an air conditioner, and a steering device. The size of the sealing resin 30 is about 6.6 mm in the horizontal direction X, about 6.1 mm in the vertical direction Y, and about 2.3 mm in the thickness direction Z. The semiconductor device 1 may be used in a control device of a device other than the on-vehicle electrical device (for example, an outdoor unit of an air conditioner).

[0021] The sealing resin 30 has a first side surface 31 and a second side surface 32 which are side surfaces in the horizontal direction X, a third side surface 33 and a fourth side surface 34 which are side surfaces in the vertical direction Y, and a fifth side surface 35 and a sixth side surface 36 which are side surfaces in the thickness direction Z. The sealing resin 30 is made of a thermosetting resin in which a filler is dispersed and blended. An example of the thermosetting resin is an epoxy resin. An example of the filler is a silica filler. An example of the blending ratio of the filler to the epoxy resin is 85 to 90 volume %. The sealing resin 30 is preferably made of a material having a linear expansion coefficient greater than 10 ppm / K and smaller than 15 ppm / K. The linear expansion coefficient of the sealing resin 30 can be changed by, for example, the blending ratio of the filler. In this embodiment, the linear expansion coefficient of the sealing resin 30 is 12 ppm / K.

[0022] The lead frame 10 has a first lead frame 11, a second lead frame 12, and a third lead frame 13. Each of the lead frames 11, 12, and 13 is formed of, for example, copper (Cu). The outer surfaces of each of the lead frames 11, 12, and 13 are plated with nickel (Ni). Figures 3 and 4 show an example of the plating layer 14 of the first lead frame 11 and the second lead frame 12.

[0023] As shown in Fig. 1(a) and Fig. 2, the first lead frame 11 is configured to include an output terminal OUT. It has a first island portion 11a and a first terminal portion 11b. The first island portion 11a and the first terminal portion 11b are integrally formed. Alternatively, the first island portion 11a and the first terminal portion 11b may be formed separately and then connected to each other.

[0024] The first island portion 11a is formed in a substantially rectangular shape in a plan view. A part of the first island portion 11a in the vertical direction Y protrudes from the third side surface 33 of the sealing resin 30 in the vertical direction Y. As shown in FIG. 1(b)(c), the first island portion 11a is exposed from the sixth side surface 36 of the sealing resin 30. The first island portion 11a has a main body portion 11c located in the sealing resin 30, a narrow width portion 11d provided at a position near the third side surface 33 in the sealing resin 30, and a tip portion 11e extending in the vertical direction Y from the narrow width portion 11d. A part of the tip portion 11e protrudes from the third side surface 33 of the sealing resin 30. In this embodiment, the dimension of the tip portion 11e in the horizontal direction X is smaller than the dimension of the main body portion 11c in the horizontal direction X. A recess 11f recessed toward the third side surface 33 is provided at the tip edge of the tip portion 11e in the vertical direction Y. Since the narrow portion 11d forms a recess in the horizontal direction X in the first island portion 11a, the adhesion to the sealing resin 30 is improved and the movement of the first island portion 11a in the vertical direction Y relative to the sealing resin 30 can be suppressed.

[0025] 1(a) and 1(c), the area of ​​the portion of the main body 11c of the first island portion 11a exposed from the sixth side surface 36 of the sealing resin 30 is smaller than the area of ​​the main body 11c in a plan view. In detail, the portion of the main body 11c on the fifth side surface 35 of the sealing resin 30 in the thickness direction Z is longer in the lateral direction X than the portion of the main body 11c on the sixth side surface 36 of the sealing resin 30. As a result, the portion of the main body 11c on the fifth side surface 35 of the sealing resin 30 is sandwiched by the sealing resin 30 in the thickness direction Z, so that the first lead frame 11 can be prevented from moving in the thickness direction Z.

[0026] The shape of the first island portion 11a can be changed arbitrarily. For example, at least one of the narrow portion 11d and the recessed portion 11f may be omitted. The dimension of the tip portion 11e in the lateral direction X may be equal to or greater than the dimension of the main body portion 11c in the lateral direction X. The tip portion 11e may constitute the output terminal OUT. The area of ​​the portion of the main body portion 11c of the first island portion 11a exposed from the sixth side surface 36 of the sealing resin 30 may be equal to the area of ​​the main body portion 11c in a plan view.

[0027] As shown in FIG. 4, the first terminal portion 11b constituting the output terminal OUT protrudes in the vertical direction Y from the fourth side surface 34 of the sealing resin 30. The portion of the first terminal portion 11b protruding from the fourth side surface 34 of the sealing resin 30 is located closer to the fifth side surface 35 of the sealing resin 30 than the first island portion 11a in the thickness direction Z. The first terminal portion 11b has a first bent portion 11g bent from a portion connected to the first island portion 11a toward the fifth side surface 35 of the sealing resin 30, an inclined portion 11h that inclines so as to extend toward the fifth side surface 35 as it approaches the fourth side surface 34 of the sealing resin 30, a second bent portion 11i that is bent again near the fourth side surface 34 of the sealing resin 30, and a tip portion 11j that is perpendicular to the thickness direction Z and extends in the vertical direction Y. A part of the tip portion 11j protrudes from the fourth side surface 34 of the sealing resin 30. In this embodiment, the first bent portion 11g, the inclined portion 11h, the second bent portion 11i, and the tip portion 11j are integrally formed.

[0028] As shown in Fig. 2, the second lead frame 12 constitutes an input terminal IN. The second lead frame 12 is disposed on the first side surface 31 side and the fourth side surface 34 side of the sealing resin 30. The second lead frame 12 has a second island portion 12a and a second terminal portion 12b. The second island portion 12a and the second terminal portion 12b are integrally formed. Note that the second island portion 12a and the second terminal portion 12b may be formed separately and then connected to each other.

[0029] The second island portion 12a is formed in a rectangular shape whose length in the horizontal direction X is longer than its length in the vertical direction Y in a plan view. The second island portion 12a is disposed closer to the fourth side surface 34 of the sealing resin 30 than the first island portion 11a in the vertical direction Y. The second island portion 12a is disposed closer to the first side surface 31 of the sealing resin 30 than the first terminal portion 11b in the horizontal direction X. The second island portion 12a is disposed closer to the fifth side surface 35 of the sealing resin 30 than the first island portion 11a in the thickness direction Z.

[0030] The second terminal portion 12b extends in the vertical direction Y from a portion of the second island portion 12a closer to the first side surface 31 of the sealing resin 30. The second terminal portion 12b protrudes from the fourth side surface 34 of the sealing resin 30. The length in the vertical direction Y of the portion of the second terminal portion 12b protruding from the fourth side surface 34 of the sealing resin 30 is longer than the length in the vertical direction Y of the portion of the first terminal portion 11b protruding from the fourth side surface 34 of the sealing resin 30. The second terminal portion 12b is bent so that its tip portion is at the same position as the thickness direction Z of the first island portion 11a.

[0031] The third lead frame 13 constitutes a ground terminal GND. The third lead frame 13 has a third island portion 13a and a third terminal portion 13b. The third island portion 13a and the third terminal portion 13b are integrally formed. Alternatively, the third island portion 13a and the third terminal portion 13b may be formed separately and then connected to each other.

[0032] The third island portion 13a is formed in a rectangular shape whose length in the horizontal direction X is longer than its length in the vertical direction Y in a plan view. The third island portion 13a is disposed closer to a fourth side surface 34 of the sealing resin 30 than the first island portion 11a in the vertical direction Y. The third island portion 13a is disposed closer to a second side surface 32 of the sealing resin 30 than the first terminal portion 11b in the horizontal direction X. The third island portion 13a is disposed closer to a fifth side surface 35 of the sealing resin 30 than the first island portion 11a in the thickness direction Z (see FIG. 3).

[0033] The third terminal portion 13b extends in the vertical direction Y from a portion of the third island portion 13a close to the second side surface 32 of the sealing resin 30. The third terminal portion 13b protrudes from the fourth side surface 34 of the sealing resin 30. The length in the vertical direction Y of the portion of the third terminal portion 13b protruding from the fourth side surface 34 of the sealing resin 30 is longer than the length in the vertical direction Y of the portion of the first terminal portion 11b protruding from the fourth side surface 34 of the sealing resin 30 and is equal to the length in the vertical direction Y of the portion of the second terminal portion 12b protruding from the fourth side surface 34 of the sealing resin 30. The third terminal portion 13b is bent so that its tip portion is at the same position as the thickness direction Z of the first island portion 11a (see FIG. 3).

[0034] As shown in Figures 2 and 3, a semiconductor element 20 is mounted on a surface 11x of a main body portion 11c of a first lead frame 11. More specifically, solder SD is applied to the surface 11x of the main body portion 11c. The semiconductor element 20 is placed on the solder SD. As shown in Figure 2, the semiconductor element 20 is disposed in a portion of the main body portion 11c closer to the fourth side surface 34 of the sealing resin 30 in the vertical direction Y (closer to the second island 12a and the third island 13a in the vertical direction Y). The semiconductor element 20 is disposed in the center of the main body portion 11c in the horizontal direction X.

[0035] The semiconductor element 20 of this embodiment is a power MOSFET or an IGBT. The semiconductor element 20 is formed in a rectangular shape in which the horizontal direction X is longer than the vertical direction Y in a plan view. The size of the semiconductor element 20 of this embodiment is 2.25 mm in the vertical direction Y and 2.68 mm in the horizontal direction X. The shape or size of the semiconductor element 20 in a plan view is not limited to this. For example, the semiconductor element 20 may be formed in a square shape in which the vertical direction Y and the horizontal direction X are equal to each other.

[0036] A source pad 21, which is an example of an electrode pad, and a gate pad 22, which is an example of a control electrode pad, are provided on a front surface 20x of the semiconductor element 20. A drain electrode is provided on a back surface 20y (see FIG. 3) of the semiconductor element 20, i.e., the surface of the semiconductor element 20 facing the first island portion 11a. The drain electrode is electrically connected to the first island portion 11a (first lead frame 11) via solder SD.

[0037] One end of a first wire 41, which is an example of a connection member, is connected to the source pad 21. The other end of the first wire 41 is connected to the third island portion 13a of the third lead frame 13. The first wire 41 is connected to the source pad 21 and the third island portion 13a, for example, by wedge bonding. In this embodiment, the number of the first wires 41 is one. The first wire 41 in this embodiment is an aluminum wire using aluminum (Al). The wire diameter of the first wire 41 is preferably, for example, 100 μm or more. It is more preferable that the wire diameter of the first wire 41 is, for example, 300 μm to 400 μm. In this embodiment, the wire diameter of the first wire 41 is about 300 μm. The first wire 41 may be a copper wire using copper (Cu).

[0038] As shown in FIG. 2, one end of a second wire 42 is connected to the gate pad 22. The other end of the second wire 42 is connected to the second island portion 12a of the second lead frame 12. The second wire 42 is connected to the gate pad 22 and the second island portion 12a, respectively, by, for example, wedge bonding. In this embodiment, the number of second wires 42 is one. The material of the second wire 42 is, for example, aluminum (Al) or copper (Cu). The second wire 42 in this embodiment is made of aluminum. The wire diameter of the second wire 42 is smaller than the wire diameter of the first wire 41. The wire diameter of the second wire 42 is, for example, 125 μm.

[0039] 2 and 5, the semiconductor element 20 has a substrate 50 that is rectangular in plan view. The substrate 50 has a first side surface 51 and a second side surface 52 that are aligned along the vertical direction Y, and a third side surface 53 and a fourth side surface 54 that are aligned along the horizontal direction X. The first side surface 51 is a side surface of the substrate 50 that faces the first side surface 31 of the sealing resin 30, the second side surface 52 is a side surface of the substrate 50 that faces the second side surface 32 of the sealing resin 30, the third side surface 53 is a side surface of the substrate 50 that faces the third side surface 33 of the sealing resin 30, and the fourth side surface 54 is a side surface of the substrate 50 that faces the fourth side surface 34 of the sealing resin 30.

[0040] The semiconductor element 20 has a switching circuit 23 having a plurality of power metal insulator semiconductor field effect transistors (MISFETs) as an example of a functional element fabricated in a surface layer of the substrate 50. The semiconductor element 20 further has an overcurrent protection (OCD: Over Current Detection) circuit 24, a thermal protection (TSD: Thermal Shut Down) circuit 25, a low voltage malfunction prevention (UVLO: Under Voltage Lock Out) circuit 26, a temperature sensor 27, and a current sensor 28 as an example of a control circuit that controls the switching circuit 23. The overcurrent protection circuit 24, the thermal protection circuit 25, the low voltage malfunction prevention circuit 26, the temperature sensor 27, and the current sensor 28 are all fabricated in the surface layer of the substrate 50. In other words, the semiconductor element 20 is an IPS (Intelligent Power Switch) in which a switching circuit 23 (power MISFET), an overcurrent protection circuit 24, an overheat protection circuit 25, an undervoltage malfunction prevention circuit 26, a temperature sensor 27, and a current sensor 28 are fabricated on the surface layer of a common substrate 50.

[0041] The switching circuit 23 is formed in an active area 29 set in the substrate 50. The active area 29 is formed in a substantially L-shape in plan view so as to avoid the gate pad 22 and the temperature sensor 27. In detail, the active area 29 has, in plan view, a first side 29a closest to the first side surface 51 of the substrate 50, a second side 29b closest to the third side surface 53 of the substrate 50, a third side 29c closest to the second side surface 52 of the substrate 50, a fourth side 29d closest to the fourth side surface 54 of the substrate 50, and a fifth side 29e and a sixth side 29f constituting a cutout portion of the active area 29. The fifth side 29e is a side extending in the vertical direction Y, and the sixth side 29f is a side extending in the horizontal direction X. One end of the first side 29a is connected to the second side 29b, and the other end of the first side 29a is connected to the sixth side 29f. The end of the second side 29b opposite to the first side 29a is connected to the third side 29c. The end of the third side 29c opposite to the second side 29b is connected to the fourth side 29d. The end of the fourth side 29d opposite to the third side 29c is connected to the fifth side 29e. The end of the fifth side 29e opposite to the fourth side 29d is connected to the sixth side 29f. As can be seen from FIG. 5, the length of the first side 29a is shorter than the length of the third side 29c, and the length of the second side 29b is longer than the length of the fourth side 29d. The active region 29 is covered by the source pad 21. The source pad 21 is formed in a substantially L-shape in a plan view. In more detail, the source pad 21 is provided on the substrate 50 near the third side surface 53. The source pad 21 is formed into a substantially L-shape in a plan view by cutting out a region of the substrate 50 on the side where the gate pad 22 is arranged, i.e., a region on the first side surface 51 side and the second side surface 52 side of the substrate 50. In this embodiment, the shape of the source pad 21 is similar to the shape of the active region 29. The shapes of the source pad 21 and the active region 29 can be changed as desired. In one example, the shape of the source pad 21 may be different from the shape of the active region 29.

[0042] 2 and 5, the semiconductor element 20 has a control circuit region 29LG formed to avoid the source pad 21 and the gate pad 22. The control circuit region 29LG includes a first portion closer to the fourth side surface 54 of the substrate 50 than the source pad 21 and the gate pad 22, and a second portion extending from the first portion toward the third side surface 53 of the substrate 50. The second portion is formed between the gate pad 22 and the source pad 21 in the lateral direction X. The control circuit region 29LG includes an overcurrent protection circuit 24, an overheat protection circuit 25, an undervoltage malfunction prevention circuit 26, and a temperature sensor 27. The overcurrent protection circuit 24, the overheat protection circuit 25, and the undervoltage malfunction prevention circuit 26 are provided in a region of the control circuit region 29LG closer to the fourth side surface 54 of the substrate 50 than the active region 29. The overcurrent protection circuit 24, the overheat protection circuit 25, and the undervoltage malfunction prevention circuit 26 are arranged in a row in the lateral direction X. The low voltage malfunction prevention circuit 26 is arranged on the first side surface 51 side of the substrate 50 relative to the overcurrent protection circuit 24 and the overheat protection circuit 25 in the control circuit region 29LG. A part of the low voltage malfunction prevention circuit 26 is adjacent to the gate pad 22 in the vertical direction Y.

[0043] The temperature sensor 27 is provided in the control circuit region 29LG. The position of the temperature sensor 27 is set to a position where the temperature becomes highest in the region outside the source pad 21 when the semiconductor device 1 is driven. The position of the temperature sensor 27 is set based on the temperature distribution of the substrate 50 when the semiconductor device 1 is driven, for example, by simulation or the like. In this embodiment, the temperature sensor 27 is disposed near the intersection of the fifth side 29e and the sixth side 29f of the active region 29.

[0044] The current sensor 28 is disposed between the overcurrent protection circuit 24 and the source pad 21 on the substrate 50. The current sensor 28 is provided in an active region 29. The current sensor 28 is disposed closer to the overcurrent protection circuit 24 than the source pad 21 in the vertical direction Y.

[0045] Next, the electrical configuration of the semiconductor device 1 will be described with reference to Fig. 6. Fig. 6 shows an example of a circuit configuration of the semiconductor device 1. Fig. 6 shows an example in which a battery 2 and an inductive load 3 are externally connected to an output terminal OUT and a ground terminal GND. Fig. 6 also shows an example in which the inductive load 3 is a relay including a coil L.

[0046] The switching circuit 23 is connected between the output terminal OUT and the ground terminal GND. The switching circuit 23 includes the power MISFET (hereinafter, "MISFET 23a"), which is an example of a power transistor. The MISFET 23a has a gate terminal G as a control terminal, a drain terminal D, and a source terminal S. The switching circuit 23 is provided such that the drain terminal D of the MISFET 23a is connected to the output terminal OUT, and the source terminal S is connected to the ground terminal GND. Note that the switching circuit 23 includes a plurality of power MISFETs, but for convenience of explanation, only one MISFET 23a is shown in FIG. 6.

[0047] An input wiring 43 is connected between the input terminal IN and the gate terminal G of the MISFET 23a. A ground wiring 44 is connected between the ground terminal GND and the source terminal S of the MISFET 23a. A diode D1, a first resistor R1, an overcurrent protection circuit 24, an overheat protection circuit 25, an undervoltage malfunction prevention circuit 26, and a second resistor R2 are connected in parallel between the input wiring 43 and the ground wiring 44, in this order from the input terminal IN side. A third resistor R3 is connected in series between the first resistor R1 and the overcurrent protection circuit 24 in the input wiring 43. A fourth resistor R4 is connected in series between the undervoltage malfunction prevention circuit 26 and the second resistor R2 in the input wiring 43.

[0048] The current sensor 28 is electrically connected to the overcurrent protection circuit 24. The current sensor 28 detects, for example, a current flowing through the switching circuit 23. The current value detected by the current sensor 28 is provided to the overcurrent protection circuit 24. The overcurrent protection circuit 24 is driven based on the current value provided by the current sensor 28. In one example, when a current (overcurrent) of a predetermined value or more flows through the switching circuit 23 due to a short circuit, the overcurrent protection circuit 24 limits the current to protect the circuit.

[0049] The temperature sensor 27 is electrically connected to the overheat protection circuit 25. The temperature sensor 27 detects the temperature of the substrate 50. The temperature of the substrate 50 detected by the temperature sensor 27 is provided to the overheat protection circuit 25. The overheat protection circuit 25 is driven based on the temperature of the substrate 50 provided by the temperature sensor 27. In one example, when the temperature of the substrate 50 reaches or exceeds a predetermined value, the overheat protection circuit 25 stops the switching circuit 23 by the overcurrent protection circuit 24 to protect the circuit. As a result, the temperature rise of the substrate 50 is suppressed.

[0050] The low voltage malfunction prevention circuit 26 is configured to prohibit the switching circuit 23 from operating when the potential difference between the input wiring 43 and the ground wiring 44 is equal to or less than a predetermined value, and to permit the switching circuit 23 to operate when the potential difference is equal to or greater than the predetermined value.

[0051] A clamp diode D2 is electrically connected between the gate terminal G and drain terminal D of the MISFET 23a. The clamp diode D2 is formed by connecting two diodes in a reverse bias state. The two diodes may include Zener diodes. The number of diodes constituting the clamp diode D2 can be changed as desired.

[0052] When the input terminal IN is at a high level, the MISFET 23a of the semiconductor device 1 is turned on, and a current flows from the battery 2 through the coil L of the inductive load 3 and the MISFET 23a. Next, when the input terminal IN changes from high level to low level, the MISFET 23a turns off. At this time, the voltage Vout of the output terminal OUT rises due to the current flowing from the inductive load 3. The voltage Vout of the output terminal OUT rises to a voltage (for example, 48 V) determined by the clamp diode D2 from the battery 2. The gate voltage of the MISFET 23a rises slightly due to the current flowing to the resistor R2 via the clamp diode D2 due to the rise in the output voltage Vout. This causes a current to flow through the MISFET 23a. In this way, a gate voltage is generated to cause a small amount of current to flow through the MISFET 23a, that is, an active clamp state is reached. This active clamp state continues until the current from the battery 2 to the MISFET 23a becomes 0 A, and the output voltage Vout drops to the voltage of the battery 2.

[0053] [Connection of the first wire to the source pad] 7 and 8 are enlarged plan views showing a portion of the substrate 50. In Fig. 7, the active area 29 is shown by a solid line, and the source pad 21 is shown by a two-dot chain line. In Fig. 8, the active area 29 is shown by a dashed line, and the source pad 21 is shown by a solid line.

[0054] The present inventors have focused on the connection position of the first wire 41 connected to the source pad 21 of the semiconductor element 20 in order to improve the active clamp withstand capability Eac of the semiconductor device 1. The present inventors have found that the active clamp withstand capability Eac improves when the first wire 41 is connected to a connection position including the center of gravity GC of the active region 29 of the semiconductor element 20. In view of this, in this embodiment, the first wire 41 is connected to the source pad 21 so as to overlap with the center of gravity GC of the active region 29.

[0055] Here, the center of gravity GC of the active area 29 is determined as follows. As shown in FIG. 7, first, the active area 29 is divided into two areas, a first area RA1 and a second area RA2. The first area RA1 and the second area RA2 are preferably rectangular areas. Next, the center of gravity GA1 of the first area RA1 and the center of gravity GA2 of the second area RA2 are obtained. As shown in FIG. 7, since the first area RA1 and the second area RA2 are each rectangular, the center of gravity GA1 of the first area RA1 is the intersection of the diagonals of the first area RA1, and the center of gravity GA2 of the second area RA2 is the intersection of the diagonals of the second area RA2. Next, the area SA1 of the first area RA1 and the area SA2 of the second area RA2 are obtained. Next, in the line segment LA connecting the center of gravity GA1 and the center of gravity GA2, the center of gravity GC of the active region 29 is calculated based on the distance DA1 between the center of gravity GA1 and the center of gravity GC of the active region 29, the distance DA2 between the center of gravity GA2 and the center of gravity GC of the active region 29, and the relationship between the area SA1 of the first region RA1 and the area SA2 of the second region RA2. In detail, the ratio (DA2 / DA1) of the distance DA2 to the distance DA1 is equal to the inverse ratio (SA1 / SA2) of the ratio of the area SA2 of the second region RA2 to the area SA1 of the first region RA1 (DA2 / DA1=SA1 / SA2). Thus, the center of gravity GC of the active region 29 is calculated by calculating at least one of the distances DA1 and DA2. As shown in FIG. 7, the source pad 21 is provided so as to cover the center of gravity GC of the active region 29.

[0056] A dot-dash line region RX shown in FIG. 7 indicates a tool head (hereinafter referred to as wedge RX) for ultrasonically bonding the first wire 41 to the source pad 21 in a wedge bonding device (not shown). The wedge bonding device moves the wedge RX so that the center of the wedge RX is positioned on the center of gravity GC of the active area 29. An end of the first wire 41 passed through the wedge RX is connected so as to overlap the center of gravity GC of the active area 29, as shown in FIG. 8. That is, the contact region (wedge RX) of the first wire 41 with the source pad 21 includes the center of gravity GC of the active area 29. In this embodiment, the center position of the connection region (wedge RX) of the first wire 41 to the source pad 21 coincides with the center of gravity GC of the active area 29.

[0057] 2 and 8, a connection portion 41a of the first wire 41 connected to the source pad 21 extends in a direction different from the horizontal direction X and the vertical direction Y in a plan view of the semiconductor device 1. In this embodiment, the connection portion 41a extends from the semiconductor element 20 toward the third island portion 13a.

[0058] 8, a region RS surrounded by a two-dot chain line around the connection portion 41a of the first wire 41 is a margin that takes into consideration variations in the wire diameter of the first wire 41 and variations in the connection position of the first wire 41 to the source pad 21 by a wedge bonding device. In other words, the connection portion 41a of the first wire 41 is always located within the region RS. For example, the region RS may be set as an opening 89 (see FIG. 9 for both) that opens the surface protective film 88 from the source pad 21. It is preferable that the opening 89 is set to be wider than the region RS.

[0059] That is, in the first embodiment, the active area 29 is a substantially L-shaped combination of a small rectangular first area RA1 and a large rectangular second area RA2, as shown in Fig. 7. The first wire 41 as a connecting member and the source pad 21 are connected to each other at a position on a line segment LA connecting the center of gravity GA1 of the first area RA1 and the center of gravity GA2 of the second area RA2.

[0060] The semiconductor element 20 also includes a transistor. The semiconductor device includes a second lead frame (external control terminal) 12 for controlling the on / off of the transistor, and a third lead frame (external terminal) 13 connected to a first wire 41 serving as a connecting member. As shown in FIG. 2, the second lead frame 12 is disposed on the side of a small rectangular first region RA1, and the third lead frame 13 is disposed on the side of a large rectangular second region RA2. In other words, the second lead frame 12 is disposed at a position closer to the first region RA1 than the second region RA2, and the third lead frame 13 is disposed at a position closer to the second region RA2 than the first region RA1.

[0061] 2 and 5, the semiconductor element 20 includes a gate pad (control metal pad) 22 connected to the second lead frame (external control terminal) 12. The gate pad 22 is disposed in a rectangular region surrounded by an extension line of a side (first side 29a) of the small rectangular first region RA1 and an extension line of a side (fourth side 29d) of the large rectangular second region RA2, in which no transistor is located.

[0062] 5, the source pad 21 is also substantially L-shaped. The source pad 21 is formed across a small rectangular first region RA1 and a large rectangular second region RA2 included in the active region 29. The source pad 21 is configured such that a first side 29a of the source pad 21 that is farthest from the second region RA2 coincides with a position where the gate pad 22 is provided in the horizontal direction X. In detail, the gate pad 22 has a left side and a right side in the horizontal direction X as shown in FIG. 5, and the left side of the gate pad 22 extends to a position farther away from the second region RA2 than the right side of the gate pad 22 in the horizontal direction X. The first side 29a of the source pad 21 coincides with a position between the left side and the right side of the gate pad 22 in the horizontal direction X.

[0063] In addition, the temperature sensor 27 is disposed between the gate pad 22 and the source pad 21 . [MISFET structure] The detailed structure of the MISFET 23a will be described with reference to FIGS.

[0064] 9, a substrate 50 on which the MISFET 23a is formed is, for example, a silicon substrate. + A type semiconductor substrate 61 and a n-type - The substrate 50 includes a semiconductor substrate 61 and an epitaxial layer 62 of a type I type. A drain region 63 is formed by the semiconductor substrate 61 and the epitaxial layer 62. The front surface of the substrate 50 is formed by the epitaxial layer 62, and the back surface of the substrate 50 is formed by the semiconductor substrate 61. An example of the thickness of the epitaxial layer 62 is 9.5 μm.

[0065] A source pad 21 is formed on the front surface side of the substrate 50, and a drain electrode 64 is formed on the back surface side of the substrate 50. A plurality of trench gate structures 65 are provided on the front surface side of the active region 29 of the substrate 50. The plurality of trench gate structures 65 are fabricated in a surface layer portion of the epitaxial layer 62, and each include a trench 66 formed by digging down the epitaxial layer 62, and a gate electrode 68 and a buried electrode 69 buried in the trench 66 with a gate insulating film 67 sandwiched therebetween.

[0066] 10, the gate electrode 68 and the buried electrode 69 are separated (insulated) by a gate insulating film 67 in the depth direction of the trench 66. The gate electrode 68 is disposed on the opening side of the trench 66, and the buried electrode 69 is disposed closer to the bottom of the trench 66 than the gate electrode 68. An example of the gate insulating film 67 is a silicon oxide film.

[0067] The gate insulating film 67 includes a thick film portion 67a in contact with the embedded electrode 69 and a thin film portion 67b in contact with the gate electrode 68. One surface (the surface on the drain region 63 side) and the opposite surface of the thick film portion 67a of the gate insulating film 67 are formed along the inner wall of the trench 66, and it has a laminated structure in which a silicon oxide film with a low density is laminated on a silicon oxide film with a high density. The thickness T1 of the thick film portion 67a of the gate insulating film 67 is thicker than the thickness T2 of the thin film portion 67b (T2 < T1). The thickness T1 of the thick film portion 67a is thicker than the thickness T3 of the separation portion 67c that separates the gate electrode 68 and the embedded electrode 69 in the gate insulating film 67 (T3 < T1). The thickness T3 of the separation portion 67c is thicker than the thickness T2 of the thin film portion 67b (T2 < T3 < T1). Note that the thickness T1 of the thick film portion 67a, the thickness T2 of the thin film portion 67b, and the thickness T3 of the separation portion 67c can each be arbitrarily changed. For example, the thickness T2 of the thin film portion 67b and the thickness T3 of the separation portion 67c may be equal to each other.

[0068] The gate electrode 68 is made of, for example, polysilicon. A concave portion 68a that opens toward the embedded electrode 69 is formed at the lower end portion of the gate electrode 68. The upper end portion 69a of the embedded electrode 69 is accommodated in the concave portion 68a. Thus, the upper end portion 69a of the embedded electrode 69 faces the gate electrode 68 through the thin film portion 67b of the gate insulating film 67. The embedded electrode 69 is made of, for example, polysilicon. In this embodiment, the embedded electrode 69 is electrically floating from the outside by being covered with the thick film portion 67a and the separation portion 67c of the gate insulating film 67. Note that the embedded electrode 69 may have the same potential (ground potential) as the source pad 21. In a cross-sectional view of the embedded electrode 69, the width dimension D1 of the upper end portion 69a is smaller than the width dimension D2 of the portion below the upper end portion 69a (on the back surface side of the substrate 50) in the embedded electrode 69.

[0069] 9 and 10 show an example in which the trench 66 is formed substantially perpendicular to the surface of the epitaxial layer 62. However, the trench 66 may be formed to have a tapered cross-sectional shape in which the opening width gradually narrows toward the bottom of the trench 66 in the depth direction of the trench 66. Also, in FIG. 9 and 10, an example is shown in which the bottom of the trench 66 has a flat portion parallel to the surface of the epitaxial layer 62. However, the bottom of the trench 66 may be formed to be curved outward from the side surface of the trench 66.

[0070] On the sides (both side surfaces) of the trench gate structure 65, n + Source region 70, p - A source region 70, a body region 71, and a drain region 63 (epitaxial layer 62) are provided in this order. The source region 70, the body region 71, and the drain region 63 are all formed to be in contact with the trench gate structure 65, and face the gate electrode 68 with a gate insulating film 67 interposed therebetween. Furthermore, the drain region 63 faces the buried electrode 69 with the gate insulating film 67 interposed therebetween.

[0071] The body region 71 is shared between the trench gate structure 65 on one side and the trench gate structure 65 on the other side between adjacent trench gate structures 65. The source region 70 is provided so as to be exposed from the surface of the body region 71. The planar shape of the source region 70 corresponds to the planar shape of a channel formation region 72 which becomes a current path. Below the source region 70, the body region 71 which forms the side surface of the trench gate structure 65 is the channel formation region 72. The formation of a channel in the channel formation region 72 is controlled by the trench gate structure 65 (gate electrode 68).

[0072] Fig. 11 shows an example of a planar structure of the epitaxial layer 62 of the MISFET 23a. As shown in Fig. 11, in a body region 71 (see Fig. 10) sandwiched between adjacent trench gate structures 65, a plurality of source regions 70 are alternately formed on one trench gate structure 65 side and the other trench gate structure 65 side. The area of ​​each source region 70 is the same. Thus, in the MISFET 23a of this embodiment, the ratio of the area of ​​the channel formation region 72 to the unit area is about 50%.

[0073] Here, when the channel formation region 72 exists in the entire region between the trench gate structures 65, the ratio of the area of ​​the channel formation region 72 to the unit area is defined as 100%. The area of ​​the channel formation region 72 is defined as the area of ​​the region that becomes a current path in a plan view. Specifically, the area of ​​the channel formation region 72 is defined as the area of ​​the source region 70 facing the drain region 63 (epitaxial layer 62) with the body region 71 interposed therebetween in a plan view. The ratio of the area of ​​the channel formation region 72 to the unit area is the ratio of the area of ​​the channel formation region 72 to the area that is predetermined between the trench gate structures 65. The predetermined region is a region of a predetermined area obtained by multiplying the width between the trench gate structures 65 by an arbitrary length along the longitudinal direction of the trench gate structures 65.

[0074] In addition, between the plurality of trench gate structures 65, p + A body contact region 73 having a gate insulating film 67 is formed in the source region 70. The body contact region 73 is formed so as to contact a side surface of the trench gate structure 65, and a part of the body contact region 73 faces the gate electrode 68 with the gate insulating film 67 interposed therebetween. In this embodiment, the depth of the body contact region 73 and the depth of the source region 70 are equal to each other.

[0075] The depths of the body contact region 73 and the source region 70 can be changed arbitrarily. In one example, the depth of the body contact region 73 may be deeper than the depth of the source region 70. The body contact region 73 may be omitted from the MISFET 23a. In this case, the body region 71 is exposed from the surface of the epitaxial layer 62.

[0076] 9, the epitaxial layer 62 is provided with a DTI (Deep Trench Isolation) structure 90 as an element isolation structure that separates the region where the MISFET 23a is formed from other regions. For example, the DTI structure 90 is formed in a substantially annular shape in a plan view (hereinafter, simply referred to as a "plan view") of the surface of the epitaxial layer 62 viewed from the normal direction. The DTI structure 90 has a trench 91 formed by digging into the epitaxial layer 62, and an insulator 92 embedded in the trench 91 with the gate insulating film 67 sandwiched therebetween. An example of the insulator 92 is polysilicon. The insulator 92 may be silicon oxide. In the present embodiment, an example in which the DTI structure 90 is formed as the element isolation structure has been described, but the element isolation structure may be one that utilizes a diffusion isolation method including a ring-shaped p-type diffusion region that separates the region where the MISFET 23a is formed, that is, a pn junction isolation method.

[0077] An interlayer insulating film 74 is formed on the surface of the epitaxial layer 62. The interlayer insulating film 74 includes at least one of a silicon oxide film and a silicon nitride film. The interlayer insulating film 74 has a laminated structure in which a first interlayer insulating film 75, a second interlayer insulating film 76, a third interlayer insulating film 77, and a fourth interlayer insulating film 78 are laminated in this order from the surface side of the epitaxial layer 62. The first interlayer insulating film 75, the second interlayer insulating film 76, the third interlayer insulating film 77, and the fourth interlayer insulating film 78 are formed of an insulator such as silicon oxide or silicon nitride. For example, USG (HDP-USG: High Density Plasma-CVD-Undoped Silica Glass) by a high density plasma CVD method may be used for the first interlayer insulating film 75, the second interlayer insulating film 76, the third interlayer insulating film 77, and the fourth interlayer insulating film 78. The first interlayer insulating film 75 covers the surface of the epitaxial layer 62. The first interlayer insulating film 75 fills a recess 79 formed by the difference in height between the upper surface of the gate electrode 68 and the surface of the epitaxial layer 62. The first interlayer insulating film 75 has a thickness TF1 of, for example, 13,500 Å, the second interlayer insulating film 76 has a thickness TF2 of, for example, 8,000 Å, the third interlayer insulating film 77 has a thickness TF3 of, for example, 13,500 Å, and the fourth interlayer insulating film 78 has a thickness TF4 of, for example, 10,000 Å.

[0078] A first source electrode 80 is formed on the first interlayer insulating film 75 as a first metal (first metal layer). The first source electrode 80 is an electrode film containing one or more metal species selected from a group including, for example, aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), and tantalum (Ta). The thickness of the first source electrode 80 is, for example, 4000 Å. The first source electrode 80 is electrically connected to the source region 70 and the body contact region 73 via corresponding contacts 81. The first source electrode 80 is covered with a second interlayer insulating film 76.

[0079] Further, in the body region 71 between the trench gate structure 65 and the DTI structure 90, a body contact region 73 is formed, but a source region 70 is not formed. Therefore, a contact 81 on the body region 71 between the trench gate structure 65 and the DTI structure 90 is electrically connected to the body contact region 73. A wiring 93 is formed on the first interlayer insulating film 75 so as to be electrically connected to the contact 81. The wiring 93 extends so as to cover the DTI structure 90. A contact 94 is electrically connected to the wiring 93. The contact 94 is connected to the insulator 92. Although not shown in FIG. 9, the wiring 93 is connected to the first source electrode 80.

[0080] A second source electrode 82 is formed on the third interlayer insulating film 77 as a second metal (second metal layer). The second source electrode 82 is an electrode film containing one or more metal species selected from a group including, for example, aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), and tantalum (Ta). The second source electrode 82 has a thickness of, for example, 8000 Å. The second source electrode 82 is electrically connected to the first source electrode 80 via a corresponding contact 83. The outer periphery of the second source electrode 82 is covered with a fourth interlayer insulating film 78.

[0081] A passivation film 84 is formed on the surface of the fourth interlayer insulating film 78. The passivation film 84 includes, for example, at least one of silicon nitride and silicon oxide. The passivation film 84 may be a laminated film including a silicon oxide film and a silicon nitride film formed on the silicon oxide film. The passivation film 84 in this embodiment is made of a silicon nitride film. The thickness of the passivation film 84 is, for example, 11,000 Å.

[0082] The source pad 21 is provided in an opening 85 that penetrates the fourth interlayer insulating film 78 and the passivation film 84. The source pad 21 has an inner periphery 86 that contacts the second source electrode 82 within the opening 85, and an outer periphery 87 that extends beyond the opening 85 and covers the surface of the passivation film 84. The thickness of the inner periphery 86 of the source pad 21 is, for example, 42,000 Å.

[0083] A surface protective film 88 is formed on the surface of the source pad 21. An example of the surface protective film 88 is a film containing polyimide. The surface protective film 88 covers a part of an inner periphery 86 and a part of an outer periphery 87 of the source pad 21. The surface protective film 88 has an opening 89 for connecting the first wire 41 to the source pad 21.

[0084] [Structure of semiconductor elements constituting the control circuit] 12 to 17, the structures of the control semiconductor elements constituting the overcurrent protection circuit 24, the overheat protection circuit 25, and the low voltage malfunction prevention circuit 26, which are control circuits for controlling the MISFET 23a of the semiconductor device 1, will be described. Examples of the control semiconductor elements include a low voltage CMOS (Complementary MOS) FET, a MOS capacitor, a polysilicon resistor, a high voltage P channel type MOSFET, a high voltage N channel type MOSFET, and an NPN transistor. These control semiconductor elements are provided on a substrate 50, similar to the MISFET 23a. In the following description, n-type impurities (n-type) refer to elements containing pentavalent elements (e.g., phosphorus (P), arsenic (As), etc.) as the main impurity, and p-type impurities (p-type) refer to elements containing trivalent elements (e.g., boron (B), indium (In), gallium (Ga), etc.) as the main impurity.

[0085] The low-voltage CMOSFET shown in FIG. 12 has a CMOS region 100 in which a CMOS transistor is formed. In the epitaxial layer 62 of the substrate 50, a DTI structure 101 is formed as an element isolation structure that separates the CMOS region 100 from other regions. The DTI structure 101 is formed in a substantially annular shape in a plan view seen from a normal direction of the surface of the epitaxial layer 62 (hereinafter, simply referred to as "plan view"). The DTI structure 101 includes an insulator 101b embedded in a trench 101a formed in the epitaxial layer 62. An example of the insulator 101b is polysilicon. Note that the insulator 101b may be silicon oxide. Note that, in the present embodiment, an example in which the DTI structure 101 is formed as the element isolation structure has been described, but the element isolation structure may be one that utilizes a diffusion isolation method including a ring-shaped p-type diffusion region that separates the CMOS region 100, that is, a pn junction isolation method.

[0086] In the CMOS region 100, a first P well region 102, which is a p-type high-voltage well region, is formed at a distance from the DTI structure 101. In order to secure a distance between the DTI structure 101 and the first P well region 102, a second P well region 103, which is a p-type low-voltage well region, is formed in a surface layer portion of the epitaxial layer 62. The second P well region 103 is formed in a substantially annular shape so as to be adjacent to the DTI structure 101. Note that, when the DTI structure 101 is formed in a striped shape instead of a substantially annular shape, the second P well region 103 is formed in a striped shape so as to be adjacent to each DTI structure 101. The impurity concentration of the second P well region 103 is higher than the impurity concentration of the first P well region 102.

[0087] In the first P well region 102, a first N well region 104 and a second N well region 105, which are two n-type well regions, are formed in the surface layer portion of the epitaxial layer 62. The first N well region 104 is formed so as to surround the second N well region 105. The thickness of the first N well region 104 is thinner than the thickness of the first P well region 102. The thickness of the second N well region 105 is thinner than the thickness of the first N well region 104. The impurity concentration of the first N well region 104 is higher than the impurity concentration of the first P well region 102. The impurity concentration of the second N well region 105 is higher than the impurity concentration of the first N well region 104. In the following description, the thickness refers to the length in the normal direction of the surface of the epitaxial layer 62.

[0088] In the second N-well region 105, a p-type source region 106, a p-type drain region 107, and an n-type contact region 108 are formed in a surface layer portion of the epitaxial layer 62. The source region 106, the drain region 107, and the contact region 108 are formed with an interval between them. The source region 106 is formed between the contact region 108 and the drain region 107. The impurity concentrations of the source region 106, the drain region 107, and the contact region 108 are each higher than the impurity concentration of the second N-well region 105.

[0089] In the CMOS region 100, a third P well region 109, which is a p-type low-voltage well region, is formed at a distance from the first N well region 104 in the surface layer of the epitaxial layer 62. The third P well region 109 is integrated with the second P well region 103. An n-type source region 110, an n-type drain region 111, and a p-type contact region 112 are formed at a surface layer of the third P well region 109. The source region 110, the drain region 111, and the contact region 112 are formed at a distance from each other. The contact region 112 is formed in the third P well region 109 near the DTI structure 101 adjacent to the third P well region 109 (the second P well region 103). In other words, the contact region 112 is formed in the region of the third P well region 109 where the second P well region 103 is integrated. That is, the contact region 112 also serves as a contact region for the second P well region 103. The source region 110 is formed between the drain region 111 and the contact region 112.

[0090] An insulating film 113 is formed on the surface of the epitaxial layer 62 in the CMOS region 100 and between the trench 101a and the insulator 101b of the DTI structure 101. An example of the insulating film 113 is a silicon oxide film. A first gate electrode 114 facing the second N-well region 105 and a second gate electrode 115 facing the third P-well region 109 are formed on the insulating film 113. Each of the gate electrodes 114, 115 is, for example, polysilicon doped with an impurity. Both side surfaces of each of the gate electrodes 114, 115 are covered with sidewalls 116, 117 including an insulating material such as silicon oxide or silicon nitride.

[0091] As in the MISFET 23a, an interlayer insulating film 74 and a passivation film 84 are laminated in this order on the epitaxial layer 62 in the CMOS region 100. A first source electrode 118, a first drain electrode 119, a first gate electrode (not shown), a second source electrode 120, a second drain electrode 121, a second gate electrode (not shown), a backgate electrode 122, and a ground electrode 123 are formed as first metals on the first interlayer insulating film 75. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0092] The first source electrode 118 is electrically connected to the source region 106 of the second n-well region 105 via a contact, the first drain electrode 119 is electrically connected to the drain region 107 of the second n-well region 105 via a contact, and the backgate electrode 122 is electrically connected to the contact region 108 of the second n-well region 105 via a contact. In this manner, a p-type MOSFET is formed.

[0093] The second source electrode 120 is electrically connected to the source region 110 of the third P well region 109 via a contact, and the second drain electrode 121 is electrically connected to the drain region 111 of the third P well region 109 via a contact. In this manner, an n-type MOSFET is formed.

[0094] The ground electrode 123 is electrically connected to the contact region 112 of the second P well region 103 via a contact. The ground electrode 123 is electrically connected to the insulator 101b of the DTI structure 101 via a contact. The ground electrode 123 is electrically connected to the contact region 112 of the third P well region 109, and serves as a back gate of an n-type MOSFET formed in the third P well region 109. In this way, the DTI structure 101, the third P well region 109, and the first P well region 102 are at ground potential.

[0095] On the third interlayer insulating film 77, a third source electrode, a third drain electrode, a third gate electrode, a fourth source electrode, and a fourth gate electrode are formed as a second metal (all not shown). The third source electrode is electrically connected to the first source electrode 118, the third drain electrode is electrically connected to the first drain electrode 119 and the second drain electrode 121, and the third gate electrode is electrically connected to the first gate electrode 114. The fourth source electrode is electrically connected to the second source electrode 120, and the fourth gate electrode is electrically connected to the second gate electrode. In this manner, the first drain electrode 119 and the second drain electrode 121 are electrically connected via the third drain electrode to form a CMOS transistor.

[0096] The MOS capacitor shown in FIG. 13 has a capacitor region 130 in which a capacitor is formed. In the epitaxial layer 62 of the substrate 50, a DTI structure 131 is formed as an element isolation structure that separates the capacitor region 130 from other regions. The DTI structure 131 has the same structure as the DTI structure 101 (see FIG. 12) of the low-voltage CMOSFET, and is a structure in which an insulator 131b is embedded in a trench 131a. An example of the insulator 131b is polysilicon. The insulator 131b may be silicon oxide. In the present embodiment, an example in which the DTI structure 131 is formed as the element isolation structure has been described, but the element isolation structure may be one that utilizes a pn junction isolation method including a ring-shaped p-type diffusion region that separates the capacitor region 130.

[0097] In the capacitor region 130, a first P well region 132 which is a p-type high voltage well region and a second P well region 133 which is a p-type low voltage well region are formed. The first P well region 132 is formed at a distance from the DTI structure 131. The second P well region 133 is formed so as to straddle the first P well region 132 and be adjacent to the DTI structure 131 in order to secure a distance between the DTI structure 131 and the first P well region 132. The thickness of the second P well region 133 is thinner than the thickness of the first P well region 132. The impurity concentration of the second P well region 133 is higher than the impurity concentration of the first P well region 132. A p-type contact region 134 is formed in a surface layer portion of the second P well region 133.

[0098] In the first P well region 132, a first N well region 135, a second N well region 136, and a third N well region 137, which are three n-type well regions, are formed in the surface layer portion of the epitaxial layer 62. The first N well region 135 is formed so as to surround the second N well region 136. The second N well region 136 is formed so as to surround the third N well region 137. The thickness of the first N well region 135 is thinner than the thickness of the first P well region 132. The thickness of the second N well region 136 is thinner than the thickness of the first N well region 135. The thickness of the third N well region 137 is thinner than the thickness of the second N well region 136. The impurity concentration of the first N well region 135 is higher than the impurity concentration of the first P well region 132. The impurity concentration of the second N well region 136 is higher than the impurity concentration of the first N well region 135. The impurity concentration of the third n-well region 137 is higher than the impurity concentration of the second n-well region 136. An n-type contact region 138 is formed in a surface layer portion of the second n-well region 136 outside the third n-well region 137. The impurity concentration of the contact region 138 is higher than the impurity concentration of the second n-well region 136.

[0099] An insulating film 139 is formed on the surface of the epitaxial layer 62 in the capacitor region 130 and between the trench 131a and the insulator 131b of the DTI structure 131. An example of the insulating film 139 is a silicon oxide film. A gate electrode 140 is formed on the insulating film 139. The gate electrode 140 is formed so as to cover the entire third n-well region 137 and a part of the second n-well region 136. The gate electrode 140 is, for example, polysilicon to which an impurity is added. Both end faces of the gate electrode 140 are covered with sidewalls 141 including an insulating material such as silicon oxide or silicon nitride.

[0100] Similar to the MISFET 23a, an interlayer insulating film 74 and a passivation film 84 are laminated in this order on the epitaxial layer 62 in the capacitor region 130. A first electrode 142, a first gate electrode 143, and a ground electrode 144 are formed as first metals on the first interlayer insulating film 75. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0101] The first electrode 142 is electrically connected to the contact region 138 of the second N well region 136 via a contact, and the first gate electrode 143 is electrically connected to the gate electrode 140 via a contact. The ground electrode 144 is electrically connected to the contact region 134 of the second P well region 133 via a contact. The ground electrode 144 is electrically connected to the insulator 131b of the DTI structure 131 via a contact. In this manner, the DTI structure 131 and the second P well region 133 are at ground potential.

[0102] A second electrode and a second gate electrode (both not shown) are formed as a second metal on the third interlayer insulating film 77. The second electrode is electrically connected to the first electrode 142, and the second gate electrode is electrically connected to the first gate electrode 143.

[0103] The polysilicon resistor shown in FIG. 14 has a resistor region 150 in which a resistor is formed. In the epitaxial layer 62 of the substrate 50, a DTI structure 151 is formed as an element isolation structure that separates the resistor region 150 from other regions. The DTI structure 151 has the same structure as the DTI structure 101 (see FIG. 12) of the low-voltage CMOSFET, and is a structure in which an insulator 151b is embedded in a trench 151a. An example of the insulator 151b is polysilicon. The insulator 151b may be silicon oxide. In the present embodiment, an example in which the DTI structure 151 is formed as the element isolation structure has been described, but the element isolation structure may be one that utilizes a pn junction isolation method including a ring-shaped p-type diffusion region that separates the resistor region 150.

[0104] In the resistance region 150, a first P well region 152 which is a p-type high voltage well region and a second P well region 153 which is a p-type low voltage well region are formed. The first P well region 152 is formed at a distance from the DTI structure 151. The second P well region 153 is formed so as to straddle the first P well region 152 and be adjacent to the DTI structure 151 in order to secure a distance between the DTI structure 151 and the first P well region 152. The thickness of the second P well region 153 is thinner than the thickness of the first P well region 152. The impurity concentration of the second P well region 153 is higher than the impurity concentration of the first P well region 152. A p-type contact region 154 is formed in a surface layer portion of the second P well region 153.

[0105] An insulating film 155 is formed on the surface of the epitaxial layer 62 in the resistor region 150 and between the trench 151a and the insulator 151b of the DTI structure 151. An example of the insulating film 155 is a silicon oxide film. A first polysilicon resistor 156 and a second polysilicon resistor 157 are formed on the insulating film 155 with a gap between them. The first polysilicon resistor 156 and the second polysilicon resistor 157 face the first P well region 152. Both sides of the first polysilicon resistor 156 are covered with sidewalls 156a including an insulating material such as silicon oxide or silicon nitride, and both sides of the second polysilicon resistor 157 are covered with sidewalls 157a similarly to the first polysilicon resistor 156. In this embodiment, the first polysilicon resistor 156 has a low concentration of impurities added to the polysilicon, i.e., has a high resistance, and the second polysilicon resistor 157 has a low concentration of impurities added to the polysilicon, i.e., has a low resistance. It is possible to arbitrarily change the number and type of polysilicon resistors formed in the resistor region 150. For example, one of the first polysilicon resistor 156 and the second polysilicon resistor 157 may be omitted.

[0106] On the epitaxial layer 62 in the resistance region 150, an interlayer insulating film 74 and a passivation film 84 are laminated in this order, as in the MISFET 23a. On the first interlayer insulating film 75, a ground electrode 158 is formed as a first metal. The ground electrode is an electrode film containing one or more metal species selected from a group including, for example, aluminum, copper, titanium, tungsten, and tantalum. The ground electrode 158 is electrically connected to the insulator 151b and the contact region 154 of the DTI structure 151 via a plurality of contacts. In this way, the DTI structure 151, the second P well region 153, and the first P well region 152 are at ground potential.

[0107] The high-voltage N-channel MOSFET shown in FIG. 15 has an NMOS region 160 in which an N-channel MOSFET is formed. In the epitaxial layer 62 of the substrate 50, a DTI structure 161 is formed as an element isolation structure that separates the NMOS region 160 from other regions. The DTI structure 161 has the same structure as the DTI structure 101 (see FIG. 12) of the low-voltage CMOSFET, and is a structure in which an insulator 161b is embedded in a trench 161a. An example of the insulator 161b is polysilicon. The insulator 161b may be silicon oxide. In the present embodiment, an example in which the DTI structure 161 is formed as the element isolation structure has been described, but the element isolation structure may be one that utilizes a pn junction isolation method including a ring-shaped p-type diffusion region that separates the NMOS region 160.

[0108] In the NMOS region 160, a first P well region 162, which is a p-type low-voltage well region, is formed at a distance from the DTI structure 161. In order to secure a distance between the DTI structure 161 and the first P well region 162, a second P well region 163, which is a p-type low-voltage well region, is formed in a surface layer portion of the epitaxial layer 62. The second P well region 163 is formed in a substantially annular shape so as to be adjacent to the DTI structure 161. Note that, when the DTI structure 161 is formed in a striped shape instead of a substantially annular shape, the second P well region 163 is formed in a striped shape so as to be adjacent to each DTI structure 161. The impurity concentration of the second P well region 163 is higher than the impurity concentration of the first P well region 162.

[0109] In the NMOS region 160, an N-well region 164, which is an n-type well region, is formed in a surface portion of the epitaxial layer 62. The N-well region 164 is formed in the first P-well region 162. The thickness of the N-well region 164 is thinner than the thickness of the first P-well region 162. The impurity concentration of the N-well region 164 is higher than the impurity concentration of the first P-well region 162. An n-type drain region 165 is formed in a surface portion of the N-well region 164. The impurity concentration of the drain region 165 is higher than the impurity concentration of the N-well region 164.

[0110] In addition, in the NMOS region 160, a third P well region 166, which is a p-type low-voltage well region, is formed in the surface layer of the epitaxial layer 62. The third P well region 166 is formed at a distance from the N well region 164. The third P well region 166 is formed integrally with the second P well region 163. The thickness of the third P well region 166 is thinner than the thickness of the first P well region 162 and the thickness of the N well region 164. An n-type source region 167 and a p-type contact region 168 are formed in the surface layer of the third P well region 166. The source region 167 and the contact region 168 are formed at a distance from each other. The contact region 168 is formed in a region of the third P well region 166 where the second P well region 163 is integrated. That is, the contact region 168 also serves as a contact region of the second P well region 163.

[0111] An insulating film 169 is formed on the surface of the epitaxial layer 62 in the NMOS region 160 and between the trench 161a and the insulator 161b of the DTI structure 161. An example of the insulating film 169 is a silicon oxide film. A gate electrode 170 is formed on the insulating film 169 so as to extend across the third P well region 166, the first P well region 162, and the N well region 164 and face the third P well region 166. The gate electrode 170 is, for example, polysilicon to which an impurity is added. Both side surfaces of the gate electrode 170 are covered with sidewalls 171 including an insulating material such as silicon oxide or silicon nitride.

[0112] Similar to the MISFET 23a, an interlayer insulating film 74 and a passivation film 84 are laminated in this order on the epitaxial layer 62 in the NMOS region 160. A first source electrode 172, a first drain electrode 173, a first gate electrode 174, and a ground electrode 175 are formed as first metals on the first interlayer insulating film 75. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0113] The first source electrode 172 is electrically connected to the source region 167, the first drain electrode 173 is electrically connected to the drain region 165, and the first gate electrode 174 is electrically connected to the gate electrode 170. In addition, the ground electrode 175 is electrically connected to the contact region 168 of the second P well region 163 and the insulator 161b of the DTI structure 161 via a plurality of contacts. In this manner, the DTI structure 161, the second P well region 163, and the first P well region 162 are at ground potential.

[0114] A second source electrode, a second drain electrode, and a second gate electrode (all not shown) are formed as a second metal on the third interlayer insulating film 77. The second source electrode is electrically connected to the first source electrode 172, the second drain electrode is electrically connected to the first drain electrode 173, and the second gate electrode is electrically connected to the first gate electrode 174. These electrodes are formed of, for example, the same material as the electrodes (such as the first source electrode 172) that form the first metal.

[0115] In the high-voltage P-channel MOSFET shown in FIG. 16, a PMOS region 180 in which a P-channel MOSFET is formed is formed. In the epitaxial layer 62 of the substrate 50, a DTI structure 181 is formed as an element isolation structure that separates the PMOS region 180 from other regions. The DTI structure 181 has the same structure as the DTI structure 101 (see FIG. 12) of the low-voltage CMOSFET, and is a structure in which an insulator 181b is embedded in a trench 181a. An example of the insulator 181b is polysilicon. The insulator 181b may be silicon oxide. In the present embodiment, an example in which the DTI structure 181 is formed as the element isolation structure has been described, but the element isolation structure may be one that utilizes a pn junction isolation method including a ring-shaped p-type diffusion region that separates the PMOS region 180.

[0116] In the PMOS region 180, a P-well region 182 which is a p-type high voltage well region and an N-well region 183 which is an n-type well region are formed in a surface layer portion of the epitaxial layer 62. The P-well region 182 and the N-well region 183 are formed at a distance from the DTI structure 181. The P-well region 182 and the N-well region 183 are formed at a distance from each other. The thickness of the N-well region 183 is thinner than the thickness of the P-well region 182. A p-type drain region 184 is formed in a surface layer portion of the P-well region 182. A p-type source region 185 is formed in a surface layer portion of the N-well region 183.

[0117] An n-type contact region 186 is formed in a surface layer portion of the epitaxial layer 62 in the PMOS region 180. The contact region 186 is formed in a substantially annular shape, and is formed between the P-well region 182 and the DTI structure 181 at a distance from the P-well region 182 and the DTI structure 181, and is formed between the N-well region 183 and the DTI structure 181 at a distance from the N-well region 183 and the DTI structure 181.

[0118] An insulating film 187 is formed on the surface of the epitaxial layer 62 in the PMOS region 180 and between the trench 181a and the insulator 181b of the DTI structure 181. An example of the insulating film 187 is a silicon oxide film. A gate electrode 188 is formed on the insulating film 187 so as to extend across the N-well region 183, the epitaxial layer 62, and the P-well region 182 and face the N-well region 183. The gate electrode 188 is, for example, polysilicon to which an impurity is added. Both side surfaces of the gate electrode 188 are covered with sidewalls 189 including an insulating material such as silicon oxide or silicon nitride.

[0119] As in the MISFET 23a, an interlayer insulating film 74 and a passivation film 84 are laminated in this order on the epitaxial layer 62 in the PMOS region 180. A first source electrode 190, a first drain electrode 191, and a first gate electrode 192 are formed as first metals on the first interlayer insulating film 75. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0120] The first source electrode 190 is electrically connected to the source region 185 via a contact, the first drain electrode 191 is electrically connected to the drain region 184 via a contact, and the first gate electrode 192 is electrically connected to the gate electrode 188 via a contact.

[0121] A second source electrode, a second drain electrode, and a second gate electrode (all not shown) are formed as a second metal on the third interlayer insulating film 77. The second source electrode is electrically connected to the first source electrode 190, the second drain electrode is electrically connected to the first drain electrode 191, and the second gate electrode is electrically connected to the first gate electrode 192. These electrodes are formed of, for example, the same material as the electrodes (such as the first source electrode 190) that form the first metal.

[0122] The NPN transistor shown in FIG. 17 has a transistor region 200 forming a bipolar transistor. In the epitaxial layer 62 of the substrate 50, a DTI structure 201 is formed as an element isolation structure that separates the transistor region 200 from other regions. The DTI structure 201 has the same structure as the DTI structure 101 (see FIG. 12) of the low-voltage CMOSFET, and is a structure in which an insulator 201b is embedded in a trench 201a. An example of the insulator 201b is polysilicon. The insulator 201b may be silicon oxide. In the present embodiment, an example in which the DTI structure 201 is formed as the element isolation structure has been described, but the element isolation structure may be one that utilizes a pn junction isolation method including a ring-shaped p-type diffusion region that separates the transistor region 200.

[0123] In the transistor region 200, a first P well region 202, which is a p-type low-voltage well region, is formed at a distance from the DTI structure 201. In order to secure a distance between the DTI structure 201 and the first P well region 202, a second P well region 203, which is a p-type low-voltage well region, is formed in the surface layer portion of the epitaxial layer 62. The second P well region 203 is formed in a substantially annular shape so as to be adjacent to the DTI structure 201. In addition, when the DTI structure 201 is formed in a striped shape instead of a substantially annular shape, the second P well region 203 is formed in a striped shape so as to be adjacent to each DTI structure 201. The impurity concentration of the second P well region 203 is higher than the impurity concentration of the first P well region 202. In the surface layer portion of the second P well region 203, a ring-shaped p-type contact region 204 is formed. The impurity concentration of the contact region 204 is higher than the impurity concentration of the second P well region 203.

[0124] An N-well region 205, which is an n-type well region, is formed in a surface portion of the epitaxial layer 62 in the transistor region 200. The N-well region 205 is formed in the first P-well region 202. The thickness of the N-well region 205 is thinner than the thickness of the first P-well region 202. The impurity concentration of the N-well region 205 is higher than the impurity concentration of the first P-well region 202.

[0125] In the N-well region 205, a p-type base region 206 is formed in a surface layer portion of the epitaxial layer 62. The N-well region 205 is formed so as to surround the base region 206. The thickness of the base region 206 is thinner than the thickness of the N-well region 205. In the surface layer portion of the base region 206, a p-type base contact region 207 and an n-type emitter region 208 are formed. The base contact region 207 and the emitter region 208 are formed with a gap between them. The impurity concentrations of the base contact region 207 and the emitter region 208 are higher than the impurity concentration of the N-well region 205. In the N-well region 205, an annular n-type collector region 209 is formed outside the base region 206. The impurity concentration of the collector region 209 is higher than the impurity concentration of the N-well region 205.

[0126] An insulating film 210 is formed on the surface of the epitaxial layer 62 in the transistor region 200 and between the trench 201a and the insulator 201b of the DTI structure 201. An example of the insulating film 210 is a silicon oxide film.

[0127] Similar to the MISFET 23a, an interlayer insulating film 74 and a passivation film 84 are laminated in this order on the epitaxial layer 62 in the transistor region 200. A first emitter electrode 211, a first collector electrode 212, a first base electrode 213, and a ground electrode 214 are formed as first metals on the first interlayer insulating film 75. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0128] The first emitter electrode 211 is electrically connected to the emitter region 208 via a contact, the first collector electrode 212 is electrically connected to the collector region 209 via a contact, and the first base electrode 213 is electrically connected to the base contact region 207 via a contact. The ground electrode 214 is electrically connected to the contact region 204 of the second P well region 203 via a contact. The ground electrode 214 is electrically connected to the insulator 201b of the DTI structure 201 via a plurality of contacts. In this way, the DTI structure 201, the second P well region 203, and the first P well region 202 are at ground potential.

[0129] A second emitter electrode, a second collector electrode, and a second base electrode (all not shown) are formed as a second metal on the third interlayer insulating film 77. The second emitter electrode is electrically connected to the first emitter electrode 211, the second collector electrode is electrically connected to the first collector electrode 212, and the second base electrode is electrically connected to the first base electrode 213. These electrodes are formed of, for example, the same material as the electrodes (such as the first emitter electrode 211) that form the first metal.

[0130] [Method of manufacturing a semiconductor device] A manufacturing method of semiconductor device 1 will be described with reference to FIGS. 18 to 19F. As shown in FIG. 18, the manufacturing method of the semiconductor device 1 includes an element mounting process (step S1), a first wire connecting process (step S2), a second wire connecting process (step S3), a molding process (step S4), a frame separation process (step S5), and a terminal bending process (step S6).

[0131] In the element mounting process shown in FIG. 19A, a frame FL including a lead frame 10 is first prepared. The frame FL is configured by connecting a first lead frame 11, a second lead frame 12, and a third lead frame 13 to an outer frame portion FL1. The first terminal portion 11b of the first lead frame 11 is connected to a second terminal portion 12b of the second lead frame 12 and a third terminal portion 13b of the third lead frame 13 by a connecting portion FL2 (diver). In the frame FL, the first terminal portion 11b is in a state in which the first bent portion 11g, the inclined portion 11h, the second bent portion 11i, and the tip portion 11j are already formed. In the frame FL, the second terminal portion 12b and the third terminal portion 13b are provided so as to be in the same position as the tip portion 11j of the first terminal portion 11b. The frame FL is also nickel-plated in advance.

[0132] Next, solder SD (not shown in FIG. 19A, see FIG. 3) is applied to each first island portion 11a of the frame FL. Then, a semiconductor element 20 is mounted on each solder SD. In one example, the semiconductor element 20 is picked up by a die bonder device (not shown), and the semiconductor element 20 is fixed onto the solder SD of the first island portion 11a.

[0133] 19B, the first wire 41 is connected by wedge bonding to the source pad 21 of the semiconductor element 20 and the third island portion 13a of the third lead frame 13. In detail, a wedge bonding device (not shown) that performs wedge bonding first connects the first wire 41 to the source pad 21 (first bonding) and then connects it to the third island portion 13a (second bonding).

[0134] 7 and 8, the connection portion 41a of the first wire 41 to the source pad 21 includes the center of gravity GC of the active region 29 of the semiconductor element 20. At this time, the connection portion 41a is formed so as to extend toward the third island portion 13a of the third lead frame 13 by a wedge bonding device.

[0135] In a second wire connecting step shown in FIG. 19C, the second wire 42 is connected to the gate pad 22 of the semiconductor element 20 and the second island portion 12a of the second lead frame 12 by wedge bonding.

[0136] In the molding step shown in Fig. 19D, the sealing resin 30 is molded, for example, by a molding device. In one example, molten epoxy resin is poured into a cavity of a mold of the molding device with the assembly manufactured in the second wire connection step placed in the cavity of the mold. This forms the sealing resin 30 that seals the semiconductor element 20, the first wire 41, and the second wire 42 (all see Fig. 19C).

[0137] In a frame separation step shown in Fig. 19E, the lead frame 10 is separated from the frame FL (see Fig. 19D) by, for example, a press molding device. In detail, the first lead frame 11, the second lead frame 12, and the third lead frame 13 are cut from the outer frame portion FL1 (see Fig. 19D), and the connecting portion FL2 (see Fig. 19D) connecting the first terminal portion 11b of the first lead frame 11 to the second terminal portion 12b of the second lead frame 12 and the third terminal portion 13b of the third lead frame 13 is cut.

[0138] 19F, the portions of the second terminal portion 12b of the second lead frame 12 and the third terminal portion 13b of the third lead frame 13 that protrude from the sealing resin 30 are bent by, for example, a press molding device. Through the above steps, the semiconductor device 1 shown in FIG.

[0139] According to this embodiment, the following effects can be obtained. (1-1) The region where the first wire 41 is connected to the source pad 21, i.e., the connection portion 41a of the first wire 41, includes the center of gravity GC of the active region 29, which is the transistor formation region. With this configuration, it is possible to improve the active clamp withstand capability Eac compared to a case where the connection portion 41a of the first wire 41 is connected to a portion of the source pad 21 other than the center of gravity GC of the active region 29.

[0140] (1-2) The connection portion 41a of the first wire 41 extends toward the second island portion 12a of the second lead frame 12. Therefore, although the middle portion of the first wire 41 connecting the semiconductor element 20 and the second island portion 12a is bent, the degree of bending can be reduced. As a result, the reliability of the semiconductor device 1 can be improved.

[0141] (1-3) A plating layer 14 is formed on the surface of the first island portion 11a of the first lead frame 11. With this configuration, when the solder SD is applied to the first island portion 11a, the wettability of the solder SD decreases, so that the solder SD is less likely to spread over the surface of the first island portion 11a. This prevents the thickness of the solder SD from becoming excessively thin, so that the semiconductor element 20 and the first island portion 11a can be appropriately connected.

[0142] (1-4) The first wire 41 is made of aluminum, and the second lead frame 12 is made of copper. A plating layer 14 is formed on the surface of the second island portion 12a of the second lead frame 12 to which the first wire 41 is connected. With this configuration, it is possible to suppress corrosion of the connection portion between the first wire 41 and the second island portion 12a.

[0143] (1-5) The second wire 42 is made of aluminum, and the third lead frame 13 is made of copper. A plating layer 14 is formed on the surface of the third island portion 13a of the third lead frame 13 to which the second wire 42 is connected. With this configuration, it is possible to suppress corrosion of the connection portion between the second wire 42 and the third island portion 13a.

[0144] (1-6) The temperature sensor 27 is disposed in a location in the active region 29 outside the source pad 21 where the most heat is concentrated when the semiconductor device 1 is driven. This allows the temperature of the semiconductor device 1 to be detected with high accuracy.

[0145] (1-7) In general, the linear expansion coefficient of an encapsulating resin (hereinafter, comparative encapsulating resin) that encapsulates an LSI that does not include a power transistor is 8 ppm / K to 10 ppm / K. The inventor of the present application conducted, for example, a temperature cycle test on a semiconductor device using the comparative encapsulating resin. In the temperature cycle test, the temperature conditions were changed from -65°C to 150°C for approximately 1000 cycles. As a result, it was found that pitting corrosion occurred in the first wire connected to the source pad of the semiconductor element and the third island portion of the third lead frame. The first wire used is the same as the first wire 41 of the semiconductor device 1.

[0146] From this, it is believed that the surface of the first wire is protected by a natural oxide film, but when a load is applied to the first wire based on the difference between the linear expansion coefficient of the first wire and the linear expansion coefficient of the sealing resin during the temperature cycle test, the natural oxide film is broken and the chloride ions of the sealing resin bond with the first wire, resulting in pitting corrosion on the first wire.

[0147] In this regard, in the present embodiment, a material having a linear expansion coefficient larger than 10 ppm / K is used as the sealing resin 30. More specifically, a sealing resin 30 having a linear expansion coefficient of 12 ppm / K is used. This reduces the difference between the linear expansion coefficient of the first wire 41 and the linear expansion coefficient of the sealing resin 30, thereby reducing the load on the first wire 41 due to the temperature cycle test. This prevents the natural oxide film of the first wire 41 from being broken, thereby preventing the occurrence of pitting corrosion of the first wire 41.

[0148] On the other hand, in this embodiment, the filler content is increased in order to increase the linear expansion coefficient of the sealing resin 30. However, if the filler content is too high, the moldability of the sealing resin 30 is excessively reduced. Specifically, if the linear expansion coefficient of the sealing resin 30 is 15 ppm / K or more, the moldability of the sealing resin 30 is excessively reduced.

[0149] In this regard, since the sealing resin 30 in this embodiment has a linear expansion coefficient smaller than 15 ppm / K, it is possible to suppress deterioration in the moldability of the sealing resin 30. In this manner, in this embodiment, it is possible to suppress the occurrence of pitting corrosion of the first wire 41 and to suppress deterioration in the moldability of the sealing resin 30.

[0150] (1-8) In the MISFET 23a, the ratio of the area of ​​the channel formation region 72 to the unit area is less than 100%. In the MISFET 23a of this embodiment, the ratio of the area of ​​the channel formation region 72 to the unit area is about 50%. Therefore, compared to when the ratio is 100%, it is possible to suppress heat generation in the active region 29. Therefore, it is possible to improve the active clamp withstand voltage Eac.

[0151] (1-9) The surface of the source pad 21 of the MISFET 23a is formed with projections and recesses. With this configuration, the adhesion between the source pad 21 and the sealing resin 30 can be improved.

[0152] Second embodiment A semiconductor device 1 of the second embodiment will be described with reference to Figs. 20 to 22. The semiconductor device 1 of this embodiment is different from the semiconductor device 1 of the first embodiment in the connection structure of the first wire 41 to the source pad 21. In the following description, the same components as those of the semiconductor device 1 of the first embodiment are given the same reference numerals, and the description thereof will be omitted. Figs. 20 and 21 are enlarged plan views showing a part of the substrate 50. In Fig. 20, the active region 29 is indicated by a solid line, and the source pad 21 is indicated by a two-dot chain line. In Fig. 21, the active region 29 is indicated by a dashed line, and the source pad 21 is indicated by a solid line.

[0153] The present inventors have focused on the connection position of the source pad 21 of the first wire 41 connected to the semiconductor element 20 with respect to the active clamp withstand voltage Eac of the semiconductor device 1. The present inventors have found that when the first wire 41 is connected to the source pad 21 at two points, the active clamp withstand voltage Eac is improved when the first wire 41 is connected to the source pad 21 at positions corresponding to the center positions of two divided regions obtained by dividing the active region 29 into two equal areas. In view of this, in this embodiment, as shown in FIG. 21, the first wire 41 is connected to the source pad 21 at two connection points. These two connection points are the center positions GB1 and GB2 of the divided active region 29 when the area of ​​the active region 29 is divided into two equal areas.

[0154] Here, the center of gravity positions GB1, GB2 of the active area 29 are determined as follows. As shown in Fig. 20, first, the source pad 21 is divided into two divided regions (a first region RB1 and a second region RB2) having an equal area. As shown in Fig. 20, at least one of the first region RB1 and the second region RB2 may be a region other than a rectangular shape. The first region RB1 shown in Fig. 20 is a region having a rectangular convex portion. On the other hand, the second region RB2 is a rectangular region.

[0155] Next, the center of gravity GB1 of the first region RB1 and the center of gravity GB2 of the second region RB2 are obtained. As shown in FIG. 20, since the second region RB2 is rectangular, the center of gravity GB2 of the second region RB2 is the intersection of the diagonal lines of the second region RB2. On the other hand, since the first region RB1 is not rectangular, the first region RB1 is further divided into a first divided region RB11 and a second divided region RB12. In detail, the region that is a rectangular convex part of the first region RB1 is set as the first divided region RB11, and the remaining region (rectangular region) of the first region RB1 is set as the second divided region RB12. Then, the center of gravity GB11 of the first divided region RB11 and the center of gravity GB12 of the second divided region RB12 are obtained. The center of gravity GB11 of the first divided region RB11 is the intersection of the diagonal lines of the first divided region RB11. The center of gravity position GB12 of the second divided region RB12 is the intersection of the diagonal lines of the second divided region RB12. Next, the area SB1 of the first divided region RB11 and the area SB2 of the second divided region RB12 are obtained. Next, in the line segment LB connecting the center of gravity positions GB11 and GB12, the center of gravity position GB1 of the first region RB1 is obtained based on the relationship between the distance DB1 between the center of gravity positions GB11 and GB1, the distance DB2 between the center of gravity positions GB12 and GB1, and the area SB1 of the first divided region RB11 and the area SB2 of the second divided region RB12. In more detail, the ratio (DB2 / DB1) of the distance DB2 to the distance DB1 is equal to the inverse ratio (SB1 / SB2) of the ratio of the area SB2 of the second divided region RB12 to the area SB1 of the first divided region RB11 (DB2 / DB1=SB1 / SB2). In this way, by determining at least one of the distances DB1 and DB2, the center of gravity GB1 of the first region RB1 is determined. Also, as shown in Fig. 20, the source pad 21 is provided so as to cover the center of gravity GB1 and GB2 of the divided active region 29 (the center of gravity GB1 of the first region RB1 and the center of gravity GB2 of the second region RB2).

[0156] The two dashed-dotted line regions RY shown in FIG. 20 indicate a tool head (hereinafter, referred to as a wedge RY) for ultrasonically bonding the first wire 41 to the source pad 21 in a wedge bonding device (not shown). The wedge bonding device moves the wedge RY so that the wedge RY is positioned on the center of gravity GB1 of the first region RB1 of the active region 29, and connects the end of the first wire 41 to the source pad 21. As a result, the end of the first wire 41 passed through the wedge RY is connected so as to overlap the center of gravity GB1 of the first region RB1, as shown in FIG. 21. That is, the first connection portion 41b (connection region) of the first wire 41 to the source pad 21 includes the center of gravity GB1 of the first region RB1. In this embodiment, the center position of the first connection portion 41b and the center of gravity GB1 of the first region RB1 coincide with each other. Next, the wedge bonding device moves the wedge RY away from the source pad 21, so that the first wire 41 moves away from the source pad 21 (see FIG. 22). Then, the wedge bonding device moves the wedge RY so that the wedge RY is located on the center of gravity GB2 of the second region RB2 of the active region 29, and connects the first wire 41 to the source pad 21 (see FIG. 22). As a result, the first wire 41 passed through the wedge RY is connected so as to overlap the center of gravity GB2 of the second region RB2, as shown in FIG. 21. That is, the second connection portion 41c (connection region) of the first wire 41 to the source pad 21 includes the center of gravity GB2 of the second region RB2. In this embodiment, the center position of the second connection portion 41c and the center of gravity GB2 of the second region RB2 coincide with each other. Also, as shown in FIG. 22, the portion of the first wire 41 between the first connection portion 41b and the second connection portion 41c is separated upward from the source pad 21.

[0157] 21, the first connection portion 41b and the second connection portion 41c connected to the source pad 21 in the first wire 41 extend in directions different from the horizontal direction X and the vertical direction Y in a plan view of the semiconductor device 1. More specifically, the first connection portion 41b and the second connection portion 41c extend from the semiconductor element 20 toward the second island portion 12a (see FIG. 2). The extending direction of the first connection portion 41b and the extending direction of the second connection portion 41c can be changed arbitrarily. In one example, the extending direction of the first connection portion 41b and the extending direction of the second connection portion 41c may be different from each other.

[0158] 21, a region RS surrounded by a two-dot chain line and including the first connection portion 41b and the second connection portion 41c of the first wire 41 is a margin that takes into consideration variations in the wire diameter of the first wire 41 and variations in the connection position of the first wire 41 to the source pad 21 by a wedge bonding device. That is, the first connection portion 41b and the second connection portion 41c of the first wire 41 are always located within the region RS. In this embodiment, the region RS includes the vicinity of the intersection of the fifth side 29e and the sixth side 29f of the active region 29. In this embodiment, the temperature sensor 27 is provided adjacent to the region RS in a plan view of the semiconductor device 1.

[0159] According to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained. (2-1) The first wire 41 is connected to the center of gravity GB1, GB2 of the first region RB1 and the second region RB2, which are two divided regions having equal areas of the active region 29. This reduces the concentration of heat in the active region 29 when the semiconductor device 1 is driven, thereby improving the active clamp withstand voltage Eac.

[0160] Third embodiment A semiconductor device 1 of the third embodiment will be described with reference to FIG. 23. The semiconductor device 1 of the present embodiment is different from the semiconductor device 1 of the first embodiment in that the structure of the MISFET 23a is partially different. In the following description, the same components as those of the semiconductor device 1 of the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. Also, the following description will be given in detail of the points that are different from the MISFET 23a of the first embodiment.

[0161] 23, one or more first slits 220 are provided in at least a portion of the first source electrode 80 serving as the first metal layer that faces the source pad 21. The first slits 220 penetrate the first source electrode 80 and extend in the direction in which the trench gate structure 65 extends (the depth direction of the paper). The first slits 220 in this embodiment face the trench gate structure 65.

[0162] In the second source electrode 82 as the second metal layer, at least a portion facing the source pad 21 is provided with one or more second slits 221. The second slits 221 penetrate the second source electrode 82 and extend in the direction in which the trench gate structure 65 extends.

[0163] The second slit 221 is provided such that at least a portion of it faces the first slit 220. The width dimension DS2 of the second slit 221 and the width dimension DS1 of the first slit 220 can each be changed arbitrarily. In this embodiment, the width dimension DS2 of the second slit 221 and the width dimension DS1 of the first slit 220 are equal to each other. Furthermore, in this embodiment, the entire second slit 221 faces the first slit 220.

[0164] The first slit 220 is filled with the second interlayer insulating film 76. The second slit 221 is filled with the fourth interlayer insulating film 78. The fourth interlayer insulating film 78 extends over the second slit 221 to cover the periphery of the second slit 221 of the second source electrode 82. In this manner, in the portion of the semiconductor element 20 where the first slit 220 and the second slit 221 are provided, a support pillar 222 made of the first interlayer insulating film 75 to the fourth interlayer insulating film 78 is provided. The support pillar 222 is configured by laminating the first interlayer insulating film 75, the second interlayer insulating film 76, the third interlayer insulating film 77, and the fourth interlayer insulating film 78 in this order. The upper end of the support pillar 222 is covered by the source pad 21. As a result, the support pillar 222 supports the source pad 21.

[0165] Such a configuration including the first slit 220 and the second slit 221 is preferably provided at least on the periphery of the source pad 21. In this embodiment, the configuration including the first slit 220 and the second slit 221 is provided over the entire source pad 21. In more detail, the MISFET 23a is formed by combining a number of configurations including the first slit 220 and the second slit 221. An example of a configuration including the first slit 220 and the second slit 221 is a configuration in which the first slit 220 and the second slit 221 are provided at a position corresponding to one of three trench gate structures 65 and one of the three trench gate structures 65. The MISFET 23a is formed by combining a number of configurations including the first slit 220 and the second slit 221.

[0166] The source pad 21 of this embodiment is made of copper (Cu). The thickness of the source pad 21 is preferably about 4 μm or more. The thickness of the source pad 21 is preferably about 20 μm or less. The thickness of the source pad 21 of this embodiment is about 8 μm. The source pad 21 can be formed by copper plating growth. A connection layer 21a including nickel (Ni) plating is formed on the surface of the copper constituting the source pad 21. The connection layer 21a of this embodiment is formed by nickel palladium (NiPd) plating. The source pad 21 may be made of an aluminum alloy (for example, AlCu).

[0167] (action) The operation of this embodiment will be described. For example, when a semiconductor device is connected to an inductive load and is required to absorb the energy released from the inductive load when the semiconductor device's switching element (MISFET) is turned off, the active clamp withstand capability Eac is known as an index of how much energy stored in the inductive load can be absorbed.

[0168] However, if the energy applied to the semiconductor device exceeds a certain value, the semiconductor device may fail due to a rise in temperature. Thus, the active clamp withstand capability Eac is determined mainly by the failure of the semiconductor device due to heat. For this reason, for example, when energy is applied to the semiconductor device, there may be a portion of the substrate that becomes transiently and locally hot, which may cause failure in that portion and may cause the semiconductor device to be unable to absorb the energy. This makes it difficult to improve the active clamp withstand capability Eac.

[0169] To address this issue, it is possible to change the power electrode pad (source pad) of the semiconductor device to copper, which has excellent heat dissipation properties, and to increase the thickness of the source pad in order to absorb the transient energy of the semiconductor device, thereby improving the active clamp withstand voltage Eac.

[0170] However, when heat is applied to the source pad during the manufacturing process of the semiconductor device, the copper source pad is more likely to stretch than the aluminum source pad. This causes the outer periphery of the source pad to press the interlayer insulating film formed in the source pad against the epitaxial layer. As a result, passivation cracks may occur in the outer region of the source pad, for example, the first metal may pop out of the passivation film.

[0171] In view of this situation, in this embodiment, a first slit 220 is formed in the first source electrode 80, and a second slit 221 is formed in the second source electrode 82. As a result, even if the first source electrode 80 is deformed, the deformation is interrupted at the first slit 220, and even if the second source electrode 82 is deformed, the deformation is interrupted at the second slit 221, so that the amount of deformation of each of the first source electrode 80 and the second source electrode 82 can be reduced.

[0172] In addition, since the support pillars 222 that support the source pad 21 are formed so as to connect the first slits 220 and the second slits 221, the support pillars 222 support the source pad 21 against deformation due to heat, and therefore deformation of the first source electrode 80 and the second source electrode 82 can be suppressed. Therefore, the occurrence of passivation cracks can be suppressed.

[0173] According to this embodiment, in addition to the above-mentioned actions and effects, the following effects can be obtained. (3-1) For example, when the source pad 21 is made of aluminum, it is difficult to make the source pad 21 sufficiently thick because the source pad 21 is formed by sputtering. This makes it difficult to increase the thermal capacity of the source pad 21, and there is a risk that the heat cannot be sufficiently dissipated when heat is instantaneously applied to the semiconductor device. For this reason, there is room for improvement in sufficiently increasing the active clamp withstand voltage Eac.

[0174] In this embodiment, the source pad 21 is made of copper grown by plating. This allows the thickness of the source pad 21 to be made thicker than that of a source pad 21 made of aluminum. This allows the heat capacity of the source pad 21 to be increased, thereby improving the active clamp withstand voltage Eac. In addition, by making the source pad 21 thicker, when the first wire 41 is connected to the source pad 21, the impact can be prevented from being transmitted to the interlayer insulating film 74.

[0175] (3-2) Nickel plating is formed on the copper surface of the source pad 21. The first wire 41 is made of aluminum. This makes it possible to prevent the connection portion between the source pad 21 and the first wire 41 from corroding.

[0176] (Fourth embodiment) The semiconductor device 1 of the fourth embodiment will be described with reference to FIGS. 24 to 27K. The semiconductor device 1 of the present embodiment is different from the semiconductor device 1 of the first embodiment in the structure of the MISFET 23a. In the following description, the same components as those of the semiconductor device 1 of the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. In the MISFET 23a of the present embodiment, the channel formation region 72 is different, so that for convenience of description, the interlayer insulating film 74, the first source electrode 80, the second source electrode 82, and the source pad 21 are shown in a simplified manner in FIGS. 27J and 27K. In the present embodiment, the configuration including the first source electrode 80, the second source electrode 82, and the source pad 21 is defined as the source metal 230.

[0177] The MISFET 23a of this embodiment has a plurality of functional element formation regions 231 in which the ratio of the area of ​​the channel formation region 72 to the unit area is different. In this embodiment, the active region 29 of the MISFET 23a is composed of a plurality of functional element formation regions 231. The plurality of functional element formation regions 231 include a first functional element formation region 232 in which the ratio of the area of ​​the channel formation region 72 to the unit area is relatively small, and a second functional element formation region 233 in which the ratio of the area of ​​the channel formation region 72 to the unit area is relatively high. The plurality of functional element formation regions 231 of this embodiment also includes a third functional element formation region 234 in which the ratio of the area of ​​the channel formation region 72 to the unit area is larger than that of the first functional element formation region 232 and smaller than that of the second functional element formation region 233.

[0178] The first functional element forming region 232 generates a relatively small amount of heat because the ratio of the area of ​​the channel formation region 72 per unit area is smaller than those of the second functional element forming region 233 and the third functional element forming region 234. On the other hand, the first functional element forming region 232 has a larger on-resistance than the second functional element forming region 233 and the third functional element forming region 234 due to the relatively small channel formation region 72.

[0179] In contrast, the second functional element formation region 233 and the third functional element formation region 234 generate a relatively large amount of heat because the ratio of the area of ​​the channel formation region 72 per unit area is larger than that of the first functional element formation region 232. On the other hand, the second functional element formation region 233 and the third functional element formation region 234 have a smaller on-resistance than the first functional element formation region 232 due to the relatively large area of ​​the channel formation region 72.

[0180] The magnitude relationship of the heat amounts of the first to third functional element forming regions 232 to 234 is: heat amount of the first functional element forming region 232<heat amount of the third functional element forming region 234<heat amount of the second functional element forming region 233. The magnitude relationship of the on-resistances of the first to third functional element forming regions 232 to 234 is: on-resistance of the second functional element forming region 233<on-resistance of the third functional element forming region 234<on-resistance of the first functional element forming region 232. In addition, the magnitude relationship of the active clamp withstand currents Eac of the first to third functional element forming regions 232 to 234 is: active clamp withstand currents Eac of the second functional element forming region 233<active clamp withstand currents Eac of the third functional element forming region 234<active clamp withstand currents Eac of the first functional element forming region 232.

[0181] In the semiconductor device 1 (MISFET 23a) of this embodiment, an arrangement pattern of the first functional element forming region 232, the second functional element forming region 233, and the third functional element forming region 234 is devised to provide a semiconductor device 1 that can achieve both excellent active clamp withstand capability Eac and on-resistance while suppressing a temperature rise in the entire semiconductor device 1 (semiconductor element 20). The semiconductor device 1 particularly achieves the above object by arranging the first functional element forming region 232 in a portion of the source pad 21 that is prone to temperature rise, and arranging the second functional element forming region 233 and the third functional element forming region 234 in other portions.

[0182] For example, examples of regions in the source pad 21 that are prone to temperature rise and that should be suppressed include an inner region spaced a predetermined distance inward from the periphery of the source pad 21, a region surrounded by a plurality of channel formation regions 72 (a plurality of functional element formation regions 231), a region to which the first wire 41 is not connected in a plan view, and a region that is a selective combination of these regions. In these regions, heat is difficult to dissipate and tends to be easily trapped. In particular, the inner region of the source pad 21 is prone to temperature rise and tends to be relatively hotter than other parts.

[0183] Therefore, in this embodiment, the first functional element forming region 232 is disposed in the inner region of the active region 29, and the second functional element forming region 233 and the third functional element forming region 234 are disposed in the outer region of the active region 29. This results in a configuration in which the proportion of the area of ​​the channel formation region 72 per unit area gradually increases from the inside to the outside of the active region 29.

[0184] Furthermore, in the active region 29, the temperature of the active region 29 is likely to drop at a location where the first wire 41 is connected to the source pad 21 because heat is dissipated to the first wire 41 through the source pad 21. In consideration of this, the location where the first wire 41 is connected to the source pad 21 is disposed in the second functional element formation region 233, which generates the largest amount of heat.

[0185] The following provides a detailed description of the arrangement of the multiple functional element forming regions 231. Figures 24 and 25 show one example of the arrangement of the multiple functional element forming regions 231, and the size and number of regions dividing the active region 29 can be changed as desired.

[0186] As shown in Figures 24 and 25, the multiple functional element formation regions 231 include a first functional element formation region unit U1 including a multiple (four in this embodiment) first functional element formation regions 232, a second functional element formation region unit U2 including a multiple (four in this embodiment) second functional element formation regions 233, and a third functional element formation region unit U3 including a multiple (four in this embodiment) third functional element formation regions 234.

[0187] In this embodiment, the first to third function element forming region units U1 to U3 are rectangular in plan view and have approximately the same area, and are arranged in a predetermined layout so as to spread out the active region 29 in a matrix (a regular lattice in the vertical and horizontal directions). In other words, the first to third function element forming region units U1 to U3 are arranged in a predetermined layout within a plurality of rectangular regions that partition the active region 29 in a matrix.

[0188] More specifically, the first to third functional element formation region units U1 to U3 are arranged according to the amount of heat generated in each region of the active region 29 when the semiconductor device 1 is driven, which is calculated, for example, by simulation. For example, the second functional element formation region unit U2 is arranged in the region where the amount of heat generated is a first threshold or less, the first functional element formation region unit U1 is arranged in the region where the amount of heat generated is a second threshold or more that is greater than the first threshold, and the third functional element formation region unit U3 is arranged in the region where the amount of heat generated is greater than the first threshold and less than the second threshold.

[0189] FIG. 24 shows an arrangement of the first to third function element forming region units U1 to U3 in the active region 29 when the first wire 41 is connected to the source pad 21 at one point.

[0190] 24, the first functional element forming region unit U1 is provided in a region where heat generation should be suppressed. The first functional element forming region unit U1 is disposed in an inner region of the active region 29. The third functional element forming region unit U3 is provided in a region adjacent to the first functional element forming region unit U1. The second functional element forming region unit U2 is provided in a region adjacent to the third functional element forming region unit U3 on the opposite side to the first functional element forming region unit U1.

[0191] In addition, in the active region 29, a second functional element forming region unit U2 is provided in a region including a region (a region indicated by a dashed line) where the first wire 41 is connected to the source pad 21. A first functional element forming region unit U1 is provided in a region surrounding the second functional element forming region unit U2. A third functional element forming region unit U3 is provided in a region surrounding the first functional element forming region unit U1.

[0192] FIG. 25 shows an arrangement of the first to third function element forming region units U1 to U3 in the active region 29 when the first wire 41 is connected to the source pad 21 at two points.

[0193] 25, the first functional element forming region unit U1 is provided in a region where heat generation should be suppressed. The first functional element forming region unit U1 is disposed in an inner region of the active region 29. In one example, the first functional element forming region unit U1 is provided in an inner region between two regions (regions indicated by dashed lines) in the active region 29 where the first wire 41 is connected to the source pad 21. The third functional element forming region unit U3 is provided in a region adjacent to the first functional element forming region unit U1.

[0194] In the active region 29, a region including two regions where the first wire 41 is connected to the source pad 21 (region where the wedge RY is arranged) is provided with a second functional element forming region unit U2. A first functional element forming region unit U1 is provided in the region surrounding the second functional element forming region unit U2. A first functional element forming region unit U1 is provided in the region surrounding the second functional element forming region unit U2. A third functional element forming region unit U3 is provided in the region surrounding the first functional element forming region unit U1.

[0195] In addition, the outer region in the active region 29 is not limited to the arrangement of the second functional element formation region unit U2 and the third functional element formation region unit U3 shown in Figures 24 and 25, and it is sufficient that either the second functional element formation region unit U2 or the third functional element formation region unit U3 is arranged.

[0196] Next, the planar structures of the first to third function element forming region units U1 to U3 will be described with reference to FIGS. 26A to 26C. As shown in Figures 26A to 26C, in the first to third functional element formation region units U1 to U3, the proportion of the area of ​​the channel formation region 72 per unit area is adjusted, and the layout of the first to third functional element formation regions 232 to 234 is changed.

[0197] The first functional element formation region unit U1 shown in Fig. 26A includes a plurality of functional element formation regions 231 in which the area ratio of the channel formation region 72 per unit area is about 25%. The second functional element formation region unit U2 shown in Fig. 26B includes a plurality of functional element formation regions 231 in which the area ratio of the channel formation region 72 per unit area is about 75%. The third functional element formation region unit U3 shown in Fig. 26C includes a plurality of functional element formation regions 231 in which the area ratio of the channel formation region 72 per unit area is about 50%.

[0198] As shown in FIGS. 26A to 26C, in this embodiment, a plurality of channel formation regions 72 are formed in first to third function element formation regions 232 to 234 in a layout based on a staggered or meandering pattern.

[0199] As shown in FIG. 26A, in each first functional element forming region 232 of the first functional element forming region unit U1, the multiple channel forming regions 72 are arranged in a staggered pattern along the length direction of the trench gate structure 65. In each trench gate structure 65, the multiple channel forming regions 72 are arranged alternately at intervals on one side and the other side of each trench gate structure 65 along the length direction of the trench gate structure 65. The multiple channel forming regions 72 are arranged only on one side or the other side in the lateral direction intersecting with the trench gate structure 65. With this configuration, in the first functional element forming region unit U1, the ratio of the area of ​​the channel forming regions 72 per unit area is about 25%. In the first functional element forming region unit U1, the channel forming regions 72 are arranged at intervals from the other channel forming regions 72 on one side or the other side of the trench gate structure 65, so that the heat source can be effectively dispersed.

[0200] In addition, the channel formation region 72 arranged on one side does not face the channel formation region 72 arranged on the other side across the trench gate structure 65. Therefore, in the lateral direction intersecting with the trench gate structure 65, multiple heat generation sources do not face each other across the trench gate structure 65. This makes it possible to prevent heat generated in one channel formation region 72 from being transferred to another channel formation region 72, thereby effectively suppressing the occurrence of thermal interference. In this way, the first functional element formation region unit U1 is configured to effectively suppress temperature rise.

[0201] As shown in FIG. 26B, each second functional element formation region 233 of the second functional element formation region unit U2 has a configuration in which the source region 70 and the body contact region 73 are interchanged in the configuration shown in FIG. 26A. In detail, the channel formation region 72 extends along the length direction of the trench gate structure 65. In the lateral direction intersecting with the trench gate structure 65, the channel formation region 72 formed on one trench gate structure 65 side and the channel formation region 72 formed on the other trench gate structure 65 side are integrally formed. As a result, a meandering channel formation region 72 is formed in each second functional element formation region 233. With this configuration, in the second functional element formation region unit U2, the ratio of the area of ​​the channel formation region 72 per unit area is about 75%.

[0202] 26C, each of the third functional element formation regions 234 of the third functional element formation region unit U3 is obtained by extending the length of the channel formation region 72 by about twice the length in the length direction of the trench gate structure 65 in the configuration shown in FIG. 26A. With this configuration, the ratio of the area of ​​the channel formation region 72 to the unit area in the third functional element formation region unit U3 is about 50%. The cross-sectional structures of the first to third functional element formation region units U3 in this embodiment are substantially the same as the cross-sectional structure of the MISFET 23a shown in FIG.

[0203] (MISFET manufacturing method) An example of a method for manufacturing the MISFET 23a will be described with reference to Figures 27A to 27K, which are vertical cross-sectional views of a portion corresponding to line 27-27 in Figure 26A.

[0204] First, as shown in FIG. 27A, a wafer-like substrate 50 including a semiconductor substrate 61 and an epitaxial layer 62 formed on the semiconductor substrate 61 is prepared. 27B, a hard mask 240 having openings 241 selectively in regions where trenches 66 are to be formed is formed on the epitaxial layer 62. Then, a surface portion of the epitaxial layer 62 is selectively removed by etching through the hard mask 240. As a result, a plurality of trenches 66 are formed. After the trenches 66 are formed, the hard mask 240 is removed.

[0205] Next, as shown in FIG. 27C, a thermal oxide film 242 made of silicon oxide is formed on the inner wall surface of the trench 66 by, for example, thermal oxidation. 27D, a polysilicon film 244 is deposited as a conductor on the epitaxial layer 62. The polysilicon film 244 fills the trenches 66 and covers the surface of the epitaxial layer 62. Thereafter, n-type impurities are implanted into the polysilicon film 244 and diffused by heat treatment (drive-in). Examples of n-type impurities include phosphorus (P) and arsenic (As).

[0206] 27E, the polysilicon film 244 is etched. Etching of the polysilicon film 244 is continued until the etching surface reaches the middle of each depth direction of the trench 66. As a result, a buried electrode 69 made of the remaining polysilicon film 244 is formed in the trench 66.

[0207] Next, as shown in FIG. 27F, the thick gate insulating film 67 located between the opening of the trench 66 and the upper end 69a of the embedded electrode 69 is etched. The thick gate insulating film 67 is removed so that a portion of the thick gate insulating film 67 remains on each inner wall surface of the trench 66. At this time, a portion of the upper end 69a of the embedded electrode 69 is exposed from the thick gate insulating film 67. In this case, the etching performed may be wet etching.

[0208] 27G, the substrate 50 is thermally oxidized to form a thermal oxide film 242 on the exposed side surface of the trench 66 and on the surface of the substrate 50. At this time, a part of the exposed upper end 69a of the embedded electrode 69 is also oxidized to form the thermal oxide film 242. At the upper end 69a of the embedded electrode 69, oxidation proceeds more rapidly than on the exposed surface side of the trench 66 due to the polysilicon doped with impurities, so that a relatively thick thermal oxide film 242 is formed. In this process, a recess 245 is formed between the upper end 69a of the embedded electrode 69 and the side surface of the trench 66 by the thick film portion 67a and the thin film portion 67b of the gate insulating film 67.

[0209] Next, as shown in FIG. 27H, a polysilicon film 246 is deposited on the substrate 50 as a conductor. The polysilicon film 246 fills the trench 66 and covers the surface of the substrate 50. The polysilicon film 246 enters the recess 245 in the trench 66 and forms a protrusion extending downward between the upper end 69a of the buried electrode 69 of the trench 66 and the upper end 69a, thereby forming a recess 68a that opens toward the buried electrode 69. Thereafter, impurities are implanted into the polysilicon film 246 and diffused by heat treatment (drive-in). Next, the polysilicon film 246 is etched.

[0210] Etching of the polysilicon film 246 continues until the etching surface reaches a position slightly inside the trench 66 relative to the surface of the substrate 50. As a result, a gate electrode 68 made of the remaining polysilicon film 246 is formed in each of the trenches 66. In addition, a recess 247 is formed on the gate electrode 68.

[0211] Next, as shown in FIG. 27I, an ion implantation mask (not shown) that selectively opens in a region where the body region 71 is to be formed is formed on the substrate 50. Then, p-type impurities are implanted into the surface portion of the epitaxial layer 62 through the ion implantation mask. As a result, the body region 71 is formed in the surface portion of the epitaxial layer 62. After the body region 71 is formed, the ion implantation mask is removed. Next, n-type impurities and p-type impurities are implanted in this order into the substrate 50. Thereafter, the implanted impurity ions are diffused by heat treatment (drive-in). As a result, the n + The source region 70 and p + 27J, a silicon nitride film and a silicon oxide film are deposited in this order by, for example, a CVD method, thereby forming an interlayer insulating film 74.

[0212] Here, the source region 70 is formed by implanting n-type impurities through an ion implantation mask having selective openings in the region where the source region 70 is to be formed. As a result, the source region 70 having a relatively small area ratio per unit area in a plan view and the source region 70 having a relatively large area ratio per unit area in a plan view are selectively formed. That is, a first functional element formation region 232 (first functional element formation region unit U1), a second functional element formation region 233 (second functional element formation region unit U2), and a third functional element formation region 234 (third functional element formation region unit U3) are formed.

[0213] Moreover, the body contact region 73 is formed by implanting p-type impurities through an ion implantation mask having openings selectively in the regions where the body contact region 73 is to be formed. Next, the interlayer insulating film 74 is selectively etched by reactive ion etching (RIE) to form a contact hole 248. Then, as shown in FIG. 27K, contacts 81, 83 (not shown in FIG. 27K) are embedded in the contact hole 248, and then an electrode film (not shown) is formed so as to cover an area on the substrate 50. The electrode film is patterned to form the source pad 21 (source metal 230) and the gate pad 22 (see FIG. 5). In addition, an electrode film (not shown) is formed so as to cover the semiconductor substrate 61 of the substrate 50. The electrode film is patterned to form the drain electrode 64. Through the above steps, the semiconductor device 1 (MISFET 23a) is obtained.

[0214] According to this embodiment, the following effects can be obtained. (4-1) A first functional element formation region unit U1 having a configuration in which the amount of heat generated is small and the active clamp withstand current Eac is arranged in a region in the active region 29 in which heat generation should be suppressed. This makes it possible to suppress a rise in temperature in the active region 29, and to prevent the region in the active region 29 in which heat generation should be suppressed from becoming transiently and locally hot. In addition, since the first functional element formation region unit U1 is arranged in the active region 29, it is easier to improve the active clamp withstand current Eac compared to, for example, a configuration in which the active region 29 is composed of the second functional element formation region unit U2 and the third functional element formation region unit U3.

[0215] (4-2) In the active region 29, in a region other than the region where heat generation should be suppressed, for example, in the outer region of the active region 29, the second function element formation region unit U2 or the third function element formation region unit U3, in which the ratio of the area of ​​the channel formation region 72 per unit area is larger than that of the first function element formation region unit U1, is arranged. As a result, the area of ​​the channel formation region 72 is larger than that of the first function element formation region unit U1, and a large current path can be secured, so that even when the first function element formation region unit U1 is used together, it is possible to suppress a reduction in the current path as viewed from the entire active region 29. As a result, it is possible to suppress an increase in the on-resistance of the semiconductor element 20 by utilizing the region in the active region 29 other than the region where heat generation should be suppressed.

[0216] (4-3) In the active region 29, a second functional element formation region unit U2 having a configuration in which a large amount of heat is generated and a small active clamp withstand current Eac is disposed in a region corresponding to the portion where the first wire 41 is connected to the source pad 21. With this configuration, heat in the active region 29 is transferred to the first wire 41 through the source pad 21, so that the temperature is unlikely to rise in the region in the active region 29 corresponding to the portion where the first wire 41 is connected to the source pad 21. For this reason, using the second functional element formation region unit U2 having a large amount of heat can contribute to suppressing an increase in the on-resistance of the semiconductor element 20.

[0217] (4-4) The active region 29 is composed of a first functional element formation region unit U1, a second functional element formation region unit U2, and a third functional element formation region unit U3. This makes it easier to adjust the on-resistance and active clamp withstand voltage Eac of the semiconductor element 20 compared to a case where the active region 29 is composed of, for example, two types of functional element formation region units.

[0218] Moreover, in a part of the active region 29, a third functional element forming region unit U3 is disposed between the first functional element forming region unit U1 and the second functional element forming region unit U2. This makes it possible to suppress abrupt changes in the on-resistance and the active clamp withstand voltage Eac.

[0219] (Modification) The above-described embodiments are merely examples of possible forms of the semiconductor device of the present disclosure, and are not intended to limit the forms. The semiconductor device of the present disclosure may take the following modified forms of the above-described embodiments, or a combination of at least two mutually compatible modified forms.

[0220] Combination of embodiments The second embodiment and the third embodiment may be combined. That is, the structure of the interlayer insulating film 74, the first source electrode 80, and the second source electrode 82 immediately below the source pad 21 of the semiconductor device 1 of the second embodiment may be replaced with the structure of the interlayer insulating film 74, the first source electrode 80, and the second source electrode 82 of the third embodiment.

[0221] The third embodiment and the fourth embodiment may be combined. That is, the active region 29 of the semiconductor device 1 of the third embodiment may be replaced with a structure having a plurality of functional element formation regions 231 in which the ratio of the area of ​​the channel formation region 72 per unit area is different, as in the fourth embodiment.

[0222] [Addition of heat dissipation components] In order to improve the active clamp resistance Eac, it is necessary to improve the heat dissipation of the semiconductor device 1. Therefore, in each of the above-described embodiments, the heat dissipation of the semiconductor device 1 can be improved by connecting a heat dissipation member 250 to the source pad 21. As an example, as shown in FIG. 28A and FIG. 28B, a plurality of heat dissipation members 250 are connected to the source pad 21. FIG. 28A shows an arrangement of the heat dissipation member 250 when the first wire 41 is connected to the source pad 21 at one connection point, and FIG. 28B shows an arrangement of the heat dissipation member 250 when the first wire 41 is connected to the source pad 21 at two connection points.

[0223] 28A and 28B, the heat dissipation members 250 are connected to regions of the source pad 21 corresponding to regions in the active region 29 where heat generation should be suppressed. In detail, in FIG. 28A, the heat dissipation members 250 are connected to regions of the source pad 21 corresponding to inner regions of the active region 29. Specifically, the heat dissipation members 250 are arranged so as to surround a part of the connection portion 41a (dotted line) of the first wire 41. Note that, in order to avoid interference with the first wire 41, the heat dissipation members 250 are not arranged in the direction in which the first wire 41 extends.

[0224] 28B, the heat dissipation members 250 are arranged to surround a part of the first connection portion 41b and the second connection portion 41c (both indicated by dashed lines) which are ends of the first wire 41. In order to avoid interference with the first wire 41, the heat dissipation members 250 are not arranged in the direction in which the first wire 41 extends. The heat dissipation members 250 are connected to a region of the source pad 21 corresponding to an inner region of the active region 29, that is, a region between the first connection portion 41b and the second connection portion 41c of the first wire 41 in the active region 29, and adjacent to the first wire 41 in the vertical direction Y.

[0225] Such a heat dissipation member 250 is formed by connecting a wire to the source pad 21 by wedge bonding or ball bonding. That is, the shape of the heat dissipation member 250 is the same as the shape of the connection portion when the wire is connected. The heat dissipation member 250 is made of, for example, copper or aluminum. Also, for example, the heat dissipation member 250 may be formed by connecting a first wire 41 to the source pad 21.

[0226] Fig. 29 shows an example of a heat dissipation member 250. In the heat dissipation member 250 shown in Fig. 29, a wire is connected to the source pad 21 by ball bonding. 28A and 28B is merely an example, and the arrangement can be changed as desired. For example, the heat dissipation members 250 may be connected to at least one of the regions of the source pad 21 corresponding to the region in which the third functional element forming region units U3 are arranged in the active region 29 shown in FIG. 28A and 28B.

[0227] In the first to third embodiments, one or more heat dissipation members 250 may be connected onto the source pad 21. According to this configuration, the heat dissipation performance of the semiconductor device 1 is improved via the source pad 21, and therefore the active clamp withstand voltage Eac can be improved.

[0228] [Connection position of connection member] 7, the first wire 41 and the source pad 21 as a connecting member are connected to each other at a position on a line segment LA connecting the center of gravity GA1 of the first region RA1 and the center of gravity GA2 of the second region RA2. The first wire 41 and the source pad 21 may be connected to each other at two positions, the center of gravity GA1 of the first region RA1 and the center of gravity GA2 of the second region RA2.

[0229] [Active area shape and center of gravity] In each of the above embodiments, the shape of the active area 29 can be changed as desired. The active area 29 can be changed as follows (A) to (C). The positions of the centers of gravity of the active areas 29 of (A) to (C) will also be described.

[0230] (A) As shown in FIG. 30A and FIG. 30B, the active area 29 has a concave shape. FIG. 30A shows a case where the first wire 41 is connected to the source pad 21 at one point. As shown in FIG. 30A, the active area 29 is divided into a rectangular first area RD1 in which the concave portion 29x is filled, and a second area RD2 corresponding to the rectangular concave portion 29x. Next, the center of gravity GD1 of the first area RD1 and the center of gravity GD2 of the second area RD2 are obtained. As shown in FIG. 30A, since the first area RD1 and the second area RD2 are each rectangular, the center of gravity GD1 of the first area RD1 is the intersection of the diagonals of the first area RD1, and the center of gravity GD2 of the second area RD2 is the intersection of the diagonals of the second area RD2. Next, the area SD1 of the first area RD1 and the area SD2 of the second area RD2 are obtained. Next, in the line segment LD connecting the center of gravity GD1 and the center of gravity GD2, the center of gravity GD of the active region 29 is obtained based on the distance DD1 between the center of gravity GD1 and the center of gravity GD of the active region 29, the distance DD2 between the center of gravity GD2 and the center of gravity GD of the active region 29, and the relationship between the area SD1 of the first region RD1 and the area SD2 of the second region RD2. In detail, the ratio (DD2 / DD1) of the distance DD2 to the distance DD1 is equal to the inverse ratio (SD1 / SD2) of the ratio of the area SD2 of the second region RD2 to the area SD1 of the first region RD1 (DD2 / DD1=SD1 / SD2). Thus, the center of gravity GD of the active region 29 is obtained by obtaining at least one of the distances DD1 and DD2. Also, as shown in FIG. 30A, the source pad 21 is provided so as to cover the center of gravity GD of the active region 29.

[0231] The dashed-dotted line region RX shown in FIG. 30A indicates a tool head (hereinafter referred to as wedge RX) for ultrasonically bonding the first wire 41 to the source pad 21 in a wedge bonding device (not shown). The wedge bonding device moves the wedge RX so that the wedge RX is positioned on the center of gravity GD of the active area 29. The end of the first wire 41 threaded through the wedge RX is connected so as to overlap the center of gravity GD of the active area 29. That is, the contact region of the first wire 41 with the source pad 21 includes the center of gravity GD of the active area 29. In FIG. 30A, the center position of the contact region (wedge RX) of the first wire 41 with the source pad 21 coincides with the center of gravity GD of the active area 29. In this modified example, the contact area (wedge RX) of the first wire 41 to the source pad 21 only needs to include the center of gravity GD of the active area 29, and the center position of the contact area (wedge RX) of the first wire 41 to the source pad 21 may be a position different from the center of gravity GD of the active area 29.

[0232] FIG. 31A shows an example of a semiconductor device 1 using the active region 29 and the contact region (wedge RX) of the first wire 41 to the source pad 21 of FIG. 30A. As shown in FIG. 31A, a part of the active region 29 is cut out to form the gate pad 22, compared with the active region 29 of FIG. 30A. However, the center position of the contact region (wedge RX) of the first wire 41 to the source pad 21 coincides with the center of gravity GD of the active region 29. As shown in FIG. 31A, the recess 29x of the active region 29 is formed to be recessed in the horizontal direction X. The control circuit region 29LG is formed across the recess 29x and the cutout portion 29w where the gate pad 22 is formed in the active region 29. The temperature sensor 27 is provided at the center of the recess 29x in the vertical direction Y and adjacent to the bottom surface 29xa of the recess 29x in the horizontal direction X. As shown in FIG. 31A, the temperature sensor 27 is provided at a position that does not overlap the first wire 41 in a plan view, that is, at a position closer to the gate pad 22 in the horizontal direction X than the first wire 41.

[0233] FIG. 30B shows a case where the first wire 41 is connected to the source pad 21 at two points. As shown in FIG. 30B, the active region 29 is divided into two regions (a first region RE1 and a second region RE2) having equal areas. As shown in FIG. 30B, the first region RE1 and the second region RE2 are formed in a substantially L-shape. Next, the center of gravity GE1 of the first region RE1 and the center of gravity GE2 of the second region RE2 are obtained. The first region RE1 is divided into two rectangular regions, a first division region RE11 and a second division region RE12. Then, the center of gravity GE11 of the first division region RE11 and the center of gravity GE12 of the second division region RE12 are obtained. Since the first division region RE11 is rectangular, the intersection of the diagonals of the first division region RE11 is the center of gravity GE11 of the first division region RE11. Since the second divided region RE12 is rectangular, the intersection of the diagonals of the second divided region RE12 is the second center of gravity GE12 of the divided region RE12. Next, the area SE1 of the first divided region RE11 and the area SE2 of the second divided region RE12 are obtained. Next, in the line segment LE1 connecting the center of gravity GE11 and the center of gravity GE12, the center of gravity GE1 of the first region RE1 is obtained based on the relationship between the distance DE1 between the center of gravity GE11 and the center of gravity GE1, the distance DE2 between the center of gravity GE12 and the center of gravity GE1, and the area SE1 of the first divided region RE11 and the area SE2 of the second divided region RE12. In detail, the ratio (DE2 / DE1) of the distance DE2 to the distance DE1 is equal to the inverse ratio (SE1 / SE2) of the ratio of the area SE2 of the second divided region RE12 to the area SE1 of the first divided region RE11 (DE2 / DE1=SE1 / SE2). Thus, by determining at least one of the distances DE1 and DE2, the center of gravity position GE1 of the first region RE1 is determined. Similarly to the method for determining the center of gravity position GE1 of the first region RE1, the center of gravity position GE2 of the second region RE2 is determined on the line segment LE2 connecting the center of gravity position GE21 of the first divided region RE21 and the center of gravity position GE22 of the second divided region RE22 based on the area SE21 of the first divided region RE21 and the area SE22 of the second divided region RE22.As shown in FIG. 30B, the source pad 21 is provided so as to cover the respective centers of gravity GE1, GE2 of the divided active regions 29 (the center of gravity GE1 of the first region RE1 and the center of gravity GE2 of the second region RE2).

[0234] The two dashed-dotted areas RY shown in FIG. 30B indicate a tool head (hereinafter, referred to as a wedge RY) for ultrasonically bonding the first wire 41 to the source pad 21 in a wedge bonding device (not shown). The wedge bonding device moves the wedge RY so that the wedge RY is positioned on the center of gravity GE1 of the first region RE1 of the active region 29, and connects the end of the first wire 41 to the source pad 21. As a result, the end of the first wire 41 passed through the wedge RY is connected so as to overlap the center of gravity GB1 of the first region RB1. That is, the first connection portion 41b of the first wire 41 to the source pad 21 includes the center of gravity GE1 of the first region RE1. In FIG. 30B, the center position of the first connection portion 41b coincides with the center of gravity GE1 of the first region RE1. Next, the wedge bonding device moves the wedge RY away from the source pad 21, so that the first wire 41 moves away from the source pad 21. Then, the wedge bonding device moves the wedge RY so that the wedge RY is positioned on the center of gravity GB2 of the second region RB2 of the active region 29, and connects the first wire 41 to the source pad 21. As a result, the first wire 41 passed through the wedge RY is connected so as to overlap the center of gravity GE2 of the second region RE2. That is, the second connection portion 41c of the first wire 41 to the source pad 21 includes the center of gravity GE2 of the second region RE2. In FIG. 30B, the center position of the second connection portion 41c coincides with the center of gravity GE2 of the second region RE2. Note that in this modification, the first connection portion 41b only needs to include the center of gravity GE1 of the first region RE1, and the center position of the first connection portion 41b may be a position different from the center of gravity GE1 of the first region RE1. Furthermore, the second connection portion 41c only needs to include the center of gravity GE2 of the second region RE2, and the center position of the second connection portion 41c may be a position different from the center of gravity GE2 of the second region RE2.

[0235] Fig. 31B shows an example of a semiconductor device 1 using the active region 29 and the contact region (wedge RX) of the first wire 41 with the source pad 21 of Fig. 30B. The shape of the active region 29, the shape of the control circuit region 29LG, and the position of the temperature sensor 27 are similar to those of Fig. 31A. As shown in Fig. 31B, the temperature sensor 27 is provided at a position that does not overlap with the first wire 41 in a plan view, that is, at a position closer to the gate pad 22 in the lateral direction X than the first wire 41.

[0236] The position of the temperature sensor 27 is not limited to the position shown in FIG. 31A and FIG. 31B, and can be changed arbitrarily. In one example, as shown in FIG. 31C, the temperature sensor 27 may be provided so as to be close to a region of the active region 29 where the temperature becomes highest when the semiconductor element 20 is driven. In detail, the active region 29 shown in FIG. 31C has a second recess 29v recessed from the center of the bottom surface 29xa of the recess 29x in the vertical direction Y toward the horizontal direction X. The control circuit region 29LG has a protrusion 29u that enters the second recess 29v. The temperature sensor 27 is provided at the tip of the protrusion 29u. As shown in FIG. 31C, the temperature sensor 27 is provided at a position that does not overlap the first wire 41 in a plan view, that is, at a position closer to the gate pad 22 in the horizontal direction X than the first wire 41.

[0237] (B) As shown in FIG. 32A and FIG. 32B, the active region 29 has a convex shape. FIG. 32A shows a case where the first wire 41 is connected to the source pad 21 at one point. As shown in FIG. 32A, the active region 29 is divided into a rectangular first region RF1 excluding the convex portion 29y, and a second region RF2 corresponding to the rectangular convex portion 29y. Next, the center of gravity GF1 of the first region RF1 and the center of gravity GF2 of the second region RF2 are obtained. As shown in FIG. 32A, since the first region RF1 and the second region RF2 are each rectangular, the center of gravity GF1 of the first region RF1 is the intersection of the diagonals of the first region RF1, and the center of gravity GF2 of the second region RF2 is the intersection of the diagonals of the second region RF2. Next, the area SF1 of the first region RF1 and the area SF2 of the second region RF2 are obtained. Next, in the line segment LF connecting the center of gravity GF1 and the center of gravity GF2, the center of gravity GF of the active region 29 is obtained based on the relationship between the distance DF1 between the center of gravity GF1 and the center of gravity GF of the active region 29, the distance DF2 between the center of gravity GF2 and the center of gravity GF of the active region 29, and the area SF1 of the first region RF1 and the area SF2 of the second region RF2. In detail, the ratio (DF2 / DF1) of the distance DF2 to the distance DF1 is equal to the inverse ratio (SF1 / SF2) of the ratio of the area SF2 of the second region RF2 to the area SF1 of the first region RF1 (DF2 / DF1=SF1 / SF2). Thus, the center of gravity GF of the active region 29 is obtained by obtaining at least one of the distances DF1 and DF2. Also, as shown in FIG. 32A, the source pad 21 is provided so as to cover the center of gravity GF of the active region 29.

[0238] The region RX indicated by the dashed line in FIG. 32A indicates a tool head (hereinafter referred to as wedge RX) for ultrasonically bonding the first wire 41 to the source pad 21 in a wedge bonding device (not shown). The wedge bonding device moves the wedge RX so that the wedge RX is positioned on the center of gravity GF of the active area 29. The end of the first wire 41 threaded through the wedge RX is connected so as to overlap the center of gravity GF of the active area 29. That is, the contact region of the first wire 41 with the source pad 21 includes the center of gravity GF of the active area 29. In FIG. 32A, the center position of the contact region (wedge RX) of the first wire 41 with the source pad 21 coincides with the center of gravity GF of the active area 29. In this modified example, the contact area (wedge RX) of the first wire 41 to the source pad 21 only needs to include the center of gravity GF of the active area 29, and the center position of the contact area (wedge RX) of the first wire 41 to the source pad 21 may be a position different from the center of gravity GF of the active area 29.

[0239] FIG. 33A shows an example of the semiconductor device 1 using the active region 29 and the contact region (wedge RX) of the first wire 41 to the source pad 21 of FIG. 32A. In FIG. 33A, the semiconductor element 20 is provided so that the protruding portion 29y of the active region 29 is on the second lead frame 12 and the third lead frame 13 side in the vertical direction Y. As shown in FIG. 33A, a part of the active region 29 is cut out for the arrangement of the temperature sensor 27 compared to the active region 29 of FIG. 32A, but the center position of the contact region (wedge RX) of the first wire 41 to the source pad 21 coincides with the center of gravity position GD of the active region 29. Also, as shown in FIG. 33A, the region adjacent to the protruding portion 29y in the active region 29 on the opposite side to the gate pad 22 side has a recessed portion 29t formed to be recessed in the vertical direction Y. The control circuit region 29LG is aligned with the active region 29 in the vertical direction Y and is formed to surround the protruding portion 29y of the active region 29 from the horizontal direction X and the vertical direction Y. The control circuit region 29LG has a protrusion 29s that fits into the recess 29t of the active region 29. The temperature sensor 27 is provided at the tip of the protrusion 29s. As shown in Fig. 33A, the temperature sensor 27 is provided at a position that does not overlap with the first wire 41 in a plan view, that is, at a position on the opposite side of the first wire 41 from the gate pad 22 side in the horizontal direction X.

[0240] FIG. 32B shows a case where the first wire 41 is connected to the source pad 21 at two points. As shown in FIG. 32B, the active region 29 is divided into two regions (a first region RG1 and a second region RG2) having equal areas. As shown in FIG. 32B, the first region RG1 and the second region RG2 are formed in a substantially L-shape. Next, the center of gravity GG1 of the first region RG1 and the center of gravity GG2 of the second region RG2 are obtained. The first region RG1 is divided into two rectangular regions, a first division region RG11 and a second division region RG12. Then, the center of gravity GG11 of the first division region RG11 and the center of gravity GG12 of the second division region RG12 are obtained. Since the first division region RG11 is rectangular, the intersection of the diagonals of the first division region RG11 is the center of gravity GG11 of the first division region RG11. Since the second divided region RG12 is rectangular, the intersection of the diagonals of the second divided region RG12 is the second center of gravity GG12 of the divided region RG12. Next, the area SG1 of the first divided region RG11 and the area SG2 of the second divided region RG12 are calculated. Next, in the line segment LG1 connecting the center of gravity GG11 and the center of gravity GG12, the center of gravity GG1 of the first region RG1 is calculated based on the relationship between the distance DG1 between the center of gravity GG11 and the center of gravity GG1, the distance DG2 between the center of gravity GG12 and the center of gravity GG1, and the area SG1 of the first divided region RG11 and the area SG2 of the second divided region RG12. More specifically, the ratio (DG2 / DG1) of the distance DG2 to the distance DG1 is equal to the inverse ratio (SG1 / SG2) of the ratio of the area SG2 of the second divided region RG12 to the area SG1 of the first divided region RG11. Thus, by determining at least one of the distances DG1 and DG2, the center of gravity position GG1 of the first region RG1 is determined. Similarly to the method of determining the center of gravity position GG1 of the first region RG1, the center of gravity position GG2 of the second region RG22 is determined based on the area SG21 of the first divided region RG21 and the area SG22 of the second divided region RG22 on the line segment LG2 connecting the center of gravity position GG21 of the first divided region RG21 and the center of gravity position GG22 of the second divided region RG22.As shown in FIG. 32B, the source pad 21 is provided so as to cover the respective centers of gravity GG1, GG2 of the divided active regions 29 (the center of gravity GG1 of the first region RG1 and the center of gravity GG2 of the second region RG2).

[0241] The two double-dashed line regions RY shown in FIG. 32B indicate a tool head (hereinafter, referred to as a wedge RY) for ultrasonically connecting the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus moves the wedge RY so that the wedge RY is positioned on the center of gravity GG1 of the first region RG1 of the active region 29, and connects the end of the first wire 41 to the source pad 21. As a result, the end of the first wire 41 passed through the wedge RY is connected so as to overlap the center of gravity GG1 of the first region RG1. That is, the first connection portion 41b of the first wire 41 to the source pad 21 includes the center of gravity GG1 of the first region RG1. In FIG. 32B, the center position of the first connection portion 41b coincides with the center of gravity GG1 of the first region RG1. Next, the wedge bonding apparatus moves the wedge RY away from the source pad 21, so that the first wire 41 moves away from the source pad 21. Then, the wedge bonding device moves the wedge RY so that the wedge RY is positioned on the center of gravity GG2 of the second region RG2 of the active region 29, and connects the first wire 41 to the source pad 21. As a result, the first wire 41 passed through the wedge RY is connected so as to overlap the center of gravity GG2 of the second region RG2. That is, the second connection portion 41c of the first wire 41 to the source pad 21 includes the center of gravity GG2 of the second region RG2. In FIG. 32B, the center position of the second connection portion 41c coincides with the center of gravity GG2 of the second region RG2. Note that in this modification, the first connection portion 41b only needs to include the center of gravity GG1 of the first region RG1, and the center position of the first connection portion 41b may be a position different from the center of gravity GG1 of the first region RG1. Furthermore, it is sufficient that the second connection portion 41c includes the center position GG2 of the second region RG2, and the center position of the second connection portion 41c may be a position different from the center position GG2 of the second region RG2.

[0242] FIG. 33B shows an example of the semiconductor device 1 using the active region 29 and the contact region (wedge RX) of the first wire 41 with the source pad 21 of FIG. 32B. In FIG. 33B, the protruding portion 29y of the active region 29 extends in the horizontal direction X, and the semiconductor element 20 is provided so that the protruding portion 29y is on the second lead frame 12 side in the horizontal direction X. As shown in FIG. 33B, a part of the active region 29 is cut out for the arrangement of the temperature sensor 27 compared to the active region 29 of FIG. 32B, but the center position of the contact region (wedge RX) of the first wire 41 with the source pad 21 coincides with the center of gravity position GD of the active region 29. Also, as shown in FIG. 33B, a region adjacent to the protruding portion 29y in the active region 29 on the opposite side to the gate pad 22 side has a recess 29r formed to be recessed in the vertical direction Y. The recess 29r is formed to be recessed obliquely toward the third lead frame 13. The control circuit region 29LG is arranged next to the active region 29 in the horizontal direction X, and is formed to surround the protruding portion 29y of the active region 29 in the horizontal direction X and the vertical direction Y. The gate pad 22 is formed closer to the second lead frame 12 than the protruding portion 29y of the active region 29 in the vertical direction Y, and is formed between the control circuit region 29LG and the active region 29 in the horizontal direction X. The control circuit region 29LG has a protruding portion 29q that fits into the recessed portion 29r of the active region 29. The temperature sensor 27 is provided at the tip of the protruding portion 29q. As shown in FIG. 33B, the temperature sensor 27 is provided at a position that does not overlap the first wire 41 in a plan view, that is, at a position between the first wire 41 and the gate pad 22 in the horizontal direction X.

[0243] (C) As shown in FIG. 34A and FIG. 34B, the shape of the active region 29 is a combination of a plurality of rectangular shapes. FIG. 34A shows a case where the first wire 41 is connected to the source pad 21 at one point. As shown in FIG. 34A, the active region 29 is divided into a rectangular first region RH1 and a convex second region RH2. Next, the center of gravity GH1 of the first region RH1 and the center of gravity GH2 of the second region RH2 are obtained. As shown in FIG. 34A, since the first region RH1 is rectangular, the center of gravity GH1 of the first region RH1 is the intersection of the diagonals of the first region RH1. Since the second region RH2 is convex, the second region RH2 is divided into two rectangular regions, a first division region RH21 and a second division region RH22, in the same manner as the active region 29 in FIG. 33A. Then, the center of gravity GH21 of the first division region RH21 and the center of gravity GH22 of the second division region RH22 are obtained. Since the first divided region RH21 is rectangular, the intersection of the diagonals of the first divided region RH21 is the center of gravity GH21 of the first divided region RH21. Since the second divided region RH22 is rectangular, the intersection of the diagonals of the second divided region RH22 is the second center of gravity GH22 of the second divided region RH22. Next, the area SH21 of the first divided region RH21 and the area SH22 of the second divided region RH22 are calculated. Next, in the line segment LH1 connecting the center of gravity GH21 and the center of gravity GH22, the center of gravity GH2 of the second region RH2 is calculated based on the relationship between the area SH21 of the first divided region RH21 and the area SH22 of the second divided region RH22, the distance DH21 between the center of gravity GH21 and the center of gravity GH2, and the distance DH22 between the center of gravity GH22 and the center of gravity GH2. More specifically, the ratio of the distance DH22 to the distance DH21 (DH22 / DH21) is equal to the inverse ratio (SH21 / SH22) of the ratio of the area SH22 of the second divided region RH22 to the area SH21 of the first divided region RH21. (DH22 / DH21=SH21 / SH22) Thus, by calculating at least one of the distances DH21 and DH22, the center of gravity position GH2 of the second region RH2 is calculated.

[0244] Next, in the line segment LH2 connecting the center of gravity GH1 of the first region RH1 and the center of gravity GH2 of the second region RH2, the center of gravity GH of the active region 29 is calculated based on the distance DH1 between the center of gravity GH1 and the center of gravity GH of the active region 29, the distance DH2 between the center of gravity GH2 and the center of gravity GH of the active region 29, and the relationship between the area SH1 of the first region RH1 and the area SH2 of the second region RH2. More specifically, the ratio (DH1 / DH2) of the distance DH2 to the distance DH1 is equal to the inverse ratio (SH1 / SH2) of the ratio of the area SH2 of the second region RH2 to the area SH1 of the first region RH1 (DH2 / DH1=SH1 / SH2). Thus, the center of gravity GH of the active region 29 is calculated by calculating at least one of the distances DH1 and DH2.

[0245] The region RX indicated by the dashed line in FIG. 34A indicates a tool head (hereinafter referred to as wedge RX) for ultrasonically bonding the first wire 41 to the source pad 21 in a wedge bonding device (not shown). The wedge bonding device moves the wedge RX so that the wedge RX is positioned on the center of gravity GD of the active area 29. The end of the first wire 41 threaded through the wedge RX is connected so as to overlap the center of gravity GH of the active area 29. That is, the contact region of the first wire 41 with the source pad 21 includes the center of gravity GH of the active area 29. In FIG. 34A, the center position of the contact region (wedge RX) of the first wire 41 with the source pad 21 coincides with the center of gravity GH of the active area 29. In this modified example, the contact area (wedge RX) of the first wire 41 to the source pad 21 only needs to include the center of gravity GH of the active area 29, and the center position of the contact area (wedge RX) of the first wire 41 to the source pad 21 may be a position different from the center of gravity GH of the active area 29.

[0246] FIG. 35A shows an example of the semiconductor device 1 using the active region 29 and the contact region (wedge RX) of the first wire 41 to the source pad 21 in FIG. 34A. In FIG. 35A, the first region RH1 and the second region RH2 in the active region 29 are arranged in the horizontal direction X, and the semiconductor element 20 is provided so that the second division region RH22 of the second region RH2 is on the second lead frame 12 side. As shown in FIG. 35A, the gate pad 22 is formed adjacent to the second division region RH22 on the opposite side of the first region RH1 with respect to the second division region RH22. The control circuit region 29LG is arranged with the active region 29 in the vertical direction Y, and has a protrusion 29p that enters between the second division region RH22 and the first region RH1 of the active region 29 in the horizontal direction X. The temperature sensor 27 is provided at the tip of the protrusion 29p. As shown in FIG. 35A, the temperature sensor 27 is provided at a position that does not overlap the first wire 41 in a plan view, that is, at a position closer to the second lead frame 12 in the vertical direction Y than the first wire 41.

[0247] FIG. 34B shows a case where the first wire 41 is connected to the source pad 21 at two points. As shown in FIG. 34B, the active area 29 is divided into two areas (a first area RJ1 and a second area RJ2) having equal areas. As shown in FIG. 34B, the first area RJ1 is formed in a substantially L-shape, and the second area RJ2 is formed in a convex shape. Next, the center of gravity GJ1 of the first area RJ1 and the center of gravity GJ2 of the second area RJ2 are obtained. The first area RJ1 is divided into two rectangular areas, a first divided area RJ11 and a second divided area RJ12. Then, the center of gravity GJ11 of the first divided area RJ11 and the center of gravity GJ12 of the second divided area RJ12 are obtained. Since the first divided area RJ11 is rectangular, the intersection of the diagonals of the first divided area RJ11 is the center of gravity GJ11 of the first divided area RJ11. Since the second divided region RJ12 is rectangular, the intersection of the diagonals of the second divided region RJ12 is the center of gravity GJ12 of the divided region RJ12. Next, the area SJ11 of the first divided region RJ11 and the area SJ12 of the second divided region RJ12 are calculated. Next, in the line segment LJ1 connecting the center of gravity GJ11 and the center of gravity GJ12, ​​the center of gravity GJ1 of the first region RJ1 is calculated based on the relationship between the distance DJ11 between the center of gravity GJ11 and the center of gravity GJ1, the distance DJ12 between the center of gravity GJ12 and the center of gravity GJ1, and the area SJ11 of the first divided region RJ11 and the area SJ12 of the second divided region RJ12. More specifically, the ratio of the distance DJ12 to the distance DJ11 (DJ12 / DJ11) is equal to the inverse ratio (SJ11 / SJ12) of the ratio of the area SJ12 of the second divided region RJ12 to the area SJ11 of the first divided region RJ11. Thus, by finding at least one of the distances DJ11 and DJ12, the center of gravity position GJ1 of the first region RJ1 is found.

[0248] Also, the second region RJ2 is divided into two rectangular regions, a first divided region RJ21 and a second divided region RJ22. Then, the center of gravity GJ21 of the first divided region RJ21 and the center of gravity GJ22 of the second divided region RJ22 are obtained. Since the first divided region RJ21 is rectangular, the intersection of the diagonals of the first divided region RJ21 is the center of gravity GJ21 of the first divided region RJ21. Since the second divided region RJ22 is rectangular, the intersection of the diagonals of the second divided region RJ22 is the second center of gravity GJ22 of the divided region RJ22. Next, the area SJ21 of the first divided region RJ21 and the area SJ22 of the second divided region RJ22 are obtained. Next, in the line segment LJ2 connecting the center of gravity positions GJ21 and GJ22, the center of gravity position GJ2 of the second region RJ2 is obtained based on the relationship between the distance DJ21 between the center of gravity positions GJ21 and GJ2, the distance DJ22 between the center of gravity positions GJ22 and GJ2, and the area SJ21 of the first divided region RJ21 and the area SJ22 of the second divided region RJ22. More specifically, the ratio (DJ22 / DJ21) of the distance DJ22 to the distance DJ21 is equal to the inverse ratio (SJ21 / SJ22) of the ratio of the area SJ22 of the second divided region RJ22 to the area SJ21 of the first divided region RJ21 (DJ22 / DJ21=SJ21 / SJ22). In this way, by determining at least one of the distances DJ21, DJ22, the center of gravity position GJ2 of the second region RJ2 is determined.

[0249] The two dashed-dotted areas RY shown in FIG. 34B indicate a tool head (hereinafter, referred to as a wedge RY) for ultrasonically connecting the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus moves the wedge RY so that the wedge RY is positioned on the center of gravity GJ1 of the first region RJ1 of the active region 29, and connects the end of the first wire 41 to the source pad 21. As a result, the end of the first wire 41 passed through the wedge RY is connected so as to overlap the center of gravity GJ1 of the first region RJ1. That is, the first connection portion 41b of the first wire 41 to the source pad 21 includes the center of gravity GJ1 of the first region RJ1. In FIG. 34B, the center position of the first connection portion 41b coincides with the center of gravity GJ1 of the first region RJ1. Next, the wedge bonding apparatus moves the wedge RY away from the source pad 21, so that the first wire 41 moves away from the source pad 21. Then, the wedge bonding device moves the wedge RY so that the wedge RY is positioned on the center of gravity GJ2 of the second region RJ2 of the active region 29, and connects the first wire 41 to the source pad 21. As a result, the first wire 41 passed through the wedge RY is connected so as to overlap the center of gravity GJ2 of the second region RJ2. That is, the second connection portion 41c of the first wire 41 to the source pad 21 includes the center of gravity GJ2 of the second region RJ2. In FIG. 34B, the center position of the second connection portion 41c coincides with the center of gravity GJ2 of the second region RJ2. Note that in this modified example, the first connection portion 41b only needs to include the center of gravity GJ1 of the first region RJ1, and the center position of the first connection portion 41b may be a position different from the center of gravity GJ1 of the first region RJ1. Furthermore, it is sufficient that the second connection portion 41c includes the center of gravity GJ2 of the second region RJ2, and the center position of the second connection portion 41c may be a position different from the center of gravity GJ2 of the second region RJ2.

[0250] Fig. 35B shows an example of a semiconductor device 1 using the active region 29 and the contact region (wedge RX) of the first wire 41 with the source pad 21 of Fig. 34B. The shapes of the active region 29 and the control circuit region 29LG of Fig. 35B and the position of the temperature sensor 27 are the same as those of Fig. 35A. As shown in Fig. 35B, the temperature sensor 27 is provided at a position that does not overlap with the first wire 41 in a plan view, that is, at a position closer to the second lead frame 12 side in the vertical direction Y than the first wire 41.

[0251] [Multiple first wires] In the second embodiment, the number of the first wires 41 is one, but the number of the first wires 41 is not limited to this. For example, as shown in FIG. 36, the semiconductor element 20 and the third lead frame 13 may be connected by two first wires 41A and 41B. In this case, as shown in FIG. 37, when the active area 29 is divided into a first area RB1 and a second area RB2 having equal areas as in the second embodiment, the semiconductor element 20 is provided so that the first area RB1 and the second area RB2 are arranged in the vertical direction Y and the second area RB2 is on the third lead frame 13 side. The gate pad 22 is formed so as to be adjacent in the horizontal direction X to the end of the second area RB2 on the third lead frame 13 side in the vertical direction Y. The gate pad 22 is formed closer to the second lead frame 12 side than the second area RB2. The position of the temperature sensor 27 with respect to the active area 29 is the same as in the second embodiment.

[0252] 37, the active area 29 is divided into a first region RB1 and a second region RB2 of equal area as in the second embodiment, and the center of gravity GB1 of the first region RB1 and the center of gravity GB2 of the second region RB2 are obtained. As shown in FIG. 37, the first wire 41A is connected to the region of the source pad 21 corresponding to the center of gravity GB1 of the first region RB1, and the first wire 41B is connected to the region of the source pad 21 corresponding to the center of gravity GB2 of the second region RB2. As shown in FIG. 36, the temperature sensor 27 is provided at a position not to overlap with the two first wires 41A and 41B in a plan view. That is, the temperature sensor 27 is located closer to the second lead frame 12 in the horizontal direction X than the first wire 41A, and is located on the opposite side to the gate pad 22 in the vertical direction Y than the first wire 41B.

[0253] [Modification of the first connecting member] In each of the above embodiments, the first wire 41 is used as the first connecting member, but this is not limited thereto. Instead of the first wire 41, for example, a connecting plate (hereinafter, "clip 45") shown in Fig. 38 may be used as the first connecting member. The clip 45 has an element connecting portion 46 connected to the semiconductor element 20, a lead connecting portion 47 connected to the third island portion 13a of the third lead frame 13, and a connecting portion 48 connecting the element connecting portion 46 and the lead connecting portion 47.

[0254] The element connection portion 46 is connected to the source pad 21 of the semiconductor element 20 by, for example, solder. The element connection portion 46 is formed in a band shape in a plan view. A first protrusion 46a and a second protrusion 46b are formed on the element connection portion 46. The first protrusion 46a and the second protrusion 46b are provided so as to be closer to the source pad 21 than other portions of the element connection portion 46. The first protrusion 46a is disposed at a position including a wedge RY including the center of gravity GB1 of the first region RB1, and the second protrusion 46b is disposed at a position including a wedge RY including the center of gravity GB2 of the second region RB2.

[0255] The lead connection portion 47 is formed in a rectangular plate shape and is connected to the third island portion 13a of the third lead frame 13 by soldering. The connecting portion 48 extends along the vertical direction Y. In Fig. 38, the size of the connecting portion 48 in the horizontal direction X is formed to increase from the lead connecting portion 47 toward the element connecting portion 46 in the vertical direction Y. The connecting portion 48 is bent from each of the element connecting portion 46 and the lead connecting portion 47, and is thereby disposed at a position farther away from the semiconductor element 20 in the thickness direction Z than the element connecting portion 46 and the lead connecting portion 47.

[0256] The clip 45 may be made of, for example, copper (Cu), aluminum (Al), a copper alloy, an aluminum alloy, or the like. The clip 45 is covered with a plating layer over substantially the entire surface. The plating layer may be made of, for example, silver (Ag), nickel (Ni), tin (Sn), or an alloy containing these. A plurality of plating layers may be used. The shape of the clip 45 is not limited to that shown in FIG. 38, and may be changed as desired.

[0257] [MISFET structure] In each of the above embodiments, the structure of the MISFET 23a can be changed as desired. As an example, the MISFET 23a may have the structure shown in Fig. 39. The MISFET 23a in Fig. 39 has a gate electrode structure and a source pad 21 structure different from those of the MISFET 23a in each of the above embodiments.

[0258] As shown in FIG. 39, only the gate electrode 260 is embedded in the trench 66. That is, the MISFET 23a in FIG. 39 has a structure in which the embedded electrode 69 is omitted from the MISFET 23a in each of the above embodiments. In accordance with this configuration, the gate electrode 260 is not formed with a recess 68a. The depth of the trench 66 can be changed arbitrarily. For example, the trench 66 of the MISFET 23a shown in FIG. 39 may be formed shallower than the trench 66 of the MISFET 23a in each of the above embodiments. Note that, as shown in FIG. 39, the thickness of the body contact region 73 may be thicker than the thickness of the source region 70.

[0259] 39, the source pad 270 has a multi-layer structure. In detail, the source pad 270 includes a first protective layer 271 covering the epitaxial layer 62 and the interlayer insulating film 74, a first electrode layer 272 covering the first protective layer 271, a second protective layer 273 covering the first electrode layer 272, and a second electrode layer 274 covering the second protective layer 273. In addition, a connection layer 275 for connecting the first wire 41 is formed on the second electrode layer 274. The connection layer 275 is formed by nickel-palladium (NiPd) alloy plating.

[0260] The first protective layer 271 and the second protective layer 273 are made of, for example, titanium nitride (TiN). The thickness of each of the first protective layer 271 and the second protective layer 273 is thinner than the thickness of each of the first electrode layer 272 and the second electrode layer 274. The first electrode layer 272 and the second electrode layer 274 are made of, for example, aluminum or an aluminum alloy. In one example, the first electrode layer 272 is made of AlSiCu. The second electrode layer 274 is made of AlCu. The first electrode layer 272 and the second electrode layer 274 may be made of copper. In addition, the Vickers hardness of each of the first protective layer 271 and the second protective layer 273 is greater than the Vickers hardness of each of the first electrode layer 272 and the second electrode layer 274. This makes it more difficult for the first protective layer 271 and the second protective layer 273 to deform than the first electrode layer 272 and the second electrode layer 274.

[0261] According to such a configuration of the source pad 270, it is possible to reduce stress applied to the gate insulating film 67 due to force or vibration applied to the source pad 270 when the first wire 41 is connected to the source pad 270 by wedge bonding, for example. Therefore, it is possible to suppress the occurrence of cracks in the gate insulating film 67.

[0262] Furthermore, the thickness Tsp of the source pad 270 is 16000 Å or more, and preferably 20000 Å or more. 40 is a graph showing the relationship between the thickness Tsp of the source pad 270 and the stress (maximum principal stress) applied to the gate insulating film 67 when the first wire 41 is connected to the source pad 270. As can be seen from the graph in FIG. 40, as the thickness Tsp of the source pad 270 increases, the stress applied to the gate insulating film 67 decreases. In particular, when the thickness Tsp is thinner than 20,000 Å, the degree of increase in the stress applied to the gate insulating film 67 increases as the thickness Tsp decreases. On the other hand, when the thickness Tsp is thicker than 20,000 Å, the degree of increase in the stress applied to the gate insulating film 67 is small even if the thickness Tsp decreases.

[0263] 41 is a graph showing the relationship between the thickness Tsp of the source pad 270 and the TDDB failure time. Here, the TDDB failure time is, for example, the time until the cumulative failure rate reaches 0.1% in a TDDB (Time Dependent Dielectric Breakdown) test.

[0264] As can be seen from FIG. 41, when the thickness Tsp of the source pad 270 is 8000 Å or more and less than 16000 Å, the stress applied to the gate insulating film 67 becomes large when the first wire 41 is connected to the source pad 270, and damage occurs to the gate insulating film 67, causing the semiconductor element 20 to fail in a short time. On the other hand, when the thickness Tsp of the source pad 21 is 16000 Å or more, especially in the range of 16000 Å or more and 20000 Å or less, the TDDB failure time increases rapidly as the thickness Tsp increases. That is, the semiconductor element 20 becomes less likely to fail rapidly as the thickness Tsp increases in the range of 16000 Å or more and 20000 Å or less. In this way, the semiconductor element 20 becomes less likely to fail when the thickness Tsp of the source pad 270 is 16000 Å or more, especially 20000 Å or more.

[0265] [Sealing resin] In each of the above embodiments, an ion trapping material containing aluminum (Al) and magnesium (Mg) may be added to the sealing resin 30. According to this configuration, the chloride ions (Cl - ) is trapped by the ion trapping material, it is possible to suppress the chloride ions from bonding with the first wire 41 and causing pitting corrosion.

[0266] [Lead frame] In each of the above embodiments, the location where the plating layer 14 is formed on the lead frame 10 can be changed as desired. For example, the plating layer 14 may be formed partially on the lead frame 10. In one example, the plating layer 14 is formed on each of the first island portion 11a of the first lead frame 11, the second island portion 12a of the second lead frame 12, and the third island portion 13a of the third lead frame 13. The plating layer 14 is not formed on at least one of the first terminal portion 11b of the first lead frame 11, the second terminal portion 12b of the second lead frame 12, and the third terminal portion 13b of the third lead frame 13.

[0267] [Functional element formation area] In the first to third embodiments, the ratio of the area of ​​the channel formation region 72 to the unit area is not limited to 50% and can be changed arbitrarily. For example, the ratio of the area of ​​the channel formation region 72 to the unit area may be 25% or 75%. The ratio of the area of ​​the channel formation region 72 to the unit area is set based on a balance between the active clamp withstand voltage Eac and the on-resistance. Note that the ratio of the area of ​​the channel formation region 72 to the unit area is preferably, for example, 20% or more and 80% or less.

[0268] In the fourth embodiment, the second functional element formation region unit U2, which generates a large amount of heat, may be disposed in a region of the active region 29 adjacent to the temperature sensor 27. This allows adjustment so that the temperature in the active region 29 is highest near the temperature sensor 27.

[0269] In the fourth embodiment, the plurality of functional element forming regions 231 are composed of the first to third functional element forming regions 232 to 234, but the types of the plurality of functional element forming regions 231 are not limited to this. The number of types of the functional element forming regions 231 can be changed arbitrarily. For example, the types of the functional element forming regions 231 may be composed of two types of functional element forming regions, or may be composed of four or more types of functional element forming regions. In addition, the ratio of the area of ​​the channel forming region 72 per unit area in the fourth embodiment is 25%, 50%, or 75%, but is not limited to this and may be other values ​​(for example, 30%, 60%, 80%, etc.).

[0270] [Application example of semiconductor device 1] 42 to 46, examples of circuits to which the semiconductor device 1 is applied will be described. (First application example) 42, the semiconductor device 1 can constitute an asynchronous rectification type switching power supply circuit 280. The switching power supply circuit 280 has one semiconductor device 1, an inductor 281, and a smoothing capacitor 282. The switching power supply circuit 280 drives the semiconductor device 1 to generate a desired output voltage Vout from an input voltage Vin.

[0271] (Second application example) As shown in FIG. 43, the semiconductor device 1 can configure a synchronous rectification type switching power supply circuit 290. The switching power supply circuit 290 has an inverter section 291, an inductor 292, and a smoothing capacitor 293. The inverter section 291 has an upper switching element 294U and a lower switching element 294L. The source terminal of the upper switching element 294U and the drain terminal of the lower switching element 294L are electrically connected. The gate terminal of the upper switching element 294U and the gate terminal of the lower switching element 294L are connected to a gate drive circuit 295. The switching power supply circuit 290 drives the upper switching element 294U and the lower switching element 294L complementarily (exclusively) to generate a desired output voltage Vout from an input voltage Vin. The semiconductor device 1 can be applied to at least one of the upper switching element 294U and the lower switching element 294L. For example, when the semiconductor device 1 is applied to the lower switching element 294L, the semiconductor device 1 replaces the lower switching element 294L of the inverter unit 291 and a gate drive circuit for driving the lower switching element 294L of the gate drive circuit 295.

[0272] (Third Application Example) The semiconductor device 1 can be applied to an H-bridge converter. Fig. 44 shows a circuit configuration of an H-bridge step-up / step-down converter circuit (hereinafter simply referred to as "converter circuit 300"), which is an example of an H-bridge converter.

[0273] The converter circuit 300 includes a first inverter unit 301, a second inverter unit 302, an input capacitor 303, an output capacitor 304, an inductance 305, and a gate drive circuit 306, and steps up or down an input voltage Vi to an output voltage Vo.

[0274] The first inverter unit 301 has an upper switching element 301U and a lower switching element 301L. A source terminal of the upper switching element 301U and a drain terminal of the lower switching element 301L are electrically connected. The first inverter unit 301 is connected in parallel with the input capacitor 303. In detail, a drain terminal of the upper switching element 301U is electrically connected to a first terminal of the input capacitor 303, and a source terminal of the lower switching element 301L is electrically connected to a second terminal of the input capacitor 303.

[0275] The second inverter unit 302 has an upper switching element 302U and a lower switching element 302L. A source terminal of the upper switching element 302U and a drain terminal of the lower switching element 302L are electrically connected. The second inverter unit 302 is connected in parallel with the output capacitor 304. In detail, a drain terminal of the upper switching element 302U is electrically connected to a first terminal of the output capacitor 304, and a source terminal of the lower switching element 302L is electrically connected to a second terminal of the output capacitor 304.

[0276] The inductance 305 is connected to the first inverter unit 301 and the second inverter unit 302. More specifically, a first terminal of the inductance 305 is connected to a connection point between a source terminal of the upper switching element 301U and a drain terminal of the lower switching element 301L in the first inverter unit 301. A second terminal of the inductance 305 is connected to a connection point between a source terminal of the upper switching element 302U and a drain terminal of the lower switching element 302L in the second inverter unit 302.

[0277] The gate drive circuit 306 is electrically connected to the gate terminals of the switching elements 301U, 301L, 302U, and 302L, respectively. The gate drive circuit 306 controls the on / off of the switching elements 301U, 301L, 302U, and 302L.

[0278] The semiconductor device 1 can be applied to at least one of the switching elements 301U, 301L, 302U, and 302L. For example, when the semiconductor device 1 is applied to the lower switching element 301L of the first inverter unit 301, the lower switching element 301L of the first inverter unit 301 and a gate drive circuit for driving the lower switching element 301L of the gate drive circuit 306 are replaced with the semiconductor device 1.

[0279] (Example 4) The semiconductor device 1 can be applied to a full-bridge inverter circuit (hereinafter, simply referred to as "inverter circuit 310") shown in Fig. 45. The inverter circuit 310 includes a first inverter section 311, a second inverter section 312, an input capacitor 313, and a gate drive circuit 314, and converts an input voltage Vi into an output voltage Vo between the first inverter section 311 and the second inverter section 312.

[0280] The first inverter unit 311 has an upper switching element 311U and a lower switching element 311L. A source terminal of the upper switching element 311U and a drain terminal of the lower switching element 311L are electrically connected. The first inverter unit 311 is connected in parallel with the input capacitor 313. In detail, a drain terminal of the upper switching element 311U is electrically connected to a first terminal of the input capacitor 313, and a source terminal of the lower switching element 311L is electrically connected to a second terminal of the input capacitor 313.

[0281] The second inverter section 312 has an upper switching element 312U and a lower switching element 312L. The source terminal of the upper switching element 312U and the drain terminal of the lower switching element 312L are electrically connected. The second inverter section 312 is connected in parallel with the first inverter section 311. In detail, the drain terminal of the upper switching element 312U is electrically connected to the drain terminal of the upper switching element 311U, and the source terminal of the lower switching element 312L is electrically connected to the source terminal of the lower switching element 311L. The output voltage Vo is defined by a voltage obtained between a connection point between the source terminal of the upper switching element 311U and the drain terminal of the lower switching element 311L, and a connection point between the source terminal of the upper switching element 312U and the drain terminal of the lower switching element 312L.

[0282] The gate drive circuit 314 is electrically connected to the gate terminals of the switching elements 311U, 311L, 312U, and 312L. The gate drive circuit 314 controls the on / off of the switching elements 311U, 311L, 312U, and 312L.

[0283] The semiconductor device 1 can be applied to at least one of the switching elements 311U, 311L, 312U, and 312L. For example, when the semiconductor device 1 is applied to the lower switching element 311L of the first inverter unit 311, the semiconductor device 1 replaces the lower switching element 311L of the first inverter unit 311 and a gate drive circuit for driving the lower switching element 311L of the gate drive circuit 314.

[0284] (Fifth Application Example) The semiconductor device 1 can be applied to a three-phase AC inverter circuit shown in FIG. 46 (hereinafter simply referred to as a "three-phase inverter circuit 320").

[0285] The three-phase inverter circuit 320 includes a power driver 321 electrically connected to coils of U-, V-, and W-phases of a three-phase AC motor (hereinafter simply referred to as "motor 327"), a gate driver circuit 325 that controls the power driver 321, and a converter unit 326 connected to the power driver 321 and a power source ES. The converter unit 326 has a positive power terminal EP and a negative power terminal EN.

[0286] The power driving unit 321 controls the power supplied to the U-phase, V-phase, and W-phase coils of the motor 327. The power driving unit 321 has a U-phase inverter unit 322, a V-phase inverter unit 323, and a W-phase inverter unit 324. The U-phase inverter unit 322, the V-phase inverter unit 323, and the W-phase inverter unit 324 are connected in parallel with each other between the positive power terminal EP and the negative power terminal EN.

[0287] The U-phase inverter unit 322 has an upper switching element 322U and a lower switching element 322L. The drain terminal of the upper switching element 322U is electrically connected to the positive power terminal EP. The source terminal of the upper switching element 322U and the drain terminal of the lower switching element 322L are electrically connected. The source terminal of the lower switching element 322L is connected to the negative power terminal EN. A snubber diode 322A is connected in anti-parallel to the upper switching element 322U, and a snubber diode 322B is connected in anti-parallel to the lower switching element 322L. In more detail, the anode of the snubber diode 322A is electrically connected to the source terminal of the upper switching element 322U, and the cathode of the snubber diode 322A is electrically connected to the drain terminal of the upper switching element 322U. The anode of the snubber diode 322B is electrically connected to the source terminal of the lower switching element 322L, and the cathode of the snubber diode 322B is electrically connected to the drain terminal of the lower switching element 322L.

[0288] The V-phase inverter unit 323 has an upper switching element 323U and a lower switching element 323L. The drain terminal of the upper switching element 323U is electrically connected to the positive power terminal EP. The source terminal of the upper switching element 323U and the drain terminal of the lower switching element 323L are electrically connected. The source terminal of the lower switching element 323L is connected to the negative power terminal EN. A snubber diode 323A is connected in anti-parallel to the upper switching element 323U, and a snubber diode 323B is connected in anti-parallel to the lower switching element 323L. In more detail, the anode of the snubber diode 323A is electrically connected to the source terminal of the upper switching element 323U, and the cathode of the snubber diode 323A is electrically connected to the drain terminal of the upper switching element 323U. The anode of the snubber diode 323B is electrically connected to the source terminal of the lower switching element 323L, and the cathode of the snubber diode 323B is electrically connected to the drain terminal of the lower switching element 323L.

[0289] The W-phase inverter unit 324 has an upper switching element 324U and a lower switching element 324L. The drain terminal of the upper switching element 324U is electrically connected to the positive power terminal EP. The source terminal of the upper switching element 324U and the drain terminal of the lower switching element 324L are electrically connected. The source terminal of the lower switching element 324L is connected to the negative power terminal EN. A snubber diode 324A is connected in anti-parallel to the upper switching element 324U, and a snubber diode 324B is connected in anti-parallel to the lower switching element 324L. In more detail, the anode of the snubber diode 324A is electrically connected to the source terminal of the upper switching element 324U, and the cathode of the snubber diode 324A is electrically connected to the drain terminal of the upper switching element 324U. The anode of the snubber diode 324B is electrically connected to the source terminal of the lower switching element 324L, and the cathode of the snubber diode 324B is electrically connected to the drain terminal of the lower switching element 324L.

[0290] The gate drive circuit 325 is electrically connected to the gate terminals of the switching elements 322U, 322L, 323U, 323L, 324U, and 324L. The gate drive circuit 325 controls the on / off of the switching elements 322U, 322L, 323U, 323L, 324U, and 324L.

[0291] The semiconductor device 1 can be applied to at least one of the switching elements 322U, 322L, 323U, 323L, 324U, and 324L. For example, when the semiconductor device 1 is applied to the lower switching element 322L of the U-phase inverter unit 322, the semiconductor device 1 replaces the lower switching element 322L of the U-phase inverter unit 322 and a gate drive circuit for driving the lower switching element 322L of the gate drive circuit 325.

[0292] [Additional Notes] The technical ideas that can be understood from the above embodiment and the above modified examples will be described below. (Appendix 1-1) A semiconductor device, wherein an active area is approximately L-shaped, combining a small rectangular first area and a large rectangular second area, and a first wire and a source pad as a connecting member are connected to each other at a position on a line segment connecting the center of gravity of the first area and the center of gravity of the second area.

[0293] (Appendix 1-2) The semiconductor device described in Appendix 1-1, wherein the semiconductor element includes a transistor, and the semiconductor device comprises a second lead frame for controlling the on / off of the transistor and a third lead frame connected to the first wire, the second lead frame being arranged on the first region side and the third lead frame being arranged on the second region side.

[0294] (Appendix 1-3) The semiconductor device described in Appendix 1-2, wherein the semiconductor element has a gate pad connected to the second lead frame, and the gate pad is arranged in a rectangular area surrounded by an extension line of a side (first side) of the first region RA1 and an extension line of a side (fourth side) of the second region, in which the transistor is not located.

[0295] (Appendix 1-4) The semiconductor device described in Appendix 1-3, wherein a source pad is also approximately L-shaped, the source pad is formed across the first region and the second region included in the active region, and the source pad is configured such that a first side of the source pad that is furthest from the second region horizontally coincides with a position at which the gate pad is provided.

[0296] (Appendix 1-5) The semiconductor device according to claim 1-3, wherein a temperature sensor is disposed between the gate pad and the source pad.

[0297] (Appendix 1-6) The semiconductor device according to claim 1-1, wherein the first wire and the source pad are connected to each other at two locations, a center of gravity of the first region and a center of gravity of the second region.

[0298] (Appendix 2-1) 1. A semiconductor device comprising: a substrate including a transistor formation region in which a transistor is formed; a semiconductor element having an electrode pad on the transistor formation region; and a first connection member connected to the electrode pad at one location, wherein the transistor formation region is formed in a concave shape having a single recess in the vertical center of a rectangle or a single recess in the horizontal center of the rectangle in a planar view; the electrode pad is provided so as to cover a center of gravity of the transistor formation region in the planar view; and a connection region where the first connection member is connected to the electrode pad includes a center of gravity of the transistor formation region in the planar view.

[0299] (Appendix 2-2) The semiconductor device according to claim 2-1, wherein a center position of the connection region coincides with a center of gravity position of the transistor formation region.

[0300] (Appendix 2-3) 1. A semiconductor device comprising: a substrate including a transistor formation region in which a transistor is formed; a semiconductor element having an electrode pad on the transistor formation region; and a first connection member connected to the electrode pad at multiple points, wherein the transistor formation region is formed in a concave shape having one recess in the vertical center of a rectangle or one recess in the horizontal center in a plan view, and is divided into a plurality of divided regions of equal area according to the number of connection points of the first connection member, the electrode pad is provided so as to cover the center of gravity of each of the plurality of divided regions in the plan view, and a connection region where the first connection member is connected to the electrode pad includes the center of gravity of each of the plurality of divided regions in the plan view.

[0301] (Appendix 2-4) a semiconductor device comprising: a substrate including a transistor formation region in which a transistor is formed; a semiconductor element having an electrode pad on the transistor formation region; and a plurality of first connection members connected to the electrode pad, wherein the transistor formation region is formed in a concave shape having one recess in the vertical center of a rectangle or one recess in the horizontal center in a plan view; and the transistor formation region is divided into a plurality of divided regions of equal area according to the number of the first connection members, the electrode pad is provided so as to cover the center of gravity of each of the plurality of divided regions in the plan view, and the connection region in which the plurality of first connection members are respectively connected to the electrode pad includes the center of gravity of each of the plurality of divided regions in the plan view.

[0302] (Appendix 2-5) The semiconductor device of Appendix 4, wherein the number of the first connection members is two, and the transistor formation region is divided into two of the divided regions at the center in the vertical direction by a virtual line extending in the horizontal direction when the recess is provided in the center in the vertical direction, and is divided into two of the divided regions at the center in the horizontal direction by a virtual line extending in the vertical direction when the recess is provided in the center in the horizontal direction.

[0303] (Appendix 2-6) The semiconductor device according to any one of Appendices 2-1 to 2-5, further comprising a control circuit region formed in a region of the semiconductor element different from the transistor formation region, the control circuit region controlling a current flowing through the semiconductor device.

[0304] (Appendix 2-7) The semiconductor device according to claim 2-6, wherein at least a portion of the control circuit region is disposed within a recess of the transistor formation region.

[0305] (Appendix 2-8) The semiconductor device according to claim 2-6 or 2-7, wherein a temperature sensor is provided in the control circuit region.

[0306] (Appendix 2-9) The semiconductor device according to claim 2-8, wherein the temperature sensor is arranged in a portion of the control circuit region that does not overlap with the first connection member in the planar view.

[0307] (Appendix 2-10) The semiconductor device according to claim 2-8 or 2-9, wherein the temperature sensor is provided in a portion of the control circuit region arranged in the recess, adjacent to a bottom surface of the recess.

[0308] (Appendix 2-11) The semiconductor device described in Appendix 2-8 or 2-9, wherein the transistor formation region has a first recess and a second recess as the recess, the second recess is recessed from a bottom surface of the first recess, at least a portion of the control circuit region is located within the second recess, and the temperature sensor is provided at a portion of the control circuit region that is located within the second recess.

[0309] (Appendix 2-12) The semiconductor device according to any one of Appendices 2-1 to 2-11, wherein the semiconductor element has a power transistor and a control electrode pad connected to a control terminal of the power transistor, and the control electrode pad is disposed in a cut-out region at a location different from the recess in the transistor formation region.

[0310] (Appendix 3-1) A semiconductor element having a substrate including a transistor formation region having a shape other than a rectangle in which a transistor is formed, and an electrode pad on the transistor formation region; A first connection member connected to the electrode pad at one point; having the electrode pad is provided so as to cover a center of gravity of the transistor formation region in a plan view, In the plan view, a connection region where the first connection member is connected to the electrode pad includes a center of gravity of the transistor formation region. Semiconductor device.

[0311] (Appendix 3-2) The center position of the connection region coincides with the center of gravity of the transistor formation region. The semiconductor device according to claim 3-1. (Appendix 4-1) a semiconductor element including a substrate including a transistor forming region having a shape other than a rectangle in which a transistor is formed and a control circuit region in which a circuit for controlling the transistor is provided, a temperature sensor provided in the control circuit region, and an electrode pad on the transistor forming region; A first connection member connected to the electrode pad; having The transistor formation region is A first region; A second region having an area larger than that of the first region; having the temperature sensor is disposed at a position adjacent to the transistor formation region, the electrode pad is provided so as to cover the center of gravity of each of the first region and the second region in a plan view; In the plan view, a connection region where the first connection member is connected to the electrode pad includes a center of gravity of the transistor formation region. Semiconductor device. (Appendix 4-2) The temperature sensor is disposed in a location where the most heat is concentrated in the control circuit region outside the electrode pads when the semiconductor device is operating. The semiconductor device according to claim 4-1. (Appendix 4-3) The temperature sensor is provided adjacent to the connection region in the plan view. The semiconductor device according to claim 4-1 or 4-2. (Appendix 4-4) a current sensor for detecting a current flowing through the transistor; The current sensor is disposed between the electrode pad and the control circuit area. The semiconductor device according to any one of Supplementary Notes 4-1 to 4-3. (Appendix 4-5) The current sensor is provided in the transistor formation region. The semiconductor device according to claim 4-4. (Appendix 4-6) The center position of the connection region coincides with the center of gravity of the transistor formation region. The semiconductor device according to any one of Supplementary Notes 4-1 to 4-5. (Appendix 4-7) the semiconductor device has a power transistor and a control electrode pad connected to a control terminal of the power transistor; a first lead frame on which the semiconductor element is mounted; a second lead frame having one end connected to the control electrode pad and the other end connected to a second connection member; a third lead frame having one end connected to the semiconductor element and the other end connected to the first connection member; have The semiconductor device according to any one of Supplementary Notes 4-1 to 4-6. (Appendix 4-8) the first lead frame and the third lead frame are formed of copper, the first connection member is configured to include aluminum, At least one surface of the first lead frame and the third lead frame has a plating layer. The semiconductor device according to claim 4-7. (Appendix 4-9) the first lead frame has a first island portion on which the semiconductor element is mounted, The first island portion has a plating layer on a surface on which the semiconductor element is mounted. The semiconductor device according to claim 4-8. (Appendix 4-10) the third lead frame has a third island portion to which the first connection member is connected; The third island portion has a plating layer on a surface to which the first connection member is connected. The semiconductor device according to appendix 4-8 or 4-9. (Appendix 4-11) the second lead frame containing copper has a second island portion to which the second connection member is connected; the second connection member is configured to include aluminum, The second island portion has a plating layer on a surface to which the second connection member is connected. The semiconductor device according to any one of Appendixes 4-7 to 4-10. (Appendix 4-12) the first connection member is connected to the electrode pad by wedge bonding and has a connection portion connected to the electrode pad; In a plan view, the connection portion extends from the semiconductor element toward the third island portion. The semiconductor device according to claim 4-10. (Appendix 4-13) The substrate is provided with a plurality of trenches and a plurality of functional element forming regions arranged along the plurality of trenches, each of the functional element forming regions including a channel forming region serving as a current path; the plurality of functional element formation regions include a first functional element formation region in which an area of ​​the channel formation region per unit area is relatively small, and a second functional element formation region in which an area of ​​the channel formation region per unit area is relatively large, The first functional element forming region is provided in a region in which heat generation should be suppressed among the plurality of functional element forming regions. The semiconductor device according to any one of Supplementary Notes 4-1 to 4-12. (Appendix 4-14) the first connection member is electrically connected to the plurality of functional element forming regions; The second functional element forming region is provided in a region of the plurality of functional element forming regions to which the first connection member is electrically connected. The semiconductor device according to claim 4-13. (Appendix 4-15) the first connection member is connected to the electrode pad at a plurality of points, The first functional element forming region is provided in a region between adjacent second functional element forming regions among the second functional element forming regions in which the first connecting member is connected to the plurality of functional element forming regions. The semiconductor device according to claim 4-14. (Appendix 4-16) a metal layer is formed between the functional element forming region and the electrode pad, the metal layer electrically connecting the functional element forming region and the electrode pad; The metal layer has one or more slits at least in a portion facing the electrode pad. The semiconductor device according to any one of Supplementary Notes 4-13 to 4-15. (Appendix 4-17) the metal layer includes a first metal layer and a second metal layer provided so as to be laminated with the first metal layer through a contact electrically connected to the first metal layer; one or more slits are provided in at least a portion of the first metal layer and a portion of the second metal layer facing the electrode pad, The slits of the first metal layer and the slits of the second metal layer face each other in a stacking direction of the first metal layer and the second metal layer. The semiconductor device according to claim 4-16. (Appendix 4-18) an interlayer insulating film formed on the functional element formation region and covering the first metal layer and the second metal layer; The interlayer insulating film is embedded in the slits of the first metal layer and the slits of the second metal layer. The semiconductor device according to claim 4-17. (Appendix 4-19) The electrode pad is made of copper. The semiconductor device according to any one of Supplementary Notes 4-1 to 4-18. (Appendix 4-20) A connection layer for connecting the first connection member is provided on the surface of the electrode pad. The semiconductor device according to any one of Appendixes 4-1 to 4-19. (Appendix 4-21) The thickness of the electrode pad is 16000 Å or more. The semiconductor device according to any one of Appendixes 4-1 to 4-20. (Appendix 4-22) The thickness of the electrode pad is 20000 Å or more. The semiconductor device according to claim 4-21. (Appendix 4-23) the first connection member is made of aluminum; a sealing resin that seals at least the semiconductor element and the first connection member; The linear expansion coefficient of the sealing resin is greater than 10 ppm / K and less than 15 ppm / K. The semiconductor device according to any one of Appendixes 4-1 to 4-22. (Appendix 4-24) The linear expansion coefficient of the sealing resin is 12 ppm / K. The semiconductor device according to claim 4-23. (Appendix 4-25) The sealing resin is doped with an ion trap material containing aluminum and magnesium. The semiconductor device according to appendix 4-23 or 4-24. (Appendix 4-26) The electrode pad is a first protective layer covering the interlayer insulating film; a first electrode layer covering the first protective layer; A second protective layer covering the first electrode layer; A second electrode layer covering the second protective layer; having The Vickers hardness of each of the first protective layer and the second protective layer is greater than the Vickers hardness of each of the first electrode layer and the second electrode layer. The semiconductor device according to any one of Appendixes 4-1 to 4-25. (Appendix 4-27) the first electrode layer and the second electrode layer are made of aluminum or an aluminum alloy; The first protective layer and the second protective layer are made of titanium nitride. The semiconductor device according to claim 4-26. (Appendix 4-28) The first connection member is an aluminum wire that is wedge bonded to the electrode pad. The semiconductor device according to any one of Supplementary Notes 4-1 to 4-27. (Appendix 4-29) The diameter of the aluminum wire is 300 μm or more and 400 μm or less. The semiconductor device according to claim 4-28. (Appendix 4-30) The first connection member is a copper wire that is wedge bonded to the electrode pad. The semiconductor device according to any one of Appendices 4-1 to 4-29. (Appendix 4-31) The on-resistance of the semiconductor device is 30 mΩ or less. The semiconductor device according to any one of Appendixes 4-1 to 4-30. [Explanation of symbols]

[0312] 1...Semiconductor device 11…First lead frame 11a…First Island 12…2nd lead frame 12a…Second Island 13…Third lead frame 13a…Third Island 14…Plating layer 20...Semiconductor element 21...Source pad (electrode pad) 21a…Connection layer 22...Gate pad (control electrode pad) 23a...MISFET (power transistor) 27...Temperature sensor 29...Active area (transistor formation area) 30…Sealing resin 41...First wire (first connection member) 41a…Connection part 41b…First connection part 41c…Second connection part 42...Second wire (second connection member) 50…Substrate 66…Trench 72…Channel formation region 74...Interlayer insulating film 80...First source electrode (first metal layer, metal layer) 81…Contact 82...Second source electrode (second metal layer, metal layer) 83…Contact 220…First slit 221...Second slit 231...Functional element formation region 232...first functional element forming region 233...Second functional element forming region 270…Source pad (electrode pad) 271…1st protective layer 272...First electrode layer 273…Second protective layer 274…Second electrode layer 275…Connection layer GC,GD,GF,GH…Center of gravity position GB1, GE1, GG1, GJ1...Center of gravity of the transistor formation area divided into equal areas GB2, GE2, GG2, GJ2...Center of gravity of the transistor formation area divided into equal areas RX, RY…Wedge (connection area)

Claims

1. a semiconductor element including a substrate including a transistor forming region having a shape other than a rectangle in which transistors are formed and a control circuit region in which a circuit for controlling the transistors is provided, a temperature sensor provided in the control circuit region, and an electrode pad on the transistor forming region; A first connection member connected to the electrode pad; having The transistor formation region is A first region; and A second region having an area larger than that of the first region; having the temperature sensor is disposed at a position adjacent to the transistor formation region, the electrode pad is provided so as to cover the center of gravity of each of the first region and the second region in a plan view; a connection region where the first connection member is connected to the electrode pad includes a center of gravity of the transistor formation region in the plan view, The center position of the connection region coincides with the center of gravity of the transistor formation region. Semiconductor device.

2. The temperature sensor is disposed in a location where the most heat is concentrated in the area outside the electrode pads in the control circuit area when the semiconductor device is operating. The semiconductor device according to claim 1 .

3. The temperature sensor is provided adjacent to the connection region in the plan view. The semiconductor device according to claim 1 .

4. a current sensor for detecting a current flowing through the transistor; The current sensor is disposed between the electrode pad and the control circuit area. The semiconductor device according to any one of claims 1 to 3.

5. The current sensor is provided in the transistor formation region. The semiconductor device according to claim 4.

6. the semiconductor device has a power transistor and a control electrode pad connected to a control terminal of the power transistor; a first lead frame on which the semiconductor element is mounted; a second lead frame having one end connected to the control electrode pad and the other end connected to a second connection member; a third lead frame having one end connected to the semiconductor element and the other end connected to the first connection member; have The semiconductor device according to any one of claims 1 to 5.

7. the first lead frame and the third lead frame are configured to include copper; The first connection member is configured to include aluminum, At least one surface of the first lead frame and the third lead frame has a plating layer. The semiconductor device according to claim 6.

8. the first lead frame has a first island portion on which the semiconductor element is mounted, The first island portion has a plating layer on a surface on which the semiconductor element is mounted. The semiconductor device according to claim 7.

9. the third lead frame has a third island portion to which the first connection member is connected; The third island portion has a plated layer on a surface to which the first connection member is connected. The semiconductor device according to claim 7 or 8.

10. the second lead frame containing copper has a second island portion to which the second connection member is connected; The second connection member is configured to include aluminum, The second island portion has a plating layer on a surface to which the second connection member is connected. The semiconductor device according to any one of claims 6 to 9.

11. the first connection member is connected to the electrode pad by wedge bonding and has a connection portion connected to the electrode pad; In a plan view, the connection portion extends from the semiconductor element toward the third island portion. The semiconductor device according to claim 9.

12. The substrate is provided with a plurality of trenches and a plurality of functional element forming regions arranged along the plurality of trenches, each of the functional element forming regions including a channel forming region serving as a current path; the plurality of functional element formation regions include a first functional element formation region in which an area of ​​the channel formation region per unit area is relatively small, and a second functional element formation region in which an area of ​​the channel formation region per unit area is relatively large, The first functional element forming region is provided in a region of the plurality of functional element forming regions where heat generation should be suppressed. The semiconductor device according to any one of claims 1 to 11.

13. the first connection member is electrically connected to the plurality of functional element forming regions; The second functional element forming region is provided in a region of the plurality of functional element forming regions to which the first connection member is electrically connected. The semiconductor device according to claim 12.

14. the first connection member is connected to the electrode pad at a plurality of points, The first functional element forming region is provided in a region between adjacent second functional element forming regions among the second functional element forming regions in which the first connection member is connected to the plurality of functional element forming regions. The semiconductor device according to claim 13.

15. a metal layer is formed between the functional element forming region and the electrode pad, the metal layer electrically connecting the functional element forming region and the electrode pad; The metal layer has one or more slits at least in a portion facing the electrode pad. The semiconductor device according to any one of claims 12 to 14.

16. the metal layer includes a first metal layer and a second metal layer provided so as to be laminated with the first metal layer through a contact electrically connected to the first metal layer; one or a plurality of slits are provided in each of the first metal layer and the second metal layer at least in a portion facing the electrode pad; The slits of the first metal layer and the slits of the second metal layer face each other in a stacking direction of the first metal layer and the second metal layer. The semiconductor device according to claim 15.

17. an interlayer insulating film formed on the functional element forming region and covering the first metal layer and the second metal layer; The interlayer insulating film is embedded in the slits of the first metal layer and the slits of the second metal layer. The semiconductor device according to claim 16.

18. The electrode pad is made of copper. The semiconductor device according to any one of claims 1 to 17.

19. A connection layer for connecting the first connection member is provided on the surface of the electrode pad. The semiconductor device according to any one of claims 1 to 18.

20. The thickness of the electrode pad is 16000 Å or more. The semiconductor device according to any one of claims 1 to 19.

21. The thickness of the electrode pad is 20000 Å or more. The semiconductor device according to claim 20.

22. the first connection member is made of aluminum; a sealing resin that seals at least the semiconductor element and the first connection member; The linear expansion coefficient of the sealing resin is greater than 10 ppm / K and less than 15 ppm / K. The semiconductor device according to any one of claims 1 to 21.

23. The linear expansion coefficient of the sealing resin is 12 ppm / K. The semiconductor device according to claim 22.

24. The sealing resin is doped with an ion trap material containing aluminum and magnesium.

24. The semiconductor device according to claim 22 or 23.

25. The electrode pad is a first protective layer covering the interlayer insulating film; a first electrode layer covering the first protective layer; A second protective layer covering the first electrode layer; A second electrode layer covering the second protective layer; having The Vickers hardness of each of the first protective layer and the second protective layer is greater than the Vickers hardness of each of the first electrode layer and the second electrode layer. The semiconductor device according to any one of claims 1 to 24.

26. the first electrode layer and the second electrode layer are made of aluminum or an aluminum alloy; The first protective layer and the second protective layer are made of titanium nitride. The semiconductor device according to claim 25.

27. The first connection member is an aluminum wire that is wedge bonded to the electrode pad. The semiconductor device according to any one of claims 1 to 26.

28. The diameter of the aluminum wire is 300 μm or more and 400 μm or less.

28. The semiconductor device according to claim 27.

29. The first connection member is a copper wire that is wedge bonded to the electrode pad. The semiconductor device according to any one of claims 1 to 6.

30. The on-resistance of the semiconductor device is 30 mΩ or less. The semiconductor device according to any one of claims 1 to 29.

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