Method for fabricating semiconductor-on-insulator structures for high frequency applications - Patents.com

Abstract

The present invention relates to a method for fabricating a semiconductor-on-insulator structure (10), comprising the steps of: providing an FD-SOI substrate (1) having, from its base to its top, an electrical resistivity between 500 Ω.cm and 30 kΩ.cm, an interstitial oxygen content (Oi) between 20 and 40 ppma, and successively comprising a monocrystalline substrate (2) with N-type or P-type doping, an electrically insulating layer (3) with a thickness between 20 nm and 400 nm, and a monocrystalline layer (4) with P-type doping, and heat-treating the FD-SOI substrate (1) at a temperature of 1175°C or higher for a time of 1 hour or more to form a PN junction (5) in the substrate. The present invention also relates to such a semiconductor-on-insulator structure.

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor-on-insulator structure, in particular for high frequency applications, and also to a semiconductor-on-insulator structure obtained by implementing this method. [Background technology]

[0002] A semiconductor-on-insulator structure is a multi-layer structure that includes a substrate, typically formed from silicon, an electrically insulating layer, typically an oxide layer such as a silicon oxide layer, disposed on the substrate, and a semiconductor layer, typically a silicon layer, disposed on the insulating layer.

[0003] Such structures are called "semiconductor-on-insulator" structures (SeOI), especially when the semiconductor material is silicon, "silicon-on-insulator" (SOI).

[0004] Among the existing SOI structures, a structure called "fully depleted silicon-on-insulator" (FD-SOI) structure is commonly used for digital applications. The FD-SOI structure is characterized by the presence of a thin oxide layer disposed on a silicon support substrate and a very thin semiconductor layer disposed on the oxide layer, called the SOI layer.

[0005] The oxide layer is located between the substrate and the SOI layer, in which case the oxide layer is called "buried" and referred to as "BOX" for "buried oxide".

[0006] The SOI layer allows the implementation of a conductive channel in the FD-SOI structure.

[0007] Due to the thin and uniform thickness of the BOX and SOI layers, there is no need to dope the conduction channel, and therefore the structure can operate in a fully depleted mode.

[0008] The FD-SOI structure has improved electrostatic characteristics compared to a structure without the BOX layer, which reduces the parasitic capacitance between the source and drain and also allows any electron leakage from the conduction channel to the substrate to be significantly reduced by restricting the flow of electrons in the conduction channel, thereby reducing any current loss and improving the performance capabilities of the structure.

[0009] Although FD-SOI structures are suitable for radio frequency (RF) applications, they nevertheless suffer from electrical losses in the substrate.

[0010] To compensate for these electrical losses and improve the RF performance capabilities, it is known to use substrates of a particularly high electrical resistivity, SOI type, commonly referred to as "HR substrates" (High Resistivity Substrates), which are advantageously combined with a charge trapping layer (or "trap rich layer").

[0011] However, this type of substrate is not compatible with the use of transistors with a threshold voltage that needs to be controlled via a backside gate (back bias voltage). In fact, the presence of this layer containing trapped charges prevents back bias (application of a potential difference to the back surface).

[0012] The scientific publication entitled "Low-loss Si substrates enhanced using buried PN junctions for RF applications" (M. Rack, L. Nyssens, and JP. Raskin, IEEE Electron Device Letters, vol. 40, Issue 5) describes the formation of PN junctions laterally disposed under an electrically insulating layer of a substrate for high frequency applications.

[0013] Lateral is understood to mean that two P-doped and N-doped regions, respectively, are located at the same depth in the substrate and the junction between said regions is approximately perpendicular to the main surface of the substrate. Such a junction is obtained by implanting phosphorus throughout the substrate for N-type doping, followed by local implantation of boron through a mask to form the P-doped regions, followed by a heat treatment to activate the dopants.

[0014] Although doped semiconductors are good conductors, the junctions pass very little current, thus preventing the propagation of parasitic electric fields.

[0015] One drawback resulting from the lateral arrangement of the PN junction as described in the scientific publication is that it requires a lithography step to form a mask and two implantation steps, which results in significant additional costs. Summary of the Invention

[0016] The object of the present invention is to propose a method for manufacturing a semiconductor-on-insulator structure that makes it possible to overcome the aforementioned drawbacks.

[0017] The object of the present invention is to propose such a manufacturing method for producing FD-SOI structures exhibiting good high frequency performance capabilities.

[0018] To this end, the present invention provides a method for fabricating a semiconductor-on-insulator structure, comprising the steps of: From its base to its top, a monocrystalline semiconductor substrate having an electrical resistivity in the range of 500 Ω.cm to 30 kΩ.cm and an interstitial oxygen content in the range of 20 to 40 ppma and having a first P-type or N-type doping; an electrically insulating layer having a thickness in the range of 20 nm to 400 nm; a single-crystal semiconductor layer having a P-type doping; providing an FD-SOI substrate having a continuous Heat treating the FD-SOI substrate at a temperature of 1175° C. or higher for a time period of 1 hour or more, Diffusion of a P-type dopant from the single crystal semiconductor layer through an electrically insulating layer in the substrate; forming a thermal donor by precipitation of interstitial oxygen in said substrate, if the substrate is P-type doped; forming a PN junction in the single crystal semiconductor substrate at a depth determined relative to the electrically insulating layer; forming a first N-type doped region in the substrate extending between a base of the substrate and the PN junction and a second P-type doped region located between the first region and the electrically insulating layer; We propose a method including the following:

[0019] The primary technique for measuring interstitial oxygen in the silicon of semiconductor substrates is infrared absorption using Fourier transform infrared (FTIR) spectroscopy.

[0020] This FTIR measurement is based on the absorption coefficient α OX The interstitial oxygen concentration is calculated by the absorption coefficient α OX Based on the above, the calculations are performed according to the method described in particular in the article entitled "Study of Oxygen Precipitation in Heavily Doped Silicon" (1989), Graupner, Robert Kurt, Dissertations and Theses, Paper 1218.

[0021] According to this method, 1 cm 3 Number of atoms per cm (at / cm 3 The oxygen concentration as a function of the total number of atoms present in parts per million (ppma) is known as the absorption coefficient α OX is obtained by multiplying by a conversion factor.

[0022] The oxygen concentrations referred to in this invention (old ppma) are obtained using the first of four conversion factors shown in the list below, referred to as "old ASTM" (American Society for Testing and Materials), expressed as ppma:

[0023] Old ASTM ppma=9.63α OX (ASTM F121-79) atoms / cm 3 =4.81×10 17 α OX New ASTM ppma=4.9α OX (ASTM F121-83) atoms / cm 3 =2.45×10 17 α OX JEIDA ppma=6.1α OX atoms / cm 3 =3.03×10 17 α OX IOC-88 ppma=6.28α OX atoms / cm 3 =3.14×10 17 α OX According to other aspects, the process of the invention has the following distinct features, taken alone or according to their technically conceivable combinations:

[0024] The single crystal substrate is formed from silicon and / or the single crystal layer is a silicon layer.

[0025] The FD-SOI substrate is a donor substrate comprising a monocrystalline semiconductor layer having a P-type doping and a weakened zone located in the monocrystalline silicon layer defining the layer to be transferred; a single crystal semiconductor receiving substrate having an electrical resistivity in the range of 500 Ω.cm to 30 kΩ.cm, an interstitial oxygen content in the range of 20 to 40 ppma, and P-type or N-type doping; and bonding the donor substrate to a receiving substrate using an electrically insulating layer having a thickness in the range of 20 nm to 400 nm; Pulling the donor substrate away along the embrittlement zone to form a FD-SOI substrate. The method is obtained by transferring a layer of a donor substrate onto a receiving substrate according to

[0026] The FD-SOI substrate is a donor substrate comprising a monocrystalline semiconductor layer having a P-type doping; a single crystal semiconductor receiving substrate having an electrical resistivity in the range of 500 Ω.cm to 30 kΩ.cm, an interstitial oxygen content in the range of 20 to 40 ppma, and P-type or N-type doping; and bonding the donor substrate to a receiving substrate using an electrically insulating layer having a thickness in the range of 20 nm to 400 nm; thinning the donor substrate from a surface opposite to the receiving substrate to form a transferred layer to obtain a FD-SOI substrate; The method is obtained by transferring a layer of a donor substrate onto a receiving substrate according to

[0027] Atomic species are implanted into the donor substrate to create an embrittlement zone and define the transferred layer.

[0028] The single crystal layers of the recipient substrate and the donor substrate are P-doped with boron.

[0029] A PN junction is formed at a depth ranging from 1 μm to 5 μm from the electrical insulating layer.

[0030] The electrically insulating layer comprises a silicon oxide layer.

[0031] The present invention also relates to a semiconductor-on-insulator structure directly obtained by carrying out the manufacturing method described above, the semiconductor-on-insulator structure having, from its base to its top end: It has an electrical resistivity in the range of 500 Ω.cm to 30 kΩ.cm and an interstitial oxygen content in the range of 20 to 40 ppma, a first region with N-type doping; a second region disposed on the first region with a P-type doping, the second region being separated from the first region by a PN junction; A single crystal semiconductor substrate comprising: An electrical insulating layer; a monocrystalline semiconductor layer having a P-type doping; The present invention relates to a semiconductor-on-insulator structure comprising:

[0032] According to other aspects, the structure of the invention has the following distinct features, taken alone or according to their technically conceivable combinations:

[0033] The single crystal semiconductor layer is P-doped with boron.

[0034] The PN junction is located at a depth in the range of 1 μm to 5 μm from the electrical insulating layer.

[0035] The electrically insulating layer comprises a silicon oxide layer.

[0036] The single crystal substrate is formed from silicon and / or the single crystal layer is a silicon layer.

[0037] Further advantages and features of the present invention will become apparent on reading the following description, given by way of illustrative and non-limiting example, in connection with the attached figures, in which: [Brief description of the drawings]

[0038] [Figure 1] FIG. 1 is a diagram of an FD-SOI substrate. [Diagram 2] FIG. 1 is a diagram of a semiconductor-on-insulator structure with a PN junction according to the present invention. [Diagram 3] FIG. 1 illustrates the reversal of doping in a portion of a high resistivity single crystal substrate. [Figure 4] FIG. 1 illustrates the diffusion of dopants from a single crystalline layer through an underlying electrically insulating layer. [Figure 5A] FIG. 2 illustrates the formation of an embrittlement zone by implanting atomic species into a donor substrate according to a first embodiment. [Figure 5B] FIG. 2 illustrates bonding of a donor substrate to a receiving substrate according to a first embodiment. [Figure 5C] 2A-2D show detachment of a donor substrate along the embrittlement zone and transfer of a layer from the donor substrate to a receiving substrate according to a first embodiment; [Figure 6A] FIG. 10 illustrates bonding of a donor substrate to a receiving substrate according to a second embodiment. [Figure 6B] FIG. 1 illustrates thinning of a donor substrate from the surface opposite to a recipient substrate to form a transferred layer. [Figure 7] 1 is a graph showing gain HD2 for a semiconductor-on-insulator structure with and without a PN junction in a substrate with high electrical resistivity. [Figure 8] 1 is a graph showing gain S21 for a semiconductor-on-insulator structure with and without a PN junction in a high resistivity substrate. [Figure 9] 1 is a graph showing the resistivity of semiconductor-on-insulator structures with and without PN junctions in a high resistivity substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] The present invention relates to a method for fabricating a semiconductor-on-insulator structure and to such a structure.

[0040] The manufacturing method of the invention makes it possible to produce semiconductor-on-insulator structures with PN junctions, endowing said structures with good high frequency properties, and doing so in a simple and inexpensive manner.

[0041] An FD-SOI substrate, shown diagrammatically in FIG. 1 using the reference numeral 1, is first provided, which comprises successively from its base to its top end a monocrystalline semiconductor substrate 2, an electrically insulating layer 3 and a monocrystalline semiconductor layer 4.

[0042] The single crystal substrate 2 is a substrate with high electrical resistivity, and therefore has an electrical resistivity in the range of 500 Ω.cm to 30 kΩ.cm.

[0043] The single crystal substrate 2 is also an oxygen-rich substrate and therefore has an interstitial oxygen content (Oi) in the range of 20-40 ppma. The oxygen is trapped in the structure of the single crystal substrate, more specifically in the gaps located between the grains of the material forming the single crystal substrate, and is therefore referred to as "interstitial oxygen".

[0044] Single crystal substrates with high electrical resistivity and high amount of interstitial oxygen are also called HR HiOi (a combination of the acronyms "high resistivity" and "high oxygen") substrates.

[0045] The single crystal substrate is preferably formed from silicon.

[0046] The single crystal substrate may have a P-type or N-type doping.

[0047] In the case of N-type doping, the monocrystalline substrate 2 is preferably doped with phosphorus, more preferably it is made of phosphorus doped silicon.

[0048] In the case of P-type doping, the monocrystalline substrate 2 is preferably doped with boron, more preferably the monocrystalline substrate is made of boron doped silicon.

[0049] The thickness of the electrically insulating layer 3, also referred to as a BOX layer because it is located between the underlying single crystal substrate 2 and the overlying single crystal layer 4, is in the range of 20 nm to 400 nm.

[0050] The electrically insulating layer 3 preferably comprises a silicon oxide layer.

[0051] The monocrystalline layer 3 has a P-type doping.

[0052] The monocrystalline layer is preferably a silicon layer.

[0053] According to the method of the present invention, the FD-SOI substrate is subjected to a heat treatment at a temperature of 1175° C. or more for a time period of 1 hour or more.

[0054] During said heat treatment, a PN junction, indicated with reference numeral 5, is formed in the monocrystalline substrate 2 at a determined depth relative to the electrically insulating layer 3, as shown in FIG.

[0055] More specifically, the heat treatment causes the following phenomena.

[0056] On the one hand, the P-type dopants in the single crystal layer diffuse through the electrically insulating layer into the single crystal substrate in regions of the substrate adjacent to the electrically insulating layer.

[0057] On the other hand, if the monocrystalline substrate is P-doped, the doping type of the monocrystalline substrate 2 is inverted.

[0058] The combination of these two phenomena creates a region 6 in the substrate, called the first region, which extends from the base of the monocrystalline substrate to the PN junction and is N-doped due to a doping type reversal. The PN junction then marks the boundary between the first region 6 and the remaining region 7 of the monocrystalline substrate, called the second region, which extends from the PN junction to the electrically insulating layer 3 and remains P-doped, the diffusion of P-type dopants in this second region compensating for the doping type reversal.

[0059] When the single crystal substrate is N-doped, the aforementioned phenomenon of diffusing the P-type dopant in the second region occurs. However, the phenomenon of inverting the doping type does not occur. As a result, the first region remains N-doped.

[0060] Regardless of the initial type of doping of the single crystal substrate, upon completion of the heat treatment, the single crystal substrate comprises a PN junction separating a first N-type doped region (located adjacent the base of the substrate) and a second P-type doped region (located adjacent the electrically insulating layer).

[0061] A PN junction can be formed due to three functions: P doping of the single crystal layer 4. Heat treatment temperatures above 1175°C for periods of time greater than 1 hour. In the case of a P-type doped single crystal substrate, a high interstitial oxygen concentration in said single crystal substrate 2 .

[0062] The presence of the PN junction coupled with the high electrical resistivity of the crystalline substrate 2, in the range of 500 Ω.cm to 30 kΩ.cm, allows for a structure to be obtained that exhibits very good high frequency properties. These properties are explained throughout the remainder of this specification. By adjusting these three features, the formation of the PN junction can be controlled, and in particular the depth of the PN junction in the single crystal substrate 2 from the electrically insulating layer 3 can be controlled.

[0063] For example, the parameters of the method, such as the three aforementioned features, are adjusted to form a PN junction at a depth ranging from 1 μm to 5 μm from the electrically insulating layer.

[0064] In the case of a P-type monocrystalline substrate, the heat treatment causes the precipitation of interstitial oxygen present in the monocrystalline substrate 2, resulting in the formation of sulfur oxides S with an excess charge for doping the material of the monocrystalline substrate. x O y The formation of a thermal donor reverses the doping. This first phenomenon is shown diagrammatically in Figure 3, which uses an upwards vertical arrow 8 to indicate the doping of the material of the single crystal substrate by the thermal donor.

[0065] Furthermore, regardless of whether the single crystal substrate is N-type or P-type doped, the heat treatment will cause dopants in the single crystal layer 4, such as boron, to diffuse through a sufficiently thin electrically insulating layer 3 into the single crystal substrate 2; these dopants can also be used to control the formation of the PN junction, and in particular the depth of the PN junction in the single crystal substrate from the electrically insulating layer. This second phenomenon is shown diagrammatically in Figure 4, which uses a downwards pointing vertical arrow 9 to indicate the diffusion of dopants through the electrically insulating layer.

[0066] This second phenomenon combines with the first phenomenon in the case of a P-type doped single crystal substrate to result in the formation of a first region of an N-doped substrate and a second P-doped region located between the first region and the electrically insulating layer shown in the semiconductor-on-insulator structure 10 of FIG.

[0067] The method of the present invention offers the advantage that the three aforementioned features allow these two phenomena to occur without the need for further processing steps. In particular, unlike the lateral PN junction described in the aforementioned paper by M. Rack et al., forming the PN junction in the thickness of the substrate in the present invention does not require any local implantation of dopants or a mask to be deposited on the substrate.

[0068] According to a preferred embodiment, the FD-SOI substrate is obtained by transferring a layer of a donor substrate onto a recipient substrate.

[0069] According to a first alternative of this embodiment shown in FIGS. 5A, 5B and 5C, as shown in FIG. 5A, a monocrystalline layer 21, preferably P A donor substrate 20 is provided comprising a silicon layer with type doping and an embrittled zone 23 located in a monocrystalline layer 24 defining the layer to be transferred.

[0070] The monocrystalline layer 24 to be transferred is preferably a silicon layer.

[0071] The single crystal receiving substrate 30, preferably formed from silicon, is also provided with an electrical resistivity in the range of 500 Ω.cm to 30 kΩ.cm, an interstitial oxygen content (Oi) in the range of 20 to 40 ppma, and P-type or N-type doping.

[0072] 5B, the donor substrate 20 is then bonded onto the receiving substrate 30 by an electrically insulating layer 22 having a thickness in the range of 20 nm to 400 nm. At this time, the electrically insulating layer 22 is located between the donor substrate 20 and the receiving substrate 30.

[0073] The electrically insulating layer 22 can originate from the donor substrate or from the receiving substrate, ie, can be initially located on the donor substrate or on the receiving substrate prior to bonding.

[0074] Referring to FIG. 5C, the donor substrate 20 is then pulled apart along the embrittlement zone 23 to obtain a FD-SOI substrate.

[0075] The layer 24 is preferably transferred from the donor substrate 20 to the recipient substrate 30 according to the Smart Cut™ method, in which an embrittlement zone 23 is formed by implanting atomic species, such as hydrogen and / or helium atoms, into the donor substrate, and then the donor substrate is pulled away along said embrittlement zone.

[0076] According to a second alternative of this embodiment, illustrated in Figures 6A and 6B, a donor substrate 20 is provided, comprising a monocrystalline semiconductor layer 21, preferably a silicon layer, with P-type doping.

[0077] The single crystal layer 21 is preferably a silicon layer.

[0078] The single crystal receiving substrate 30, preferably formed from silicon, is also provided with an electrical resistivity in the range of 500 Ω.cm to 30 kΩ.cm, an interstitial oxygen content (Oi) in the range of 20 to 40 ppma, and P-type or N-type doping.

[0079] 6A, the donor substrate 20 is then bonded onto the receiving substrate 30 by an electrically insulating layer 22 having a thickness in the range of 20 nm to 400 nm. At this time, the electrically insulating layer 22 is located between the donor substrate 20 and the receiving substrate 30.

[0080] The electrically insulating layer 22 may originate from the donor substrate or the receiving substrate, ie, may be initially located on the donor substrate or on the receiving substrate prior to bonding.

[0081] Referring to FIG. 6B, the donor substrate 20 is then thinned from its surface opposite the receiving substrate to form a transferred layer 24 to obtain the FD-SOI substrate 1.

[0082] The good high frequency properties of the semiconductor-on-insulator structure obtained by the above described method are illustrated in connection with FIGS.

[0083] FIG. 7 is a graph showing the gain HD2 (dBm) for semiconductor-on-insulator structures with and without PN junctions in a high resistivity substrate.

[0084] The gain HD2 corresponds to the second harmonic measured at a frequency of 900 MHz.

[0085] More specifically, HD2 is a harmonic generated by the substrate that may interfere with the operation of a high frequency device with a structure according to the present invention. The weaker the HD2, the more insulating the substrate. HD2 is measured over a coplanar line with the input and output points. At the input point, the power P in (dBm), the power P out is measured and this power is resolved into several harmonics including, in particular, HD1, which corresponds to the power measured at the output approximately equal to the input power, and HD2, which corresponds to the harmonics generated by the substrate.

[0086] According to the graph of Fig. 7, the gain HD2 obtained for the structure with a PN junction (curve C1) is less than the gain HD2 obtained for the structure without a PN junction (curve C2). This downward offset of curve C2 with respect to curve C1 corresponds to a loss of about 10 dBm.

[0087] For this reason, a high resistivity substrate having a structure with a PN junction has higher electrical insulation than a substrate having a structure without a PN junction.

[0088] FIG. 8 is a graph showing gain S21 (dB) as a function of frequency (Hz) for semiconductor-on-insulator structures with and without PN junctions.

[0089] The gain S21 corresponds to a crosstalk or noise measurement (called "crosstalk") and reflects the ability of any component to communicate through the substrate relative to other components, and thus represents a function of the isolation performance of the substrate.

[0090] 8, a reduction between 1e+3 Hz and 1e+8 Hz is observed in the gain S21 obtained for a structure with a PN junction (curve C3) compared to the gain S21 obtained for a junction without a PN structure (curve C4). This reduction in curve C4 compared to curve C3 corresponds to a reduced noise.

[0091] FIG. 9 is a graph showing resistivity R (ohm.cm) as a function of frequency (Hz) for semiconductor-on-insulator structures with and without PN junctions on a highly resistive substrate.

[0092] According to the graph of Figure 9, the resistivity obtained for the structure with a PN junction (curve C5) is greater than that obtained for the structure without a PN junction (curve C6). This downward offset of curve C5 compared to curve C6 corresponds to a loss of approximately 1200 ohm.cm.

[0093] This confirms the fact that a highly resistive substrate for a structure with a PN junction is more electrically insulating than a substrate for a structure without a PN junction.

[0094] Thus, the graphs of Figures 7, 8 and 9 show that the high frequency performance capabilities of the inventive semiconductor-on-insulator structure including a PN junction are significantly improved compared to the high frequency performance capabilities of a structure without a PN junction.

Claims

1. A method for manufacturing a semiconductor-on-insulator structure (10), comprising the steps of: A step of preparing an FD-SOI substrate (1), A monocrystalline semiconductor substrate (2) having an electrical resistivity in the range of 500 Ω.cm to 30 kΩ.cm and an interstitial oxygen content (Oi) in the range of 20 to 40 old ppma and having a first P-type or N-type doping; an electrically insulating layer (3) having a thickness in the range of 20 nm to 400 nm; a monocrystalline semiconductor layer (4) having a P-type doping; continuously from a base portion of the FD-SOI substrate (1) to an upper end of the FD-SOI substrate (1); A step of heat treating the FD-SOI substrate (1) at a temperature of 1175° C. or higher for a period of 1 hour or more, By diffusing a P-type dopant from the single crystal semiconductor layer (4) into the single crystal semiconductor substrate (2) through the electrical insulating layer (3), forming a heat donor by precipitation of the interstitial oxygen in the single crystal semiconductor substrate (2) when the single crystal semiconductor substrate (2) has a P-type doping, forming a PN junction (5) in the single crystal semiconductor substrate (2) at a depth determined relative to the electrically insulating layer (3); forming in said monocrystalline semiconductor substrate (2) a first region (6) having an N-type doping extending between said base of said monocrystalline semiconductor substrate (2) and a P-N junction, and a second P-doped region (7) located between said first region (6) and said electrically insulating layer (3); The method includes:

2. 2. The method of claim 1, wherein the monocrystalline semiconductor substrate (2) is made of silicon and / or the monocrystalline semiconductor layer (4) is a silicon layer.

3. The FD-SOI substrate (1), a donor substrate (20) comprising a monocrystalline semiconductor layer (21) with P-type doping and a weakened zone (23) located in said monocrystalline semiconductor layer (21) defining a layer (24) to be transferred; a single crystal semiconductor receiving substrate (30) having an electrical resistivity in the range of 500 Ω.cm to 30 kΩ.cm, an interstitial oxygen content (Oi) in the range of 20 to 40 old ppma, and a first P-type or N-type doping; and bonding the donor substrate (20) to the receiving substrate (30) using an electrically insulating layer (22) having a thickness in the range of 20 nm to 400 nm; Pulling away the donor substrate (20) along the embrittlement zone (23) to form the FD-SOI substrate (1); 3. The method according to claim 1 or 2, wherein the layer (24) of the donor substrate (20) is obtained by transferring the layer (24) onto the receiving substrate (30) according to

4. The FD-SOI substrate (1), a donor substrate (20) comprising a monocrystalline semiconductor layer (21) having a P-type doping; a receiving substrate (30) having an electrical resistivity in the range of 500 Ω.cm to 30 kΩ.cm, an interstitial oxygen content (Oi) in the range of 20 to 40 old ppma, and a P-type or N-type doping; and bonding the donor substrate (20) to the receiving substrate (30) using an electrically insulating layer (22) having a thickness in the range of 20 nm to 400 nm; thinning the donor substrate (20) from the surface opposite the receiving substrate (30) to form a layer (24) to obtain the FD-SOI substrate (1); 3. The method according to claim 1 or 2, wherein the layer (24) of the donor substrate (20) is obtained by transferring the layer (24) onto the receiving substrate (30) according to

5. 4. The method of claim 3, wherein the embrittlement zone (23) is formed by implanting atomic species into the donor substrate (20) to define the layer (24) to be transferred.

6. The method according to any one of claims 3 to 5, wherein the receiving substrate (30) and the monocrystalline semiconductor layer (21) of the donor substrate are P-doped with boron.

7. The method according to any one of the preceding claims, wherein the PN junction (5) is formed at a depth in the range of 1 μm to 5 μm from the electrically insulating layer (3).

8. The method according to any one of the preceding claims, wherein the electrically insulating layer (3) comprises a silicon oxide layer.

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