Integrated circuit die with in-chip heat sink

Abstract

Methods and apparatus, as well as electronic devices and chip packages having the integrated circuit die, and methods for manufacturing the chip packages, are provided that include an integrated circuit die 114, 116 with an in-chip heat sink 112. In one example, the integrated circuit die 114, 116 has an in-chip heat sink 112 that isolates high heat-generating integrated circuit devices from other integrated circuit devices disposed within the die 114, 116. The in-chip heat sink 112 provides a highly conductive thermal path from the interior of the die 114, 116 to at least one exposed die surface.

Description

[Technical field]

[0001] background Field of Disclosure Examples of the present disclosure generally relate to integrated circuit (IC) dies having in-chip heat sinks, as well as packages and methods for manufacturing the same. [Background technology]

[0002] 2. Description of Related Art Electronic devices such as tablets, computers, copiers, digital cameras, smartphones, control systems, and automated teller machines may use electronic components that utilize chip packaging, especially for increased functionality and component density. Traditional chip packaging methods may use multiple integrated circuit (IC) dies mounted on a single organic substrate. The dies may contain memory, logic, or other solid-state circuitry.

[0003] In many instances, at least one solid state circuit disposed within a die generates a significant amount of heat. This can be problematic in that the generated heat is transferred laterally to neighboring solid state circuits within the chip package that cannot tolerate additional heat. This problem is exacerbated when the die containing the heat generating circuitry is stacked below one or more other dies, isolating the die containing the heat generating circuitry from an external heat sink and making it difficult to transfer heat outside the package. This heat transfer limitation reduces design freedom, and thermal budgets along with IC die selection and location can limit power consumption, thereby unnecessarily limiting the performance of the chip package.

[0004] Therefore, there is a need for IC dies with improved thermal transfer performance, as well as packages and methods for manufacturing the same. Summary of the Invention [Means for solving the problem]

[0005] overview In one example, an integrated circuit die is provided that includes a die body, a first circuit, a second circuit, and an in-chip heat sink. The die body includes an upper surface and a lower surface, the lower surface having a plurality of bond pads for establishing electrical connections with circuitry within the die body. The first circuit is disposed on the die body and electrically coupled to at least one of the plurality of bond pads. The first circuit is configured to operate at a first temperature. The second circuit is disposed on the die body and electrically coupled to at least one of the plurality of bond pads. The second circuit is configured to operate at a second temperature that is lower than the first temperature. The in-chip heat sink has a ring shape and a direction that extends between the upper surface and the lower surface of the die body. The in-chip heat sink separates the first circuit from the second circuit.

[0006] In another example, an integrated circuit chip package is provided that includes a package substrate, a first integrated circuit (IC) die, and a second IC die. The first IC die is coupled to a top side of the package substrate by a first solder connection. The first IC die includes a die body, a first circuit, a second circuit, and an in-chip heat sink. The die body includes a top surface and a bottom surface, the bottom surface having a plurality of bond pads for establishing an electrical connection with the circuitry within the die body. The first circuit is disposed on the die body and electrically coupled to at least one of the plurality of bond pads. The first circuit is configured to operate at a first temperature. The second circuit is disposed on the die body and electrically coupled to at least one of the plurality of bond pads. The second circuit is configured to operate at a second temperature that is lower than the first temperature. The in-chip heat sink has a ring shape and a direction extending between the top surface and the bottom surface of the die body. The in-chip heat sink separates the first circuit from the second circuit.

[0007] In yet another example, an integrated circuit package is provided that includes a package substrate, a first integrated circuit die, and a second integrated circuit die. The package substrate has a top side and a bottom side. The first integrated circuit die has a first in-chip heat sink. The second integrated circuit die has a second in-chip heat sink disposed on the top side of the package substrate and coupled to the first in-chip heat sink via one or more solder connections.

[0008] In yet another example, a method for forming an integrated circuit die is provided, the method comprising forming a first circuit in a die body of the IC die, forming a second circuit in the die body of the IC die, and forming an in-chip heat sink in the die body of the IC die between the first circuit and the second circuit.

[0009] In yet another example, a method for forming an integrated circuit die is provided, the method comprising mounting a first IC die over a second IC die having an in-chip heat sink, mounting the stacked dies on a package substrate, bonding one or more of a stiffener, a cover, and an external heat sink to the package substrate upon which the dies are stacked to form a chip package, mounting the chip package to a printed circuit board, and mounting an optional heat sink to a bottom surface of the printed circuit board.

[0010] In a manner in which the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the implementations briefly outlined above may be provided by reference to examples, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical examples of the present disclosure and should not be considered as limiting its scope, as other equally effective examples of the present disclosure may be recognized. [Brief description of the drawings]

[0011] [Figure 1]1 is a schematic front view of an exemplary electronic device having an integrated chip package including multiple IC dies, at least one of which has an in-chip heat sink. [Diagram 2] 2 is a cross-sectional view of one of the IC dies shown in FIG. 1 through an in-chip heat sink. [Diagram 3] 3 is a schematic partial cross-sectional view of the IC die taken along section line 3-3 shown in FIG. 2, showing a portion of the in-chip heat sink. [Figure 4] 1 is another partial schematic cross-sectional view of an IC die showing a portion of an in-chip heat sink disposed adjacent to a dummy island. [Diagram 5] 2 is a schematic cross-sectional view of a portion of the electronic device of FIG. 1 illustrating conductive connections between in-chip heat sinks disposed on IC dies stacked within an integrated chip package of the electronic device. [Figure 6] FIG. 1 is a flow diagram of a method for manufacturing an integrated circuit die having an in-chip heat sink. [Figure 7] FIG. 1 is a flow diagram for manufacturing an integrated circuit chip package having stacked dies with interconnected in-chip heat sinks. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements common to the figures, and it is believed that elements of one example may be usefully incorporated in other examples.

[0013] Detailed Description Examples of the present disclosure generally provide an integrated circuit (IC) die with an in-chip heat sink, as well as a package and method for manufacturing the same. The in-chip heat sink isolates an integrated circuit device that generates high heat from other integrated circuit devices disposed within the same die, substantially reducing the amount of lateral heat transfer between devices disposed within the die. In this manner, an integrated circuit device that generates high heat does not thermally contaminate nearby integrated circuit devices, allowing the nearby integrated circuit devices to operate more efficiently. Furthermore, the thermal isolation provided by the in-chip heat sink allows the nearby devices to consume more power with reduced risk of overheating, resulting in improved performance and increased design freedom. Furthermore, the in-chip heat sink increases heat transfer to the outside of the die, resulting in better die performance at lower operating temperatures.

[0014] In some examples, an integrated circuit package is provided with stacked IC dies, at least one of which has an in-chip heat sink. The in-chip heat sink facilitates efficient transfer of heat to the exterior of the package, allowing greater freedom in die selection within the package. Furthermore, the in-chip heat sink is particularly useful for removing heat from one die that is spatially separated from the heat sink by routing heat from the die through the in-chip heat sink of an adjacent die, making it practical to use high power dies anywhere within the package. This allows for increased package design freedom while desirably increasing performance without the use of an external, expensive die external heat sink device.

[0015] Advantageously, in-chip heat sinks can be incorporated into IC dies using conventional semiconductor manufacturing techniques, and in some instances can be manufactured using metal layers already used in the die, thus with little impact on manufacturing costs.

[0016] Therefore, an in-chip heat sink advantageously improves thermal management of heat generated within the die, resulting in better device performance over a wider range of operating conditions, at little cost, and with reduced manufacturing complexity.

[0017] 1, there is shown a schematic diagram of an exemplary electronic device 100. The electronic device 100 comprises an integrated chip package 110 disposed on a printed circuit board (PCB) 102. The electronic device 100 may be part of a computer, tablet, cell phone, smartphone, consumer electronics, control system, automated teller machine, programmable logic controller, printer, copier, digital camera, television, monitor, stereo, radio, radar, or other solid state device that utilizes and has the chip package 110 disposed herein.

[0018] Chip package 110 includes at least one integrated circuit (IC) die 114 disposed on a package substrate 122. One or more additional IC dies 116 may be stacked on and coupled to IC die 114. Although only one other IC die 116 is shown stacked on IC die 114 in FIG. 1, any reasonable number of other IC dies 116 may be stacked on IC 114 within chip package 110. Although package substrate 122 is shown as a single element, package substrate 122 may include an interposer for mounting dies 114, 116.

[0019] At least one of the IC dies 114, 116 includes one or more in-chip heat sinks 112, as described further below. The in-chip heat sinks 112 provide efficient heat transfer from the interior of the die to at least one exterior surface.

[0020] The chip package 110 may also include a cover 104, a stiffener 106, and an external heat sink 108. The stiffener 106 is mounted on the package substrate 122 to maintain the flatness of the package substrate 122. The cover 104 is disposed over the topmost die within the package substrate 122 to provide more surface area for dissipating heat from the dies 114, 116 while helping to maintain the dimensional stability of the package 110. The heat sink 108 is mounted on the cover 104 on the side of the cover 104 opposite the dies 114, 116.

[0021] The die 114 includes a die body 124 on which at least two integrated circuits (solid-state circuits) 130, 132 are formed. The first solid-state circuit 130 has circuitry that generates more heat during operation than the circuitry of the second solid-state circuit 132. For example, the first circuit 130 may consume more heat than the second circuit 132. In one example, the first circuit 130 is a processor circuit, while the second circuit 132 is a memory circuit. To prevent lateral heat transfer from the hot first circuit 130 to the cooler second circuit 132, an in-chip heat sink 112 is disposed therebetween. The in-chip heat sink 112 is typically a thermally conductive wall that extends between the top surface 136 and the bottom surface 138 of the die body 124. In one example, the in-chip heat sink 112 forms part of a highly conductive heat transfer path that is exposed through the top surface 136 of the die body 124. In another example, the in-chip heat sink 112 forms part of a highly conductive heat transfer path that is exposed through the bottom surface 138 of the die body 124. In another embodiment, the in-chip heat sink 112 extends from the bottom surface 138 to the top surface of the die body 124 to provide an efficient bidirectional heat transfer path from an interior region of the die 114 to the exterior surfaces 136, 138 of the die 114. The heat transfer path is highly conductive to heat moving through dielectric materials, including non-metallic portions of the die 114.

[0022] Additionally, because the in-chip heat sink 112 provides a highly conductive thermal path to one or more exposed surfaces of the die body 124, the in-chip heat sink 112 may also be beneficially used with circuitry of the same or similar power consumption so as to prevent the maximum operating temperature of the IC die from being exceeded.

[0023] The circuits 130, 132 of the die 114 are coupled to exposed contact pads on the top 136 and bottom 138 of the die body 124 by interconnect circuitry 134, such as vias and traces, formed in the metal layer that comprises the die 114. The interconnect circuitry 134 may optionally pass laterally through the in-chip heat sink 112. Solder connections 140 electrically and mechanically connect the pads exposed on the bottom 138 of the die 114, and the interconnect circuitry 134, to contact pads formed on the top 142 of the package substrate 122. Similarly, the solder connections 140 electrically and mechanically connect the pads exposed on the top 136 of the die 114, and the interconnect circuitry 134, to contact pads formed on the bottom 146 of an adjacent die 116 stacked above the die 114.

[0024] The contact pads formed on the top surface 142 of the package substrate 122 are connected to the conductors 148 of the package substrate 122. The conductors 148 of the package substrate 122 may be provided on the top surface 142 of the package substrate 122, within the package substrate 122, and / or through the package substrate 122. The conductors 148 of the package substrate 122 may be traces, printed traces, vias, and the like. In the example shown in FIG. 1, the conductors 148 extend through the package substrate 122 and are coupled to contact pads formed on the bottom surface 150 of the package substrate 122. The contact pads formed on the bottom surface 150 of the package substrate 122 are electrically and mechanically connected to contact pads formed on the top surface 152 of the PCB 102.

[0025] The contact pads formed on the top surface 152 of the PCB 102 are connected to the conductors 154 of the PCB 102. The conductors 154 of the PCB 102 may be provided on the top surface 152 of the PCB 102, within the PCB 102, and / or through the PCB 102. The conductors 154 of the package substrate 122 may be wires, printed traces, vias, and the like. In the example shown in FIG. 1, the conductors 154 extend through the PCB 102 and are coupled to contact pads formed on the bottom surface 156 of the PCB 102. The contact pads formed on the bottom surface 156 of the PCB 102 are electrically and mechanically connected to any heat sink 118 disposed on the bottom surface 156 of the PCB 102.

[0026] Die 116 is stacked on and in contact with die 114. Die 116 includes a die body 126 having a bottom surface 146 and a top surface 160. Contact pads exposed on bottom surface 146 of die 116 are electrically and mechanically coupled to contact pads exposed on top surface 136 of die 114.

[0027] The die body 126 includes one or more solid state circuits 162 formed therein, such as memory, logic or other solid state circuit devices. In the example shown in FIG. 1 , the circuits 162 are shown as circuits 130, 132. However, one or more, or even all, of the circuits 162 formed in the die body 126 may be the same power, lower power, or higher power than one of the circuits 130, 132 formed in the die 114. The circuits 130, 132 of the die 116 are coupled to conductor pads exposed on the bottom surface 146 and possibly the top surface 160 of the die 116 by interconnect circuitry 164, such as vias and traces, formed in a metal layer that includes the die body 126.

[0028] A thermal interface material (TIM) 166, such as thermally conductive grease, is disposed between the top surface 160 of the die 116 and the cover 104. The TIM 166 provides good communication between the die 116 and the cover 104 to efficiently transfer excess heat to the dies 114, 116 within the chip package 110 and away from the circuits 130, 132 to keep the circuits 130, 132 within a safe operating temperature range. An external heat sink 108 can optionally be mounted to the cover 104 to further transfer heat outside the package 110.

[0029] It is contemplated that some implementations of chip package 110 may not include cover 104 and / or heat sink 108. However, in examples of package 110 that use cover 104, stiffener 106 may optionally be coupled to cover 104.

[0030] The die 116 further includes one or more in-chip heat sinks 112 disposed within the die body 126. The in-chip heat sink 112 typically extends between the top surface 160 and the bottom surface 146 of the die 116 to provide an efficient heat transfer path from an interior region of the die body 126 to the exterior surfaces 160, 146 of the die 116. The in-chip heat sink 112 disposed through the die 116 provides an efficient heat transfer path for transferring heat from the die 114 through the die 116 to the cover 104. In one example, the in-chip heat sink 112 of the die 114 is connected to the in-chip heat sink 112 of the die 116 by a metallic or thermally conductive path, such as a metal interconnect circuit configuration and a solder connection between the dies 114, 116. In its most straightforward form, the in-chip heat sink 112 of the die 116 may be configured as a metal filled via. The in-chip heat sinks 112 used with the dies 114, 116 are described in more detail below.

[0031] 2 is a cross-sectional view of the IC die 114 shown in FIG. 1 through the in-chip heat sink 112. The in-chip heat sink 112 used with the die 116 may be similarly configured. As discussed above, the in-chip heat sink 112 provides a thermal barrier that isolates the hotter first circuit 130 from the cooler second circuit 132 to significantly reduce thermal contamination of the second circuit 132 by heat generated by the first circuit 130. Although the in-chip heat sink 112 is shown isolating one high power first circuit 130 from one low power second circuit 132, the in-chip heat sink 112 may isolate one or more high power circuits 130 from one or more low power second circuits 132. It is contemplated that more than one in-chip heat sink 112 may be used with a die.

[0032] The in-chip heat sink 112 may simply be a wall between the IC circuits 130, 132, or may partially or completely surround the high power first circuit 130. In the example shown in FIG. 2, the in-chip heat sink 112 has a ring shape that completely surrounds the high power first circuit 130. In other examples, the in-chip heat sink 112 may surround the high power first circuit 130 discontinuously, for example, but leave space for the interconnect circuitry 134 to pass through the in-chip heat sink 112 without shorting. In yet other embodiments, the in-chip heat sink 112 may be coupled to power or ground circuitry with the die 114. In other examples, the in-chip heat sink 112 is floating with respect to power or ground and isolated from the signal transmission line connected to the first circuit 130 by the interconnect circuitry 134.

[0033] The in-chip heat sink 112 is typically formed by the metal layers that comprise the die 114. As such, the in-chip heat sink 112 may be fabricated from aluminum, copper, tungsten, titanium, tantalum or other suitable metals or similar thermally conductive materials. The metal layers that comprise the in-chip heat sink 112 are separated within the die 114 by dielectric layers.

[0034] 2, a single in-chip heat sink 112 is used to laterally separate and thermally isolate the IC circuits 130, 132. However, multiple in-chip heat sinks 112 may be used within a single die body 124 to separate one or more hotter circuits 130 from cooler circuits 132. Conversely, multiple in-chip heat sinks 112 may be used within a single die body 124 to separate one or more cooler circuits 132 from one or more hotter circuits 130.

[0035] Figure 3 is a partial schematic cross-sectional view of IC die 114 taken along section line 3-3 shown in Figure 2, showing a portion of in-chip heat sink 112. In-chip heat sink 112 is shown in Figure 3 as extending between top surface 136 and bottom surface 138 of die 124, with edges of heat sink 112 exposed at exterior surfaces 136, 138 of die 114.

[0036] The in-chip heat sink 112 typically consists of vias 302 coupling stacked traces 304 that form a thermally conductive wall within the die body 124. The top via 302 may couple the traces 304 to a contact pad (not shown) exposed on the top surface 136 of the die 114. Similarly, the bottom via 302 may couple the traces 304 to a contact pad (not shown) exposed on the bottom surface 138 of the die 114. The vias 302 and traces 304 that make up the in-chip heat sink 112 are fabricated from metal layers separated by dielectric layers within the die body 124, making the in-chip heat sink 112 thermally conductive to the dielectric material that comprises the die body 124.

[0037] 3, the in-chip heat sink 112 (i.e., traces 304 or vias 302) includes at least one metal layer that also includes the first circuit 130. Although the in-chip heat sink 112 is shown extending between the exterior surfaces 136, 138 of the die body 124 to provide a bidirectional heat transfer path, the heat sink 112 may alternatively extend from only one of the exterior surfaces 136, 138 of the die 114 and the metal layer shared with the first circuit 130 to provide a unidirectional heat transfer path (i.e., to only one of the surfaces 136, 138).

[0038] During operation, a significant amount of heat generated by the first circuit 130 is preferentially transferred through the in-chip heat sink 112 to one or both of the exterior surfaces 136, 138 of the die 114, and is therefore effectively prevented from reaching the second circuit 132. As such, the in-chip heat sink 112 can provide better thermal control of both the IC circuits 130, 132, thereby allowing more high performance circuitry to be used within the die 114 without overheating or compromising performance.

[0039] Because the in-chip heat sink 112 effectively improves the performance of the single die 114, the benefits of the in-chip heat sink 112 can be realized within the single die 114 without even further packaging, such as in the chip package 110 described herein. However, the in-chip heat sink 112 is particularly useful in chip packages 110 having stacked dies.

[0040] 3 as a rectangle having four straight (e.g., linear) sides, the in-chip heatsink 112 may have other configurations, including other polygonal shapes, irregular shapes, or other desired shapes. Additionally, the portions of the in-chip heatsink 112 that include the "sides" of the rectangle or other planar shape may have non-linear configurations.

[0041] 4 is another partial schematic cross-sectional view of IC die 400 showing a portion of in-chip heat sink 112 disposed adjacent to dummy island 404. IC die 400 may be configured essentially the same as IC die 114 described above, except for the addition of dummy island 404, and may be used in place of either or both of IC dies 114, 116 of chip package 110.

[0042] The dummy islands 404 are not coupled to the circuitry of the circuits 130, 132 and are distributed within the die body 124 to provide the necessary balance of metallurgy to obtain good planarity and good tolerance control between layers. In a conventional IC die, the dummy islands are not interconnected. Here, the dummy islands 404 are connected by one or more vias 402 to improve vertical heat transfer within the die body 124. The vias 402 provide a thermal path with a high heat transfer rate that is used to transfer heat from the hot first circuit 130 toward at least one of the outer surfaces 136, 138 of the die 114. Although the dummy islands 404 interconnected by the vias 402 are shown on the hotter circuit side of the in-chip heat sink 112 in FIG. 4, the dummy islands 404 interconnected by the vias 402 may alternatively or additionally be provided on the cooler circuit side of the in-chip heat sink 112.

[0043] The heat sinking properties of the dummy islands 404 interconnected by the vias 402 may be increased by coupling one or more of the dummy islands 404 to the in-chip heat sink 112 by bridges 410 (shown by dashed lines). In this configuration, heat heatsinked by the dummy islands 404 is effectively transferred from the first circuitry 130 to the in-chip heat sink 112, and the heat is effectively transferred to the exterior surfaces 136, 138 of the die 114. Beneficially, the dummy islands 404 also significantly improve heat removal by transferring heat laterally from the circuitry 130 to the in-chip heat sink 112 more quickly than can occur through the dielectric material of the die body 124.

[0044] Alternatively, the dummy islands 404 may not be interconnected by vias 402 and one or more of the dummy islands 404 may be in direct contact with the in-chip heat sink 112 .

[0045] 5 is a partial schematic cross-sectional view of the electronic device 100 of FIG. 1 illustrating a solder connection 140 between in-chip heat sinks 112 disposed on IC dies 114, 116 stacked in an integrated chip package 110 of the electronic device 100. As shown in FIG. 5, the in-chip heat sink 112 formed on the die body 124 terminates at contact pads 502, 504 exposed on the outer surfaces 136, 138 of the die 114. Similarly, the in-chip heat sink 112 formed on the die body 126 terminates at contact pads 512, 514 exposed on the outer surfaces 146, 160 of the die 116. The dies 114, 116 are stacked in an orientation that aligns the contact pads 504 with the contact pads 512. The in-chip heat sinks 112 disposed on the IC dies 114, 116 are not necessarily vertically aligned with the pads 504, 512 via appropriate vias of the interconnect circuitry. In other words, the in-chip heat sinks 112 disposed on the IC dies 114, 116 may be laterally offset while still being thermally connected through the solder connections 140 and via interconnects within the dies 114, 116.

[0046] The contact pads 504, 512 are electrically and mechanically coupled using a solder connection 140. In one example, the solder connection 140 is comprised of solder. The solder connection 140 facilitates rapid and direct transfer of heat between the contact pads 504, 512 and, therefore, between the in-chip heat sinks 112 of the IC dies 114, 116. As such, heat generated by the first circuit 130 can be preferentially transferred from the die 114 through the heat sink 112 and into the adjacent stacked die 116 without transferring a significant amount of heat laterally to the second circuit 132 in the die 114.

[0047] In embodiments in which one or more further dies 116 are stacked on the die 116, solder connections 140 may be used between each of the adjacent dies 116, 116 so that heat can be easily transferred through the neighboring dies 116, 116 and away from the die 114 that includes the heat-generating first circuit 130.

[0048] As discussed above, having a single die 114 that includes an in-chip heat sink 112 provides the important advantage of temperature control within the single die 114, even if no other heat transfer techniques are used. However, without limitation, one or more of the other thermal enhancements discussed above may be used in conjunction with the in-chip heat sink 112 to further improve temperature control within a package 110 having stacked dies 114, 116.

[0049] One such temperature control enhancement is to route heat out via the underside 138 of the die 114. In such an example, the contact pads 502 may be coupled to the package substrate 122 via a solder connection 140. The solder connection 140 between the package substrate 122 and the die 114 provides thermal mass to the heat sink that is pulled away from the die 114 through the in-chip heat sink 112.

[0050] The package substrate 122 may include one or more metal layers, paths, or patterns suitable for acting as a heat sink. In such an embodiment, the solder connections 140 to the package substrate 122 may contact pads or other thermal conductors coupled to conductors 148 of the package substrate 122. The conductors 148 may have sufficient mass to act as a heat sink or may be used to transfer heat through the in-chip heat sink 112 and into the package substrate 122.

[0051] In other examples, the conductors 148 may be routed through or across the package substrate 122 to the optional stiffener 106. The stiffener 106 may be made of metal or other material with sufficient thermal mass to act as a heat sink for heat to be transferred from the die body 124, through the in-chip heat sink 112, into the package substrate 122, and then to the stiffener 106.

[0052] In other examples, the conductors 148 may be routed through the package substrate 122 to an optional heat sink 118 disposed below the PCB 102, or to other heat transfer devices such as heat pipes, coolers or canisters, particularly of phase change material.

[0053] Another temperature control enhancement is to transfer heat out via the top surface 136 of the die 114. In such an example, the contact pad 504 may be in contact with a contact pad 512 of the adjacent die 116, thereby drawing heat from the die 114 into the in-chip heat sink 112 of the die 116.

[0054] Another temperature control enhancement is to route heat out of the in-chip heat sink 112 of the die 116 through the top surface 160 of the die 116. In such an example, the top surface 160 of the die 116 may be in contact with a TIM 166 that draws heat away from the die body 126. Additionally, the in-chip heat sink 112 of the die 116 may optionally be in contact with the TIM 166 to improve the efficiency of heat transfer from the die 116. The TIM 166 is in contact with the cover 104, which functions as a heat sink. Optionally, an external heat sink 108, particularly other heat transfer devices such as phase change material heat pipes, coolers or canisters, may be mounted on the cover 104 to further increase the efficiency of heat transfer from the in-chip heat sink 112 of the die 116 and ultimately from the in-chip heat sink 112 of the die 114 and the first circuit 130.

[0055] 5, the dummy islands 404 may be used in conjunction with any of the above examples. The dummy islands 404 may be interconnected by vias 402. Alternatively or in addition to the dummy islands 404 being interconnected by vias 402, one or more dummy islands 404 may be interconnected to the in-chip heat sink 112 by bridges 410. In the above examples, at least a portion of the dummy islands 404 are provided on the same side of the in-chip heat sink 112 as the first circuit 130.

[0056] 6 is a flow diagram of a method 600 for manufacturing a die having an IC die 114 and an in-chip heat sink, such as the in-chip heat sink 112 described above. The method 600 begins, in operation 602, by forming a first circuit 130 on the die body 124 of the IC die 114. The first circuit 130 can be formed by sequentially depositing and patterning metal and conductive layers using semiconductor fabrication techniques. The first circuit 130 may be configured as a processor or other similar circuitry.

[0057] In operation 604, a second circuit 132 is formed in the die body 124 of the IC die 114. The first circuit 130 is capable of generating a greater amount of heat during operation than the second circuit 132. For example, the second circuit 132 may be configured as a memory or other circuit that has less power during operation relative to the first circuit 130. The second circuit 132 is formed by sequentially depositing and patterning metal and conductive layers using semiconductor fabrication techniques.

[0058] In operation 606, an in-chip heat sink 112 is formed in the die body 124 of the IC die 114 between the first circuit 130 and the second circuit 132. The in-chip heat sink 112 is formed between the top and bottom surfaces 136, 138. The in-chip heat sink 112 is formed by connecting traces 304 formed in a metal layer of the die body 124 with vias 302. The traces 304 and vias 302 are stacked in the die body 124 to form a conductive wall between the circuits 130, 132. The in-chip heat sink 112 may be formed in a pattern that circumscribes one of the IC circuits 130, 132, e.g., the hotter first circuit 130. The conductive traces 304 and vias 302 may be formed using conventional metallization techniques or other suitable techniques. The conductive traces 304 and vias 302 may be stacked such that ends of the in-chip heat sink 112 are exposed at the outer surfaces 136, 138 of the die body 124.

[0059] 7 is a flow diagram of a method 700 for manufacturing an integrated chip package having stacked dies with interconnected in-chip heat sinks. The method 700 begins at operation 702 by mounting an IC die 116 on an IC die 114 having an in-chip heat sink 112. The IC die 116 may be mounted on the IC die 114 using a number of solder connections 140. As described above, the in-chip heat sink 112 extends between the top surface 136 and the bottom surface 138 of the die body 124 of the IC die 114.

[0060] In one example, when IC die 116 is mounted on IC die 114, the in-chip heat sink 112 of IC 114 is connected to the in-chip heat sink 112 of IC 116 via one or more solder connections 140. In this manner, heat is effectively transferred from IC 114 through top surface 136 and away from second circuit 132 disposed within IC 114 that may be adversely affected by heat generated by nearby first circuit 130 disposed within die body 124.

[0061] In operation 704, the stacked dies 114, 116 are mounted to a package substrate 122. A bottom surface 138 of the IC die 114 may be mounted onto the package substrate 122 using a number of solder connections 140.

[0062] In one example, the in-chip heat sink 112 of the IC die 114 is coupled to conductors 148 disposed in or on the package substrate 122 through one or more solder connections 140. The solder connections 140 couple the conductors 148 of the package substrate 122 to the in-chip heat sink 112 of the IC die 114 to provide an efficient thermal transfer path for heat generated by the first circuit 130 through the underside 138 of the die body 124 and out into the package substrate 122.

[0063] In operation 706, one or more of the stiffener 106, cover 104, and external heat sink 108 can be coupled to the package substrate 122 with the dies 114, 116 stacked thereon to form the chip package 110. If the cover 104 is used, a TIM 166 is provided between the cover 104 and the top surface 160 of the IC die 116.

[0064] At operation 708, the chip package 110 is mounted on the PCB 102. In one example, the chip package 110 is coupled to conductors 154 disposed in or on the PCB 102 through one or more solder connections 140. The solder connections 140 couple the conductors 154 of the PCB 102 to the conductors 148 of the package substrate 122 and to the in-chip heat sink 112 of the IC die 114. In this manner, an efficient heat transfer path for heat generated by the first circuit 130 is formed through the underside 138 of the die body 124, through the package substrate 122 and into the conductors 154 of the PCB 102.

[0065] In operation 710, an optional heat sink 118 can be mounted on the bottom surface 156 of the PCB 102. The heat sink 118 is coupled by the conductors 154 of the PCB 102 to the in-chip heat sink 112 of the IC die 114 via the thermal transfer path described above. Advantageously, the heat sink 118 thus provides a heat sink for heat generated by the first circuit 130.

[0066] Thus, an in-chip heat sink has been described that isolates a high heat generating integrated circuit from other integrated circuits disposed within the same die, substantially reducing the amount of lateral heat transfer within the die that can thermally contaminate nearby IC devices. The in-chip heat sink effectively draws heat away from the high heat generating integrated circuit, effectively enabling high power devices that can become excessively hot or thermally contaminate other circuits on the die. Thus, the in-chip heat sink can improve performance and expand design options compared to conventional packages. Additionally, the in-chip heat sink increases heat transfer from the die, enabling good die performance at lower operating temperatures without resorting to expensive cooling solutions.

[0067] In one example, an integrated circuit die is provided that includes a die body having an upper surface and a lower surface, the lower surface having a plurality of bond pads for establishing electrical connections with circuitry within the die body, a first circuit disposed within the die body and electrically coupled to at least one of the plurality of bond pads and configured to operate at a first temperature, a second circuit disposed within the die body and electrically coupled to at least one of the plurality of bond pads and configured to operate at a second temperature that is lower than the first temperature, and an in-chip heat sink having a ring shape and an orientation extending between the upper surface and the lower surface, and isolating the first circuit from the second circuit.

[0068] In some such integrated circuit dies, the in-chip heat sink includes vias and traces formed in a metal layer of the die body.

[0069] In one such integrated circuit die, the in-chip heat sink includes at least one metal layer that is also disposed on the first circuit.

[0070] In one such integrated circuit die, an in-chip heat sink circumscribes the first circuit.

[0071] In one such integrated circuit die, the interconnect circuitry coupled to the first circuit passes through an in-chip heat sink.

[0072] Such an integrated circuit die may further include a first dummy metal island disposed on the die body adjacent to the first circuit and separated from the second circuit by an in-chip heat sink, a second dummy metal island, and a via connecting the first dummy metal island to the second dummy metal island.

[0073] In one such integrated circuit die, the first dummy metal island is in direct contact with the in-chip heat sink.

[0074] In some such integrated circuit die, the top surface of the die body further includes a plurality of metal filled recesses.

[0075] In one such integrated circuit die, at least one of the metal-filled recesses overlies or is in direct contact with an in-chip heat sink.

[0076] In some such integrated circuit die, at least one of the plurality of contact pads is in direct contact with the in-chip heat sink.

[0077] In another example, an integrated circuit chip package may be provided, which may include a package substrate having a top side and a bottom side, a first integrated circuit (IC) die coupled to the top side of the package substrate by a first solder connection, the first IC die including a die body having a top side and a bottom side, the bottom side having a plurality of bond pads for establishing an electrical connection with circuitry in the die body, a first circuit disposed on the die body and electrically coupled to at least one of the plurality of bond pads and configured to operate at a first temperature, a second circuit disposed on the die body and electrically coupled to at least one of the plurality of bond pads and configured to operate at a second temperature lower than the first temperature, and an in-chip heat sink having a ring shape and an orientation extending between the top side and the bottom side, isolating the first circuit from the second circuit.

[0078] One such integrated circuit chip package may further include a heat sink coupled to the bottom side of the package substrate, conductively coupled by vias formed through the package substrate, and in contact with the in-chip heat sink through some of the first solder connections.

[0079] One such integrated circuit chip package may further include a second IC die coupled to the first IC by second solder connections and having an in-chip heat sink coupled to the first IC by a portion of the second solder connections.

[0080] In one such integrated circuit chip package, the in-chip heat sink of the second IC die extends to the top surface of the second IC die.

[0081] In some such integrated circuit chip packages, the in-chip heat sink of the second IC die is electrically floating.

[0082] One such integrated circuit chip package may further include a cover mounted over a top surface of the second IC die, a thermal interface material disposed in contact with the top surface of the second die and contact pads on the cover that terminate an in-chip heat sink, and a heat sink disposed on the cover.

[0083] In yet another example, an integrated circuit chip package may be provided that may include a package substrate having a top side and a bottom side, a first integrated circuit die having a first in-chip heat sink, and a second integrated circuit die having a second in-chip heat sink disposed on the top side of the package substrate and coupled to the first in-chip heat sink via one or more solder connections.

[0084] In one such integrated circuit chip package, the second integrated circuit die further includes a first circuit disposed on the second integrated circuit die and configured to operate at a first temperature, and a second circuit disposed on the second integrated circuit die, separated from the first circuit by a second in-chip heat sink, and configured to operate at a second temperature lower than the first temperature.

[0085] In one such integrated circuit chip package, a first in-chip heat sink is electrically floating and defines a portion of a highly conductive heat transfer path outward through a top surface of a second IC die.

[0086] In some such integrated circuit packages, a second in-chip heat sink is coupled by solder connections to the package substrate that forms a highly conductive heat transfer path to the outside through the underside of the second IC die.

[0087] While the above is directed to examples of the present implementations, other and still other examples of the present disclosure may be devised without departing from the basic scope, which is determined by the following claims.

Claims

1. 1. An integrated circuit die comprising: a die body having an upper surface and a lower surface, the lower surface having a plurality of bond pads for establishing electrical connections with circuitry within the die body; a first circuit disposed on the die body, electrically coupled to at least one of the plurality of bond pads, and configured to operate at a first temperature; a second circuit disposed on the die body, electrically coupled to at least one of the plurality of bond pads, and configured to operate at a second temperature lower than the first temperature; and an in-chip heat sink having a ring shape surrounding the first circuit and a direction extending between the upper surface and the lower surface, the in-chip heat sink isolating the first circuit from the second circuit; the in-chip heat sink extends through the die body; The integrated circuit die, wherein the first circuit and the second circuit are solid state circuits formed within the die body.

2. The integrated circuit die of claim 1 , wherein the in-chip heat sink comprises vias and traces formed in a metal layer of the die body.

3. The integrated circuit die of claim 2 , wherein the in-chip heat sink includes at least one metal layer that is also disposed on the first circuit.

4. The integrated circuit die of claim 1 , wherein the in-chip heat sink circumscribes the first circuit.

5. The integrated circuit die of claim 1 , wherein interconnect circuitry coupled to said first circuit passes through said in-chip heat sink.

6. a first dummy metal island disposed on the die body adjacent to the first circuit and separated from the second circuit by the in-chip heat sink; a second dummy metal island; 2. The integrated circuit die of claim 1, further comprising: a via connecting said first dummy metal island to said second dummy metal island.

7. The integrated circuit die of claim 6 , wherein the first dummy metal island is in direct contact with the in-chip heat sink.

8. The integrated circuit die of claim 1 , wherein said top surface of said die body further comprises a plurality of metal filled recesses.

9. The integrated circuit die of claim 8 , wherein at least one of the plurality of metal filled recesses is above or in direct contact with the in-chip heat sink.

10. The integrated circuit die of claim 1 , wherein at least one of said bond pads is in direct contact with said in-chip heat sink.

11. 1. An integrated circuit chip package comprising: a package substrate having a top side and a bottom side; a first integrated circuit (IC) die coupled to the top side of the package substrate by first solder connections, the first IC die comprising: a die body having an upper surface and a lower surface, the lower surface having a plurality of bond pads for establishing electrical connections with circuitry within the die body; a first circuit disposed on the die body, electrically coupled to at least one of the plurality of bond pads, and configured to operate at a first temperature; a second circuit disposed on the die body, electrically coupled to at least one of the plurality of bond pads, and configured to operate at a second temperature lower than the first temperature; and an in-chip heat sink having a ring shape surrounding the first circuit and a direction extending between the upper surface and the lower surface, the in-chip heat sink isolating the first circuit from the second circuit; the in-chip heat sink extends through the die body; the first circuit and the second circuit are solid state circuits formed within the die body.

12. 12. The integrated circuit chip package of claim 11 further comprising a heat sink coupled to the bottom side of the package substrate and conductively coupled by vias formed through the package substrate and in contact with the in-chip heat sink through some of the first solder connections.

13. 12. The integrated circuit chip package of claim 11, further comprising a second IC die coupled to the first IC die by second solder connections and having an in-chip heat sink coupled to the first IC die by a portion of the second solder connections.

14. 14. The integrated circuit chip package of claim 13, wherein the in-chip heat sink of the second IC die extends to a top surface of the second IC die.

15. a cover mounted over a top surface of the second IC die; a thermally conductive material disposed in contact with the top surface of the second IC die and with contact pads on the cover that terminate the in-chip heat sink; 14. The integrated circuit chip package of claim 13, further comprising a heat sink disposed on said cover.

Images