Dead time generation circuit, method and switch circuit

Abstract

To provide a dead time generating circuit, a method, and a switching circuit.SOLUTION: The dead time generating circuit is provided with: a comparator 201 which compares drain voltage of a low-side switch with predetermined reference voltage; and a D flip-flop 202 which receives a comparison signal to be output by the comparator 201 and outputs an on-pulse signal of the low-side switch as a trigger clock signal. An output signal of the D flip-flop 202 is counted by an up-down counter 203, and an instruction signal is output. A time constant circuit 204 generates dead time based on the instruction signal. Thus, the dead time can be generated so as to be adaptively adjusted. Therefore, simple structure and low cost can be achieved, a switching loss of a switching circuit can be decreased, conversion efficiency can be improved, and processing time can be shortened to respond to fast switching operation.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] Embodiments of the present invention relate to the field of switching control techniques, particularly with respect to dead time generation circuits, methods, and switch circuits. [Background technology]

[0002] The switch circuit may include a high-side switch (e.g., a high-side controlled power element) and a low-side switch (e.g., a low-side synchronous rectifier element). When the low-side switch is turned off (OFF), the high-side switch is temporarily in an on (ON) state, and when the high-side switch is turned off, the low-side switch is temporarily in an on state. However, in general, the high-side switch and the low-side switch cannot be turned on at the same time, and it is necessary to provide a dead time (DT) between the off / on of the high-side switch and the low-side switch. For fixed dead time control, the dead time may be too long or too short, which is detrimental to the power supply conversion efficiency. Therefore, currently, a scheme has emerged that can adaptively adjust the dead time, i.e., dynamically control the dead time, and bring the power supply higher conversion efficiency. It should be noted that the above technical background introduction is provided to clearly and completely explain the technical solutions of the present application and to facilitate the understanding of persons skilled in the art. However, it is not believed that the above technical solutions are well known to persons skilled in the art just because these inventions are described in the background technology section of the present application. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Chinese Utility Model Patent No. CN20846233U Summary of the Invention [Problem to be solved by the invention]

[0004] However, the conventional dead time adaptive adjustment method is based on analog circuits, and in order to support faster switching operations, it is necessary to take into account the characteristics specific to analog circuits, such as amplifier gain, capacitance value of capacitor, amount of controlled current, and amount of buffer delay generated by dead time.

[0005] The present invention has been made in consideration of the above problems, and has an object to provide a circuit, a method, and a switch circuit that can solve the problems and further improve the dead time adaptive adjustment. [Means for solving the problem]

[0006] According to one aspect of an embodiment of the present invention, there is provided a dead time generation circuit for generating a dead time between a high-side switch and a low-side switch, the dead time generation circuit including: a comparator for comparing a drain voltage of the low-side switch with a predetermined reference voltage; a D flip-flop for receiving a comparison signal output from the comparator and outputting the comparison signal using a turn-on pulse signal of the low-side switch as a trigger clock signal; an up / down counter for counting up or down based on the comparison signal output from the D flip-flop and outputting an instruction signal; and a time constant circuit for generating the dead time based on the instruction signal. The up / down counter further uses the turn-on pulse signal of the low-side switch as a trigger clock signal, and the indication signal includes a multi-channel digital signal, and the multi-channel digital signal indicates whether a plurality of resistors in the time constant circuit are used. It is characterized by: According to another aspect of an embodiment of the present invention, there is provided a switch circuit including a high-side switch and a low-side switch, further including a dead time generation circuit as described above. According to another aspect of the present invention, A dead time generating method for generating a dead time between a high-side switch and a low-side switch in a dead time generating circuit including a comparator, a D flip-flop, an up / down counter, and a time constant circuit, the method comprising: a first step in which the comparator compares a drain voltage of the low-side switch with a predetermined reference voltage; a second step in which the comparator receives a comparison signal output from the D flip-flop and the comparator, and outputs the comparison signal using a turn-on pulse signal of the low-side switch as a trigger clock signal; a third step in which the up / down counter counts up or down based on the comparison signal and outputs an indication signal; and a fourth step in which the time constant circuit generates the dead time based on the indication signal, wherein in the third step, the up / down counter further uses the turn-on pulse signal of the low-side switch as a trigger clock signal, the indication signal includes a multi-channel digital signal, and the multi-channel digital signal indicates whether or not a plurality of resistors in the time constant circuit are used. It is characterized by: With reference to the following description and drawings, certain embodiments of the present application have been disclosed in detail and have specified the manner in which the principles of the present application may be employed. It should be understood that the embodiments of the present application are not limited in scope. The embodiments of the present application include many changes, modifications, and equivalents within the spirit and scope of the claims. Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments and may be combined with or substituted for features in the other embodiments. It should be emphasized that the term "including" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components. The drawings illustrate that elements and features described in one drawing or one embodiment of an embodiment of the invention can be associated with elements and features shown in one or more other drawings or embodiments, and in the accompanying drawings, like reference numerals may be used to indicate corresponding parts in the several drawings and to indicate corresponding components used in multiple embodiments. Effect of the Invention

[0007] One of the beneficial effects of the embodiment of the present invention is to compare the drain voltage of the low-side switch with a predetermined reference voltage, receive the comparison signal output from the comparator, output the on-pulse signal of the low-side switch as a trigger clock signal, count up or count down the comparison signal output from the D flip-flop, and output an indication signal. The dead time is generated based on the indication signal. This not only allows a better dead time to be generated and adaptively adjusted, but also reduces switching losses and improves conversion efficiency, has a simple structure, low cost, short processing time, and can accommodate high-speed switching operations. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram of a switching circuit according to one embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram showing an example of a dead time generating circuit according to an embodiment of the present invention. [Diagram 3]FIG. 3 is a schematic diagram of a time constant circuit according to one embodiment of the present invention. [Figure 4] FIG. 4 shows an example of a condition for increasing the dead time according to an embodiment of the present invention. [Diagram 5] FIG. 5 is a diagram showing an example of a condition for reducing the dead time according to the embodiment of the present invention. [Figure 6] FIG. 6 is a schematic diagram of the dead time generating method of the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The foregoing and other features of the present application will become apparent from the following description when taken in conjunction with the drawings. Although certain embodiments of the present application have been specifically disclosed in the specification and drawings, and the present application illustrates some embodiments to which the principles of the present application may be applied, it is to be understood that the present disclosure is not limited to the described embodiments, but rather, the present application includes all modifications, variations, and equivalents within the scope of the appended claims. In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish different elements from the designation, but do not represent the spatial arrangement or temporal order of these elements, and these elements should not be limited by these terms. The term "and / or" includes any or more combinations of the associated listed terms. The terms "comprise", "have", etc. refer to the presence of stated features, elements or components, but do not exclude the presence or addition of one or more other features, elements or components. In embodiments of the present invention, the singular number forms "one," "the," etc. include the plural forms and should generally be understood as "one type" unless the context explicitly indicates otherwise. Additionally, the term "based on" should be understood as "at least in part by...". The term "based on" should be understood as "based at least in part on...". In some embodiments of the present application, a Zero Voltage Switch (ZVS) is taken as an example for explanation, but the present application is not limited thereto and can be applied to other types of switching circuits. Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0010] (First embodiment) An embodiment of the application provides a switching circuit and a dead time generating circuit. 1 is a diagram of an example of a switching circuit according to an embodiment of the present invention, including a high-side switch 101, a low-side switch 102, a driver 103, and a dead time generating circuit 104. As shown in Fig. 1, the drain of the high-side switch 101 receives an input voltage Vin, the source of the low-side switch 102 is grounded, and the source of the high-side switch 101 and the drain of the low-side switch 102 are connected to output a voltage (for example, a voltage signal at the drain of the low-side switch 101 is Vsw) to a load. As shown in FIG. 1, a pulse width modulation (PWM) signal is input to a dead time generation circuit 104, which outputs control signals Ho and Lo, which are input to a driver 103, and the driver 103 outputs a control signal to the gate of the high side switch 101 (for example, a voltage signal at the gate of the high side switch 101 is Vg1) and outputs a control signal to the gate of the low side switch 102 (for example, a voltage signal at the gate of the low side switch 102 is Vg2), thereby controlling the high side switch 101 and the low side switch 102.

[0011] In the above-mentioned FIG. 1, only the switching circuit of the embodiment of the present invention is described in a schematic manner, but the present specification is not limited thereto. For example, the connection relationship between various modules or components can be appropriately adjusted, and further other modules or components can be added or some modules or components can be reduced. Those skilled in the art can appropriately modify the above content, and are not limited to the description of the above-mentioned FIG. 1.

[0012] 2 is an example of a dead time generation circuit according to an embodiment of the present application, in which the dead time generation circuit 104 generates a dead time between the high-side switch 101 and the low-side switch 102. As shown in Fig. 2, the dead time generation circuit 104 has a D flip-flop 202 that compares the drain voltage Vsw of the low-side switch 102 with a predetermined reference voltage V1, receives a comparison signal output from a comparator 201, and outputs an on-pulse signal (e.g., a gate voltage signal Vg2) of the low-side switch 102 as a trigger clock signal (CLK). The up / down counter 203 counts up / down based on the comparison signal output from the D flip-flop 202, outputs an instruction signal (represented by o3 to o0 in FIG. 2, for example), and has a time constant circuit 204 that generates a dead time based on the instruction signal.

[0013] Although the above-mentioned FIG. 2 only roughly describes the dead time generating circuit of the embodiment of the present application, the present specification is not limited thereto. For example, the connection relationship between various modules or components can be appropriately adjusted, and further other modules or components can be added, or some modules or components can be reduced. Those skilled in the art can appropriately modify the above contents, and are not limited to the description of the above-mentioned FIG. 2. In some embodiments, the predetermined reference voltage is 0 volts, although the application is not limited in this respect. In some embodiments, the time constant circuit 204 includes at least a capacitance and a resistance, and the time constant circuit 204 generates the dead time by an RC time constant formed by the capacitance and the resistance. For specific details regarding the RC circuit structure and the RC time constant, reference may be made to the related art, and the description thereof will be omitted here.

[0014] 3 is a schematic diagram of a time constant circuit according to an embodiment of the present invention, showing the case of some elements. As shown in FIG. 3, the time constant circuit 204 can include a high side section 2041 and a low side output section 2042, in which a high side input signal Hin is input to the high side and a high side output signal Ho is output, and a low side section 2042 can include a high side section 2041 and a low side output section 2042, in which a low side input signal Lin is input to the low side and a low side output signal Lo is output.

[0015] 3, the high side unit 2041 may include, for example, four resistors having different resistance values ​​(e.g., 8R, 4R, 2R, and R, respectively), each resistor 302 may be shorted to a corresponding switch 303, and one capacitor 301. In this way, in response to a signal command, the switch 303 having multiple switches is individually turned on (ON) or off (OFF), and multiple resistors 302 corresponding to the switches turned on among the switches 303 are shorted, and multiple resistors 302 corresponding to the switches turned off among the switches 303 have different resistance values, so that the overall resistance value of the RC circuit structure in the high side unit 2041 changes, and the RC time constant of the high side unit 2041 can be changed.

[0016] 3, the low-side unit 2042 may include, for example, four or more resistors 305 having different resistance values ​​(e.g., 8R, 4R, 2R, and R, respectively), each resistor 305 being shorted by a corresponding switch 306 and turned off (OFF) or on (ON) by an instruction signal from the counter 203, and one capacitor 304. In this way, the switch 306 having multiple switches is individually turned on (ON) or off (OFF) by an instruction from the signal, and multiple resistors 305 corresponding to the switches turned on among the switches 306 are shorted, and multiple resistors 305 corresponding to the switches turned off among the switches 306 have different resistance values, so that the overall resistance value of the RC circuit structure in the low-side unit 2042 changes, and the RC time constant of the low-side unit 2042 can be changed.

[0017] Here, the switches 303 and 306 are turned on and off synchronously, so that it is possible to generate and adjust a dead time between the high-side switch 101 and the low-side switch 102. In concrete implementation, the dead time is expressed by a time offset of the waveforms of the signals Ho and Lo, and the specific contents can be referred to the related art.

[0018] It should be noted that, although the above FIG. 3 only roughly describes the time constant circuit of the embodiment of the present application, the present application is not limited thereto. For example, the connection relationship between various modules or components can be appropriately adjusted, and further, other modules or components can be added, or some modules or components can be reduced. Those skilled in the art can appropriately modify the above content, and are not limited to the description of the above FIG. 3.

[0019] In some embodiments, as shown in FIG. 2, the up / down converter 203 includes a multiplexed digital signal that uses an on-pulse signal (e.g., a gate voltage signal Vg2) of the low-side switch 102 as a trigger clock signal (CLK) and controls multiple resistors in a time constant circuit. For example, as shown in Fig. 3, the up / down converter 203 may output a 4-bit digital signal (as shown by o3 to o0) and may count up or count down. For specific details of the up / down converter, reference may be made to related art.

[0020] In some embodiments, the dead time can be adjusted by changing the resistance value of the multiple resistor combination included in the time constant circuit 204 using an instruction signal to change the RC time constant formed by the capacitance and the multiple resistors.

[0021] FIG. 4 is a diagram showing an example of a condition for increasing the dead time according to an embodiment of the present invention. In some embodiments, when the drain voltage Vsw of the low-side switch 102 is greater than a reference voltage V1 (e.g., 0) (Vsw>0), the comparator 201 outputs a first signal (e.g., a low level), the up / down converter 203 counts down according to the first signal (e.g., a low level), and the time constant circuit 204 increases the resistance value according to the instruction signal to increase the dead time. Taking FIG. 3 as an example, Table 1 shows an example of dead time adjustment in the embodiment of the present application, where 0 indicates switch off (OFF) and 1 indicates switch on (ON).

[0022] [Table 1]

[0023] Assuming that the instruction signal is 1000 in the current state, in the RC circuit configuration of the high side unit 2041, the first switch of the switch 303 is on (the corresponding resistor 8R is shorted) and the other three switches are off (the corresponding resistors 4R, 2R, and R are used), so the composite resistance value is 4R+2R+R=7R. In the RC circuit configuration of the low side unit 2042, the first switch of the switch 306 is on (the corresponding resistor 8R is shorted) and the other three switches are off (the corresponding resistors 4R, 2R, and R are used), so the composite resistance value is 4R+2R+R=7R. For example, the up / down counter 203 counts down according to the first signal (e.g., low level), and when it goes from 1000 to 0111, for example, the combined resistance value becomes 8R, the resistance value increases, and therefore the dead time also increases. Furthermore, when the next trigger clock signal is received, if the first signal remains at low level, it is changed from 0111 to 0110. As a result, the combined resistance value becomes 9R, the resistance value increases, and the dead time also increases.

[0024] FIG. 5 is a diagram of an example of reducing the dead time according to an embodiment of the present invention. In some embodiments, the comparator 201 outputs a second signal (e.g., high level) when the drain voltage Vsw of the low-side switch 102 is smaller than a reference voltage (e.g., 0) (Vsw<0), the up / down counter 203 counts up according to the second signal (e.g., high level), and the time constant circuit 204 reduces the resistance value according to the instruction signal to reduce the dead time.

[0025] 3 and Table 1 as an example, assuming that the instruction signal is 1000 in the current state, in the RC circuit configuration of the high side unit 2041, the first switch of the switch 303 is on (the corresponding resistor 8R is shorted) and the other three switches are off (the corresponding resistors 4R, 2R, and R are used), so the composite resistance value is 4R+2R+R=7R. In the RC circuit configuration of the low side unit 2042, the first switch of the switch 306 is on (the corresponding resistor 8R is shorted) and the other three switches are off (the corresponding resistors 4R, 2R, and R are used), so the composite resistance value is 4R+2R+R=7R.

[0026] For example, the up / down counter 203 counts up according to the second signal (e.g., high level), and when it goes from 1000 to 1001, the combined resistance value becomes 6R, the resistance value decreases, and therefore the dead time also decreases. Furthermore, when the next trigger clock signal is received, if the second signal remains at high level, it changes from 1001 to 1010, the combined resistance value changes to 5R, and the dead time also decreases due to the decrease in the resistance value.

[0027] Also, the D flip-flop may reflect the output of the comparator to the up / down converter when the low-side switch is turned on. The up / down converter maintains the length of the dead time and adjusts the dead time according to the output of the D trigger, and the output value of the up / down converter is reflected in the dead time generation circuit. This simplifies the structure and increases the accuracy.

[0028] The above various embodiments have been described as examples of the embodiments of the present application, but the present application is not limited thereto, and appropriate modifications based on the above embodiments are also possible. For example, each of the above embodiments may be used alone, or one or more of the above embodiments may be combined.

[0029] According to the above embodiment, the drain voltage of the low-side switch is compared with a predetermined reference voltage, a comparison signal output from the comparator is received, an on-pulse signal of the low-side switch is output as a trigger clock signal, and an up / down counter counts up or down based on the comparison signal output from the D flip-flop, and an instruction signal is output to the time constant circuit. The time constant circuit generates a dead time based on the instruction signal. This makes it possible to adaptively adjust and generate a better dead time. Therefore, the structure is simple and the cost is low, and the switching loss of the switching circuit can be reduced and the conversion efficiency can be improved. In addition, the processing time can be shortened, so that high-speed switching operation can be supported.

[0030] Second Embodiment A dead time generating method for generating a dead time between a high-side switch and a low-side switch is also provided. The second embodiment corresponds to the dead time generating circuit in the first embodiment, and has the same content as the first embodiment, so it will be briefly described here.

[0031] FIG. 6 is a schematic diagram of a dead time generating method according to an embodiment of the present invention. As shown in FIG. 6, the dead time generating method includes: 601 compares the drain voltage of the low-side switch with a predetermined reference voltage; 602 includes a circuit that receives a comparison signal output by the comparator and outputs an on-pulse signal of a low-side switch as a trigger clock signal. 603 outputs a signal to instruct counting up or down according to the comparison signal; 604 generates the dead time according to the instruction signal.

[0032] It should be noted that the above-mentioned FIG. 6 has outlined an embodiment of the present application, but the present application is not limited thereto. For example, the execution order between each operation can be appropriately adjusted, and some other operations can be further added, or some operations can be reduced. Those skilled in the art can appropriately modify the above content, and are not limited to the description of the above-mentioned FIG. 6.

[0033] In some embodiments, the method further comprises adjusting the dead time by changing a resistance value of a plurality of resistor combinations that indicate the signal changes the time constant circuit and an RC time constant formed by the capacitance and the plurality of resistors.

[0034] The above-mentioned various embodiments are only examples of the embodiments of the present application, but the present specification is not limited thereto, and appropriate modifications are possible based on the above-mentioned various embodiments. For example, each of the above-mentioned embodiments may be used alone, or one or more of the above-mentioned embodiments may be combined.

[0035] The above embodiment clarifies that the drain voltage of the low-side switch is compared with a predetermined reference voltage, a comparison signal output from a comparator is received, and the D flip-flop outputs the comparison signal using the on-pulse signal of the low-side switch as a trigger clock signal, and the D flip-flop outputs an instruction signal to the up / down counter to add or subtract a count based on the received comparison signal. It has been shown that the time constant circuit generates a dead time based on the instruction signal. This not only allows a better dead time to be generated and adaptively adjusted, but also reduces switching losses and improves conversion efficiency, has a simple structure, low cost, and shortens processing time, making it possible to accommodate high-speed switching operations.

[0036] The above-mentioned apparatus and method of the embodiment of the present invention may be implemented by hardware or software. This specification relates to a computer-readable program that, when executed by a logical component, causes the logical component to realize the above-mentioned apparatus or component, or enables the logical component to realize the above-mentioned various methods or steps. This application also relates to a storage medium for storing the above-mentioned program, such as a hard disk, a magnetic disk, an optical disk, a DVD, a flash memory, etc.

[0037] The methods / apparatuses described in relation to the embodiments of the present invention may be embodied directly in hardware, as software modules executed by a processor, or a combination of the two. For example, one or more of the functional block diagrams shown in the figures and / or one or more combinations of the functional blocks may correspond to each software module of a computer program flow, and may also correspond to each hardware module. These software modules may correspond to each step shown in the figures. These hardware modules may be implemented by hardening these software modules using, for example, a field programmable gate array (FPGA).

[0038] The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. The storage medium may be coupled to the processor or may be a component of the processor such that the processor can read information from and write information to the storage medium. The processor and the storage medium may reside in an ASIC. The software module may be stored in a memory of a mobile terminal or in a memory card that can be inserted into the mobile terminal. For example, if a device such as a mobile terminal employs a large capacity MEGA-SIM card or a large capacity flash memory device, the software module may be stored in the MEGA-SIM card or the large capacity flash memory device.

[0039] One or more of the functional blocks and / or one or more combinations of the functional blocks illustrated in the accompanying drawings may be partitioned into a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, hardware components, or any suitable combination thereof, for performing the functions described herein. One or more of the functional blocks and / or one or more combinations of the functional blocks illustrated in the accompanying drawings may be realized as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in communication with a DSP, or other such configurations.

[0040] Although the present specification has been described in connection with the above specific embodiments, it should be clear to those skilled in the art that the scope of the present specification is not limited by these embodiments. Based on the spirit and principles of the present application, those skilled in the art can make various modifications and alterations to the present application, and these modifications and alterations are also within the scope of the present application. [Explanation of symbols]

[0041] 100 Switching Circuits 101 High Side Switch 102 Low Side Switch 103 Driver 104 Dead time generation circuit 201 Comparator 202 D Flip-Flop 203 Up / Down Counter 204 Time constant circuit 2041 High side part 2042 Low side section 301, 304 Capacitor 302, 305 Resistor 303, 306 Switch

Claims

1. A dead time generation circuit for generating a dead time between a high-side switch and a low-side switch, a comparator that compares a drain voltage of the low-side switch with a predetermined reference voltage; a D flip-flop that receives the comparison signal output from the comparator and outputs the comparison signal using a turn-on pulse signal of the low-side switch as a trigger clock signal; an up / down counter that counts up or down based on the comparison signal output from the D flip-flop and outputs an instruction signal; a time constant circuit that generates the dead time based on the instruction signal; Equipped with The up / down counter further uses the turn-on pulse signal of the low-side switch as a trigger clock signal, the instruction signal comprises a multi-channel digital signal; 11. A dead time generating circuit, comprising: a multi-channel digital signal that indicates whether or not a plurality of resistors in the time constant circuit are used.

2. the time constant circuit includes at least a capacitance and a resistance; 2. The dead time generating circuit according to claim 1, wherein the time constant circuit generates the dead time by an RC time constant formed by the capacitance and the resistance.

3. 3. The dead time generating circuit according to claim 2, wherein a resistance value synthesized by the plurality of resistors included in the time constant circuit is changed by the instruction signal, and the dead time is adjusted by changing the RC time constant formed by the capacitance and the plurality of resistors.

4. 4. The dead time generation circuit according to claim 3, wherein the comparator outputs a first signal when the drain voltage of the low-side switch is greater than the predetermined reference voltage, the up / down counter counts down based on the first signal, and the time constant circuit increases the dead time by increasing the resistance value based on the instruction signal.

5. 4. The dead time generation circuit according to claim 3, wherein the comparator outputs a second signal when the drain voltage of the low-side switch is smaller than the predetermined reference voltage, the up / down counter counts up based on the second signal, and the time constant circuit reduces the dead time by reducing the resistance value based on the instruction signal.

6. A switch circuit including a high-side switch and a low-side switch, the source of the high-side switch being connected to the drain of the low-side switch, A switch circuit further comprising the dead time generating circuit according to any one of claims 1 to 5.

7. A dead time generation method for generating a dead time between a high-side switch and a low-side switch in a dead time generation circuit including a comparator, a D flip-flop, an up / down counter, and a time constant circuit, comprising: A first step in which the comparator compares a drain voltage of the low-side switch with a predetermined reference voltage; a second step of receiving the comparison signal output from the D flip-flop and the comparator, and outputting the comparison signal using a turn-on pulse signal of the low-side switch as a trigger clock signal; a third step of the up / down counter counting up or down based on the comparison signal and outputting an indication signal; a fourth step in which the time constant circuit generates the dead time based on the instruction signal; a turn-on pulse signal of the low-side switch as a trigger clock signal, and the indication signal includes a multi-channel digital signal, each of the multi-channel digital signals indicating whether or not a plurality of resistors in the time constant circuit have been used.

8. The time constant circuit includes at least a capacitance and a resistance, 8. The dead time generating method according to claim 7, wherein in the fourth step, the time constant circuit generates the dead time by an RC time constant formed by the capacitance and the resistance.

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