Semiconductor device and package

Abstract

To provide a semiconductor device which can be downsized.SOLUTION: A semiconductor device includes: a conductive base substrate 11; a semiconductor chip 30 mounted on the base substrate and having a signal pad; a frame 12 configured to surround the semiconductor chip, to be mounted on the base substrate, and to include a step having an inner first upper surface 13b and an outer second upper surface 13a higher than the first upper surface in a plan view, in which a first conductor pattern 14b provided on the first upper surface is electrically connected to the base substrate; a capacitive component 40 mounted on the first conductor pattern; a signal terminal mounted on the second upper surface of the frame; a first bonding wire 25 configured to electrically connect the signal pad and an upper surface of the capacitive component; a second bonding wire 24 configured to electrically connect the upper surface of the capacitive component and the signal terminal; and a cover 18 configured to be joined to the second upper surface of the frame, and to seal the semiconductor chip in a space.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a package, for example, a semiconductor device and a package mounting a semiconductor chip and a capacitive component. [Background technology]

[0002] It is known that a semiconductor chip, a capacitive component and a frame are mounted on a base substrate, the pads on the semiconductor chip and the top surface of the capacitive component are connected by bonding wires, and the top surface of the capacitive component and a signal terminal on the frame are connected by bonding wires (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-530202 A Summary of the Invention [Problem to be solved by the invention]

[0004] In order to ensure the bonding strength between the base substrate and the frame, the width of the frame must be greater than a certain value, and therefore, if a semiconductor chip and a capacitive component are mounted inside the frame on the base substrate, the semiconductor device will become larger.

[0005] The present disclosure has been made in consideration of the above problems, and aims to achieve miniaturization. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a semiconductor device comprising: a conductive base substrate; a semiconductor chip mounted on the base substrate and having a signal pad; a frame body surrounding the semiconductor chip and mounted on the base substrate, the frame body having a step having an inner first upper surface and an outer second upper surface higher than the first upper surface in a planar view, the first conductor pattern provided on the first upper surface being electrically connected to the base substrate; a capacitive component mounted on the first conductor pattern; a signal terminal mounted on the second upper surface of the frame body; a first bonding wire electrically connecting the signal pad and the upper surface of the capacitive component; a second bonding wire electrically connecting the upper surface of the capacitive component and the signal terminal; and a lid joined to the second upper surface of the frame body and sealing the semiconductor chip in a gap.

[0007] One embodiment of the present disclosure is a package comprising: a base substrate that is conductive and has an area on which a semiconductor chip can be mounted; and a frame body that surrounds the semiconductor chip and is mounted on the base substrate, the frame body having a step having an inner first top surface and an outer second top surface higher than the first top surface in a planar view, the first top surface being electrically connected to the top surface of the base substrate, and the second top surface having an area on which a capacitive component can be mounted that is electrically isolated from the base substrate. Effect of the Invention

[0008] According to the present disclosure, miniaturization is possible. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA of FIG. [Diagram 3] FIG. 3 is an enlarged view of the semiconductor chip and the capacitive component of FIG. [Figure 4] FIG. 4 is a circuit diagram of the semiconductor device in accordance with the first embodiment. [Diagram 5] FIG. 5 is an enlarged cross-sectional view of the semiconductor device according to the first comparative example. [Figure 6] FIG. 6 is an enlarged cross-sectional view of a semiconductor device according to Comparative Example 2. As shown in FIG. [Figure 7] FIG. 7 is an enlarged cross-sectional view of a semiconductor device according to a first modification of the first embodiment. [Figure 8] FIG. 8 is an enlarged cross-sectional view of a semiconductor device according to a second modification of the first embodiment. [Figure 9] FIG. 9 is an enlarged cross-sectional view of a semiconductor device according to a third modification of the first embodiment. [Figure 10] FIG. 10 is an enlarged cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment. [Figure 11] FIG. 11 is a plan view of a semiconductor device according to a fifth modification of the first embodiment. [Figure 12] FIG. 12 is a plan view of a semiconductor device according to a sixth modified example of the first embodiment. [Figure 13] FIG. 13 is a plan view of a semiconductor device in accordance with a second embodiment. [Figure 14] FIG. 14 is an enlarged view of the vicinity of the semiconductor chip and the capacitive component in the second embodiment. [Figure 15] FIG. 15 is an enlarged cross-sectional view of a semiconductor device according to a first modification of the second embodiment. [Figure 16] FIG. 16 is an enlarged cross-sectional view of a semiconductor device according to a second modification of the second embodiment. [Figure 17] FIG. 17 is an enlarged cross-sectional view of a semiconductor device according to a third modification of the second embodiment. [Figure 18] FIG. 18 is an enlarged cross-sectional view of a semiconductor device according to a fourth modification of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device including a conductive base substrate, a semiconductor chip mounted on the base substrate and having a signal pad, a frame surrounding the semiconductor chip and mounted on the base substrate, the frame having a step having a first upper surface on the inside and a second upper surface on the outside higher than the first upper surface in a plan view, a first conductor pattern provided on the first upper surface electrically connected to the base substrate, a capacitive component mounted on the first conductor pattern, a signal terminal mounted on the second upper surface of the frame, a first bonding wire electrically connecting the signal pad and the upper surface of the capacitive component, a second bonding wire electrically connecting the upper surface of the capacitive component and the signal terminal, and a lid bonded to the second upper surface of the frame and sealing the semiconductor chip in a gap. This allows for miniaturization. (2) The second bonding wire is preferably bonded to the signal terminal. (3) It is preferable that the difference in height between the upper surface of the capacitive component and the upper surface of the signal terminal is smaller than the difference in thickness between the capacitive component and the signal terminal. (4) It is preferable that the lid has a side portion joined to the second upper surface of the frame body and an upper portion provided above the semiconductor chip, and that the side portion is joined to the upper surface of the signal terminal outside the point where the second bonding wire is joined to the signal terminal in a planar view. (5) It is preferable that the step has a third upper surface between the first upper surface and the second upper surface in a planar view, the third upper surface being higher than the first upper surface and lower than the second upper surface, a second conductor pattern electrically connected to the signal terminal is provided on the third upper surface, and the second bonding wire is connected to the signal terminal via the second conductor pattern. (6) It is preferable that the difference in height between the top surface of the capacitive component and the top surface of the second conductive pattern is smaller than the difference between the thickness of the capacitive component and the difference in height between the first top surface and the second top surface. (7) It is preferable that the lid has a side portion joined to the second top surface of the frame body and an upper portion provided above the semiconductor chip, and that the side portion is joined to the second top surface and not joined to the third top surface. (8) It is preferable that the semiconductor chip includes a transistor, and the signal pad is at least one of an input pad for inputting a high frequency signal to the transistor and an output pad for outputting a high frequency signal from the transistor. (9) It is preferable that the first conductive pattern and the base substrate are electrically connected by a through electrode that penetrates the frame or by another conductive layer provided on the inner side surface of the frame. (10) One embodiment of the present disclosure is a package comprising: a base substrate that is conductive and has an area on which a semiconductor chip can be mounted; and a frame body that surrounds the semiconductor chip and is mounted on the base substrate, the frame body having a step having a first top surface on the inside in a planar view and a second top surface on the outside that is higher than the first top surface, the first top surface being electrically connected to the top surface of the base substrate, and the second top surface having an area on which a capacitive component can be mounted that is electrically isolated from the base substrate.

[0011] [Details of the embodiment of the present disclosure] Specific examples of semiconductor devices and packages according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] [Example 1] Fig. 1 is a plan view of a semiconductor device according to a first embodiment. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. Fig. 1 is a plan view with a lid 18 removed. The normal direction to the upper surface of a base substrate 11 is the Z direction, the direction from an input lead 22 to an output lead 20 is the X direction, and the direction perpendicular to the X direction and the Z direction is the Y direction.

[0013] As shown in FIG. 1 and FIG. 2, in the semiconductor device 100 of the first embodiment, the package 10 mainly includes a base substrate 11, a frame 12, and a lid 18. The base substrate 11 is conductive, for example, a laminated substrate of copper and molybdenum. A reference potential such as a ground potential is supplied to the base substrate 11. The frame 12 and the lid 18 are dielectric layers made of resin or ceramic, for example, FR-4 (Flame Retardant Type 4). On the ±X side sides, the inner upper surface 13b of the frame 12 is lower than the outer upper surface 13a. A conductor pattern 14a is provided on the upper surface 13a, and a conductor pattern 14b is provided on the upper surface 13b. The conductor pattern 14b on the +X side is electrically connected to the base substrate 11 via a through electrode 16. That is, the conductor pattern 14b and the base substrate 11 are at approximately the same potential. The conductor pattern 14a is electrically isolated from the base substrate 11. The conductor patterns 14a, 14b and the through electrode 16 are metal layers such as gold or copper layers, for example, plated metal. An input lead 22 is mounted on the conductor pattern 14a on the -X side, and an output lead 20 is mounted on the conductor pattern 14b on the +X side. The input lead 22 and the output lead 20 are metal leads, for example, copper leads plated with gold. The base substrate 11 has an area on which a semiconductor chip 30 can be mounted, and the upper surface 13b of the thin film portion 12b of the frame 12 has an area on which a capacitive component 40 can be mounted.

[0014] A semiconductor chip 30 and a capacitive component 45 are mounted on a base substrate 11. The semiconductor chip 30 includes a semiconductor substrate 31, electrodes 32 and 33 provided on the upper surface of the semiconductor substrate 31, and an electrode 34 (see FIG. 3) formed on the lower surface of the semiconductor substrate 31. The electrodes 32, 33, and 34 are a gate electrode, a drain electrode, and a source electrode, respectively, and the electrodes 32 and 33 are signal pads such as an input pad and an output pad, respectively. The electrodes 32, 33, and 34 are metal layers such as a gold layer. The electrode 34 is electrically connected to the base substrate 11 and short-circuited. The capacitive component 45 includes a dielectric substrate 46, an electrode 47 provided on the upper surface of the dielectric substrate 46, and an electrode 48 provided on the lower surface of the dielectric substrate 46. The electrode 48 is electrically connected to the base substrate 11 and short-circuited. The capacitive component 40 is mounted on a conductor pattern 14b provided on the upper surface 13b. The capacitive component 40 includes a dielectric substrate 41, an electrode 42 provided on the upper surface of the dielectric substrate 41, and an electrode 43 provided on the lower surface of the dielectric substrate 41. The electrode 43 is electrically connected to and shorted to the base substrate 11 via the through electrode 16. The electrode 43 and the base substrate 11 are at the same potential. The dielectric substrates 41 and 46 are, for example, a high dielectric constant ceramic material having a relative dielectric constant of 30 or more, and the electrodes 42, 43, 47 and 48 are metal layers such as gold layers.

[0015] The bonding wire 24 electrically connects the output lead 20 to the electrode 42 of the capacitive component 40. The bonding wire 25 electrically connects the electrode 42 of the capacitive component 40 to the electrode 33 of the semiconductor chip 30. The bonding wire 26 electrically connects the electrode 32 of the semiconductor chip 30 to the electrode 47 of the capacitive component 45. The bonding wire 27 electrically connects the electrode 47 of the capacitive component 45 to the input lead 22. The lid 18 has a side portion 18a bonded to the upper surface 13a of the frame 12, and an upper portion 18b provided above the semiconductor chip 30, and the capacitive components 40 and 45. The lid 18 seals the semiconductor chip 30, and the capacitive components 40 and 45 in the gap 21, which is a gas.

[0016] FIG. 3 is an enlarged view of the semiconductor chip 30 and the capacitive component 40 in FIG. 2. As shown in FIG. 3, the frame 12 has a thick film portion 12a and a thin film portion 12b that is thinner than the thick film portion 12a. The lower surfaces of the thick film portion 12a and the thin film portion 12b are substantially flat. A step is formed by the upper surface of the thick film portion 12a and the thin film portion 12b. The upper surfaces of the thick film portion 12a and the thin film portion 12b are the upper surfaces 13a and 13b, respectively. A conductor pattern 15 is provided on the lower surface of the frame 12, and the conductor pattern 15 and the base substrate 11 are joined by a joining member 17. The joining member 17 is, for example, a conductive brazing material. The electrode 34 of the semiconductor chip 30 and the base substrate 11 are connected by a joining member 35. The electrode 43 of the capacitive component 40 and the conductor pattern 14b are joined by a joining member 44. The joining members 35 and 44 are, for example, conductive members obtained by sintering a metal paste such as silver paste. The top surface 13a of the frame 12 and the output leads 20 are joined to the side portion 18a of the lid 18 by a joining member 19. The joining member 19 is, for example, an insulating resin adhesive.

[0017] 3 of the first embodiment, the heights from the upper surface of the base substrate 11 to the upper surfaces 13a and 13b of the frame 12 are H1 and H2, respectively. The conductive patterns 14a, 14b, and 15 and the bonding member 17 are sufficiently thinner than the frame 12, so the heights H1 and H2 are approximately the thicknesses of the thick film portion 12a and the thin film portion 12b. The height from the upper surface of the output lead 20 to the lower surface of the upper portion 18b of the lid 18 is H4, the width of the joint between the frame 12 and the base substrate 11 is D1, the width of the joint between the side portion 18a and the frame 12 and the output lead 20 is D2, the distance between the frame 12 and the semiconductor chip 30 is D3, the distance between the thick film portion 12a and the capacitive component 40 is D4, the distance between the lower surface of the lid 18 and the bonding wire 25 is D5, and the width of the side portion 18a is D6. As an example, H1, H2, H4, D1, D2, D3, D4, D5 and D6 are 0.5 mm, 0.25 mm, 0.8 mm, 1.25 mm, 0.55 mm, 0.3 mm, 0.2 mm, 0.43 mm and 0.6 mm, respectively.

[0018] FIG. 4 is a circuit diagram of a semiconductor device according to a first embodiment. As shown in FIG. 4, the semiconductor device 100 is a high-power amplifier circuit, and includes an amplifier 50, an output matching circuit 52, and an input matching circuit 54. The amplifier 50 includes a transistor Q1, such as a FET. The transistor Q1 is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor). The source S of the transistor Q1 is connected to the ground, the gate G is connected to an input terminal Tin via the input matching circuit 54, and the drain D is connected to an output terminal Tout via the output matching circuit 52. The amplifier 50 corresponds to the semiconductor chip 30, and the source S, the gate G, and the drain D correspond to the electrodes 34, 32, and 33, respectively.

[0019] The output matching circuit 52 includes inductors L1, L2, and a capacitor C1. The inductors L1 and L2 are connected in series between the drain D and the output terminal Tout. One end of the capacitor C1 is connected to a node between the inductors L1 and L2, and the other end is connected to ground. The inductors L1, L2, and the capacitor C1 correspond to the bonding wires 25, 24, and the capacitive component 40, respectively. The output matching circuit 52 matches the output impedance of the amplifier 50 to the output impedance of the output terminal Tout.

[0020] The input matching circuit 54 includes inductors L3, L4 and a capacitor C2. The inductors L3 and L4 are connected in series between the gate G and the input terminal Tin. One end of the capacitor C2 is connected to a node between the inductors L3 and L4, and the other end is connected to ground. The inductors L3, L4 and the capacitor C2 correspond to the bonding wires 27, 26 and the capacitive component 45, respectively. The input matching circuit 54 matches the input impedance of the amplifier 50 to the input impedance of the input terminal Tin.

[0021] The amplifier circuit is, for example, a power amplifier circuit of 3.3 GHz to 3.8 GHz, and a high-frequency signal inputted from an input terminal Tin is amplified by the amplifier 50 and outputted from an output terminal Tout.

[0022] [Comparative Example 1] FIG. 5 is an enlarged cross-sectional view of the semiconductor device according to Comparative Example 1. As shown in FIG. 5, the capacitive component 40 is not provided in the package. That is, the internal output matching circuit is not provided. The frame body 12 is not formed in a stepped shape, and the output lead 20 is provided on the upper surface 13a of the frame body 12. The bonding wire 25 electrically connects the electrode 33 of the semiconductor chip 30 and the output lead 20. In order to ensure the bonding between the base substrate 11 and the frame body 12 by the bonding member 17, the design rule requires that the width D1 be set to a predetermined value or more. On the other hand, the width D2 of the bonding between the side portion 18a and the frame body 12 and the output lead 20 is not required to be as large as D1. This is because a resin-based insulating adhesive can be used for the bonding member 19, whereas a conductive brazing material or the like is used for the bonding member 17. In addition, since the base substrate 11 is, for example, a metal layer and the frame body 12 is an insulator, the difference in thermal expansion coefficient is likely to be large, and thermal stress is likely to be applied between the base substrate 11 and the frame body 12. In one design rule, D1 is 1.55 mm. H1, H4, D2 and D3 are, for example, 0.5 mm, 0.8 mm, 0.6 mm and 0.3 mm.

[0023] In Comparative Example 1, the semiconductor chip 30 and the output lead 20 are connected using a bonding wire 25. Since the output impedance of the semiconductor chip 30 is very low, the output impedance of the output lead 20 is also low in Comparative Example 1. This makes it difficult to improve the characteristics of the amplifier circuit. It is preferable to provide an internal matching circuit between the semiconductor chip 30 and the output lead 20. However, in order to provide the internal matching circuit in the base package, the capacitive component 40 must be mounted on the base substrate 11, which increases the size of the semiconductor device.

[0024] [Comparative Example 2] FIG. 6 is an enlarged cross-sectional view of a semiconductor device according to Comparative Example 2. As shown in FIG. 6, in Comparative Example 2, a conductor pattern 14b is provided on the frame body 12. The conductor pattern 14b is electrically isolated from the conductor pattern 14a. The conductor pattern 14b is electrically connected to the base substrate 11 via the through electrode 16. In Comparative Example 1, by mounting the capacitive component 40 on the frame body 12, the capacitive component 40 can be mounted in the package without widening the width of the base substrate 11 in the X direction. By providing the bonding wires 24 and 25, the output matching circuit 52 of FIG. 4 can be mounted in the package. This allows the semiconductor device to be miniaturized. The reason why the capacitive component 40 can be mounted on the frame body 12 is that the width D2 of the joint between the side portion 18a of the lid 18 and the frame body 12 may be narrower than the width D1 of the joint between the frame body 12 and the base substrate 11.

[0025] In the case of an amplifier circuit for the 3.3 GHz to 3.8 GHz band, an example of the inductance of the inductor L1 and the capacitance of the capacitor C1 of the output matching circuit 52 in FIG. 4 is 0.387 nH and 8 pF, respectively. When impedance matching is performed mainly by the inductor L1 and the capacitor C1, the inductance of the inductor L2 is reduced to 0.15 nH. The inductance of 0.387 nH in the inductor L1 can be realized by setting the length of the bonding wires 25 to 1.76 mm, the number of the bonding wires 25 to 16, and the spacing between the bonding wires 25 to 0.25 mm. The inductance is influenced not only by the length of the bonding wires 25 but also by the shape of the bonding wires 25. The capacitance of 8 pF in the capacitor C1 can be realized by setting the relative dielectric constant of the dielectric substrate 41 to 250, the thickness to 0.25 mm, the outer shape of the dielectric substrate 41 to 3.5 mm×0.4 mm, and the shape of the electrode 42 to 3.4 mm×0.3 mm. In order to reduce the inductance of the inductor L2, the length of the bonding wires 24 is shortened and the number of them is increased.

[0026] In order to miniaturize the semiconductor device, the distance D3 between the semiconductor chip 30 and the frame 12 is set to the smallest possible value under the design rules, and the length of the bonding wire 25 is set to, for example, 1.76 mm so that the desired inductance is obtained as the inductor L1. In this case, the distance D5 between the bonding wire 25 and the lower surface of the upper portion 18b of the lid 18 is set to, for example, 0.2 mm. After the bonding wire 25 is formed, the lid 18 is bonded onto the frame 12. At this time, if the bonding wire 25 and the lower surface of the upper portion 18b interfere with each other (for example, come into contact with each other), the shape of the bonding wire 25 changes. This changes the inductance of the inductor L1. This changes the characteristics of the output matching circuit 52, and there is a possibility that the desired performance of the amplifier circuit cannot be obtained.

[0027] In order to suppress interference between the bonding wires 25 and the underside of the upper portion 18b of the lid 18, it is conceivable to increase the height of the underside of the upper portion 18b from the base substrate 11. However, this would increase the height of the package, resulting in a larger semiconductor device. It is conceivable to make the frame 12 thinner. However, making the frame 12 thinner would shorten the distance between the output lead 20 and the base substrate 11 to which the ground potential is supplied, which would affect the propagation characteristics of the high-frequency signal of the output lead 20.

[0028] Furthermore, in Comparative Example 2, when the electrode 42 of the capacitive component 40 becomes higher than the upper surface of the output lead 20, the distance D4 between the side portion 18a of the lid 18 and the capacitive component 40 is shortened in order to shorten the bonding wire 24. The distance D4 is, for example, 0.14 mm. The design rule for the distance D4 as a margin when mounting the capacitive component 40 and when joining the lid 18 to the frame body 12 is, for example, 0.2 mm, and this design rule cannot be satisfied.

[0029] According to the first embodiment, as shown in FIG. 3, a semiconductor chip 30 having electrodes 33 (signal pads) is mounted on a base substrate 11. A frame 12 surrounds the semiconductor chip 30 and is mounted on the base substrate 11. The frame 12 has a step having an inner upper surface 13b (first upper surface) and an outer upper surface 13a (second upper surface) higher than the upper surface 13b in a plan view. A conductor pattern 14b (first conductor pattern) provided on the upper surface 13b is electrically connected to the base substrate 11. A capacitive component 40 is mounted on the conductor pattern 14b, and an output lead 20 and a conductor pattern 14a are mounted on the upper surface 13a of the frame 12. A bonding wire 25 (first bonding wire) electrically connects the electrode 33 to the upper surface of the capacitive component 40, and a bonding wire 24 (second bonding wire) electrically connects the upper surface of the capacitive component 40 to the output lead 20. The lid 18 is joined to the upper surface 13 a of the frame 12 to seal the semiconductor chip 30 in the gap 21 .

[0030] As a result, the capacitive component 40 is disposed at a height position closer to the base substrate 11 than in Comparative Example 2. This allows the distance D5 between the lower surface of the upper portion 18b of the lid 18 and the bonding wires 25 to be increased. For example, D5 can be set to approximately 0.43 mm. This prevents the lid 18 from interfering with the bonding wires 25, keeps the characteristics of the output matching circuit 52 unchanged, and allows the semiconductor device to be miniaturized.

[0031] The bonding wire 24 is directly bonded to the upper surface of the output lead 20. This allows the bonding wire 24 to be shortened. In addition, by appropriately setting the height H2 of the upper surface 13b, the height difference H5 between the upper surface of the electrode 42 of the capacitive component 40 and the upper surface of the output lead 20 can be made smaller than the height difference H5a between the upper surface of the electrode 42 of the capacitive component 40 and the upper surface of the output lead 20 of the comparative example 2. This allows the length of the bonding wire 24 to be approximately the same as that of FIG. 6 of the comparative example 2, even if the distance D4 between the capacitive component 40 and the side portion 18a is set to, for example, 0.2 mm, which is a design rule. The conductor patterns 14a, 14b and the bonding member 44 are sufficiently thinner than the capacitive component 40 and the output lead 20. At this time, in order to make the height difference H5 of FIG. 3 in the first embodiment smaller than the height difference H5a in the comparative example 2, it is preferable that the height difference H5 is smaller than the difference between the thickness T1 of the capacitive component 40 and the thickness T2 of the output lead 20. The height difference H5 is more preferably equal to or less than half the difference between the thicknesses T1 and T2.

[0032] [Modification 1 of Example 1] FIG. 7 is an enlarged cross-sectional view of a semiconductor device according to a first modified example of the first embodiment. As shown in FIG. 7, the width D6 of the side 18a of the lid 18 is the same as that of FIG. 3 of the first embodiment. The outer side surface of the side 18a is located a distance D8 outward from the outer side surface of the frame body 12. The distance D8 is, for example, 0.2 mm. This allows the distance D7 between the inner end face of the thick film portion 12a and the inner side surface of the side 18a to be increased. The distance D7 is, for example, 0.25 mm. The width D2 at which the side 18a is joined to the frame body 12 and the output lead 20 is smaller than that of the second embodiment. If the joining strength between the side 18a and the frame body 12 is sufficient, the width D2 may be shortened. The other configurations are the same as those of the first embodiment, and a description thereof will be omitted.

[0033] In FIG. 3 of the first embodiment, the distance between the inner side surface of the side portion 18a and the bonding wire 24 is small, and there is a possibility that the bonding wire 24 may be crushed when the lid 18 is bonded onto the frame body 12 and the output lead 20. In the first modification of the first embodiment, the side portion 18a is disposed on the outer side than in the first embodiment, so that the distance D7 can be made wider. That is, the area on the output lead 20 where the bonding wire 24 is bonded can be made wider. This makes it possible to suppress the crushing of the bonding wire 24. Also, by making the width D6 of the side portion 18a the same as in FIG. 3 of the first embodiment, the strength of the side portion 18a can be maintained.

[0034] [Modification 2 of Example 1] FIG. 8 is an enlarged cross-sectional view of a semiconductor device according to Modification 2 of Example 1. As shown in FIG. 8, in Modification 2 of Example 1, the width D6 of the side portion 18a is made thinner to the same size as the width D2 compared to Modification 1 of Example 1. The other configurations are the same as Modification 1 of Example 1, and the description will be omitted. In Modification 2 of Example 1, crushing of the bonding wire 24 can be suppressed as in Modification 1 of Example 1. Furthermore, the outer side surface of the side portion 18a and the outer side surface of the frame body 12 are approximately aligned. As a result, compared to FIG. 7 of Modification 1 of Example 1, the external shape of the semiconductor device can be made smaller to the same extent as in Example 1.

[0035] [Modification 3 of Example 1] 9 is an enlarged cross-sectional view of a semiconductor device according to Modification 3 of Example 1. In Modification 3 of Example 1, the position of the output lead 20 is moved outward, compared to Modification 2 of Example 1, so that the position of the inner end face of the output lead 20 and the position of the inner side face of the side portion 18a of the lid 18 are substantially the same. As a result, as shown in FIG. 9, the bonding wire 24 is bonded to the conductor pattern 14a. The other configurations are the same as those of Modification 2 of Example 1, and the description will be omitted. As in Modification 3 of Example 1, the bonding wire 24 may be bonded to the conductor pattern 14a. The conductor pattern 14a and the output lead 20 function as an output terminal.

[0036] In the first embodiment and its first to third modifications, the bonding wire 24 is bonded to the output lead 20 or the conductor pattern 14a (i.e., the signal terminal). This allows the capacitive component 40 and the output terminal to be electrically connected. The side portion 18a of the lid 18 is bonded to the output lead 20 on the outer side of the portion where the bonding wire 24 is bonded to the output lead 20 or the conductor pattern 14a in a plan view. This prevents the bonding wire 24 from being crushed when the lid 18 is bonded to the frame 12. As in the first to third modifications of the first embodiment, the distance D7 between the inner end face of the thick film portion 12a and the inner side surface of the side portion 18a is preferably ¼ or more of the width of the thick film portion 12a. This allows the area where the bonding wire 24 is bonded to the output lead 20 or the conductor pattern 14a to be secured.

[0037] [Variation 4 of Example 1] Fig. 10 is an enlarged cross-sectional view of a semiconductor device according to Modification 4 of Example 1. As shown in Fig. 10, no through electrode 16 is provided, and a conductor layer 16a is provided on the inner side surface of thin film portion 12b. Conductor layer 16a electrically connects conductor pattern 14a and conductor pattern 15. The other configurations are the same as those of Example 1, and therefore description thereof will be omitted.

[0038] As in Example 1 and its Modifications 1 to 4, the conductor pattern 14b and the base substrate 11 are electrically connected by the through electrode 16 penetrating the thin film portion 12b of the frame body 12 or another conductor layer 16a provided on the inner side surface of the thin film portion 12b of the frame body 12. This allows for easy electrical connection between the conductor pattern 14b and the base substrate 11. As a result, the electrode 43 on the lower surface of the capacitive component 40 mounted on the thin film portion 12b of the frame body 12 can be easily electrically connected to the base substrate 11 via the bonding member 44.

[0039] [Modification 5 of Example 1] FIG. 11 is a plan view of a semiconductor device according to a fifth modified example of the first embodiment. As shown in FIG. 11, the capacitive component 45 is mounted on the upper surface 13b of the frame 12 on the input lead 22(-X) side. An electrode 48 (not shown) of the capacitive component 45 is connected to the base substrate 11 via a through electrode penetrating the conductive pattern 14b and the frame 12. The other configurations are the same as those of the first embodiment, and a description thereof will be omitted. As in the fifth modified example of the first embodiment, the capacitive component 45 corresponding to the capacitor C2 of the input matching circuit 54 may also be mounted on the upper surface 13b. In this way, the signal pad of the semiconductor chip 30 to which the capacitive component 40 or 45 is connected is at least one of the electrode 32 (input pad) for inputting a high-frequency signal to a transistor and the electrode 33 (output pad) for outputting a high-frequency signal from the transistor.

[0040] [Modification 6 of Example 1] FIG. 12 is a plan view of a semiconductor device according to a sixth modified example of the first embodiment. As shown in FIG. 12, two semiconductor chips 30 and two capacitive components 45 are mounted on a base substrate 11, and two capacitive components 40 are mounted on an upper surface 13b of a thin film portion 12b of a frame body 12. Two input leads 22 and two output leads 20 are provided on an upper surface 13a of a thick film portion 12a of a frame body 12. The two semiconductor chips 30 correspond to, for example, a carrier amplifier and a peak amplifier of a Doherty amplifier circuit. The other configurations are the same as those of the first embodiment, and therefore description thereof will be omitted. A semiconductor device may be provided with a plurality of semiconductor chips 30, capacitive components 40, and the like.

[0041] [Example 2] FIG. 13 is a plan view of a semiconductor device according to a second embodiment. FIG. 14 is an enlarged view of the vicinity of the semiconductor chip 30 and the capacitive component 40 in the fourth embodiment. As shown in FIGS. 13 and 14, in the semiconductor device 102, the frame 12 has an intermediate portion 12c between the thin film portion 12b and the thick film portion 12a. The intermediate portion 12c is thicker than the thin film portion 12b and thinner than the thick film portion 12a. A conductor pattern 14c is provided on the upper surface 13c of the intermediate portion 12c. The conductor pattern 14c extends into the thick film portion 12a. The conductor patterns 14a and 14c are electrically connected and short-circuited by the internal wiring 16b in the thick film portion 12a. The conductor patterns 14a and 14c are at the same potential. The bonding wire 24 is bonded to the conductor pattern 14c. The height of the upper surface 13c of the intermediate portion 12c from the base substrate 11 is H3. H1, H2 and H3 are, for example, 0.5 mm, 0.125 mm and 0.375 mm. The distance D9 between the inner side surface of the thick film portion 12a and the inner side surface of the intermediate portion 12c is, for example, 0.2 mm. The other configurations are the same as those in the first embodiment, and the description will be omitted.

[0042] According to the second embodiment, the step has an upper surface 13c (third upper surface) of the intermediate portion 12c, which is higher than the upper surface 13b and lower than the upper surface 13a, between the upper surface 13a of the thick film portion 12a and the upper surface 13b of the thin film portion 12b in a plan view. A conductor pattern 14c (second conductor pattern) is provided on the upper surface 13c of the intermediate portion 12c. The conductor pattern 14c is electrically connected to the output lead 20 (signal terminal) via the internal wiring 16b. The bonding wire 24 is bonded to the conductor pattern 14c and is electrically connected to the output lead 20 via the conductor pattern 14c, the internal wiring 16b, and the conductor pattern 14a.

[0043] 3 of the first embodiment, the position at which the capacitive component 40 is mounted can be made lower. This makes it possible to increase the distance D5 between the lower surface of the upper portion 18b of the lid 18 and the bonding wires 25. This makes it possible to suppress interference between the upper portion 18b of the lid 18 and the bonding wires 25.

[0044] In addition, even if the height H2 of the upper surface 13b of the thin film portion 12b on which the capacitive component 40 is mounted is lower than that of the first embodiment, the height difference H5b between the upper surface of the electrode 42 of the capacitive component 40 and the upper surface of the conductor pattern 14c can be reduced. As a result, even if the length of the bonding wire 24 is approximately the same as that of the second comparative example, the distance D4 between the side surface of the capacitive component 40 and the inner side surface of the intermediate portion 12c can be secured. Therefore, the semiconductor device can be miniaturized. The conductor patterns 14a to 14c and the bonding member 44 are sufficiently thinner than the frame 12, the capacitive component 40, and the output lead 20. At this time, in order to make the height difference H5b of FIG. 14 in the second embodiment smaller than the height difference H5 in the first embodiment, it is preferable that the height difference H5b is smaller than the difference between the thickness T1 of the capacitive component 40 and the height difference H1-H2 between the upper surface 13b of the thin film portion 12b and the upper surface 13a of the thick film portion 12a. The height difference H5b is more preferably equal to or less than half the difference between the thickness T1 and the difference H1-H2.

[0045] [Modification 1 of Example 2] FIG. 15 is an enlarged cross-sectional view of a semiconductor device according to Modification 1 of Example 2. As shown in FIG. 15, the width D6 of the side portion 18a of the lid 18 is the same as that of FIG. 3 of Example 1. The outer side surface of the side portion 18a is positioned a distance D8 outward from the outer side surface of the frame body 12. The distance D8 is, for example, 0.15 mm. This allows the distance D7 between the end face of the middle portion 12c and the inner side surface of the side portion 18a to be increased. If the bonding strength between the side portion 18a and the frame body 12 is sufficient, the width D2 may be shortened. The other configurations are the same as those of Example 2, and a description thereof will be omitted.

[0046] In the first modification of the second embodiment, the side portion 18a is disposed on the outer side than in the second embodiment, so that the distance D7 can be made wider. This can suppress the crushing of the bonding wire 24. In addition, by making the width D6 of the side portion 18a the same as that in FIG. 14 of the second embodiment, the strength of the side portion 18a can be maintained.

[0047] [Modification 2 of Example 2] FIG. 16 is an enlarged cross-sectional view of a semiconductor device according to Modification 2 of Example 2. As shown in FIG. 16, the width D6 of the side portion 18a is the same as the width D2 of the joint between the side portion 18a and the output lead 20. The other configurations are the same as Modification 1 of Example 2, and the description will be omitted. In Modification 2 of Example 2, crushing of the bonding wire 24 can be suppressed as in Modification 1 of Example 2. Furthermore, the outer side surface of the side portion 18a and the outer side surface of the frame body 12 are approximately aligned. As a result, the external shape of the semiconductor device can be made smaller to the same extent as in Example 2, as compared to FIG. 15 of Modification 1 of Example 2.

[0048] [Modification 3 of Example 1] Fig. 17 is an enlarged cross-sectional view of a semiconductor device according to Modification 3 of Example 2. As shown in Fig. 17, the width D2 of the junction between side portion 18a and output lead 20 and the width D6 of side portion 18a are substantially the same. D2 and D6 are, for example, 0.25 mm. The inner side surface of side portion 18a is located, for example, 0.2 mm outward from the inner side surface of thick film portion 12a. This allows the distance D7 between the inner side surface of intermediate portion 12c and side portion 18a to be increased. The other configurations are the same as those of Modification 2 of Example 2, and description thereof will be omitted.

[0049] In the third modification of the second embodiment, crushing of the bonding wires 24 can be suppressed more effectively than in the second modification of the second embodiment. Furthermore, the outer side surface of the side portion 18a and the outer side surface of the frame 12 are substantially aligned with each other. This allows the external shape of the semiconductor device to be reduced in size to the same extent as in the second embodiment.

[0050] As in the second embodiment and its modified example, the side portion 18a is bonded to the upper surface 13a but is not bonded to the upper surface 13c. This makes it possible to prevent the bonding wires 24 from being crushed when the lid 18 is bonded to the frame 12.

[0051] [Modification 4 of Example 2] FIG. 18 is an enlarged cross-sectional view of a semiconductor device according to Modification 4 of Example 2. As shown in FIG. 18, in Modification 4 of Example 2, a conductor layer 16a is provided on the side surface of the end of the thin film portion 12b instead of the through electrode 16. The conductor layer 16a electrically connects and shorts the conductor patterns 14b and 15. A conductor layer 16c is provided on the inner side surface of the thick film portion 12a between the upper surfaces 13a and 13c instead of the internal wiring 16b. The conductor layer 16c electrically connects and shorts the conductor patterns 14a and 14c. The other configurations are the same as those of Example 2, and the description thereof will be omitted. In Modification 4 of Example 2, it is not necessary to extend the conductor pattern 14c into the frame body 12. This makes it easier to manufacture the frame body 12.

[0052] As in Example 2 and its Modifications 1 to 4, the conductor pattern 14c and the output lead 20 may be electrically connected by internal wiring 16b inside the frame 12, or may be electrically connected by a conductor layer 16c provided on the side surface of the thick film portion 12a. In Examples 1 and 2 and their Modifications, the frame 12 may be molded as a plurality of members and then joined together, or may be molded integrally with resin.

[0053] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0054] 10 Packages 11 Base board 12 Frame 12a Thick film part 12b Thin film part 12c middle part 13a Top surface (second top surface) 13b Top surface (first top surface) 13c Top surface (Third top surface) 14b Conductive pattern (first conductive pattern) 14c Conductive pattern (second conductive pattern) 14a to 14c, 15 Conductive patterns 16 Through electrode 16a, 16c conductor layer 16b Internal wiring 17, 19, 35, 44 Joint members 18 Lid 18a Side 18b Upper 20 Output lead (signal terminal) 21 void 22 Input Leads 24 Bonding wire (second bonding wire) 25 Bonding wire (first bonding wire) 26, 27 Bonding wire 30 Semiconductor Chips 31 Semiconductor Substrate 32, 33 electrodes (signal pads) 34, 42, 43, 47, 48 electrodes 40, 45 Capacitive components 41, 46 Dielectric substrate 50 Amplifier 52 Output matching circuit 54 Input matching circuit Q1 Transistor

Claims

1. A base substrate that is conductive; a semiconductor chip mounted on the base substrate and having signal pads; a frame that surrounds the semiconductor chip and is mounted on the base substrate, the frame having a step having an inner first upper surface and an outer second upper surface higher than the first upper surface in a plan view, the first conductor pattern provided on the first upper surface being electrically connected to the base substrate; a capacitive component mounted on the first conductive pattern; A signal terminal mounted on the second upper surface of the frame body; a first bonding wire electrically connecting the signal pad and a top surface of the capacitive component; a second bonding wire electrically connecting the upper surface of the capacitive component and the signal terminal; a lid that is joined to the second upper surface of the frame and seals the semiconductor chip in a gap; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the second bonding wire is bonded to the signal terminal.

3. 3. The semiconductor device according to claim 2, wherein a difference in height between an upper surface of the capacitive component and an upper surface of the signal terminal is smaller than a difference in thickness between the capacitive component and a thickness of the signal terminal.

4. the lid includes a side portion joined to the second upper surface of the frame and an upper portion provided above the semiconductor chip; 4. The semiconductor device according to claim 2, wherein the side portion is joined to an upper surface of the signal terminal outside a portion where the second bonding wire is joined to the signal terminal in a plan view.

5. the step has a third upper surface between the first upper surface and the second upper surface in a plan view, the third upper surface being higher than the first upper surface and lower than the second upper surface, and a second conductor pattern electrically connected to the signal terminal is provided on the third upper surface; 2. The semiconductor device according to claim 1, wherein the second bonding wire is connected to the signal terminal via the second conductor pattern.

6. 6. The semiconductor device according to claim 5, wherein a difference in height between the top surface of the capacitive component and the top surface of the second conductive pattern is smaller than a difference between a thickness of the capacitive component and a difference in height between the first top surface and the second top surface.

7. the lid includes a side portion joined to the second upper surface of the frame and an upper portion provided above the semiconductor chip; The semiconductor device according to claim 5 , wherein the side portion is in contact with the second upper surface and is not in contact with the third upper surface.

8. 8. The semiconductor device according to claim 1, wherein the semiconductor chip includes a transistor, and the signal pad is at least one of an input pad for inputting a high-frequency signal to the transistor and an output pad for outputting a high-frequency signal from the transistor.

9. 9. The semiconductor device according to claim 1, wherein the first conductive pattern and the base substrate are electrically connected by a through electrode penetrating the frame or by another conductive layer provided on an inner side surface of the frame.

10. a base substrate that is conductive and has a first region on which a semiconductor chip can be mounted; a frame that surrounds the semiconductor chip and is mounted on the base substrate, the frame having a step having a first upper surface on the inside and a second upper surface on the outside that is higher than the first upper surface in a plan view, the first upper surface having a second region on which a capacitive component can be mounted, and the second upper surface being electrically isolated from the base substrate; a signal terminal having an upper surface to be bonded to an upper surface of the capacitive component by a bonding wire, the signal terminal being mounted on the second upper surface of the frame; A package in which the second region on which the capacitive component can be mounted is connected to the base substrate via a through electrode that penetrates the frame or another conductive layer provided on the inner side of the frame so that the second region has the same potential as the base substrate.

11. A semiconductor device as described in claim 10, wherein the difference in height between the upper surface of the capacitive component and the upper surface of the signal terminal is smaller than the difference in thickness between the capacitive component and the thickness of the signal terminal.

Images