Computer system and control method thereof

Abstract

This control method for a computer system is for a computer system which comprises a plurality of arithmetic units (11_1 to 11_N) and a host unit (12) and in which the plurality of arithmetic units each comprise a trace buffer (18) and, with the detection of prescribed events from input data serving as triggers, event detection times acquired on the basis of the operation frequencies of the arithmetic units are recorded in the trace buffers by input data type. This control method for a computer system comprises: a step in which either the host unit or the arithmetic units determine the input data types to which the event detection times recorded in the trace buffers belong; and a step in which, in accordance with the result of the determination, the most recent event detection time among event detection times belonging to the same input data type is recorded and any such event detection time other than said most recent event detection time is erased.　The present invention is thus able to provide a control method for a computer system whereby buffer overflow can be suppressed and the physical buffer size is reduced.

Description

[Technical field]

[0001] The present invention relates to a computer system having a plurality of processing units and a control method thereof. [Background technology]

[0002] Technological innovation is progressing in many fields, such as machine learning, artificial intelligence (AI), and the Internet of Things (IoT), and by utilizing various information and data, services are being actively improved and added value is being provided. This type of processing requires a large amount of calculations, and an information processing infrastructure is essential for this.

[0003] For example, Non-Patent Document 1 points out that although attempts are being made to update existing information processing infrastructure, current computers are unable to keep up with the rapidly increasing amount of data, and that in order to make progress in the future, "post-Moore technology" that goes beyond Moore's Law must be established.

[0004] As a post-Moore technology, for example, a technology called flow-centric computing is disclosed in Non-Patent Document 2. Flow-centric computing introduces a new concept of moving data to a location where a computing function is present and processing the data there, instead of the conventional computing idea of ​​performing processing where the data is located.

[0005] To realize the above-mentioned flow-centric computing, not only is a broadband communication network necessary for data movement required, but it is also necessary to efficiently control computational resources in order to obtain the desired computational performance.

[0006] Flow-centric computing (for example, Non-Patent Document 2) discloses a method for linking a plurality of computing functions. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] “NTT Technology Report for Smart World 2020,” Nippon Telegraph and Telephone Corporation, 2020. https: / / www.rd.ntt / _assets / pdf / techreport / NTT_TRFSW_2020_EN_W.pdf. [Non-Patent Document 2] R. Takano and T. Kudoh, “Flow-centric computing leveraged by photonic circuit switching for the post-moore era,” Tenth IEEE / ACM International Symposium on Networks-on-Chip (NOCS), Nara, 2016, pp. 1-3. https: / / ieeexplore.ieee.org / abstract / document / 7579339. Summary of the Invention [Problem to be solved by the invention]

[0008] However, in a computer system in which a plurality of processing elements work together, it is difficult to identify a fault that occurs within a processing element because the processing elements independently transfer data between each other without going through the host unit.

[0009] Also, it has been difficult to grasp the internal state of a computer system, such as identifying the processing unit through which input data has passed at a certain time. [Means for solving the problem]

[0010] In order to solve the problems described above, a control method for a computer system according to the present invention is a control method for a computer system comprising a plurality of arithmetic units and a host unit, each of which has a trace buffer, and which, upon detection of a specified event from input data, records in the trace buffer the detection time of the event obtained based on the operating frequency of the arithmetic units for each type of input data, the control method comprising a step of either the host unit or the arithmetic unit determining the type of input data to which the detection time of the event recorded in the trace buffer belongs, and a step of either the host unit or the arithmetic unit recording the detection time of the latest event among the detection times of the events belonging to the same type of input data according to the result of the determination, and erasing the detection times of the events other than the detection time of the latest event.

[0011] In addition, a control method for a computer system according to the present invention is a control method for a computer system in which a plurality of arithmetic units each have an arithmetic unit and a trace buffer, and upon detection of a specified event from input data, the detection time of the event, which is obtained based on the operating frequency of the arithmetic unit, is recorded in the trace buffer, and the control method includes a step in which an arithmetic unit of one of the plurality of arithmetic units processes the input data and transfers it to an arithmetic unit of another arithmetic unit, a step in which the other arithmetic unit sends a reception completion notification, and a step in which, when the one arithmetic unit receives the reception completion notification, the one arithmetic unit erases the detection time of the event recorded in the trace buffer of the one arithmetic unit.

[0012] In addition, a control method for a computer system according to the present invention is a control method for a computer system comprising a plurality of arithmetic units and a host unit, each of which has a trace buffer, and which, upon detection of a specified event from input data, records the detection time of the event, which is obtained based on the operating frequency of the arithmetic units, in the trace buffer, and is characterized in that either the host unit or the arithmetic units erases the detection time of the event recorded in the trace buffer upon the passage of a specified time.

[0013] Moreover, a computer system according to the present invention is a computer system for processing input data, comprising a plurality of arithmetic units, and a host unit connected to the plurality of arithmetic units and controlling the plurality of arithmetic units, the processed data being transferred between the plurality of arithmetic units, the arithmetic units comprising a trace buffer for recording trace data upon detection of a predetermined event from the input data, the trace data having a timestamp value which is the detection time of the event based on the operating frequency of the arithmetic units, and either the host unit or the arithmetic units erasing the trace data recorded in the trace buffer under predetermined conditions. Effect of the Invention

[0014] According to the present invention, it is possible to provide a computer system and a control method thereof that, when a failure occurs, can easily identify the location of the failure and grasp the internal data status at the time of the failure. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a block diagram showing the configuration of a computer system according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a block diagram showing a configuration of a calculation unit in the computer system according to the first embodiment of the present invention. [Figure 3A] FIG. 3A is a diagram for explaining expansion and contraction of a processing unit in a computer system according to a first embodiment of the present invention. [Figure 3B] FIG. 3B is a diagram for explaining expansion and contraction of the processing units in the computer system according to the first embodiment of the present invention. [Figure 4A] FIG. 4A is a flowchart for explaining a control method of a computer system according to a first embodiment of the present invention. [Figure 4B]FIG. 4B is a flowchart for explaining the control method of the computer system according to the first embodiment of the present invention. [Figure 4C] FIG. 4C is a diagram for explaining a control method of the computer system according to the first embodiment of the present invention. [Diagram 5] FIG. 5 is a flow chart for explaining a control method of a computer system according to the second embodiment of the present invention. [Figure 6] FIG. 6 is a flow chart for explaining a control method of a computer system according to the third embodiment of the present invention. [Figure 7A] FIG. 7A is a diagram for explaining an example of a control method of the computer system according to the first embodiment of the present invention. [Figure 7B] FIG. 7B is a diagram for explaining an example of the control method of the computer system according to the first embodiment of the present invention. [Figure 8] FIG. 8 is a flow chart for explaining a control method of a computer system according to the second embodiment of the present invention. [Figure 9] FIG. 9 is a flow chart for explaining a control method of a computer system according to the second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] <First embodiment> A computer system and a control method thereof according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG.

[0017] <Computer system configuration> As shown in FIG. 1, a computer system 10 according to this embodiment includes N calculation units 11_1 to 11_N (N is an integer equal to or greater than 1), an internal communication unit 13 that connects the calculation units 11_1 to 11_N, and a host unit 12 that sets and manages operating parameters for the calculation units 11_1 to 11_N.

[0018] The calculation units 11_1 to 11_N are constituted by processors, accelerators, etc., and include tracing units 14_1 to 14_N.

[0019] When the calculation units 11_1 to 11_N work in conjunction with each other, the trace units 14_1 to 14_N record the event detection time based on the operating frequency of each of the calculation units 11_1 to 11_N upon detection of a predetermined event at an arbitrary observation point of each of the calculation units 11_1 to 11_N.

[0020] Here, the trace units 14_1 to 14_N can record the event detection time for each data type or event type, and may further record any data.

[0021] In the interlocking of the calculation units 11_1 to 11_N, data processed in the calculation unit 11_1 is transferred to the calculation unit 11_2 via the internal communication unit 13. Subsequently, the data transfer is repeated, and the data is transferred to the calculation unit 11_N.

[0022] As a method of interlocking the calculation units 11_1 to 11_N, a processing method of connecting a plurality of calculation units in series, a processing method of connecting a plurality of calculation units in parallel, a processing method combining both, etc. By interlocking the plurality of calculation units, desired services are provided and applications are processed.

[0023] The calculation units 11_1 to 11_N (N is an integer equal to or greater than 1) have a function of executing a predetermined calculation process on input data input from outside the computer system 10. The calculation process is, for example, general calculation processes such as processing, aggregation, and combination of input data, such as a process of reducing / enlarging an image size when image data is input, a process of detecting a specific object from image data, and a process of decrypting / encrypting image data.

[0024] The arithmetic units 11_1 to 11_N may be added or removed regardless of whether the system is stopped or running. For example, this can be realized by using an FPGA, which is a device that allows dynamic reconfiguration of only a portion of the arithmetic units. As a method of implementing the arithmetic units 11_1 to 11_N, an accelerator card having a dedicated circuit specialized for a specific arithmetic operation may be added. Also, a plurality of arithmetic units that provide arithmetic functions may be provided in the arithmetic units.

[0025] The host unit 12 has a function of setting and managing operation parameters for the calculation units 11_1 to 11_N, and more specifically, a function of controlling the calculation units 11_1 to 11_N and a function of storing data. The operation parameters are, for example, information for identifying an algorithm when multiple algorithms are switched for use in image processing, and are coefficients, threshold values, etc. in the calculation process.

[0026] Furthermore, in cases where a processing unit can be added or removed even after the system has started operating, the host unit 12 manages the entire computer system 10, for example by setting circuit information for the processing unit to execute the desired processing content.

[0027] The internal communication unit 13 connects the calculation units 11_1 to 11_N and has a communication function for transmitting and receiving data between the calculation units 11_1 to 11_N. Specifically, examples of the internal communication unit 13 include a common communication standard such as PCIe or Ethernet and a physical configuration that satisfies the communication standard, that is, a PCIe switch or an Ethernet switch.

[0028] Furthermore, when the calculation units 11_1 to 11_N each include a plurality of calculators each providing a calculation function, a plurality of the observation points may be provided in the calculation units 11_1 to 11_N.

[0029] <Configuration of the calculation unit> The calculation unit 11_1 in the computer system 10 includes a plurality of (N units) calculators 15_1(1) to 15_N(1) and a tracing unit 14_1, as shown in Fig. 2. Here, the number of calculators may be one.

[0030] The trace unit 14_1 includes event generators 16_1_1 to 16_2_N, a time stamp unit 17, and a trace buffer .

[0031] The event generators 16_1_1 to 16_2_N are connected to the input and output sides of the arithmetic units 15_1(1) to 15_N(1), respectively. The outputs of the time stamp unit 17 are connected to the event generators 16_1_1 to 16_2_N. The outputs of the event generators 16_1_1 to 16_2_N are connected to the trace buffer 18.

[0032] Here, the event generators 16_1_1 to 16_2_N may be disposed on either the input side or the output side of the arithmetic units 15_1(1) to 15_N(1), may be disposed at any location, and at least one unit may be disposed. Also, a plurality of trace buffers 18 may be disposed, and at least one unit may be disposed.

[0033] The event generators 16_1_1 to 16_2_N are inserted at any position in the calculation units 11_1 to 11_N to detect events (the beginning and end of a stream) for each type of data (user ID, session ID, stream ID, service ID), and generate an opportunity to record trace data including the detection time (hereinafter referred to as the "timestamp value") in the trace buffer 18 described later.

[0034] In addition, the type of data is not limited to the above, and any information that can be used to organize data, such as header information of a packet used to organize data, or information contained in a signal that runs parallel to the data, can be applied.

[0035] The time stamp unit 17 includes at least one clock counter, synchronizes a plurality of event generators 16_1_1 to 16_2_N (observation points), and acquires time with the accuracy of the operating frequency of the calculation units 11_1 to 11_N. Here, the operating frequency (clock frequency) of the calculation units 11_1 to 11_N is usually about several nanoseconds when the function is realized using an FPGA (field-programmable gate array).

[0036] The trace buffer 18 records trace data when an event is detected by the event generators 16_1_1 to 16_2_N. Here, the trace data includes each detection time (timestamp value) acquired from the timestamp unit 17, an instance ID, an event type (event ID), a data type (TID), and arbitrary data. Here, the trace data must have at least a timestamp value.

[0037] Furthermore, the trace buffer 18 provides a constant buffer capacity, independent of the number of event generators.

[0038] Here, the time stamp value is a standardized value within the calculation unit (FPGA).

[0039] The instance ID is an ID that distinguishes an event generator instance and indicates the location (observation point) where the event is detected.

[0040] The event type (event ID) is an ID that distinguishes the event content. For example, it is distinguished by the passage of the head of a stream or the end of a stream. Also, a flag for event detection is prepared at an arbitrary position of the data, and the passing of the flag is detected.

[0041] Moreover, the arbitrary data is data that is normally processed by a computer system, such as image data, numerical data, and text data.

[0042] The data type is used to identify and classify the attributes of input data, and is information attached to the data body, such as a user ID, a session ID, a stream ID, or a service ID. Information for identifying the data type does not necessarily need to be added to the packet header, and may be defined independently in the payload of the packet, for example. When a signal running parallel to the data is used inside the calculation unit, the parallel signal may be used to obtain the data type.

[0043] <Computer system operation> The operation of the computer system 10 according to the present embodiment will now be described.

[0044] Data is input to calculators 15_1(1) to 15_N(1) in arithmetic unit 11_1 of computer system 10. The input data is composed of various elements, and includes an event type (event ID), a data type (TID), and arbitrary data.

[0045] Here, data processed by the calculator 15_1(1) of the calculation unit 11_1 is transmitted and input to the calculator 15_1(2) of the calculation unit 11_2.

[0046] In the event generators 16_1_1 to 16_2_N, first, control signals (operations) of data input to the arithmetic units 11_1 to 11_N are observed.

[0047] When the event generators 16_1_1 to 16_2_N detect an event, the event generators 16_1_1 to 16_2_N acquire the event type, the data type, and any data from the input data. Here, the event occurrence is, for example, when the head of a stream passes, or when the head of a stream passes.

[0048] In the event generators 16_1_1 to 16_2_N, an instance ID and a timestamp value transmitted from the timestamp unit 17 are added to the acquired event type, data type, and arbitrary data. As a result, the trace data is composed of the timestamp value, the instance ID, the event type, the data type, and arbitrary data.

[0049] Here, the trace data only needs to include at least a time stamp value, and based on the time stamp value, information within the computer system such as processing time, data flow rate, etc. can be ascertained. In addition, the time when a malfunction occurred can also be ascertained.

[0050] Furthermore, since the trace data has an instance ID, it is possible to identify the location where the problem occurred.

[0051] Furthermore, since the trace data includes an event type, it is possible to know when an event occurred.

[0052] Furthermore, by having the data type, the trace data can grasp the operating status for each data type, and can be used to determine when to erase data (described later).

[0053] Furthermore, the trace data can contain arbitrary data that can be used when restarting processing (described later).

[0054] Furthermore, since the trace data has priority information of the service, it can be used for managing the trace data based on priority.

[0055] Finally, the event generators 16_1_1 to 16_2_N transmit the trace data to the trace buffer 18.

[0056] Furthermore, the time stamp unit 17 receives (writes) the count start or stop setting transmitted from the host unit 12.

[0057] This triggers the clock counter to start or stop counting.

[0058] The count is started by the count start setting, and is executed based on the operating frequency of each of the arithmetic units 11_1 to 11_N, whereas the count is stopped by the count stop setting.

[0059] When the event generators 16_1_1 to 16_2_N detect an event, they read out the time counted by the clock counter as a time stamp value, and transmit the time stamp value to the event generators 16_1_1 to 16_2_N.

[0060] Additionally, events can be detected, for example, by determining whether a signal that runs parallel to the data is valid or not by using the ON / OFF state of the signal, or by preparing a field for event detection in a specific area of ​​the data and using the bit string of that field.

[0061] Here, the calculation units (FPGAs) are synchronized as necessary. As a method for synchronizing the calculation units, a signal for synchronizing or a reset signal is input from the host unit to the calculation unit to be synchronized, thereby achieving synchronization.

[0062] Furthermore, when the host unit 12 reads out trace data from the trace buffer 18, it transmits a reset signal to the time stamp unit 17 to reset the value of the clock counter.

[0063] In the trace buffer 18, the trace data received from the event generators 16_1_1 to 16_2_N is recorded and accumulated in the trace buffer 18.

[0064] Here, trace data transmitted from a plurality of event generators 16_1_1 to 16_2_N is recorded. Moreover, writing and reading of trace data is performed in a common FIFO (First-In First-Out) manner for all TIDs.

[0065] Next, the host unit 12 reads the trace data from the trace buffer 18 .

[0066] Finally, the host unit 12 performs post-processing on the read (collected) data. In detail, the data is searched (GREP) for each TID. Then, the data is sorted by the time stamp unit 17 and then visualized.

[0067] Here, an example has been shown in which the event generator acquires the event type, data type, and any data from the input data when an event is detected, but as described above, the computer system 10 can operate even if the event type, data type, and any data are not acquired, as long as at least the timestamp value is acquired.

[0068] <Addition / removal of calculation sections and calculation units> In the computer system 10, the calculation units 11_1 to 11_N can be added or removed regardless of whether the computer system 10 is stopped or in operation.

[0069] Also, for example, in the calculation unit 11_1 shown in FIG. 3A, by newly arranging (adding) event generators 16_1_2 to 16_2_N and connecting them to the time stamp unit 17 and the trace buffer 18 as shown in FIG. 3B, calculation units 15_1(1) to 15_N(1) can be added.

[0070] Moreover, in the calculation unit 11_1, by deleting the event generators 16_1_2 to 16_2_N, the calculation units 15_1(1) to 15_N(1) can be deleted.

[0071] When the computing units 15_1(1) to 15_N(1) are added, a plurality of event generators 16_1_1 to 16_2_N can be arranged at arbitrary positions in the tracing units 14_1 to 14_N.

[0072] Here, the event generators 16_1_1 to 16_2_N may be disposed both before the inputs and after the outputs of the arithmetic units 15_1(1) to 15_N(1), or may be disposed either before the inputs or after the outputs.

[0073] When the computing units 15_1(1) to 15_N(1) are deleted, the event generators 16_1_1 to 16_2_N before and after the computing units 15_1(1) to 15_N(1) in the tracing units 14_1 to 14_N may be deleted.

[0074] Here, both the event generators in the front input stage and the rear output stage of the computing units 15_1(1) to 15_N(1) to be deleted may be deleted, or either one of the event generators in the front input stage or the rear output stage may be deleted.

[0075] According to this embodiment, multiple event generators can be added at any location. Therefore, by simply adding a new event generator, a new arithmetic unit can be easily added inside the arithmetic unit, making it possible to measure the processing time in the arithmetic unit and collect trace data.

[0076] Furthermore, since multiple event generators can be deleted from any location, by deleting only the event generators, it is possible to easily delete a computing unit within the computing unit.

[0077] Furthermore, when adding a computing unit, the circuit scale can be reduced and power consumption can be suppressed compared to when an event generator, a time stamp unit, and a trace buffer are all added.

[0078] When deleting a computing unit from the computing section, the event generators arranged before and after the computing unit may be deleted. At this time, trace data related to the event generators may be deleted. Also, trace data associated with events detected by the deleted event generators does not necessarily need to be deleted.

[0079] <First Example> A control method for the computer system 10 according to the first embodiment of the present invention will be described with reference to FIGS. 4A and 4B.

[0080] In this embodiment, in the computer system 10, the trace data recorded by the trace units 14_1 to 14_N of the calculation units 11_1 to 11_N are used to efficiently resume processing when a malfunction occurs. Here, the malfunction refers to a packet loss that may normally occur, a process stuck in a functional block inside the calculation units 11_1 to 11_N, etc.

[0081] In the computer system 10, for example, the trace unit 14_1 of the calculation unit 11_1 records a time stamp value, an instance ID (information indicating a location where an event is detected), and arbitrary data as arbitrary trace data in the trace buffer 18.

[0082] As an example of a control method of the computer system 10 according to this embodiment, a case in which the host unit 12 performs control (management) will be described with reference to FIG. 4A.

[0083] First, the host unit 12 monitors the trace buffer 18 of the computer system at a predetermined period and measures the processing time in the processing unit (step S11A).

[0084] Here, in measuring the processing time, first, the host unit 12 reads (acquires) from the trace buffer 18 a first time stamp value and a second time stamp value triggered by the detection of a specified event (first event, second event) in the event generator 16_1_1 (first event generator) on the input side of the calculator 15_1(1) and the event generator 16_2_1 (second event generator) on the output side of the calculator 15_1(1).

[0085] Subsequently, the host unit 12 calculates the processing time from the difference between the first time stamp value and the second time stamp value.

[0086] In this way, the processing time of any location (section, for example, calculator 15_1(1)) is obtained by calculating the difference between the times (the first time stamp value and the second time stamp value) at which the input data passes through each of the event generators placed at any location (section, for example, before or after calculator 15_1(1)).

[0087] Next, the measured processing time is compared with a preset predetermined threshold (step S12A). If the processing time is longer than the predetermined threshold, it is determined that a malfunction has occurred.

[0088] Finally, if a problem occurs, the process detection point is identified from the instance ID, and processing is resumed using any data recorded in any of the trace buffers 18 before the process detection point (step S13A).

[0089] As an example of a control method for the computer system 10 according to the present embodiment, a case in which the calculation units 11_1 to 11_N perform control (management) will be described with reference to FIGS. 4B and 4C.

[0090] First, the calculation units 11_1 to 11_N record trace data and monitor the trace buffer 18 at a predetermined period, and measure the time (hereinafter referred to as the "processing time between calculation units") from when a timestamp value is recorded in the trace buffer 18 of any calculation unit (e.g., calculation unit 11_1) to when the data is input to the calculator 15_1(2) of the next-stage calculation unit (e.g., calculation unit 11_2) (step S11B).

[0091] In measuring the processing time between the calculation units, for example, as shown in FIG. 4C, first, the event generator 16_2_1 in the preceding stage of the trace buffer 18 of the calculation unit 11_1 acquires a time stamp value (first stamp value), which is then recorded in the trace buffer 18 of the calculation unit 11_1.

[0092] Subsequently, a notification signal is transmitted from the trace buffer 18 of the calculation unit 11_1 to the calculator 15_1(2) of the calculation unit 11_2 (dotted arrow in the figure), and this signal triggers data transfer from the calculator 15_1(1) of the calculation unit 11_1 to the calculator 15_1(2) of the calculation unit 11_2.

[0093] Subsequently, upon detection of an event in the data input to the calculator 15_1(2) of the calculation unit 11_2, the event generator 16_1_1 in the preceding stage of the calculator 15_1(2) of the calculation unit 11_2 acquires a time stamp value (second stamp value), which is recorded in the trace buffer 18 of the calculation unit 11_2.

[0094] The processing time between the calculation units is measured from the difference between the first stamp value and the second stamp value.

[0095] Next, the measured processing time is compared with a preset predetermined threshold (step S12B). If the measured processing time is longer than the predetermined threshold, it is determined that a malfunction has occurred.

[0096] Finally, if a malfunction occurs, processing is resumed using any data recorded in any of the trace buffers 18 preceding the processing detection point identified by the instance ID recorded in the trace buffer 18 (step S13B).

[0097] Here, an example has been given in which the processing time is measured using the time stamp value recorded in the trace buffer, but the processing time may also be measured directly using the time stamp value acquired by the event generator.

[0098] Thus, in the control method of a computer system according to this embodiment, an event generator placed at an arbitrary location detects a specific event and, as a result of this, acquires one timestamp value, and an event generator placed at another location similarly acquires another timestamp value, and by calculating the difference between the one timestamp value and the other timestamp value, it is determined that a malfunction has occurred and processing is resumed.

[0099] According to the control method of the computer system of this embodiment, by using the trace data recorded by the trace units 14_1 to 14_N, when a malfunction occurs, it is possible to resume processing by tracing back to the point where processing was working normally, without restarting the processing from the beginning.

[0100] Moreover, the trigger for restarting the processing of the trace data is managed by the host unit 12. Alternatively, it may be managed by the calculation units 11_1 to 11_N.

[0101] Furthermore, the restart of processing does not necessarily have to be limited to a specific functional block. For example, processing may be restarted going back to the input to the calculation unit.

[0102] In this embodiment, an example has been shown in which the processing detection location is identified by the instance ID, but this is not limited to the above, and the processing detection location may be derived using a preset processing speed of a computing unit and a measured timestamp value.

[0103] In this embodiment, an example has been shown in which the processing time is used to grasp the occurrence of a defect, but the present invention is not limited to this, and data flow rate (described later) or the like may also be used.

[0104] In this embodiment, the trace data may have a data type and an event type. Furthermore, the trace data may be recorded for each data type or each event type.

[0105] <Second Example> A control method for a computer system according to a second embodiment of the present invention will be described with reference to Fig. 5. In this embodiment, in the computer system, quality management (state management / health check) of the system is performed by using tracing units 14_1 to 14_N of computing units 11_1 to 11_N.

[0106] In the computer system 10, for example, the tracing section 14_1 of the calculation section 11_1 includes a plurality of event generators 16_1_1 to 16_2_N.

[0107] FIG. 5 is a flowchart showing a control method of the computer system 10 according to the present embodiment.

[0108] First, for example, the calculation unit 11_1 of the computer system 10 uses a plurality of event generators 16_1_1 to 16_2_N to collect the time when data passes through each of the event generators 16_1_1 to 16_2_N (step S21).

[0109] In detail, the calculation unit 11_1 collects timestamp values ​​(e.g., a first timestamp value and a second timestamp value) based on detection of a predetermined event in each of the event generators (e.g., the event generator 16_1_1 and the event generator 16_2_1) located at different locations.

[0110] Next, the difference between the collected first time stamp value and second time stamp value is obtained to calculate the time required to pass through a specific section in the calculation unit 11_1, that is, the processing time (step S22).

[0111] Next, the processing time is compared with a preset predetermined threshold value (step S23).

[0112] If the comparison result indicates that the processing time is greater than the threshold, the detection of an abnormality in the computer system 10 is notified (step S24).

[0113] In this way, according to the computer system management method of this embodiment, it is possible to monitor whether the computer system is operating normally or not.

[0114] Also, time analysis processing does not necessarily have to be performed on all data. For example, by observing the time (processing time) required to pass through a specific section in the calculation units 11_1 to 11_N at a predetermined measurement interval and judging whether the processing time falls within a predetermined range or exceeds a predetermined threshold, it is possible to monitor whether the computer system is operating normally.

[0115] Also, test data may be input and the time required for this data to pass through the inside of the calculation units 11_1 to 11_N may be analyzed.

[0116] In this embodiment, an example has been shown in which the processing time is measured directly using the timestamp value acquired by the event generator, but the processing time may also be measured using the timestamp value recorded in the trace buffer after recording the timestamp value in the trace buffer.

[0117] In this embodiment, an example has been shown in which the status of a computer system is grasped using processing time, but the present invention is not limited to this, and data flow rate or the like may also be used.

[0118] In this embodiment, an example has been shown in which the calculation unit controls the computer system, but the host unit may also control the computer system.

[0119] In this embodiment, the trace data may include a data type along with a timestamp value. It may further include an instance ID, an event type, and arbitrary data. Also, the trace data may be recorded for each data type or event type.

[0120] <Third Example> A control method for a computer system 10 according to a third embodiment of the present invention will be described with reference to Fig. 6. In this embodiment, in the computer system 10, flow management of the computer system 10 is executed using the trace units 14_1 to 14_N of the operation units 11_1 to 11_N.

[0121] In the computer system 10, the trace units 14_1 to 14_N of the calculation units 11_1 to 11_N record a time stamp value and an instance ID (information indicating a location where an event is detected) as trace data in the trace buffer 18, and the host unit 12 reads out the trace data.

[0122] FIG. 6 is a flowchart showing a control method of the computer system 10 according to this embodiment.

[0123] First, the host unit 12 collects, as trace data from the trace buffer 18, for example, timestamp values ​​and instance IDs (information indicating the location where an event is detected) acquired by the event generator 16_1 at an arbitrary location for different events (step S31).

[0124] In detail, the event generator 16_1 collects the time stamp values ​​of the beginning and end of passing data that are acquired upon detection of events, such as the beginning and end of the data, and stored in the trace buffer 18.

[0125] Next, the difference between the timestamp value at the beginning and the timestamp value at the end is calculated as the data transit time.

[0126] Next, the amount of data per unit time (data flow rate) at a predetermined location is calculated by dividing the amount of input data (or output data) that is set in advance by the time it takes for the data to pass (step S32).

[0127] Next, the data flow rate is compared with a preset predetermined threshold value (step S33).

[0128] If the comparison result shows that the data flow rate is greater than the threshold, a data flow (path) is set to avoid data concentration. For example, when allocating a path, a path that exceeds a predetermined threshold identified by an instance ID (information indicating a location where an event is detected) is avoided and a path is set (step S34).

[0129] In this way, according to the computer system management method of this embodiment, it is possible to set a data flow (route) so as to avoid data concentration.

[0130] In this embodiment, an example has been given in which the processing time is measured using the time stamp value recorded in the trace buffer, but the processing time may also be measured directly using the time stamp value acquired by the event generator.

[0131] Also, although an example has been given in which the host unit controls the computer system, the calculation unit may control the computer system.

[0132] Furthermore, if the trace data includes information about the data type, the host unit 12 can grasp the operating status for each data type.

[0133] As a result, in the computer system 10, when data is concentrated only in a specific flow, data can be migrated from that flow to other flows with lower loads, thereby preventing data concentration and enabling flow management.

[0134] The trace data may be recorded by instance ID, event type, or arbitrary data. The trace data may be recorded by data type or event type.

[0135] Furthermore, if a fault that has occurred in a specific flow or at a specific location is detected, the flow can be managed so that a route that bypasses the flow is set when a fault occurs.

[0136] Furthermore, if a malfunction occurs in a calculation unit having multiple flows with different data paths, flows other than the malfunction can be diverted to other calculation units, and then the calculation unit can be replaced, reset, analyzed, etc.

[0137] <Example of calculation unit measurement> In the control method of the computer system 10 according to the present embodiment, an example of measuring the processing time and data flow rate in the calculation unit will be described with reference to FIGS. 7A and 7B.

[0138] In this measurement example, for example, input data is observed by an event generator 16_1_1 in the previous stage of the arithmetic unit 15_1(1), and input data is observed by an event generator 16_2_1 in the subsequent stage.

[0139] When the head of the input data passes through the event generator 16_1_1, an event occurs and the timestamp value of the head of the input data is acquired by the event generator 16_1_1.

[0140] Similarly, when the end of the input data passes through the event generator 16_1_1, an event occurs and the timestamp value of the end of the input data is acquired by the event generator 16_1_1.

[0141] On the other hand, when the head of the output data passes through the event generator 16_2_1, an event occurs and the timestamp value of the head of the output data is acquired by the event generator 16_2_1.

[0142] Similarly, when the end of the output data passes through the event generator 16_2_1, an event occurs and the timestamp value of the end of the output data is acquired by the event generator 16_2_1.

[0143] An example of trace data is shown in Fig. 7A, which shows a timestamp value (Timestamp:Dec, Timestamp:0x), an instance ID (Ins), an event ID (Evt), a decoded event ID (Dec), a TID, and event data (EventData).

[0144] In the decoded event ID (Dec), H indicates the beginning of the data and L indicates the end of the data.

[0145] The amount of input data and output data is 1 MB. The operating frequency of the arithmetic units 11_1 to 11_N is 250 MHz (4 ns / cycle).

[0146] The timestamp value (Timestamp:Dec) of the beginning of the input data is "406514" and the instance ID (Ins) is "10" (upper part of dotted box 41). In addition, the event ID (Dec) "HR-" indicates the passage of the beginning of the data as an event occurrence.

[0147] Similarly, the timestamp value (Timestamp:Dec) at the beginning of the output data is "401656" and the instance ID (Ins) is "11" (lower row within dotted box 41). Also, the event ID (Dec) "HR-" indicates the passing of the beginning of the data as an event occurrence.

[0148] The timestamp value (Timestamp:Dec) of the end of the input data is "547791" and the instance ID (Ins) is "10" (upper row inside dotted line box 42). The event ID (Dec) "-LR-" indicates the passing of the end of the data as an event occurrence.

[0149] Similarly, the timestamp value (Timestamp:Dec) at the beginning of the output data is "547794" and the instance ID (Ins) is "11" (lower row within dotted line box 42). Also, the event ID (Dec) "-LR-" indicates the passing of the end of the data as an event occurrence.

[0150] 7B shows a schematic diagram of the relationship between input data 43 and output data 44. The time it takes for the input data 43 to pass through the event generator 16_1_1 is calculated as 146227 cycles = 584.9 μsec from the difference (arrow 45) between the last timestamp value (547791 cycles) and the first timestamp value (401564 cycles). Therefore, the input throughput, i.e., the data flow rate, is 1MB / 584.9 μsec = approximately 1.8GB / sec.

[0151] Similarly, the input throughput, that is, the data flow rate, can be calculated from the difference (arrow 46) between the timestamp value at the end of the output data 44 and the timestamp value at the beginning.

[0152] In this way, in the calculation unit, the data flow rate is obtained by dividing the amount of data by the difference between the beginning and end of the timestamp value of the data.

[0153] In addition, the processing time (latency) is 92 cycles, calculated from the difference between the timestamp values ​​at the start of output and the start of input, i.e., the difference between the timestamp value at the beginning of output data 44 (401,656 cycles) and the timestamp value at the beginning of input data 43 (401,564 cycles).

[0154] In this way, in the calculation unit, the processing time of the input data is obtained from the difference between the timestamp values ​​of the output start and the input start.

[0155] As described above, in the computer system control method according to the present invention, the data processing time and data flow rate can be obtained using the timestamp values ​​of the input data and output data.

[0156] <Effects> According to the computer system and its management method relating to the embodiment and example of the present invention, when a calculation process in a computer system stops midway or does not complete normally, it is possible to easily detect and identify the calculation unit among multiple calculation units whose processing has stopped.

[0157] In addition, since the trace buffer 18 records data, processing can be resumed from the middle of the process. As a result, it is not necessary to repeat processing that has already been executed from the beginning. In addition, when processing does not complete normally, the processing time can be reduced.

[0158] Furthermore, since the host unit 12 can centrally manage the status of each processing element, it is possible to set up a data flow that does not pass through a processing element where processing has stopped, for example, thereby reducing the amount of data whose processing is not completed normally.

[0159] In addition, since events can be detected for each data type (user ID, session ID, stream ID, service ID) and trace data can be accumulated, quality control, defect analysis, etc. can be easily performed by focusing on specific data types.

[0160] Furthermore, since the tracing units 14_1 to 14_N are provided independent of the calculation units, the abnormal state of the calculation units can be detected.

[0161] In addition, the flow can be managed at the granularity of each user (each session).

[0162] In addition, an event generator that detects an event can be inserted at any point, making it possible to detect problems that occur only in a specific flow.

[0163] <Second embodiment> A computer system and a control method thereof according to a second embodiment of the present invention will be described with reference to Fig. 8. A computer system 10 according to this embodiment has a similar configuration to that of the first embodiment.

[0164] In the computer system 10 according to the first embodiment, the trace buffer 18 overflows, making it difficult to record the trace data, so it is necessary to erase the trace data.

[0165] <Control method of computer system> FIG. 8 shows a flowchart of a control method for a computer system according to this embodiment.

[0166] In the computer system according to this embodiment, at least a data type is recorded as trace data together with a timestamp value in the trace buffer 18. Here, an instance ID, an event type, or any data may be recorded as trace data. Alternatively, trace data may be recorded for each data type or event type.

[0167] First, the host unit 12 monitors the trace buffers 18 of the calculation units 11_1 to 11_N at a predetermined cycle (step S51).

[0168] Next, it is determined whether or not a plurality of trace data for the same data type are recorded in the trace buffer 18 (step S52).

[0169] If it is determined that multiple pieces of trace data for the same data type are recorded in the trace buffer 18, the trace data with the most recent timestamp value is retained (recorded) from among the multiple pieces of trace data, and previously recorded trace data (trace data other than the most recent trace data) is erased (step S53).In this way, the detection time of the event recorded in the trace buffer is erased based on the detection time of the event.

[0170] According to the computer system and the control method thereof according to the present embodiment, even if the storage capacity of the trace buffer 18 is limited, it is possible to prevent buffer overflow and reduce the physical buffer amount.

[0171] Furthermore, since there is no need to provide an excessive amount of buffer, the power consumption of the calculation unit can be reduced, improving power efficiency.

[0172] In addition, by recording trace data for each data type (user ID, session ID, stream ID, service ID), it is possible to provide a highly flexible computer system, such as by retaining trace data for specific data types (such as the highest priority services) for relatively long periods of time, thereby increasing reliability.

[0173] Naturally, this embodiment has the same effects as the first embodiment.

[0174] <Modification 1 of the second embodiment> A computer system and a control method thereof according to a first modified example of the second embodiment of the present invention will be described below. A computer system 10 according to this modified example has a similar configuration to that of the first embodiment.

[0175] In the computer system according to this modification, at least a data type is recorded as trace data together with a timestamp value in the trace buffer 18. Here, an instance ID, an event type, or any data may be recorded as trace data. Alternatively, trace data may be recorded for each data type or event type.

[0176] In this modified example, before the calculation units 11_1 to 11_N of the computer system 10 record (write) the trace data (latest trace data) received from the event generators 16_1_1 to 16_2_N in the trace buffer 18, they determine whether or not trace data of the same data type as the latest trace data is recorded among the trace data already held in the trace buffer 18.

[0177] If the result of the determination is that trace data of the same data type has been recorded, the data already held (data other than the latest data) is erased, and the latest trace data is subsequently recorded, i.e., the latest trace data is overwritten. In this way, the detection time of the event recorded in the trace buffer is overwritten based on the detection time of the event.

[0178] Here, a flag or the like may be added to prevent overwriting, and the permission of overwriting may be determined based on the presence or absence of the flag.

[0179] This provides the same effect as this embodiment.

[0180] <Modification 2 of the second embodiment> A computer system and a control method thereof according to a second modification of the second embodiment of the present invention will be described below. A computer system 10 according to this modification has a similar configuration to that of the first embodiment.

[0181] In the computer system according to this modification, at least a time stamp value is recorded as trace data in the trace buffer 18. Here, the trace data may be a data type, an instance ID, an event type, or any other data. Alternatively, the trace data may be recorded for each data type or event type.

[0182] In this modification, first, data processed by the calculator 15_1(1) in the calculation unit 11_1 at the front stage is transmitted to the calculator 15_1(2) in the calculation unit 11_2 at the rear stage.

[0183] Next, the latter-stage calculation portion 11_2 sends a reception completion notification to the former-stage calculation portion 11_1.

[0184] Finally, when the front-stage calculation unit 11_1 receives a reception completion notification from the rear-stage calculation unit 11_2, it erases the data in the trace buffer 18 of the front-stage calculation unit 11_1.

[0185] Alternatively, the subsequent-stage calculation unit 11_2 may send a reception completion notification to the host unit 12 and erase the data in the trace buffer 18 of the previous-stage calculation unit 11_1 in response to an instruction from the host unit 12.

[0186] This provides the same effect as this embodiment.

[0187] Also, in this embodiment, when the host unit 12, which has a larger storage capacity than the trace buffer 18, collects and records data from the trace buffer 18, the data from the trace buffer 18 may be erased when the host unit 12 collects the data or when the collection is completed.

[0188] In this embodiment, the data in the trace buffer 18 may be erased when a preset time has elapsed.

[0189] <Third embodiment> A computer system and a control method thereof according to a third embodiment of the present invention will now be described. A computer system 10 according to this embodiment has a similar configuration to that of the first embodiment.

[0190] In the computer system 10 according to the first embodiment, since the multiple calculation units operate in conjunction with each other, it is difficult to synchronize the times of the timestamps measured by the multiple calculation units.

[0191] In particular, when the operating frequencies of the respective processing units are different, the values ​​of the clock counters based on the operating frequencies are different, making it difficult to synchronize the times of the time stamps.

[0192] <Control method of computer system> In the computer system and the control method thereof according to the present embodiment, the host unit 12 centrally sets the time stamp value to a predetermined value, for example, an initial value. Fig. 9 shows a flowchart of the control method of the computer system according to the present embodiment.

[0193] First, the host unit 12 sets a predetermined value as the initial value of the time stamp value (step S61).

[0194] Here, the time stamp value when the calculation units 11_1 to 11_N start measuring the input data may be set as the initial value.

[0195] Alternatively, the host unit 12 may write the start of counting to the time stamp unit 17, and the time stamp value at the time when the counting starts may be set as the initial value.

[0196] Next, each of the calculation units 11_1 to 11_N acquires a time stamp value (step S62).

[0197] Next, the host unit 12 compares the acquired timestamp value with a predetermined reference value for the timestamp value (step S63).

[0198] Here, the predetermined reference value for the time stamp value is set in advance. The predetermined reference value indicates a predetermined value of the time stamp value, for example, an allowable range of deviation from an initial value.

[0199] Finally, when the timestamp value of each of the calculation units 11_1 to 11_N exceeds the allowable range of a predetermined reference value, the host unit 12 resets the timestamp value of each of the calculation units 11_1 to 11_N to a predetermined value, for example, an initial value (step S64).

[0200] According to the computer system and its control method of this embodiment, when calculation units with different operating frequencies coexist (for example, when the operating frequency differs depending on the calculation content of the calculation unit), the timestamp values ​​can be handled uniformly, making it easy to analyze the trace data after it is collected.

[0201] In addition, since it becomes possible to easily synchronize a plurality of calculation units, scalability can be improved.

[0202] Furthermore, since the host unit 12 centrally sets the time stamp value to a predetermined value, for example, an initial value, when the measurement starts, etc., the deviation of the clock counters between the calculation units can be easily corrected.

[0203] Naturally, this embodiment has the same effects as the first embodiment.

[0204] <Modification 1 of the third embodiment> A computer system and a control method thereof according to a first modified example of the third embodiment of the present invention will be described below. A computer system 10 according to this modified example has a similar configuration to that of the first embodiment.

[0205] In this modification, when the frequencies differ among the arithmetic units 11_1 to 11_N, the host unit 12 adjusts the difference in the operating frequencies among the arithmetic units 11_1 to 11_N.

[0206] For example, if the frequency of calculation unit 11_1 is 100 MHZ, one clock cycle is 10 nanoseconds, and the frequency of calculation unit 11_2 is 200 MHZ, one clock cycle is 5 nanoseconds, the host unit 12 doubles the timestamp value of calculation unit 11_1, thereby synchronizing the timestamp values ​​of calculation unit 11_1 and calculation unit 11_2.

[0207] Furthermore, the host unit 12 may halve the timestamp value of the calculation unit 11_2 to synchronize the timestamp values ​​of the calculation units 11_1 and 11_2.

[0208] Also, after the host unit 12 reads out the trace data, a conversion reference value (eg, 100 MHZ) may be set and the counter values ​​of all the calculation units may be converted to match the reference value 100 MHZ.

[0209] Thus, in the computer system and control method thereof according to this modified example, the host unit multiplies the timestamp value of one of the computing units (e.g., computing unit 11_2) by a coefficient set in the other computing unit (e.g., computing unit 11_2) so that the operating frequency of the other computing unit (e.g., computing unit 11_2) is the same as the operating frequency of the other computing unit (e.g., computing unit 11_1). Here, there may be more than one other computing unit. In this way, the difference between the counter values ​​that differ for each computing unit is adjusted.

[0210] As a result, the counter values ​​of the respective calculation units become the same, and the same effect as that of this embodiment is achieved.

[0211] <Modification 2 of the third embodiment> A computer system and a control method thereof according to a second modification of the third embodiment of the present invention will be described below. A computer system 10 according to this modification has a similar configuration to that of the first embodiment.

[0212] In this modification, when the frequencies differ among the calculation units 11_1 to 11_N, the difference in the operating frequencies is adjusted among the calculation units 11_1 to 11_N.

[0213] First, a different conversion value (coefficient) is set in advance for each calculator according to the frequency. For example, when the frequency of the calculator 11_1 is 100 MHZ and the frequency of the calculator 11_2 is 200 MHZ, if the reference value is set to 100 MHZ, the conversion value (coefficient) of the calculator 11_1 is "1" and the conversion value (coefficient) of the calculator 11_2 is "1 / 2".

[0214] Next, before the timestamp value is recorded in the trace buffer 18, a value obtained by multiplying the timestamp value by a conversion value (coefficient) is recorded.

[0215] Moreover, after the time stamp value is recorded in the trace buffer 18, the clock counter value may be similarly converted when it is read out.

[0216] In this way, in the computer system and the control method thereof according to this modified example, in the stage preceding the trace buffer of one arithmetic unit (e.g., arithmetic unit 11_1), a coefficient set in the other arithmetic unit (e.g., arithmetic unit 11_2) is multiplied by the timestamp value of the other arithmetic unit (e.g., arithmetic unit 11_2) so that the operating frequency of the other arithmetic unit (e.g., arithmetic unit 11_2) is the same as the operating frequency of the other arithmetic unit. Here, there may be more than one other arithmetic unit. In this way, the difference between the counter values ​​that differ for each arithmetic unit is adjusted.

[0217] As a result, the counter values ​​of the respective calculation units become the same, and the same effect as that of this embodiment is achieved.

[0218] In an embodiment of the present invention, when the calculation unit performs measurements of processing time, data flow rate, etc., and judgments of malfunctions, etc., a calculator in the calculation unit may perform these measurements, or separate processing functions for measurement, judgment, etc. may be provided within the calculation unit.

[0219] In the embodiment of the present invention, further effects can be achieved by combining the first embodiment, the second embodiment, and the third embodiment.

[0220] In the embodiment of the present invention, the structure, dimensions, materials, etc. of each component in the configuration and management method of the computer system are shown as examples, but the present invention is not limited to these. Anything that can exert the functions and effects of the computer system can be used. [Industrial Applicability]

[0221] The present invention can be applied to computer systems in the field of information processing. [Explanation of symbols]

[0222] 10. Computer Systems 11_1~11_N Arithmetic unit 12 Host Division 13 Internal Communications Department 14_1~14_N Trace section

Claims

1. 1. A method for controlling a computer system comprising a plurality of processors and a host unit, each of the processors comprising a trace buffer, the method being configured to record, in the trace buffer, a detection time of a predetermined event from input data, the detection time being obtained based on an operating frequency of the processors for each type of input data, the method comprising: a step in which either the host unit or the calculation unit determines a type of the input data to which the detection time of the event recorded in the trace buffer belongs; a step in which either the host unit or the calculation unit records a detection time of the latest event among the detection times of the events belonging to the same type of the input data according to a result of the determination, and erases the detection times of the events other than the detection time of the latest event; A method for controlling a computer system comprising:

2. the host unit periodically monitors the trace buffer; When the detection times of a plurality of the events belong to the same type of the input data, the host unit erases the detection times of the events recorded in the trace buffer based on the detection times of the events.

2. The method for controlling a computer system according to claim 1.

3. The calculation unit executes the determination before the recording, and if the detection time of the event belongs to the same type of the input data, overwrites the detection time of the event recorded in the trace buffer based on the detection time of the event.

2. The method for controlling a computer system according to claim 1.

4. A method for controlling a computer system, wherein each of a plurality of arithmetic units includes an arithmetic unit and a trace buffer, and upon detection of a predetermined event from input data, a detection time of the event, which is obtained based on an operating frequency of the arithmetic units, is recorded in the trace buffer, the method comprising: a step in which a computing unit of one of the plurality of computing units processes the input data and transfers the input data to a computing unit of another computing unit; the other computing unit transmitting a reception completion notification; when the one of the computing units receives the reception completion notification, erasing the detection time of the event recorded in the trace buffer of the one of the computing units; A method for controlling a computer system comprising:

5. A method for controlling a computer system, wherein each of a plurality of arithmetic units includes an arithmetic unit and a trace buffer, and upon detection of a predetermined event from input data, a detection time of the event, which is obtained based on an operating frequency of the arithmetic units, is recorded in the trace buffer, the method comprising:

11. A method for controlling a computer system, comprising the steps of: erasing the detection times of the events recorded in the trace buffer when a predetermined time has elapsed.

6. 1. A computer system for processing input data, comprising: A plurality of calculation units; a host unit connected to the plurality of calculation units and controlling the plurality of calculation units; Equipped with The processed data is transferred between the plurality of computing units; The calculation unit detects a predetermined event from the input data and then generates a trace buffer for recording trace data. Equipped with the trace data has a timestamp value that is a detection time of the event based on an operating frequency of the processor; Either the host unit or the calculation unit erases the trace data recorded in the trace buffer under a predetermined condition.

23. A computer system comprising:

7. The trace data further includes at least one of a type of the input data, information indicating a location where the event is detected, information distinguishing the content of the event, and arbitrary data.

7. The computer system of claim 6.

8. When the plurality of trace data recorded in the trace buffer belong to the same type of input data, either the host unit or the arithmetic unit holds the latest trace data among the plurality of trace data, and erases the trace data other than the latest trace data.

8. A computer system according to claim 6 or claim 7.

9. Among the plurality of arithmetic units, a calculator of one arithmetic unit processes the input data and transfers it to a calculator of another arithmetic unit; The other computing unit receives the transferred data and transmits a reception completion notification; The one of the computing units receives the reception completion notification and erases the detection time of the event recorded in the trace buffer of the one of the computing units.

8. A computer system according to claim 6 or claim 7.

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