Semiconductor Device

Abstract

This semiconductor device comprises a semiconductor chip including a semiconductor substrate and a main electrode disposed on the semiconductor substrate, a buffer plate, and a bonding material disposed between the main electrode and the buffer plate, the main electrode including an aluminum or aluminum alloy layer. A first linear expansion rate of the semiconductor substrate and a second linear expansion rate of the buffer plate are smaller than a third linear expansion rate of the main electrode, and the second linear expansion rate is smaller than the first linear expansion rate.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] As an example of a semiconductor device suitable for a power module, a semiconductor device has been proposed in which a buffer plate is bonded to an electrode containing aluminum of a semiconductor chip, and bonding wires are bonded to the buffer plate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-186220 [Patent Document 2] Japanese Patent Application Publication No. 2017-005037 [Patent Document 3] Japanese Patent Publication No. 2019-057663 Summary of the Invention

[0004] The semiconductor device disclosed herein comprises a semiconductor chip having a semiconductor substrate and a main electrode provided on the semiconductor substrate, a buffer plate, and a bonding material provided between the main electrode and the buffer plate, wherein the main electrode includes an aluminum or aluminum alloy layer, a first linear expansion coefficient of the semiconductor substrate and a second linear expansion coefficient of the buffer plate are smaller than a third linear expansion coefficient of the main electrode, and the second linear expansion coefficient is smaller than the first linear expansion coefficient. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a top view showing the semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view showing an example of a source electrode. [Figure 4]FIG. 4 is a top view showing the semiconductor device according to the second embodiment. [Diagram 5] FIG. 5 is a cross-sectional view showing the semiconductor device according to the second embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing a bonding material between an anode electrode and a buffer plate in the third embodiment. [Figure 7] FIG. 7 is a cross-sectional view showing a bonding material between an anode electrode and a buffer plate in the fourth embodiment. [Figure 8] FIG. 8 is a diagram showing crystal grains constituting the wire and the second copper layer. [Figure 9] FIG. 9 shows an example of the results of the power cycle test (part 1). [Figure 10] FIG. 10 shows an example of the results of the power cycle test (part 2). [Figure 11] FIG. 11 is a schematic diagram (part 1) showing the change in deformation amount due to temperature change. [Figure 12] FIG. 12 is a schematic diagram (part 2) showing the change in deformation amount due to temperature change. [Figure 13] FIG. 13 is a schematic diagram (part 3) showing the change in deformation amount due to temperature change. [Figure 14] FIG. 14 is a diagram showing the change in linear expansion coefficient with temperature change. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] [Problem that this disclosure aims to solve] In conventional semiconductor devices, failures such as peeling off due to internal breakdown of the main electrodes containing aluminum can occur.

[0007] [Effects of this disclosure] According to the present disclosure, internal destruction of a main electrode containing aluminum can be suppressed.

[0008] The embodiments for carrying out the invention are described below.

[0009] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[0010] [1] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor chip having a semiconductor substrate and a main electrode provided on the semiconductor substrate, a buffer plate, and a bonding material provided between the main electrode and the buffer plate, wherein the main electrode includes an aluminum or aluminum alloy layer, a first linear expansion coefficient of the semiconductor substrate and a second linear expansion coefficient of the buffer plate are smaller than a third linear expansion coefficient of the main electrode, and the second linear expansion coefficient is smaller than the first linear expansion coefficient.

[0011] Since the third linear expansion coefficient is larger than the first linear expansion coefficient, the main electrode is likely to thermally deform more than the semiconductor substrate. This causes thermal stress to act on the main electrode. Therefore, as described below, in a power cycle test in which the application of a thermal load is repeated, thermal deformation occurs repeatedly, and the thermal stress causes deterioration of a semiconductor device, such as a power module, and ultimately leads to failure. On the other hand, since the buffer plate is bonded to the main electrode by the bonding material, the thermal deformation of the main electrode can be restrained by the buffer plate. At this time, as described below, since the second linear expansion coefficient is smaller than the first linear expansion coefficient, the thermal deformation of the main electrode can be more effectively suppressed by the bonding material. Therefore, the thermal stress generated in the main electrode due to thermal deformation can be suppressed, and internal destruction of the aluminum or aluminum alloy layer contained in the main electrode can be suppressed.

[0012] [2] In [1], when the thickness of the buffer plate is 0.05 mm or more and 0.25 mm or less, the first linear expansion coefficient is ρ1, and the second linear expansion coefficient is ρ2, the value of "ρ2-ρ1" is -2.8×10 -6 / ℃ or more -0.1×10 -6 / ° C. or less. In this case, it is easier to suppress the thermal stress generated in the main electrode.

[0013] [3] In [1], when the thickness of the buffer plate is 0.05 mm or more and 0.25 mm or less, the first linear expansion coefficient is ρ1, and the second linear expansion coefficient is ρ2, the value of "ρ2-ρ1" is -2.8×10 -6 / ° C. In this case, it is easier to suppress the thermal stress generated in the main electrode.

[0014] [4] In [1], when the thickness of the buffer plate is 0.10 mm or more and 0.20 mm or less, the first linear expansion coefficient is ρ1, and the second linear expansion coefficient is ρ2, the value of "ρ2-ρ1" is -2.0×10 -6 / ℃ or more -1.0×10 -6 / ° C. or less. In this case, it is easier to suppress the thermal stress generated in the main electrode.

[0015] [5] In [1] to [4], the thickness of the buffer plate may be smaller than the thickness of the semiconductor chip. In this case, as described in detail below, chipping, cracks, etc. of the semiconductor chip are easily suppressed, the failure rate is easily kept low, and heat is easily diffused through the buffer plate.

[0016] [6] In [1] to [5], the buffer plate is a laminated material or an iron-nickel alloy material, and the laminated material may have a first copper layer in contact with the bonding material, an iron-nickel alloy layer provided on the first copper layer, and a second copper layer provided on the iron-nickel alloy layer. In this case, by bonding the wire to the buffer plate, the wire can be electrically connected to the main electrode via the buffer plate. Therefore, even if ultrasonic bonding is used to bond the wire, damage to the semiconductor chip can be suppressed. When the buffer plate is an iron-nickel alloy material, the buffer plate does not have the first copper layer and the second copper layer, and the iron-nickel alloy material is connected to the wire.

[0017] [7] In [6], the first copper layer and the second copper layer may be equal in thickness, and the iron-nickel alloy layer may be 72 / 14 times or more the thicknesses of the first copper layer and the second copper layer. In this case, it is easy to keep the second linear expansion coefficient small.

[0018] [8] In any of [1] to [7], a wire may be connected to the buffer plate. In this case, electrical continuity between the main electrode and the outside can be ensured via the wire.

[0019] [9] In [8], the wire may be a copper wire, which makes it easier to bond the wire to the buffer plate and also makes it easier to obtain low electrical resistance for the wire.

[0020]

[10] In the structure of [8] or [9], crystal grains may be provided at the interface between the wire and the buffer plate, which straddles the wire and the buffer plate. In this case, a strong bond between the wire and the buffer plate can be easily obtained.

[0021]

[11] In the above [1] to [5], the buffer plate has a first copper layer in contact with the bonding material, an iron-nickel alloy layer provided on the first copper layer, and a second copper layer provided on the iron-nickel alloy layer, and further has a wire bonded to the buffer plate, the wire being a copper wire, and the interface between the wire and the buffer plate may have crystal grains that span the wire and the buffer plate. In this case, it is easy to obtain a strong bond between the wire and the second copper layer.

[0022]

[12] In the method of

[11] , the crystal grains may extend to the iron-nickel alloy layer. In this case, stronger bonding is more likely to be obtained.

[0023]

[13] In the structure of

[11] or

[12] , the first copper layer and the second copper layer may be equal in thickness, and the iron-nickel alloy layer may be 72 / 14 times or more the thicknesses of the first copper layer and the second copper layer. In this case, the second linear expansion coefficient is easily kept small.

[0024]

[14] In any one of [8] to

[13] , the bonding material may have a first region that overlaps with a portion of the buffer plate to which the wire is bonded when viewed from a direction perpendicular to the main surface of the semiconductor substrate, and a second region surrounding the first region, and the linear expansion coefficient of the first region may be lower than that of the second region. In this case, it is easy to reduce stress acting on the main electrode.

[0025]

[15] In

[14] , the first region may be made of silicon carbide, silicon, silicon oxide, silicon nitride, an iron-nickel alloy, molybdenum, or tungsten, and the second region may be made of a sintered body of an intermetallic compound containing copper, silver, nickel, or copper and tin. In this case, it is easy to reduce the stress acting on the main electrode while ensuring excellent bonding strength.

[0026]

[16] In any one of [8] to

[13] , a gap may be provided in the bonding material at a portion that overlaps with the portion of the buffer plate to which the wire is bonded when viewed from a direction perpendicular to the main surface of the semiconductor substrate, which makes it easier to reduce stress acting on the main electrode.

[0027]

[17] In any one of [1] to

[16] , the main electrode may have a plating layer, and the plating layer may be provided between the aluminum or aluminum alloy layer and the buffer plate. In this case, the main electrode is likely to have excellent corrosion resistance.

[0028]

[18] In any one of [1] to

[17] , in a power cycle test in which the maximum junction temperature of the semiconductor chip in each cycle is set to 200° C. or higher, the increase in the maximum junction temperature between 200,000 and 300,000 cycles may be 5.0° C. or less. In this case, the life span can be easily extended.

[0029]

[19] In any one of [1] to

[18] , when the buffer plate is heated from 25° C. to 250° C., and subsequently cooled from 250° C. to 25° C., and the linear expansion coefficient of the buffer plate during the heating and the cooling is continuously measured, the linear expansion coefficient of the buffer plate during the heating is ρ5 and the linear expansion coefficient of the buffer plate during the cooling is ρ4, the maximum value of "ρ5-ρ4" at the same temperature between 25° C. and 250° C. is 1.5×10 -6 / °C or less. In this case, the life is easily extended.

[0030]

[20] In any of [1] to

[19] , the semiconductor chip may be a silicon carbide chip. The silicon carbide chip has excellent high-temperature resistance and is unlikely to break down even when used at high temperatures. In addition, the silicon carbide chip has high mechanical properties. Furthermore, since internal destruction of the main electrode containing aluminum is suppressed, the semiconductor device as a whole is likely to have a long life even at high temperatures.

[0031] [Details of the embodiment of the present disclosure] Hereinafter, the embodiments of the present disclosure will be described in detail, but the present embodiment is not limited thereto. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant description. In this specification and drawings, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is defined as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is defined as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is defined as the ZX plane. For convenience, the Z1 direction is defined as the upward direction, and the Z2 direction is defined as the downward direction. In this disclosure, planar view refers to viewing an object from the Z1 side.

[0032] (First embodiment) The first embodiment relates to a semiconductor device. Fig. 1 is a top view showing the semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. Fig. 2 corresponds to a cross-sectional view taken along line II-II in Fig. 1.

[0033] As shown in FIGS. 1 and 2, the semiconductor device 1 according to the first embodiment mainly includes a heat sink 120, a substrate 110, a terminal 102, a terminal 103, a case 190, a diode 300, and a buffer plate 500.

[0034] The heat sink 120 is, for example, a rectangular plate-like body with a uniform thickness in a plan view. The material of the heat sink 120 is a metal with high thermal conductivity, such as copper (Cu), a copper alloy, aluminum (Al), an aluminum-silicon-carbon alloy (Al-Si-C alloy), etc. The heat sink 120 is fixed to a cooler or the like using a thermal interface material (TIM) or the like.

[0035] The case 190 is formed, for example, in a frame shape in a plan view, and the outer shape of the case 190 is the same as the outer shape of the heat sink 120. The material of the case 190 is an insulating material such as resin. The case 190 has a pair of side walls 191 and 192 facing each other, and a pair of end walls 193 and 194 connecting both ends of the side walls 191 and 192. The side walls 191 and 192 are arranged parallel to the ZX plane, and the end walls 193 and 194 are arranged parallel to the YZ plane. The side wall 191 is arranged on the Y1 side of the side wall 192, and the end wall 193 is arranged on the X2 side of the end wall 194.

[0036] Terminal 102 is disposed on the upper surface (surface on the Z1 side) of end wall portion 193, and terminal 103 is disposed on the upper surface (surface on the Z1 side) of end wall portion 194. Terminals 102 and 103 are each made of a metal plate.

[0037] Inside the case 190, the substrate 110 is disposed on the Z1 side of the heat sink 120. The substrate 110 has an insulating substrate 119, a second conductive pattern 112, a third conductive pattern 113, and a conductive layer 115. The first conductive pattern 111, the second conductive pattern 112, the third conductive pattern 113, the fourth conductive pattern 114, and the conductive layer 115 are made of Cu.

[0038] The second conductive pattern 112 and the third conductive pattern 113 are provided on the Z1 side surface of the insulating substrate 119. The conductive layer 115 is provided on the Z2 side surface of the insulating substrate 119. The conductive layer 115 is bonded to the heat sink 120 by a bonding material 131. The bonding material 131 may be a solder material or a sintered bonding material. When the bonding material 131 is a sintered bonding material, operation at a high temperature near the melting point of the solder or higher is possible.

[0039] As shown in FIG. 2, the diode 300 mainly includes a silicon carbide substrate 310 , an anode electrode 332 , and a cathode electrode 333 .

[0040] The silicon carbide substrate 310 has a main surface 310A and a main surface 310B opposite to the main surface 310A. The main surface 310A is on the Z1 side of the main surface 310B. The silicon carbide substrate 310 has, for example, a rectangular parallelepiped shape. The main surfaces 310A and 310B are parallel to the XY plane. The anode electrode 332 is provided on the main surface 310A, and the cathode electrode 333 is provided on the main surface 310B. The diode 300 is provided on the third conductive pattern 113. The anode electrode 332 includes, for example, an aluminum layer. The anode electrode 332 may include an aluminum alloy layer such as an aluminum-silicon alloy (Al-Si alloy) or an Al-Si-Cu alloy instead of the aluminum layer. The cathode electrode 333 has an ohmic layer and a junction layer provided on the ohmic layer. The ohmic layer includes, for example, nickel or a nickel alloy. Nickel or a nickel alloy has good contact resistance with silicon carbide. The bonding layer includes a nickel layer. The bonding layer may further include a gold layer or a silver layer provided on the nickel layer. The cathode electrode 333 has a bonding layer, so that good bonding is obtained between the cathode electrode 333 and the third conductive pattern 113. The cathode electrode 333 is bonded to the third conductive pattern 113 using a bonding material 133 such as a silver sintered body or a copper sintered body. The diode 300 is an example of a semiconductor chip. The silicon carbide substrate 310 is an example of a semiconductor substrate. The anode electrode 332 is an example of a main electrode.

[0041] The buffer plate 500 is, for example, a laminated material having a first copper layer 510, an iron-nickel alloy layer 520, and a second copper layer 530. The iron-nickel alloy layer 520 is provided on the Z1 side of the first copper layer 510, and the second copper layer 530 is provided on the Z1 side of the iron-nickel alloy layer 520. That is, the iron-nickel alloy layer 520 is provided on the first copper layer 510, and the second copper layer 530 is provided on the iron-nickel alloy layer 520. The iron-nickel alloy layer 520 is, for example, a layer of an iron-nickel alloy containing 36 mass% of nickel. The iron-nickel alloy layer 520 may contain about 0.7 mass% of manganese. The iron-nickel alloy layer 520 may contain about 17 mass% of cobalt. The material of the iron-nickel alloy layer 520 may be Invar (registered trademark). The thickness T2 of the buffer plate 500 is, for example, 0.05 mm or more and 0.25 mm or less. For example, the thickness T2 of the buffer plate 500 is smaller than the thickness T1 of the diode 300. The buffer plate 500 is provided on the anode electrode 332. A first copper layer 510 is bonded to the anode electrode 332 using a bonding material 135 such as a sintered silver body or a sintered copper body.

[0042] The silicon carbide substrate 310 has a first linear expansion coefficient ρ1, the buffer plate 500 has a second linear expansion coefficient ρ2, and the anode electrode 332 has a third linear expansion coefficient ρ3. In this disclosure, the linear expansion coefficient is the linear expansion coefficient in a direction parallel to the main surface 310A at 25° C., unless otherwise specified. In this disclosure, the linear expansion coefficient is the linear expansion coefficient when the silicon carbide substrate 310, the buffer plate 500, and the anode electrode 332 are released from the bonded state and are taken as a single body, unless otherwise specified. The first linear expansion coefficient ρ1 and the second linear expansion coefficient ρ2 are smaller than the third linear expansion coefficient ρ3, and the second linear expansion coefficient ρ2 is smaller than the first linear expansion coefficient ρ1. For example, when the first linear expansion coefficient ρ1 is 4.0×10 -6 / ℃, while the second linear expansion coefficient ρ2 is 1.2×10 -6 / ℃ or more 3.9×10 -6 / ℃ or less. In this case, the value of "ρ2-ρ1" is -2.8×10 -6 / ℃ or more -0.1×10 -6 / ℃ or less. The linear expansion coefficient of iron-nickel alloy is 1.2×10 -6 / ℃, and the linear expansion coefficient of copper is 16.5×10-6 / ℃, and the linear expansion coefficient of aluminum is 23.1×10 -6 / ℃.

[0043] The semiconductor device 1 further includes wires 162, 165, and 166. The number of each of the wires 162, 165, and 166 is not limited, and may be one, or may be two or more.

[0044] The wire 162 connects the second copper layer 530 of the buffer plate 500 and the second conductive pattern 112 to each other. The wire 165 connects the second conductive pattern 112 and the terminal 102 to each other. The wire 166 connects the third conductive pattern 113 and the terminal 103 to each other. The wires 162, 165, and 166 are, for example, copper wires. The diameter of each of the wires 162, 165, and 166 is, for example, not less than 100 μm and not more than 400 μm. The wires 162, 165, and 166 are bonded by, for example, ultrasonic bonding.

[0045] Here, when focusing on thermal deformation of the silicon carbide substrate 310 and the anode electrode 332, since the first linear expansion coefficient ρ1 is smaller than the third linear expansion coefficient ρ3, the anode electrode 332 may thermally deform to a greater extent than the silicon carbide substrate 310. Since the silicon carbide substrate 310 and the anode electrode 332 are firmly bonded to each other, the greater the difference between the first linear expansion coefficient ρ1 and the third linear expansion coefficient ρ3, the greater the thermal stress acting on the anode electrode 332, making it more likely that internal destruction will occur in the anode electrode 332.

[0046] On the other hand, the buffer plate 500 is bonded to the anode electrode 332 by the bonding material 135, and thermal deformation of the anode electrode 332 is restricted by the buffer plate 500. In this embodiment, the second linear expansion coefficient ρ2 of the buffer plate 500 is smaller than the first linear expansion coefficient ρ1. Therefore, the thermal deformation of the anode electrode 332 can be significantly suppressed by the bonding material 135. Therefore, according to this embodiment, it is possible to suppress thermal stress occurring in the anode electrode 332 due to thermal deformation, and to suppress internal destruction of the anode electrode 332 containing aluminum.

[0047] The thickness T2 of the buffer plate 500 is not particularly limited, and is, for example, 0.05 mm or more and 0.25 mm or less. The thickness T2 may be 0.07 mm or more and 0.23 mm or less, or 0.10 mm or more and 0.20 mm or less. If the thickness T2 is too large, the electrical resistance between the anode electrode 332 and the wire 162 may become excessively high, or the heat dissipation from the anode electrode 332 may be easily hindered. Also, if the thickness T2 is too small, it may become difficult to suppress the thermal deformation of the anode electrode 332.

[0048] It is preferable that the thickness T2 of the buffer plate 500 is smaller than the thickness T1 of the diode 300. This is because the inventors of the present application have confirmed the following three points through systematic testing and analysis thereof.

[0049] First, it has been confirmed that chipping, cracking, and the like are likely to occur in the diode 300 at the mounting and assembly stage where the buffer plate 500 thicker than the diode 300 is mounted. This is because the first linear expansion coefficient ρ1 of the silicon carbide substrate 310 and the second linear expansion coefficient ρ2 of the buffer plate 500 are different from each other, and therefore the thicker the buffer plate 500, the greater the thermal deformation caused by the thermal stress generated between the silicon carbide substrate 310 and the buffer plate 500. If the thickness T2 of the buffer plate 500 is greater than the thickness T1 of the diode 300, this thermal deformation becomes significant, and chipping, cracking, and the like are likely to occur in the diode 300 (see No. 10 in Table 1 described later). This is presumably because the yield strength of the iron-nickel alloy is 140 GPa, while the yield strength of silicon carbide is 40 GPa, and silicon carbide cannot withstand the strong mechanical properties of the iron-nickel alloy.

[0050] Secondly, it has been found that the failure rate of semiconductor devices equipped with a buffer plate 500 thicker than the diode 300 is significantly higher. This is thought to be because the resistivity of the iron-nickel alloy material itself is more than 10 times higher than the resistivity of copper and aluminum, which are conductor materials normally used in electronic components, and therefore generates more heat during operation. The resistivity of copper is 1.68×10 -8Ωm, and the resistivity of aluminum is 2.65×10 -8 Ωm, and the resistivity of iron-nickel alloy is 70×10 -8 It is Ωm.

[0051] Third, as a result of intensive analysis by the inventors of the present application, it has become clear that since the thermal conductivity of the iron-nickel alloy is 0.1 times or less that of silicon carbide, when the thickness T2 of the buffer plate 500 is greater than the thickness T1 of the diode 300, heat is not substantially diffused to the buffer plate 500. The thermal conductivity of silicon carbide is 120 W / mK, and the thermal conductivity of the iron-nickel alloy is 13 W / mK. In addition, due to the high resistivity as the second point, the amount of heat generated increases and the heat cannot be removed, which is considered to cause accelerated deterioration (see Nos. 7, 8, 9, and 10 in Table 1 described later).

[0052] In addition, the thickness T2 of the diode 300 during the series of studies was set to 350 μm, and the maximum test temperature was set to 200° C.

[0053] In this embodiment, by bonding the wire 162 to the buffer plate 500, the wire 162 can be electrically connected to the anode electrode 332 via the buffer plate 500. Therefore, even if ultrasonic bonding is used to bond the wire 162, damage to the diode 300 can be suppressed. If the wire 162 is a copper wire, the wire 162 can be easily bonded to the second copper layer 530 of the buffer plate 500, and low electrical resistance can be easily obtained for the wire 162.

[0054] The value of "ρ2-ρ1" is not particularly limited, and can be, for example, -2.8×10 -6 / ℃ or more -0.1×10 -6 / ℃ or less. The value of "ρ2-ρ1" is -2.0×10 -6 / ℃ or more -1.0×10 -6 / ℃ or less, -1.8×10 -6 / ℃ or more -1.2×10 -6 / °C or less. If the value of "ρ2-ρ1" is negative, internal destruction of the anode electrode 332 can be suppressed due to the difference in thermal deformation. On the other hand, the closer the value of "ρ2-ρ1" is to 0, the more difficult it may be to suppress the thermal deformation of the anode electrode 332. If the value of "ρ2-ρ1" is too small, the difference in thermal deformation between the buffer plate 500 and the anode electrode 332 may cause internal destruction of the anode electrode 332.

[0055] From the above, it is assumed that the thickness T2 of the buffer plate 500 is 0.10 mm or more and 0.20 mm or less, and the value of "ρ2-ρ1" is -2.0×10 -6 / ℃ or more -1.0×10 -6 It is particularly preferable that the temperature is 100° C. or less.

[0056] Regarding the configuration of the buffer plate 500, the first copper layer 510 and the second copper layer 530 have the same thickness, and the iron-nickel alloy layer 520 has a thickness that is preferably 72 / 14 or more times, more preferably 8 or more times, and even more preferably 18 or more times, the thickness of the first copper layer 510 and the second copper layer 530. In this case, the higher the proportion of the iron-nickel alloy layer 520, the easier it is to keep the second linear expansion coefficient ρ2 small.

[0057] When the thickness of the iron-nickel alloy layer 520 is 72 / 14 times the thickness of the first copper layer 510 and the second copper layer 530, the thickness percentage of "first copper layer 510:iron-nickel alloy layer 520:second copper layer 530" is "14%:72%:14%". In this case, the second linear expansion coefficient ρ2 of the buffer plate 500 is, for example, 3.8×10 -6 / ℃, and the value of "ρ2-ρ1" is, for example, -0.2×10 -6 / ℃.

[0058] When the thickness of the iron-nickel alloy layer 520 is eight times the thickness of the first copper layer 510 and the second copper layer 530, the thickness percentage of "first copper layer 510:iron-nickel alloy layer 520:second copper layer 530" is "10%:80%:10%". In this case, the second linear expansion coefficient ρ2 of the buffer plate 500 is, for example, 3.0×10 -6 / ℃, and the value of "ρ2-ρ1" is, for example, -1.0×10-6 / ℃.

[0059] When the thickness of the iron-nickel alloy layer 520 is 18 times the thickness of the first copper layer 510 and the second copper layer 530, the thickness percentage of "first copper layer 510:iron-nickel alloy layer 520:second copper layer 530" is "5%:90%:5%". In this case, the second linear expansion coefficient ρ2 of the buffer plate 500 is, for example, 2.1×10 -6 / ℃, and the value of "ρ2-ρ1" is, for example, -1.9×10 -6 / ℃.

[0060] The buffer plate 500 may not include the first copper layer 510 and the second copper layer 530. In other words, the buffer plate 500 may be made of an iron-nickel alloy layer 520 such as Invar. In this case, the second linear expansion coefficient ρ2 of the buffer plate 500 is, for example, 1.2×10 -6 / ℃, and the value of "ρ2-ρ1" is, for example, -2.8×10 -6 / ℃.

[0061] The anode electrode 332 preferably has an aluminum layer and a plating layer formed on the aluminum layer. Fig. 3 is a cross-sectional view showing an example of a source electrode.

[0062] For example, as shown in FIG. 3, the anode electrode 332 may have an aluminum layer 332A and a plating layer 332B. The aluminum layer 332A is located on the silicon carbide substrate 310 side (Z2 side) of the plating layer 332B, and the plating layer 332B covers the Z1 side surface of the aluminum layer 332A. The plating layer 332B is provided between the aluminum layer 332A and the buffer plate 500. The plating layer 332B is, for example, a nickel plating layer. The plating layer 332B may have, for example, a nickel plating layer, a palladium plating layer provided on the nickel plating layer, and a gold plating layer provided on the palladium layer. The anode electrode 332 includes the plating layer 332B, so that the anode electrode 332 has excellent corrosion resistance. Furthermore, the anode electrode 332 includes the plating layer 332B, so that an excellent electrical connection and mechanical connection having low electrical resistance, high bonding strength, and high reliability can be formed between the anode electrode 332 and the bonding material 135.

[0063] A plurality of diodes 300 may be provided on the third conductive pattern 113. In this case, the plurality of diodes 300 are electrically connected in parallel to each other.

[0064] Second embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in that a transistor is included. Fig. 4 is a top view showing the semiconductor device according to the second embodiment. Fig. 5 is a cross-sectional view showing the semiconductor device according to the second embodiment. Fig. 5 corresponds to a cross-sectional view taken along line VV in Fig. 4.

[0065] As shown in Figures 4 and 5, the semiconductor device 2 of the second embodiment mainly has a heat sink 120, a substrate 110, a terminal 101, a terminal 102, a terminal 103, a case 190, a transistor 200, a diode 300, a buffer plate 400, and a buffer plate 500.

[0066] Terminals 101 and 102 are arranged on the upper surface (surface on the Z1 side) of end wall portion 193, and terminal 103 is arranged on the upper surface (surface on the Z1 side) of end wall portion 194. For example, terminal 102 is arranged on the Y2 side of terminal 101. Terminals 101, 102, and 103 are each made of a metal plate.

[0067] The substrate 110 has an insulating substrate 119, a first conductive pattern 111, a second conductive pattern 112, a third conductive pattern 113, a fourth conductive pattern 114, and a conductive layer 115. The first conductive pattern 111, the second conductive pattern 112, the third conductive pattern 113, the fourth conductive pattern 114, and the conductive layer 115 are made of Cu.

[0068] The first conductive pattern 111, the second conductive pattern 112, the third conductive pattern 113, and the fourth conductive pattern 114 are provided on the Z1 side surface of the insulating substrate 119. The conductive layer 115 is provided on the Z2 side surface of the insulating substrate 119.

[0069] As shown in FIG. 5, the transistor 200 mainly includes a silicon carbide substrate 210, a gate electrode 231, a source electrode 232, and a drain electrode 233.

[0070] The silicon carbide substrate 210 has a principal surface 210A and a principal surface 210B opposite to the principal surface 210A. The principal surface 210A is on the Z1 side of the principal surface 210B. The shape of the silicon carbide substrate 210 is, for example, a rectangular parallelepiped. The principal surfaces 210A and 210B are parallel to the XY plane. The gate electrode 231 and the source electrode 232 are provided on the principal surface 210A, and the drain electrode 233 is provided on the principal surface 210B. The transistor 200 is provided on the fourth conductive pattern 114. The gate electrode 231 and the source electrode 232 include, for example, an aluminum layer. The gate electrode 231 and the source electrode 232 may include an aluminum alloy layer such as an Al-Si alloy or an Al-Si-Cu alloy instead of the aluminum layer. The drain electrode 233 has an ohmic layer and a junction layer provided on the ohmic layer. The ohmic layer includes, for example, nickel or a nickel alloy. Nickel or a nickel alloy has good contact resistance with silicon carbide. The bonding layer includes a nickel layer. The bonding layer may further include a gold layer or a silver layer provided on the nickel layer. The drain electrode 233 has a bonding layer, so that good bonding is obtained between the drain electrode 233 and the fourth conductive pattern 114. The thickness T1 of the transistor 200 is, for example, about 0.35 mm. In a plan view, the length of each side of the transistor 200 is, for example, about 3 mm. The drain electrode 233 is bonded to the fourth conductive pattern 114 using a bonding material 132 such as a silver sintered body or a copper sintered body. The transistor 200 is an example of a semiconductor chip. The silicon carbide substrate 210 is an example of a semiconductor substrate. The source electrode 232 is an example of a main electrode.

[0071] The buffer plate 400 is, for example, a laminated material having a first copper layer 410, an iron-nickel alloy layer 420, and a second copper layer 430. The iron-nickel alloy layer 420 is provided on the Z1 side of the first copper layer 410, and the second copper layer 430 is provided on the Z1 side of the iron-nickel alloy layer 420. That is, the iron-nickel alloy layer 420 is provided on the first copper layer 410, and the second copper layer 430 is provided on the iron-nickel alloy layer 420. The iron-nickel alloy layer 420 is, for example, a layer of an iron-nickel alloy containing 36 mass% of nickel. The iron-nickel alloy layer 420 may contain about 0.7 mass% of manganese. The iron-nickel alloy layer 420 may contain about 17 mass% of cobalt. The material of the iron-nickel alloy layer 420 may be Invar. The thickness T4 of the buffer plate 400 is, for example, 0.05 mm or more and 0.25 mm or less. For example, the thickness T4 of the buffer plate 400 is smaller than the thickness T3 of the transistor 200. The buffer plate 400 is disposed on the source electrode 232. A first copper layer 410 is bonded to the source electrode 232 using a bonding material 134 such as a sintered silver body or a sintered copper body.

[0072] The silicon carbide substrate 210 has a first linear expansion coefficient ρ1', the buffer plate 400 has a second linear expansion coefficient ρ2', and the source electrode 232 has a third linear expansion coefficient ρ3'. In this disclosure, the linear expansion coefficient is the linear expansion coefficient in a direction parallel to the main surface 210A at 25°C, unless otherwise specified. In this disclosure, the linear expansion coefficient is the linear expansion coefficient when the silicon carbide substrate 210, the buffer plate 400, and the source electrode 232 are released from the bonded state and are taken as a single body, unless otherwise specified. The first linear expansion coefficient ρ1' and the second linear expansion coefficient ρ2' are smaller than the third linear expansion coefficient ρ3', and the second linear expansion coefficient ρ2' is smaller than the first linear expansion coefficient ρ1'. For example, when the first linear expansion coefficient ρ1' is 4.0×10 -6 / ℃, while the second linear expansion coefficient ρ2' is 1.2×10 -6 / ℃ or more 3.9×10 -6 / ℃ or less. In this case, the value of "ρ2´-ρ1´" is -2.8×10 -6 / ℃ or more -0.1×10 -6 / ℃ or less.

[0073] The semiconductor device 2 further includes wires 161, 162, 163, 164, 165, and 166. The number of each of the wires 161 to 166 is not limited, and may be one, or may be two or more.

[0074] The wire 161 connects the gate electrode 231 of the transistor 200 to the first conductive pattern 111. The wire 162 connects the second copper layer 430 of the buffer plate 400 to the second conductive pattern 112. The wire 163 connects the third conductive pattern 113 to the fourth conductive pattern 114. The wire 164 connects the first conductive pattern 111 to the terminal 101. The wire 165 connects the second conductive pattern 112 to the terminal 102. The wire 166 connects the anode electrode 332 of the diode 300 to the terminal 103. The wires 161 to 166 are, for example, copper wires. The diameter of each of the wires 161 to 166 is, for example, 100 μm or more and 400 μm or less. The wires 161 to 166 are bonded by, for example, ultrasonic bonding.

[0075] Other configurations, such as the configurations of the diode 300 and the buffer plate 500, are similar to those of the first embodiment.

[0076] Here, when focusing on thermal deformation of the silicon carbide substrate 210 and the source electrode 232, since the first linear expansion coefficient ρ1' is smaller than the third linear expansion coefficient ρ3', the source electrode 232 may thermally deform more than the silicon carbide substrate 210. Since the silicon carbide substrate 210 and the source electrode 232 are firmly bonded to each other, the greater the difference between the first linear expansion coefficient ρ1' and the third linear expansion coefficient ρ3', the greater the thermal stress acting on the source electrode 232, making it more likely that internal destruction will occur in the source electrode 232.

[0077] On the other hand, the buffer plate 400 is bonded to the source electrode 232 by the bonding material 134, and the thermal deformation of the source electrode 232 is restrained by the buffer plate 400. In this embodiment, the second linear expansion coefficient ρ2' of the buffer plate 400 is smaller than the first linear expansion coefficient ρ1'. Therefore, the thermal deformation of the source electrode 232 can be significantly suppressed by the bonding material 134. Therefore, according to this embodiment, it is possible to suppress the thermal stress generated in the source electrode 232 due to the thermal deformation, and to suppress the internal destruction of the source electrode 232 containing aluminum.

[0078] The thickness T4 of the buffer plate 400 is not particularly limited, and is, for example, 0.05 mm or more and 0.25 mm or less. The thickness T4 may be 0.07 mm or more and 0.23 mm or less, or 0.10 mm or more and 0.20 mm or less. If the thickness T4 is too large, the electrical resistance between the source electrode 232 and the wire 162 may be excessively high, or the heat dissipation from the source electrode 232 may be easily hindered. Also, if the thickness T4 is too small, it may be difficult to suppress the thermal deformation of the source electrode 232.

[0079] In particular, since the thickness T4 of the buffer plate 400 is smaller than the thickness T3 of the transistor 200, similar to the relationship between the thickness T1 of the diode 300 and the thickness T2 of the buffer plate 500, chipping, cracks, etc. of the transistor 200 are more easily suppressed, the failure rate is more easily kept low, and heat is more easily diffused through the buffer plate 400.

[0080] In this embodiment, by bonding the wire 162 to the buffer plate 400, the wire 162 can be electrically connected to the source electrode 232 via the buffer plate 400. Therefore, even if ultrasonic bonding is used to bond the wire 162, damage to the transistor 200 can be suppressed. If the wire 162 is a copper wire, the wire 162 can be easily bonded to the second copper layer 430 of the buffer plate 400, and low electrical resistance can be easily obtained for the wire 162.

[0081] The value of "ρ2'-ρ1'" is not particularly limited, and is, for example, -2.8×10 -6 / ℃ or more -0.1×10 -6 / ℃ or less. The value of "ρ2´-ρ1´" is -2.0×10 -6 / ℃ or more -1.0×10 -6 / ℃ or less, -1.8×10 -6 / ℃ or more -1.2×10 -6 / °C or less. If "ρ2'-ρ1'" is negative, internal destruction of the source electrode 232 can be suppressed due to the difference in thermal deformation. On the other hand, the closer the value of "ρ2'-ρ1'" is to 0, the more difficult it may be to suppress the thermal deformation of the source electrode 232. If the value of "ρ2'-ρ1'" is too small, internal destruction of the source electrode 232 may occur due to the difference in thermal deformation between the buffer plate 400 and the source electrode 232.

[0082] From the above, it is found that the thickness T4 of the buffer plate 400 is 0.10 mm or more and 0.20 mm or less, and the value of "ρ2'-ρ1'" is -2.0×10 -6 / ℃ or more -1.0×10 -6 It is particularly preferable that the temperature is 100° C. or less.

[0083] Regarding the configuration of the buffer plate 400, the first copper layer 410 and the second copper layer 430 have the same thickness, and the iron-nickel alloy layer 420 has a thickness that is preferably 72 / 14 or more times, more preferably 8 or more times, and even more preferably 18 or more times, the thickness of the first copper layer 410 and the second copper layer 430. In this case, the higher the proportion of the iron-nickel alloy layer 420, the easier it is to keep the second linear expansion coefficient ρ2' small.

[0084] When the thickness of the iron-nickel alloy layer 420 is 72 / 14 times the thickness of the first copper layer 410 and the second copper layer 430, the thickness percentage of "first copper layer 410: iron-nickel alloy layer 420: second copper layer 430" is "14%:72%:14%". In this case, the second linear expansion coefficient ρ2' of the buffer plate 400 is, for example, 3.8×10 -6 / ℃, and the value of "ρ2'-ρ1'" is, for example, -0.2×10 -6 / ℃.

[0085] When the thickness of the iron-nickel alloy layer 420 is eight times the thickness of the first copper layer 410 and the second copper layer 430, the thickness percentage of "first copper layer 410: iron-nickel alloy layer 420: second copper layer 430" is "10%:80%:10%". In this case, the second linear expansion coefficient ρ2' of the buffer plate 400 is, for example, 3.0×10 -6 / °C, and the value of "ρ2'-ρ1'" is, for example, -1.0×10 -6 / ℃.

[0086] When the thickness of the iron-nickel alloy layer 420 is 18 times the thickness of the first copper layer 410 and the second copper layer 430, the thickness percentage of "first copper layer 410: iron-nickel alloy layer 420: second copper layer 430" is "5%:90%:5%". In this case, the second linear expansion coefficient ρ2' of the buffer plate 400 is, for example, 2.1×10 -6 / ℃, and the value of "ρ2'-ρ1'" is, for example, -1.9×10 -6 / ℃.

[0087] The buffer plate 400 may not include the first copper layer 410 and the second copper layer 430. In other words, the buffer plate 400 may be made of an iron-nickel alloy layer 420 such as Invar. In this case, the second linear expansion coefficient ρ2′ of the buffer plate 400 is, for example, 1.2×10 -6 / ℃, and the value of "ρ2'-ρ1'" is, for example, -2.8×10 -6 / ℃.

[0088] Like the anode electrode 332, the source electrode 232 preferably has an aluminum layer and a plating layer formed on the aluminum layer. When the source electrode 232 includes a plating layer, excellent corrosion resistance can be obtained for the source electrode 232. Furthermore, when the source electrode 232 includes a plating layer, excellent electrical and mechanical connections, such as low electrical resistance, high bonding strength, and high reliability, can be formed between the source electrode 232 and the bonding material 134.

[0089] A plurality of transistors 200 may be provided on the fourth conductive pattern 114. In this case, the plurality of transistors 200 are electrically connected in parallel to each other.

[0090] Third embodiment Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the configuration of the bonding material between the anode electrode 332 and the buffer plate 500. Fig. 6 is a cross-sectional view showing the bonding material between the anode electrode 332 and the buffer plate 500 in the third embodiment.

[0091] As shown in FIG. 6, in the third embodiment, a bonding material 630 is provided instead of the bonding material 135. The bonding material 630 has a first region 631 overlapping a portion of the buffer plate 500 to which the wire 162 is bonded in a plan view, and a second region 632 surrounding the first region 631. The linear expansion coefficient of the first region 631 is lower than that of the second region 632. For example, the second region 632 is a bonding material such as a silver sintered body or a copper sintered body, similar to the bonding material 135. On the other hand, the first region 631 may be made of, for example, silicon carbide, silicon, silicon oxide, or silicon nitride. The silicon oxide may contain boron, and phosphorus-doped silicon oxide may be used. The first region 631 may be made of a metal such as an iron-nickel alloy, molybdenum, or tungsten. The first region 631 may be made of a ceramic such as alumina or zircon.

[0092] The other configuration is similar to that of the first embodiment.

[0093] The third embodiment also provides the same effects as the first embodiment.

[0094] In addition, in the third embodiment, since the linear expansion coefficient of the first region 631 is lower than the linear expansion coefficient of the second region 632, the stress acting on the anode electrode 332 can be reduced and internal destruction of the anode electrode 332 can be further suppressed, as described below.

[0095] That is, since the wire 162 is connected to the second copper layer 530, the amount of thermal deformation of the portion of the second copper layer 530 to which the wire 162 is connected becomes larger than that of the surrounding area. Therefore, in a cross section perpendicular to the X1-X2 direction (cross section parallel to the YZ plane), although the thickness of the first copper layer 510 and the thickness of the second copper layer 530 are equal, there are localized portions where the second linear expansion coefficient ρ2 of the buffer plate 500 is large, and the value of "ρ2-ρ1" may become large. In the third embodiment, since the linear expansion coefficient of the first region 631 is lower than the linear expansion coefficient of the second region 632, the local increase in the value of "ρ2-ρ1" is suppressed, and internal destruction of the anode electrode 332 can be further suppressed.

[0096] If the value of "ρ2-ρ1" becomes excessive even locally, that part will become weak, and there is a high possibility that the whole will be destroyed from that part. In such a case, the life of the weak part will determine the whole life in a power cycle test, etc.

[0097] Since the second region 632 is made of a bonding material such as a silver sintered body or a copper sintered body, and the first region 631 is made of silicon carbide, silicon oxide, or an iron-nickel alloy, it is easy to reduce the stress acting on the anode electrode 332 while ensuring excellent bonding strength.

[0098] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment differs from the first embodiment mainly in the configuration of the bonding material between the anode electrode 332 and the buffer plate 500. Fig. 7 is a cross-sectional view showing the bonding material between the anode electrode 332 and the buffer plate 500 in the fourth embodiment.

[0099] 7, in the fourth embodiment, a bonding material 730 is provided instead of the bonding material 135. The bonding material 730 is a bonding material such as a sintered silver body or a sintered copper body, similar to the bonding material 135. However, a gap 731 is provided in a portion of the bonding material 730 that overlaps with a portion of the buffer plate 500 to which the wire 162 is bonded in a plan view. A gas such as air, hydrogen, nitrogen, or oxygen may be present inside the gap 731, or the inside of the gap 731 may be in a low-pressure vacuum state.

[0100] The other configuration is similar to that of the first embodiment.

[0101] The fourth embodiment also provides the same effects as the first embodiment.

[0102] In the fourth embodiment, the gap 731 is provided in the bonding material 730, so that the stress acting on the anode electrode 332 is reduced, and internal destruction of the anode electrode 332 can be further suppressed, as in the third embodiment.

[0103] The width in the Y1-Y2 direction of the first region 631 in the third embodiment and the void 731 in the fourth embodiment may be equal to that of the wire 162. From a stress analysis using the finite element method, it has been confirmed that if the width of the first region 631 or the void 731 is ¼ or more of the width of the wire 162, the generation of stress in the anode electrode 332 can be suppressed. On the other hand, if the width of the first region 631 or the void 731 is excessive, the current path from the wire 162 to the diode 300 is reduced. For this reason, the width of the first region 631 or the void 731 is preferably 5 times or less, more preferably 2 times or less, and even more preferably 1 time or less, of the width of the wire 162.

[0104] In the second embodiment, a bonding material similar to the bonding material 630 or 730 may be used instead of the bonding material 134. In this case, the stress acting on the source electrode 232 is easily reduced.

[0105] The wire 162 is bonded to the second copper layer 530, and it is preferable that at the interface between the wire 162 and the second copper layer 530, crystal grains are present that straddle the interface between the wire 162 and the second copper layer 530. It is more preferable that the crystal grains that straddle the interface between the wire 162 and the second copper layer 530 reach the interface with the iron-nickel alloy layer 520.

[0106] 8 is a diagram showing an example of crystal grains constituting the wire 162 and the second copper layer 530. As shown in FIG. 7, some of the crystal grains 531 constituting the wire 162 and the second copper layer 530 may straddle the interface between the wire 162 and the second copper layer 530. The presence of the crystal grains 531 straddling the interface between the wire 162 and the second copper layer 530 makes it easier to obtain a strong bond between the wire 162 and the second copper layer 530. Furthermore, the crystal grains 531 straddling the interface between the wire 162 and the second copper layer 530 reach the interface with the iron-nickel alloy layer 420, making it easier to obtain a stronger bond.

[0107] (Characteristics test) Next, preferred characteristics regarding temperature change obtained when a power cycle test is performed on the semiconductor device according to the embodiment of the present disclosure will be described. The power cycle test is performed in accordance with IEC60749 as follows.

[0108] In the power cycle test, the temperature of the sample is raised from room temperature (25°C) to 65°C, and then a current of 125A is repeatedly applied and cut off. The current application time (t on ) is 1 second, and the interruption time (t off The maximum junction temperature (Tj) in each cycle is 13 seconds. max ) shall be 200°C or higher, and the difference (ΔTj) between the maximum bonding temperature and the minimum bonding temperature (65°C) in each cycle shall be 135°C or higher.

[0109] The current-flow initiation voltage when a low current of about 100 mA is passed through the sample corresponds to the junction temperature (Tj) of the sample. Therefore, if a low current of 100 mA, which is sufficiently smaller than the current that flows immediately after current is passed through the sample for each cycle of current-flow and cut-off, is passed through the sample and the current-flow initiation voltage is measured, the current-flow initiation temperature for each cycle can be calculated as the maximum junction temperature (Tj max As the power cycle test proceeds, the sample gradually deteriorates and the maximum junction temperature (Tj max) gradually increases, so the life in this test is defined as the state where ΔTj has increased by 20% from the start of current flow. As mentioned above, when the minimum junction temperature is 65°C and the maximum junction temperature is 200°C, ΔTj is 135°C, so the temperature at which ΔTj has increased by 20% is 162°C, and the maximum junction temperature (Tj max The life is defined as the state where the temperature at which the bonding temperature reaches 227°C. This test is performed in accordance with the IEC60749 inspection standard established by the International Organization for Standardization, so that the life obtained can be compared based on the same standard even between power module samples with different structures and manufacturing methods. The bonding temperature in this disclosure is determined by the above method.

[0110] In such power cycle tests, the maximum junction temperature (Tj max ) is preferably not more than 5.0° C., more preferably not more than 4.5° C., and even more preferably not more than 4.0° C. The smaller this increase is, the easier it is to suppress the progression of internal destruction of the aluminum layer contained in the anode electrode or source electrode.

[0111] Examples of the results of the power cycle test are shown in Figures 9 and 10. Figures 9 and 10 show the results of the power cycle test for a total of 11 types of samples (samples No. 1 to No. 11). In this power cycle test, diodes were used as samples. The horizontal axis of Figures 9 and 10 shows the number of times that current was turned on and off, and the vertical axis shows the maximum junction temperature Tj max The temperature in the specimens is shown in degrees Celsius. The buffer plate configurations were different between specimens No. 1 to No. 11, but the other conditions were the same. The semiconductor substrate had a first linear expansion coefficient ρ1 of 4.0×10 -6 A silicon carbide substrate with a temperature of 1000°C was used. Table 1 shows the outline of the buffer plates for samples No. 1 to No. 11. Table 1 also shows the maximum junction temperature Tj max (Initial temperature), maximum junction temperature Tj after 200,000 cycles max (Temperature at 200,000 cycles) and maximum junction temperature Tj between 200,000 and 300,000 cycles maxTable 1 also shows the number of cycles when ΔTj has increased by 20% (life), the number of cycles when ΔTj has increased by 5% before the life is reached, and the ratio R of the number of cycles when ΔTj has increased by 5% to the number of cycles when the life is reached.

[0112] [Table 1]

[0113] As shown in Fig. 9, Fig. 10 and Table 1, in sample No. 1, the second linear expansion coefficient ρ2 of the buffer plate was 4.0 × 10 -6 / ℃), and the value of "ρ2-ρ1" is +1.2×10 -6 / ℃. And the maximum junction temperature (Tj max The increase in temperature was 8.4°C. The initial temperature of sample No. 1 at the start of the test was 203.9°C, and the life was 334,000 cycles.

[0114] In sample No. 2, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, and the value of "ρ2-ρ1" is -1.0×10 -6 / ℃. And the maximum junction temperature (Tj max The increase in temperature was 3.7°C. The initial temperature of sample No. 2 at the start of the test was 207.1°C, and the life was 845,000 cycles.

[0115] In sample No. 3, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, and the value of "ρ2-ρ1" is -1.9×10 -6 / ℃. And the maximum junction temperature (Tj max The increase in temperature was 1.2°C. The initial temperature of sample No. 3 at the start of the test was 202.9°C, and the life was 907,000 cycles.

[0116] In sample No. 4, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, and the value of "ρ2-ρ1" is -1.9×10 -6 / ℃. And the maximum junction temperature (Tj maxThe increase in temperature was 1.2°C. The initial temperature of sample No. 4 at the start of the test was 212.6°C, and the life was 472,000 cycles.

[0117] In sample No. 5, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, and the value of "ρ2-ρ1" is -1.0×10 -6 / ℃. And the maximum junction temperature (Tj max The increase in temperature was 3.1°C. The initial temperature of sample No. 5 at the start of the test was 229.3°C, and the life was 425,000 cycles.

[0118] In sample No. 5, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, and the thickness of the buffer plate is within the preferred range (0.05 mm or more and 0.25 mm or less). Therefore, although the initial temperature of sample No. 5 (229.3°C) is higher than the other samples, the temperature increase between 200,000 and 300,000 cycles can be reduced, and a good lifespan can be obtained.

[0119] In sample No. 6, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, and the value of "ρ2-ρ1" is -2.8×10 -6 / ℃. And the maximum junction temperature (Tj max The increase in temperature was 2.7°C. The initial temperature of sample No. 6 at the start of the test was 205.1°C, and the life was 558,000 cycles.

[0120] In sample No. 7, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, and the value of "ρ2-ρ1" is -1.0×10 -6 / ℃. And the maximum junction temperature (Tj max The increase in temperature was 6.5°C. The initial temperature of sample No. 7 at the start of the test was 208.3°C, and the life was 330,000 cycles.

[0121] In sample No. 7, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, but the thickness of the buffer plate is larger than the upper limit of the preferred range (0.05 mm to 0.25 mm). Therefore, compared to sample No. 1, it is considered that the heat dissipation performance is reduced due to the increase in heat generation and the decrease in thermal conduction caused by the increase in electrical resistance, resulting in a shorter lifespan.

[0122] In sample No. 8, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, and the value of "ρ2-ρ1" is -1.9×10 -6 / ℃. And the maximum junction temperature (Tj max The increase in temperature was 7.5°C. The initial temperature of sample No. 8 at the start of the test was 202.8°C, and the life was 325,000 cycles. It is believed that the life was shorter than that of sample No. 1 for the same reason as sample No. 7.

[0123] In sample No. 9, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, and the value of "ρ2-ρ1" is -1.0×10 -6 / ℃. And the maximum junction temperature (Tj max The increase in temperature was 8.8°C. The initial temperature of sample No. 9 at the start of the test was 201.2°C, and the life was 309,000 cycles. It is believed that the life was shorter than that of sample No. 1 for the same reasons as samples No. 7 and No. 8.

[0124] In sample No. 10, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, and the value of "ρ2-ρ1" is -1.9×10 -6 / °C. The initial temperature of sample No. 10 at the start of the test was 210.3°C. Note that sample No. 10 reached the end of its life before the number of cycles reached 200,000. When the inside of sample No. 10 was observed, cracks were found to have occurred in the diode.

[0125] In sample No. 10, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, but the thickness of the buffer plate is larger than the upper limit of the preferred range (0.05 mm or more and 0.25 mm or less) and is also larger than the other samples. In particular, the thickness of the buffer plate is larger than the thickness of the diode (0.35 mm). For this reason, it is presumed that the silicon carbide substrate of the diode could not withstand the stress from the buffer plate.

[0126] In sample No. 11, the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 of the semiconductor substrate, and the value of "ρ2-ρ1" is -1.9×10 -6 / ℃. And the maximum junction temperature (Tj max The increase in temperature was 2.3°C. The initial temperature of sample No. 11 at the start of the test was 206.8°C. The life was more than 400,000 cycles.

[0127] In this way, in samples No. 2 to No. 6 in which the second linear expansion coefficient ρ2 of the buffer plate is smaller than the first linear expansion coefficient ρ1 and the thickness of the buffer plate is in the range of 0.05 mm to 0.25 mm, the maximum bonding temperature (Tj max ) was small. This suggests that the deterioration of the aluminum layer in the anode electrode was suppressed. This is presumably due to the effect of the buffer plate thickness being in the range of 0.05 mm to 0.25 mm, which suppressed the increase in resistance and the decrease in heat transfer.

[0128] As summarized in Table 1, the inventors' systematic study and analysis revealed that the maximum junction temperature (Tj max It has been found that by using a semiconductor device with a small increase in ΔTj, not only can the ultimately achievable lifespan (the test lifespan at the point when ΔTj increases by 20%) be extended, but also degradation immediately after the start of the test can be reduced, ensuring a long period during which the progression of degradation is very slow.

[0129] From Table 1, it can be seen that for all samples No. 1 to No. 11, the operation test was started at a temperature of 200°C or higher. max It can be seen that samples No. 2 to No. 6 and No. 11, in which the increase in ρ was small, achieved a long life of more than 400,000 cycles, far exceeding 300,000 cycles. On the other hand, sample No. 1, in which the second linear expansion coefficient ρ2 of the buffer plate was larger than the first linear expansion coefficient ρ1, achieved an end of life of less than 400,000 cycles.

[0130] Furthermore, the maximum junction temperature (Tj max ) and the number of repetitions at which ΔTj has increased by 5% from the initial temperature as indicators, it can be seen that this disclosure not only enables the lifespan to be extended, but also suppresses deterioration from the initial stage for a long period of time.

[0131] Here, the results of the power cycle test are analyzed based on the ratio R of the number of cycles at which ΔTj has increased by 5% to the number of cycles at which the life is reached.

[0132] When the number of cycles at which ΔTj has increased by 20% is close to the number of cycles at which ΔTj has increased by 5%, i.e., when the ratio R is large, it can be seen that the state of low degradation is maintained for a long time from the beginning, and the temperature finally rises when the device is nearing the end of its life. This indicates that the characteristics are stable from the beginning until just before the end of its life. In contrast, when the ratio R is small, degradation is likely to progress from the beginning, and fluctuations in the characteristics occur as degradation progresses.

[0133] For example, in samples No. 1 and No. 7 to No. 9, the temperature rise ΔT1 from the beginning was large, and it was confirmed that the deterioration that would eventually lead to failure began at an early stage. On the other hand, in samples No. 2 to No. 6 and No. 11, the temperature rise between 200,000 and 300,000 cycles was small, and the initial deterioration was suppressed for a long period of time. In other words, it can be seen that samples No. 2 to No. 6 and No. 11 are able to maintain and ensure a level of reliability that was not previously possible. It can be confirmed that this corresponds to the temperature rise ΔT1.

[0134] As described above, when (1) life, (2) temperature rise ΔT1, and (3) number of repetitions at which ΔTj increases by 5% from the initial temperature are used as indicators, it can be seen that in samples No. 1 and No. 7 to No. 9, the temperature rise ΔT1 from the initial stage is large, and the deterioration that ultimately leads to failure begins at an early stage, resulting in a short life. On the other hand, in samples No. 2 to No. 6 and No. 11, the temperature rise between 200,000 and 300,000 times is small, and the deterioration is sufficiently suppressed for a certain period from the initial stage, and characteristics very close to the initial stage can be maintained until just before failure, and the final life can be extended. Therefore, by using semiconductor devices using samples No. 2 to No. 6 and No. 11, a more reliable system for in-vehicle use, industrial use, etc. can be constructed, and a more reliable final product can be obtained.

[0135] Next, a preferred change in the linear expansion coefficient of the buffer plate when the semiconductor device according to the embodiment of the present disclosure is subjected to one temperature increase and decrease will be described.

[0136] In this test, the buffer plate is held at 25°C for 30 minutes, then heated from 25°C to 250°C, held at 250°C for 30 minutes, and then cooled from 250°C to 25°C. After holding at 25°C for 30 minutes, the cycle of heating and then cooling is repeated, and the linear expansion coefficient of the buffer plate is continuously measured in the above temperature range. The maximum value of "ρ5-ρ4" at the same temperature between 25°C and 250°C is calculated for the linear expansion coefficient during heating (fifth linear expansion coefficient ρ5) and the linear expansion coefficient during cooling (fourth linear expansion coefficient ρ4).

[0137] Here, the meaning of the value of "ρ5-ρ4" will be explained. Figures 11 to 13 are schematic diagrams showing changes in deformation amount due to temperature changes. Figure 14 is a diagram showing changes in linear expansion coefficient due to temperature changes.

[0138] As shown in FIG. 11, it is considered that the linear expansion coefficients are equal between when the temperature is rising and when the temperature is falling. However, as shown in FIG. 12, when the temperature rises from room temperature (25°C), a difference appears between the fifth linear expansion coefficient ρ5 when the temperature is rising and the fourth linear expansion coefficient ρ4 when the temperature is falling. In such a case, the deterioration of the semiconductor device may progress within the operating temperature range of the semiconductor device, for example, within a temperature range of 25°C to 250°C. Also, as shown in FIG. 13, after one cycle of rising and falling the semiconductor device as a whole may not return to its original shape, and in the next cycle, the deformation may further accumulate from the deformed state. This is the cause of accelerated deterioration called "progressive deformation".

[0139] Therefore, as shown in FIG. 14, the maximum value Δρ of “ρ5-ρ4” at any temperature between 25° C. and 250° C. max A semiconductor device exhibiting a small temperature characteristic 11 and a maximum value Δρ of "ρ5-ρ4" at any temperature between 25°C and 250°C max In comparison with a semiconductor device exhibiting temperature characteristic 12, which has a larger temperature coefficient, the semiconductor device exhibiting temperature characteristic 11 is less likely to deteriorate.

[0140] In the semiconductor device according to the embodiment of the present disclosure, the maximum value Δρ of “ρ5−ρ4” at any temperature between 25° C. and 250° C. max However, preferably 1.5×10 -6 / °C or less, and more preferably 1.3 × 10 -6 / °C or less, and more preferably 1.1 × 10 -6 / ℃ or less. The maximum value of "ρ5-ρ4" Δρ max The smaller the value, the more stable the linear expansion coefficient of the buffer plate is, even when a temperature history of increasing and decreasing temperature is applied, and the more easily internal destruction of the aluminum layer included in the source electrode is suppressed.

[0141] In terms of thickness percentage, when the ratio of the first copper layer: iron-nickel alloy layer: second copper layer is 33%:33%:33%, the maximum value of ρ5-ρ4 is 3.8×10 -6 / °C. In terms of percentage of thickness, when the ratio of "first copper layer: iron-nickel alloy layer: second copper layer" is "20%:60%:20%, the maximum value of "ρ5-ρ4" is 1.9×10 -6 / ℃.

[0142] In contrast, when the thickness percentage of the first copper layer: iron-nickel alloy layer: second copper layer is 14%:72%:14%, the maximum value of ρ5-ρ4 is 1.5×10 -6 / °C. In terms of percentage of thickness, when the ratio of "first copper layer: iron-nickel alloy layer: second copper layer" is "10%:80%:10%, the maximum value of "ρ5-ρ4" is 1.3×10 -6 / °C. In terms of percentage of thickness, when the ratio of "first copper layer: iron-nickel alloy layer: second copper layer" is "5%:90%:5%", the maximum value of "ρ5-ρ4" is 1.1×10 -6 / ℃. If the buffer plate is made of Invar, the maximum value of "ρ5-ρ4" is 0.7×10 -6 / ℃.

[0143] The deformation of the buffer plate can be observed with high precision by a digital image correlation (DIC) method using an optical microscope or an electron microscope.

[0144] In the present disclosure, an aluminum alloy layer may be used instead of the aluminum layer. The material used for the bonding material is not limited. For example, the bonding material may be made of a sintered body of an intermetallic compound containing copper, silver, nickel, or copper and tin. The sintered body of the intermetallic compound containing copper and tin is obtained by, for example, a transient liquid phase sintering method.

[0145] In the present disclosure, the semiconductor chip is preferably a silicon carbide chip. The silicon carbide chip has excellent high temperature resistance and is unlikely to break down even when used at high temperatures. The silicon carbide chip also has high mechanical properties. Furthermore, since internal destruction of the main electrode containing aluminum is suppressed, the semiconductor device as a whole is likely to have an excellent life even at high temperatures.

[0146] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0147] 1, 2: Semiconductor device 11, 12: Temperature characteristics 101, 102, 103: Terminals 110: Substrate 111: First conductive pattern 112: second conductive pattern 113: Third conductive pattern 114: Fourth conductive pattern 115: Conductive layer 119: Insulating substrate 120: Heat sink 131, 132, 133, 134, 135: Bonding material 161, 162, 163, 164, 165, 166: Wire 190: Case 191, 192: Side wall 193, 194: End wall 200: Transistor (semiconductor chip) 210: Silicon carbide substrate (semiconductor substrate) 210A, 210B: Main surface 231: Gate electrode 232: Source electrode (main electrode) 233: Drain electrode 300: Diode (semiconductor chip) 310: Silicon carbide substrate (semiconductor substrate) 310A, 310B: Main surface 332: Anode electrode (main electrode) 332A: Aluminum layer 332B: Plating layer 333: Cathode electrode 400:Buffer plate 410: First copper layer 420: Iron-nickel alloy layer 430: Second copper layer 500:Buffer plate 510: First copper layer 520: Iron-nickel alloy layer 530: Second copper layer 531: Grain 630: Bonding material 631:First area 632:Second area 730: Bonding material 731:Void

Claims

1. A semiconductor chip including a semiconductor substrate and a main electrode provided on the semiconductor substrate; A buffer plate and A bonding material provided between the main electrode and the buffer plate; having the master electrode comprises an aluminum or aluminum alloy layer; a first linear expansion coefficient of the semiconductor substrate and a second linear expansion coefficient of the buffer plate are smaller than a third linear expansion coefficient of the main electrode; The second linear expansion coefficient is smaller than the first linear expansion coefficient.

2. The thickness of the buffer plate is 0.05 mm or more and 0.25 mm or less, When the first linear expansion coefficient is ρ1 and the second linear expansion coefficient is ρ2, the value of "ρ2-ρ1" is -2.8×10 －６ / ℃ or more -0.1 x 10 －６ 2. The semiconductor device according to claim 1, wherein the temperature is 0.1 to 100° C.

3. The thickness of the buffer plate is 0.05 mm or more and 0.25 mm or less, When the first linear expansion coefficient is ρ1 and the second linear expansion coefficient is ρ2, the value of "ρ2-ρ1" is -2.8×10 －６ 2. The semiconductor device according to claim 1, wherein the temperature is 100° C. / ° C.

4. The thickness of the buffer plate is 0.10 mm or more and 0.20 mm or less, When the first linear expansion coefficient is ρ1 and the second linear expansion coefficient is ρ2, the value of "ρ2-ρ1" is -2.0×10 －６ / ℃ or more -1.0 x 10 －６ 2. The semiconductor device according to claim 1, wherein the temperature is 0.1 to 100° C.

5. 5. The semiconductor device according to claim 1, wherein the thickness of the buffer plate is smaller than the thickness of the semiconductor chip.

6. The buffer plate is a laminate material or an iron-nickel alloy material; The laminate comprises: A first copper layer in contact with the bonding material; an iron-nickel alloy layer disposed on the first copper layer; a second copper layer disposed on the iron-nickel alloy layer; The semiconductor device according to claim 1 , further comprising:

7. the first copper layer and the second copper layer have an equal thickness; 7. The semiconductor device according to claim 6, wherein the thickness of the iron-nickel alloy layer is 72 / 14 times or more the thickness of the first copper layer and the second copper layer.

8. The semiconductor device according to claim 1 , further comprising a wire joined to the buffer plate.

9. 9. The semiconductor device according to claim 8, wherein the wire is a copper wire.

10. 10. The semiconductor device according to claim 8, wherein a crystal grain is provided at an interface between the wire and the buffer plate, the crystal grain straddling the wire and the buffer plate.

11. The buffer plate is A first copper layer in contact with the bonding material; an iron-nickel alloy layer disposed on the first copper layer; a second copper layer disposed on the iron-nickel alloy layer; having Further, a wire is attached to the buffer plate, the wire is a copper wire; 6. The semiconductor device according to claim 1, wherein a crystal grain is provided at an interface between the wire and the buffer plate, the crystal grain straddling the wire and the buffer plate.

12. 12. The semiconductor device according to claim 11, wherein the crystal grains reach the iron-nickel alloy layer.

13. the first copper layer and the second copper layer have an equal thickness; 13. The semiconductor device according to claim 11, wherein the thickness of the iron-nickel alloy layer is 72 / 14 times or more the thickness of the first copper layer and the second copper layer.

14. When viewed in a direction perpendicular to the main surface of the semiconductor substrate, the bonding material has a first region overlapping a portion of the buffer plate to which the wire is joined; A second region surrounding the first region; having The semiconductor device according to claim 8 , wherein the first region has a linear expansion coefficient lower than a linear expansion coefficient of the second region.

15. the first region is composed of silicon carbide, silicon, silicon oxide, silicon nitride, iron-nickel alloy, molybdenum, or tungsten; The semiconductor device according to claim 14 , wherein the second region is made of a sintered body of an intermetallic compound containing copper, silver, nickel, or copper and tin.

16. 14. The semiconductor device according to claim 8, wherein a gap is provided in a portion of the bonding material that overlaps with a portion of the buffer plate to which the wire is bonded when viewed from a direction perpendicular to the main surface of the semiconductor substrate.

17. The main electrode has a plating layer, 17. The semiconductor device according to claim 1, wherein the plating layer is provided between the aluminum or aluminum alloy layer and the buffer plate.

18. 18. The semiconductor device according to claim 1, wherein in a power cycle test in which the maximum junction temperature of the semiconductor chip in each cycle is 200° C. or higher, an increase in the maximum junction temperature is 5.0° C. or less between 200,000 and 300,000 repetitions.

19. The buffer plate is heated from 25° C. to 250° C., and then cooled from 250° C. to 25° C. after the heating. The linear expansion coefficient of the buffer plate during the heating and the cooling is continuously measured. When the linear expansion coefficient of the buffer plate during the heating is ρ5 and the linear expansion coefficient of the buffer plate during the cooling is ρ4, the maximum value of “ρ5-ρ4” at the same temperature between 25° C. and 250° C. is 1.5×10 －６ 19. The semiconductor device according to claim 1, wherein the temperature is 0.15 to 1.5° C. or less.

20. The semiconductor device according to claim 1 , wherein the semiconductor chip is a silicon carbide chip.

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