Semiconductor Device

Abstract

To provide a semiconductor device capable of reducing inductance.SOLUTION: A semiconductor device 1 includes: a first insulating base material 41 which has a fifth face where a first semiconductor element 10 is bonded and a sixth face, the first semiconductor element having a first face with a first electrode 11 provided thereon and a second face with a second electrode 12 provided thereon; a second insulating base material 81 which has a seventh face where a second semiconductor element 20 is bonded and an eighth face, the second semiconductor element having a third face with a third electrode 21 provided thereon and a fourth face with a fourth electrode 22 provided thereon; first wiring 61 which penetrates through the first insulating base material, and which is electrically connected to the first electrode and laminated on the sixth face of the first insulating base material; second wiring 62 which penetrates through the second insulating base material and which is electrically connected to the third electrode and laminated on the eighth face of the second insulating base material; a first wiring member 110 which has a ninth face provided on a second face side of the first semiconductor element and which is electrically connected to the second electrode; and a second wiring member 120 which has an eleventh face provided on an eighth face side of the second insulating base material and which is electrically connected to the second wiring. The first wiring member and the second wiring member have currents flowing therethrough in opposite directions from one another.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, a semiconductor device has been known in which a semiconductor element is attached to a resin film such as polyimide via an adhesive layer, and a wiring layer is formed on the surface of the resin film opposite the adhesive layer (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-046523 A Summary of the Invention [Problem to be solved by the invention]

[0004] A further reduction in inductance is desired for high-speed switching operations and the like.

[0005] An object of the present disclosure is to provide a semiconductor device capable of reducing inductance. [Means for solving the problem]

[0006] According to one embodiment of the present disclosure, there is provided a semiconductor device comprising: a first semiconductor element having a first surface and a second surface opposite to the first surface, a first electrode provided on the first surface and a second electrode provided on the second surface; a second semiconductor element having a third surface and a fourth surface opposite to the third surface, a third electrode provided on the third surface and a fourth electrode provided on the fourth surface; a first insulating base material having a fifth surface to which the first semiconductor element is bonded and a sixth surface opposite to the fifth surface; a second insulating base material having a seventh surface to which the second semiconductor element is bonded and an eighth surface opposite to the seventh surface; a first wiring that penetrates the first insulating base material and is electrically connected to the first electrode and is laminated on the sixth surface of the first insulating base material; a second wiring member having a ninth surface and a tenth surface opposite to the ninth surface, the ninth surface being provided on the second surface side of the first semiconductor element and electrically connected to the second electrode; and a second wiring member having an eleventh surface and a twelfth surface opposite to the eleventh surface, the eleventh surface being provided on the eighth surface side of the second insulating base material and electrically connected to the second wiring, the tenth surface of the first wiring member being bonded onto the seventh surface of the second insulating base material, and currents flowing in opposite directions to each other are provided in the first wiring member and the second wiring member. Effect of the Invention

[0007] According to the present disclosure, inductance can be reduced. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Diagram 2] 1 is a circuit diagram showing a semiconductor device according to a first embodiment. [Diagram 3] 1A to 1C are cross-sectional views (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 5A to 5C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 4A to 4C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment; [Figure 7] FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 8] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant description. In this disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is described as an XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is described as a YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is described as a ZX plane. For convenience, the Z1-Z2 direction is defined as the up-down direction, the Z1 side is defined as the upper side, and the Z2 side is defined as the lower side. In addition, a planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of an object viewed from the Z1 side. However, the semiconductor device can be used upside down or can be arranged at any angle.

[0010] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a semiconductor device.

[0011] [Configuration of semiconductor device] First, a description will be given of a cross-sectional configuration of the semiconductor device according to the first embodiment. Fig. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0012] As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a semiconductor element 10, a semiconductor element 20, a flexible wiring board 40, and a flexible wiring board 80. For example, devices using silicon (Si) or silicon carbide (SiC) can be used as the semiconductor elements 10 and 20. For example, devices using gallium nitride (GaN) or gallium arsenide (GaAs) can also be used as the semiconductor elements 10 and 20. For example, the semiconductor elements 10 and 20 can be semiconductor elements as active elements (for example, silicon chips such as CPUs), insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), diodes, etc. The semiconductor elements 10 and 20 of this embodiment are semiconductor elements having electrodes provided on the front and back surfaces. The planar shape of the semiconductor elements 10 and 20 can be any shape and any size. The planar shape of the semiconductor elements 10 and 20 is formed, for example, in a rectangular shape. The thickness of the semiconductor elements 10 and 20 may be, for example, about 50 μm to 500 μm.

[0013] The semiconductor element 10 has one surface 10A and another surface 10B opposite to the one surface 10A. The semiconductor element 10 also has a main body 15, an electrode 11, an electrode 12, and an electrode 13. The electrodes 11 and 13 are provided on the one surface 10A, and the electrode 12 is provided on the other surface 10B. For example, the electrodes 11, 12, and 13 can be a source electrode, a drain electrode, and a gate electrode, respectively.

[0014] The semiconductor element 20 has one surface 20A and another surface 20B opposite to the one surface 20A. The semiconductor element 20 also has a main body 25, an electrode 21, an electrode 22, and an electrode 23. The electrodes 21 and 23 are provided on the one surface 20A, and the electrode 22 is provided on the other surface 20B. For example, the electrodes 21, 22, and 23 can be a source electrode, a drain electrode, and a gate electrode, respectively.

[0015] The material of the electrodes 11, 12, 13, 21, 22, and 23 (hereinafter, these may be collectively referred to as "electrodes") may be, for example, a metal such as aluminum (Al) or copper (Cu), or an alloy containing at least one metal selected from these metals. If necessary, a surface treatment layer may be formed on the surface of the electrodes. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order). As the Au layer, Ni layer, and Pd layer, for example, a metal layer (electroless plating metal layer) formed by electroless plating may be used. The Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy.

[0016] The flexible wiring board 40 has an insulating base material 41, an insulating adhesive layer 42, and a wiring layer 45. The insulating base material 41 has one surface 41A and another surface 41B opposite to the one surface 41A. The adhesive layer 42 is provided under the one surface 41A, and the wiring layer 45 is provided on the other surface 41B. The wiring layer 45 is laminated on the other surface 41B. The wiring layer 45 has a seed layer 43 and a metal layer 44.

[0017] The flexible wiring board 80 has an insulating base material 81, an insulating adhesive layer 82, and a wiring layer 85. The insulating base material 81 has one surface 81A and another surface 81B opposite to the one surface 81A. The adhesive layer 82 is provided on the one surface 81A, and the wiring layer 85 is provided below the other surface 81B. The wiring layer 85 is laminated on the other surface 81B. The wiring layer 85 has a seed layer 83 and a metal layer 84.

[0018] The insulating substrates 41 and 81 may be, for example, a resin film. The resin film may be made of an insulating resin such as a polyimide resin, a polyethylene resin, or an epoxy resin. The insulating substrates 41 and 81 may be, for example, flexible. Here, flexibility refers to the property of being able to bend or flex. The planar shape of the insulating substrates 41 and 81 may be any shape and any size. The planar shape of the insulating substrates 41 and 81 may be, for example, rectangular. The thickness of the insulating substrates 41 and 81 may be, for example, about 50 μm to 100 μm.

[0019] The semiconductor device 1 further includes a lead terminal 110, a lead terminal 120, and a lead terminal 130. The lead terminals 110, 120, and 130 are formed of, for example, a lead frame. The lead terminals 110, 120, and 130 are an example of a wiring member.

[0020] The semiconductor element 10 and the lead terminal 130 are adhered to one surface 41A of the insulating base material 41 by an adhesive layer 42. One surface 10A of the semiconductor element 10 faces one surface 41A of the insulating base material 41. Also, one surface (Z1 side) of the lead terminal 130 faces one surface 41A of the insulating base material 41. The insulating base material 41 and the adhesive layer 42 are formed with a through hole 51 exposing the electrode 11, a through hole 53 exposing the lead terminal 130, and a through hole 54 exposing the electrode 13.

[0021] For example, an epoxy-, polyimide-, or silicone-based adhesive can be used as the material of the adhesive layer 42. The thickness of the adhesive layer 42 can be, for example, about 20 μm to 40 μm.

[0022] For example, electrode 11 and through hole 51 are on the X2 side of electrode 13 and through hole 54, and electrode 21 and through hole 52 are on the X1 side of electrode 23 and through hole 55. A plurality of pairs of electrode 11 and through hole 51 may be provided, and a plurality of pairs of electrode 21 and through hole 52 may be provided.

[0023] The wiring layer 45 has a wire 61 connected to the electrode 11 through the through hole 51 and a wire 63 connected to the electrode 13 through the through hole 54. The wire 61 is also connected to the lead terminal 130 through the through hole 53.

[0024] The wiring 61 includes a via wiring filled in the through hole 51, a via wiring filled in the through hole 53, and a wiring pattern formed on the other surface 41B of the insulating base material 41. The wiring 63 includes a via wiring filled in the through hole 54, and a wiring pattern formed on the other surface 41B of the insulating base material 41.

[0025] The seed layer 43 covers the other surface 41B of the insulating base material 41 and the inner surfaces of the through holes 51, 53, and 54. The seed layer 43 is formed so as to continuously cover the other surface 41B of the insulating base material 41, the inner surfaces of the through holes 51, 53, and 54, the surfaces of the electrodes 11, 12, and 13 exposed at the bottoms of the through holes 51, 53, and 54, and the surface of the lead terminal 130. A metal film (sputtered film) formed by a sputtering method can be used as the seed layer 43. For example, a two-layered metal film in which a Ti layer made of titanium (Ti) and a Cu layer made of copper (Cu) are laminated in order on the other surface 41B of the insulating base material 41 and the inner surfaces of the through holes 51, 53, and 54 can be used as the seed layer 43 formed by the sputtering method. In this case, the thickness of the Ti layer can be, for example, about 10 nm to 300 nm, and the thickness of the Cu layer can be, for example, about 100 nm to 1000 nm. The Ti layer functions as an adhesion layer that improves adhesion between the insulating base material 41 and the electrodes, etc., and the seed layer 43. The Ti layer also functions as a metal barrier layer that suppresses copper diffusion from the Cu layer, etc., to the insulating base material 41, etc. As the material of the metal film that functions as such an adhesion layer and metal barrier layer, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), chromium (Cr), etc. can be used in addition to Ti.

[0026] The semiconductor element 20 and the lead terminal 110 are adhered to one surface 81A of the insulating base material 81 by an adhesive layer 82. One surface 20A of the semiconductor element 20 faces one surface 81A of the insulating base material 81. The insulating base material 81 and the adhesive layer 82 are formed with a through hole 52 through which the electrode 21 is exposed and a through hole 55 through which the electrode 23 is exposed.

[0027] For example, an epoxy-, polyimide-, or silicone-based adhesive can be used as the material of the adhesive layer 82. The thickness of the adhesive layer 82 can be, for example, about 20 μm to 40 μm.

[0028] The wiring layer 85 has a wiring 62 connected to the electrode 21 through the through hole 52 and a wiring 64 connected to the electrode 23 through the through hole 55 .

[0029] The wiring 62 includes a via wiring filled in the through hole 52 and a wiring pattern formed on the other surface 81B of the insulating base material 81. The wiring 64 includes a via wiring filled in the through hole 55 and a wiring pattern formed on the other surface 81B of the insulating base material 81.

[0030] The seed layer 83 covers the other surface 81B of the insulating base material 81 and the inner surfaces of the through holes 52 and 55. The seed layer 83 is formed so as to continuously cover the other surface 81B of the insulating base material 81, the inner surfaces of the through holes 52 and 55, and the surfaces of the electrodes exposed at the bottoms of the through holes 52 and 55. A metal film (sputtered film) formed by a sputtering method can be used as the seed layer 83. For example, a two-layered metal film in which a Ti layer made of titanium (Ti) and a Cu layer made of copper (Cu) are laminated in this order on the other surface 81B of the insulating base material 81 and the inner surfaces of the through holes 52 and 55 can be used as the seed layer 83 formed by the sputtering method. In this case, the thickness of the Ti layer can be, for example, about 10 nm to 300 nm, and the thickness of the Cu layer can be, for example, about 100 nm to 1000 nm. The Ti layer functions as an adhesive layer that improves the adhesiveness between the insulating base material 81, the electrodes, and the seed layer 83. The Ti layer also functions as a metal barrier layer that suppresses the diffusion of copper from the Cu layer, etc., into the insulating base material 81, etc. As the material of the metal film that functions as such an adhesion layer and metal barrier layer, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), chromium (Cr), etc. can be used in addition to Ti.

[0031] For example, copper or a copper alloy can be used as the material of the metal layers 44 and 84. For example, a metal layer formed by electrolytic plating (electrolytic plated metal layer) can be used as the metal layers 44 and 84.

[0032] One surface (Z1 side) of the lead terminal 110 is bonded to the electrode 12 of the semiconductor element 10 by a conductive adhesive layer 71. The other surface (Z2 side) of the lead terminal 110 is bonded to an adhesive layer 82. One surface (Z1 side) of the lead terminal 120 is bonded to the wiring 62 of the wiring layer 45 by a conductive adhesive layer 72. One surface (Z2 side) of the lead terminal 130 is bonded to the electrode 22 of the semiconductor element 20 by a conductive adhesive layer 73. The other surface (Z1 side) of the lead terminal 130 is bonded to the adhesive layer 42 and is electrically connected to the wiring 61. The conductive adhesive layers 71 to 73 are, for example, solder layers or sintered metal layers. The conductive adhesive layers 71 to 73 may be made of a conductive paste.

[0033] The semiconductor element 10 and the semiconductor element 20 are arranged side by side in the lateral direction, for example, the X1-X2 direction. The semiconductor element 20 is located on the X2 side of the semiconductor element 10.

[0034] The lead terminals 110 and 120 extend parallel to each other toward the X1 side as viewed from the semiconductor element 10. Therefore, the semiconductor element 20 is disposed on the opposite side to the direction in which the lead terminals 110 and 120 extend as viewed from the semiconductor element 10. The distance between the lead terminals 110 and 120 is approximately the same as the thickness of the flexible wiring board 80, and is, for example, 1 mm or less. Moreover, the lead terminal 130 extends toward the X2 side as viewed from the semiconductor element 10.

[0035] For example, the thickness T1 of the semiconductor element 10 is equal to the thickness T2 of the semiconductor element 20. Furthermore, the thickness T3 of the lead terminal 110 is equal to the thickness T4 of the lead terminal 130. Therefore, the thickness T5 of the laminated structure of the lead terminal 110 and the semiconductor element 10 is equal to the thickness T6 of the laminated structure of the semiconductor element 20 and the lead terminal 130. Note that "equal" in this disclosure does not mean that they are completely identical mathematically, but means that they have a relationship that can be said to be "equal" according to social convention. For example, one is in the range of about 90% to 110% of the other.

[0036] An electrode 12 of the semiconductor element 10 is electrically connected to the lead terminal 110. An electrode 21 of the semiconductor element 20 is electrically connected to the lead terminal 120 via a wiring 62. An electrode 11 of the semiconductor element 10 and an electrode 22 of the semiconductor element 20 are electrically connected to the lead terminal 130 via a wiring 61. A lead terminal (not shown) is also connected to the wiring 63 of the wiring layer 45, and this lead terminal is electrically connected to the electrode 13 of the semiconductor element 10. Similarly, a lead terminal (not shown) is also connected to the wiring 64 of the wiring layer 85, and this lead terminal is electrically connected to the electrode 23 of the semiconductor element 20.

[0037] Here, a description will be given of the circuit configuration of the semiconductor device 1 according to the first embodiment. Fig. 2 is a circuit diagram showing the semiconductor device according to the first embodiment.

[0038] 2, electrode 12 of semiconductor element 10 is electrically connected to the P terminal via lead terminal 110. Electrode 21 of semiconductor element 20 is electrically connected to the N terminal via lead terminal 120. Electrode 11 of semiconductor element 10 and electrode 22 of semiconductor element 20 are electrically connected to the O terminal via lead terminal 130. The P terminal is a positive input terminal, the N terminal is a negative input terminal, and the O terminal is an output terminal. Therefore, currents flow in the opposite directions to each other through lead terminal 110 and lead terminal 120.

[0039] [Method of manufacturing semiconductor device] Next, a method for manufacturing a semiconductor device according to the first embodiment will be described. Fig. 3 to Fig. 6 are cross-sectional views showing the method for manufacturing a semiconductor device according to the first embodiment. In the following description, a so-called multi-piece manufacturing method will be described in which the parts that will become the semiconductor device 1 are manufactured collectively and then diced to manufacture a large number of semiconductor devices 1. For ease of explanation, the parts that will ultimately become the components of the semiconductor device 1 will be described with the reference numerals of the final components.

[0040] First, as shown in FIG. 3(a), a large insulating base material 41 having one surface 41A and the other surface 41B is prepared. The large insulating base material 41 has, for example, a plurality of individual regions in which semiconductor devices 1 are formed, arranged in a matrix pattern. Here, the individual regions are regions that will ultimately be cut along predetermined cutting lines to be individualized and become individual semiconductor devices 1. The number of individual regions that the large insulating base material 41 has is not particularly limited. One surface 41A of the insulating base material 41 is provided with an insulating adhesive layer 42 that covers the entire one surface 41A.

[0041] 3(b), through holes 51, 53, and 54 are formed at required locations of the insulating base material 41 and the adhesive layer 42, penetrating the insulating base material 41 and the adhesive layer 42 in the thickness direction. The through holes 51, 53, and 54 can be formed by, for example, a laser processing method using a CO2 laser, a UV-YAG laser, or the like, or a punching method. For example, the through hole 51 is formed on the X2 side of the through hole 54, and the through hole 53 is formed on the X2 side of the through hole 51.

[0042] 3(c), the semiconductor element 10 and the lead terminals 130 are bonded to the insulating base material 41 by the adhesive layer 42. At this time, one surface 10A of the semiconductor element 10 is opposed to one surface 41A of the insulating base material 41, and alignment is performed so that the electrodes 11 overlap the through holes 51 and the electrodes 13 overlap the through holes 54 in a plan view. Additionally, alignment is performed so that the lead terminals 130 overlap the through holes 53 in a plan view.

[0043] 4(a), a wiring layer 45 including a seed layer 43 and a metal layer 44 is formed on the other surface 41B of the insulating base material 41. The wiring layer 45 can be formed by, for example, a semi-additive method.

[0044] Specifically, the seed layer 43 is formed so as to cover the entire other surface 41B of the insulating base material 41 and the entire inner surfaces of the through holes 51, 53, and 54. The seed layer 43 can be formed by, for example, a sputtering method or an electroless plating method. For example, when the seed layer 43 is formed by a sputtering method, first, titanium is deposited by sputtering to form a Ti layer so as to cover the other surface 41B of the insulating base material 41 and the inner surfaces of the through holes 51, 53, and 54. Then, copper is deposited by sputtering on the Ti layer to form a Cu layer. This makes it possible to form the seed layer 43 of a two-layer structure (Ti layer / Cu layer). When the seed layer 43 is formed by an electroless plating method, for example, the seed layer 43 made of a Cu layer (one-layer structure) can be formed by an electroless copper plating method.

[0045] Next, a plating resist layer (not shown) having openings in the portion where the wiring layer 45 is to be formed, i.e., the portion where the wirings 61 and 63 are to be formed, is formed on the seed layer 43. Next, a metal layer 44 made of copper or the like is formed in the openings of the plating resist layer by electrolytic plating using the seed layer 43 as a plating power supply path. Thereafter, the plating resist layer is removed. Next, the seed layer 43 is removed by wet etching using the metal layer 44 as a mask. In this manner, the wiring layer 45 including the seed layer 43 and the metal layer 44 can be formed. The wiring layer 45 has the wirings 61 and 63. The insulating base material 41, the adhesive layer 42, and the wiring layer 45 constitute a flexible wiring board 40.

[0046] Also, as shown in FIG. 4(b), a large insulating base material 81 having one surface 81A and the other surface 81B is prepared. The large insulating base material 81 has, for example, a plurality of individual regions in which the semiconductor device 1 is formed, arranged in a matrix. Here, the individual regions are regions that are finally cut along a predetermined cutting line to be individualized and become individual semiconductor devices 1. The number of individual regions that the large insulating base material 81 has is not particularly limited. An insulating adhesive layer 82 that covers the entire one surface 81A of the insulating base material 81 is provided on one surface 81A of the insulating base material 81. Note that FIGS. 4(b) to 5(b) show a state rotated 180° around the Y1-Y2 direction with respect to FIG. 1.

[0047] 4(c), through holes 52 and 55 are formed in required locations of the insulating base material 81 and the adhesive layer 82, penetrating the insulating base material 81 and the adhesive layer 82 in the thickness direction. The through holes 51 and 54 can be formed by the same method as the through holes 52 and 55. For example, the through hole 52 is formed on the X1 side of the through hole 55.

[0048] 5(a), the semiconductor element 20 and the lead terminal 110 are bonded to the insulating base material 81 by the adhesive layer 82. At this time, one surface 20A of the semiconductor element 20 is opposed to one surface 81A of the insulating base material 81, and alignment is performed so that the electrode 21 overlaps the through hole 52 and the electrode 23 overlaps the through hole 55 in a plan view. In addition, the lead terminal 110 is positioned on the X1 side of the semiconductor element 20.

[0049] 5(b), a wiring layer 85 including a seed layer 83 and a metal layer 84 is formed on the other surface 81B of the insulating base material 81. The wiring layer 85 can be formed by a method similar to that for the wiring layer 45. The wiring layer 85 has wires 62 and 64. The insulating base material 81, the adhesive layer 82, and the wiring layer 85 form a flexible wiring board 80.

[0050] 6(a), the flexible wiring board 80 is turned upside down. Then, a conductive adhesive layer 71 is provided on the lead terminals 110, a conductive adhesive layer 72 is provided on the Z2 side surface of the wiring 62 of the wiring layer 85, and a conductive adhesive layer 73 is provided on the surface 20B of the semiconductor element 20. The conductive adhesive layers 71 to 73 are in an uncured state.

[0051] 6(b), the electrode 12 is joined to the lead terminal 110 by a conductive adhesive layer 71, and the lead terminal 130 is joined to the electrode 22 by a conductive adhesive layer 73. Furthermore, the lead terminal 120 is joined to the wiring 62 by a conductive adhesive layer 72. During this joining, the conductive adhesive layers 71 to 73 are cured.

[0052] In this manner, the semiconductor device 1 according to the first embodiment can be manufactured.

[0053] In the semiconductor device 1 according to the first embodiment, a current flows from the P terminal to the N terminal. Therefore, in the lead terminal 110, a current flows from the X1 side to the X2 side, and in the lead terminal 120, a current flows from the X2 side to the X1 side. In this embodiment, the distance between the lead terminals 110 and 120 is approximately the same as the thickness of the flexible wiring board 80. Therefore, the inductance can be significantly reduced.

[0054] Moreover, the wiring layer 45 can be formed finely and with high accuracy on the other surface 41B of the insulating base material 41 by a semi-additive method, and the wiring layer 85 can be formed finely and with high accuracy on the other surface 81B of the insulating base material 81 by a semi-additive method. The wiring layer 45 can also be formed on the other surface 41B of the insulating base material 41 by a subtractive method, and the wiring layer 85 can also be formed on the other surface 41B of the insulating base material 81 by a subtractive method. Furthermore, by adhering the semiconductor element 10 to one surface 41A of the insulating base material 41 by the adhesive layer 42, the position of the semiconductor element 10 can be fixed with respect to the insulating base material 41 and the wiring layer 45, and by adhering the semiconductor element 20 to one surface 81A of the insulating base material 81 by the adhesive layer 82, the position of the semiconductor element 20 can be fixed with respect to the insulating base material 81 and the wiring layer 85. Therefore, according to this embodiment, excellent positional accuracy and connection reliability can be obtained.

[0055] As a reference example, assume that a semiconductor device (power module) is manufactured in which a semiconductor element is fixed to a metal foil (copper foil, etc.) provided on the surface of an insulating substrate (ceramic substrate, etc.). When manufacturing such a semiconductor device, solder reflow is performed to fix the semiconductor element, and the semiconductor element may be misaligned to some extent during this reflow. For this reason, a relatively large margin is required for the placement of the semiconductor element at the design stage.

[0056] On the other hand, in this embodiment, the semiconductor element 10 is bonded to the insulating base material 41 in which the through holes 51 and 54 are formed, and the wiring layer 45 is formed by the semi-additive method. Also, the semiconductor element 20 is bonded to the insulating base material 81 in which the through holes 52 and 54 are formed, and the wiring layer 85 is formed by the semi-additive method. Therefore, excellent positional accuracy and connection reliability can be obtained, and a large margin as in the reference example is not required.

[0057] Furthermore, the thickness T5 of the laminated structure of the lead terminal 110 and the semiconductor element 10 is equal to the thickness T6 of the laminated structure of the semiconductor element 20 and the lead terminal 130. Therefore, alignment is easy when joining the electrode 12 to the lead terminal 110 with the conductive adhesive layer 71 and when joining the lead terminal 130 to the electrode 22 with the conductive adhesive layer 73.

[0058] Second embodiment Next, a second embodiment will be described with reference to Fig. 7, which is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0059] 7, the semiconductor device 2 according to the second embodiment has a lead terminal 210 instead of the lead terminal 110, and has a lead terminal 230 instead of the lead terminal 130. The lead terminals 210 and 230 are formed, for example, from a stepped lead frame. The lead terminals 210 and 230 are an example of a wiring member.

[0060] The lead terminal 210 has a joint portion 211 and an extending portion 212. The joint portion 211 is thicker than the extending portion 212. For example, the thickness of the extending portion 212 is equal to the thickness T3 of the lead terminal 110 in the first embodiment, and the thickness T7 of the joint portion 211 is greater than the thickness T3. The joint portion 211 is joined to the electrode 12 of the semiconductor element 10 by a conductive adhesive layer 71, and is bonded to one surface 81A of the insulating base material 81 by an adhesive layer 82. The extending portion 212 extends from the joint portion 211 to the X1 side. For example, the Z1 side surface of the joint portion 211 and the Z1 side surface of the extending portion 212 are flush with each other. The joint portion 211 is an example of a first joint portion, and the extending portion 212 is an example of a first extending portion.

[0061] The lead terminal 230 has a joint portion 231 and an extending portion 232. The joint portion 231 is thicker than the extending portion 232. For example, the thickness of the extending portion 232 is equal to the thickness T4 of the lead terminal 130 in the first embodiment, and the thickness T8 of the joint portion 231 is greater than the thickness T4. The joint portion 231 is joined to the electrode 22 of the semiconductor element 20 by the conductive adhesive layer 73, and is bonded to one surface 41A of the insulating base material 41 by the adhesive layer 42. The extending portion 232 extends from the joint portion 231 to the X2 side. For example, the Z2 side surface of the joint portion 231 and the Z2 side surface of the extending portion 232 are flush with each other. The joint portion 231 is an example of a second joint portion, and the extending portion 232 is an example of a second extending portion.

[0062] For example, the thickness T7 of the bonding portion 211 is equal to the thickness T8 of the bonding portion 231. Therefore, the thickness T9 of the laminated structure of the bonding portion 211 and the semiconductor element 10 is equal to the thickness T10 of the laminated structure of the semiconductor element 20 and the bonding portion 231.

[0063] The other configuration is similar to that of the first embodiment.

[0064] When manufacturing the semiconductor device 2 according to the second embodiment, the lead terminals 210 and 230 are prepared in advance. Then, instead of the lead terminal 110, the lead terminal 210 is joined to the semiconductor element 10 and the insulating base material 81, and instead of the lead terminal 130, the lead terminal 230 is joined to the semiconductor element 20 and the insulating base material 41. In this manner, the semiconductor device 2 can be manufactured.

[0065] In the semiconductor device 2 according to the second embodiment, a current also flows from the P terminal to the N terminal. Therefore, in the lead terminal 210, a current flows from the X1 side to the X2 side, and in the lead terminal 120, a current flows from the X2 side to the X1 side. Therefore, as in the first embodiment, the inductance can be significantly reduced. Also, as in the first embodiment, excellent positional accuracy and connection reliability can be obtained.

[0066] Furthermore, a thickness T9 of the laminated structure of the bonding portion 211 and the semiconductor element 10 is equal to a thickness T10 of the laminated structure of the semiconductor element 20 and the bonding portion 231. This makes it easy to perform alignment when bonding the electrode 12 to the lead terminal 210 with the conductive adhesive layer 71 and bonding the bonding portion 231 to the electrode 22 with the conductive adhesive layer 73.

[0067] In addition, since the joint portion 211 is thicker than the extending portion 212, by separating the lead terminal 210 from the lead terminal 120, it is easy to prevent a short circuit between the lead terminals 210 and 120.

[0068] Third embodiment Next, a third embodiment will be described with reference to Fig. 8, which is a cross-sectional view showing a semiconductor device according to the third embodiment.

[0069] 8, in the semiconductor device 3 according to the third embodiment, the flexible wiring board 80 extends to the X1 side along the Z2 side surface of the lead terminal 110. Also, the lead terminal 120 is not provided.

[0070] The other configuration is similar to that of the first embodiment.

[0071] When manufacturing the semiconductor device 3 of the third embodiment, for example, when the lead terminal 110 is adhered to one surface 81A of the insulating substrate 81, the lead terminal 110 and the wiring 62 are aligned so that they extend in a common direction (X1 side) when viewed from the semiconductor element 10.

[0072] In the semiconductor device 3 according to the third embodiment, the wiring 62 of the wiring layer 85 exerts the same function as the lead terminal 120. Therefore, as in the first embodiment, the inductance can be significantly reduced. Also, as in the first embodiment, excellent positional accuracy and connection reliability can be obtained. Furthermore, the process required for joining the lead terminal 120 can be omitted.

[0073] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0074] 1, 2, 3 Semiconductor Device 10, 20 Semiconductor element 10A, 10B, 20A, 20B side 11, 21 electrode 12, 22 electrodes 13, 23 electrodes 40, 80 Flexible wiring board 41, 81 Insulating substrate 42, 82 Adhesive layer 45, 85 wiring layer 51, 52, 53, 54, 55 Through holes 61, 62, 63, 64 Wiring 71, 72, 73 Conductive adhesive layer 110, 120, 130, 210, 230 Lead terminal

Claims

1. a first semiconductor element having a first surface and a second surface opposite to the first surface, a first electrode being provided on the first surface and a second electrode being provided on the second surface; a second semiconductor element having a third surface and a fourth surface opposite to the third surface, the second semiconductor element having a third electrode provided on the third surface and a fourth electrode provided on the fourth surface; a first insulating base material having a fifth surface to which the first semiconductor element is bonded and a sixth surface opposite to the fifth surface; a second insulating base material having a seventh surface to which the second semiconductor element is bonded and an eighth surface opposite to the seventh surface; a first wiring that penetrates the first insulating base material, is electrically connected to the first electrode, and is laminated on the sixth surface of the first insulating base material; a second wiring that penetrates the second insulating base material, is electrically connected to the third electrode, and is laminated on the eighth surface of the second insulating base material; a first wiring member having a ninth surface and a tenth surface opposite to the ninth surface, the ninth surface being provided on the second surface side of the first semiconductor element and electrically connected to the second electrode; a second wiring member having an eleventh surface and a twelfth surface opposite to the eleventh surface, the eleventh surface being provided on the eighth surface side of the second insulating base material and electrically connected to the second wiring; having the tenth surface of the first wiring member is joined onto the seventh surface of the second insulating base material; A semiconductor device in which currents flow in opposite directions through the first wiring member and the second wiring member.

2. a first conductive adhesive layer that bonds the first wiring member and the second electrode to each other; a second conductive adhesive layer that bonds the second wiring member and the second wiring to each other; The semiconductor device according to claim 1 ,

3. the first wiring member has a first lead terminal, 3. The semiconductor device according to claim 1, wherein the second wiring member has a second lead terminal.

4. a first semiconductor element having a first surface and a second surface opposite to the first surface, a first electrode being provided on the first surface and a second electrode being provided on the second surface; a second semiconductor element having a third surface and a fourth surface opposite to the third surface, the second semiconductor element having a third electrode provided on the third surface and a fourth electrode provided on the fourth surface; a first insulating base material having a fifth surface to which the first semiconductor element is bonded and a sixth surface opposite to the fifth surface; a second insulating base material having a seventh surface to which the second semiconductor element is bonded and an eighth surface opposite to the seventh surface; a first wiring that penetrates the first insulating base material, is electrically connected to the first electrode, and is laminated on the sixth surface of the first insulating base material; a second wiring that penetrates the second insulating base material, is electrically connected to the third electrode, and is laminated on the eighth surface of the second insulating base material; a first wiring member having a ninth surface and a tenth surface opposite to the ninth surface, the ninth surface being provided on the second surface side of the first semiconductor element and electrically connected to the second electrode; having the tenth surface of the first wiring member is joined onto the seventh surface of the second insulating base material; A semiconductor device in which currents flow in opposite directions through the first wiring member and the second wiring.

5. a third wiring member provided between the fourth surface of the second semiconductor element and the fifth surface of the first insulating base material and electrically connected to the fourth electrode, The semiconductor device according to claim 1 , wherein the first wiring passes through the first insulating base material and is connected to the third wiring member.

6. The semiconductor device according to claim 5 , further comprising a third conductive adhesive layer that bonds the third wiring member and the fourth electrode to each other.

7. 7. The semiconductor device according to claim 5, wherein the third wiring member has a third lead terminal.

8. Between the first insulating substrate and the second insulating substrate, the first wiring member and the first semiconductor element are stacked, The semiconductor device according to claim 5 , wherein the second semiconductor element and the third wiring member are stacked.

9. a thickness of a laminated structure of the first wiring member and the first semiconductor element; and The semiconductor device according to claim 8 , wherein a thickness of a laminated structure of the second semiconductor element and the third wiring member is equal to that of the third wiring member.

10. the thickness of the first semiconductor element is equal to the thickness of the second semiconductor element, The first wiring member is a first bonding portion bonded to the first semiconductor element and the second insulating substrate, the first bonding portion having a first thickness; a first extension extending from the first joint and having a second thickness less than the first thickness; having The third wiring member is a second bonding portion bonded to the first insulating substrate and the second semiconductor element and having the first thickness; a second extension portion extending from the second joint portion and having the second thickness; The semiconductor device according to claim 5 , further comprising:

11. the first semiconductor element has a fifth electrode provided on the first surface, the second semiconductor element has a sixth electrode provided on the third surface, a third wiring that penetrates the first insulating base material, is electrically connected to the fifth electrode, and is laminated on the sixth surface of the first insulating base material; a fourth wiring that penetrates the second insulating base material, is electrically connected to the sixth electrode, and is laminated on the eighth surface of the second insulating base material; The semiconductor device according to claim 1 , further comprising:

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