Semiconductor Device

Abstract

To provide a semiconductor device capable of reducing inductance.SOLUTION: A semiconductor device 1 includes: a first semiconductor element 10 which has a first face with a first electrode 11 provided thereon and a second face with a second electrode 12 provided thereon; a second semiconductor element 20 which has a third face with a third electrode 21 provided thereon and a fourth face with a fourth electrode 22 provided thereon; a first insulating base material 41 having a fifth face and a sixth face; first wiring 51 which is electrically connected to the first electrode and laminated on the sixth face of the first insulating base material; a second insulating base material 81 having a seventh face bonded to a third face side of the second semiconductor element and an eighth face; second wiring 62 which is electrically connected to the third electrode and laminated on the eighth face of the second insulating base material; a first wiring member 110 electrically connected to the second electrode of the first semiconductor element; a second wiring member 130 which is electrically connected to the first wring on a ninth face facing the sixth face of the first insulating base material and electrically connected to the fourth electrode of the semiconductor element on a tenth face on a side opposite to the ninth face; and a third wiring member 120 which is electrically connected to the second wiring, the third wiring member and the first wiring member having currents flowing therethrough in opposite directions from one another.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, a semiconductor device has been known in which a semiconductor element is attached to a resin film such as polyimide via an adhesive layer, and a wiring layer is formed on the surface of the resin film opposite the adhesive layer (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-046523 A Summary of the Invention [Problem to be solved by the invention]

[0004] A further reduction in inductance is desired for high-speed switching operations and the like.

[0005] An object of the present disclosure is to provide a semiconductor device capable of reducing inductance. [Means for solving the problem]

[0006] According to one embodiment of the present disclosure, there is provided a first semiconductor element having a first surface and a second surface opposite to the first surface, a first electrode being provided on the first surface and a second electrode being provided on the second surface; a second semiconductor element having a third surface and a fourth surface opposite to the third surface, a third electrode being provided on the third surface and a fourth electrode being provided on the fourth surface; a first insulating base material having a fifth surface bonded to the first surface side of the first semiconductor element and a sixth surface opposite to the fifth surface; a first wiring penetrating the first insulating base material and electrically connected to the first electrode and laminated on the sixth surface of the first insulating base material; a seventh surface bonded to the third surface side of the second semiconductor element and an eighth surface opposite to the seventh surface. the eighth surface of the second insulating substrate; a second wiring that penetrates the second insulating substrate and is electrically connected to the third electrode and is laminated on the eighth surface of the second insulating substrate; a first wiring member that is electrically connected to the second electrode of the first semiconductor element; a ninth surface facing the sixth surface of the first insulating substrate and a tenth surface opposite the ninth surface; a second wiring member that is electrically connected to the first wiring on the ninth surface and is electrically connected to the fourth electrode of the second semiconductor element on the tenth surface; and a third wiring member that is electrically connected to the second wiring, wherein currents flow in mutually opposite directions through the first wiring member and the third wiring member. Effect of the Invention

[0007] According to the present disclosure, inductance can be reduced. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Diagram 2] 1 is a circuit diagram showing a semiconductor device according to a first embodiment. [Diagram 3] 1A to 1C are cross-sectional views (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 5A to 5C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5]5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 7] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 8] FIG. 11 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 9] FIG. 13 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. [Figure 10] FIG. 13 is a cross-sectional view showing a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant description. In this disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is described as an XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is described as a YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is described as a ZX plane. For convenience, the Z1-Z2 direction is defined as the up-down direction, the Z1 side is defined as the upper side, and the Z2 side is defined as the lower side. In addition, a planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of an object viewed from the Z1 side. However, the semiconductor device can be used upside down or can be arranged at any angle.

[0010] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a semiconductor device.

[0011] [Configuration of semiconductor device] First, a description will be given of a cross-sectional configuration of the semiconductor device according to the first embodiment. Fig. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0012] As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a semiconductor element 10, a semiconductor element 20, a flexible wiring board 40, and a flexible wiring board 80. For example, devices using silicon (Si) or silicon carbide (SiC) can be used as the semiconductor elements 10 and 20. For example, devices using gallium nitride (GaN) or gallium arsenide (GaAs) can also be used as the semiconductor elements 10 and 20. For example, the semiconductor elements 10 and 20 can be semiconductor elements as active elements (for example, silicon chips such as CPUs), insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), diodes, etc. The semiconductor elements 10 and 20 of this embodiment are semiconductor elements having electrodes provided on the front and back surfaces. The planar shape of the semiconductor elements 10 and 20 can be any shape and any size. The planar shape of the semiconductor elements 10 and 20 is formed, for example, in a rectangular shape. The thickness of the semiconductor elements 10 and 20 may be, for example, about 50 μm to 500 μm.

[0013] The semiconductor element 10 has one surface 10A and another surface 10B opposite to the one surface 10A. The semiconductor element 10 also has a main body 15, an electrode 11, an electrode 12, and an electrode 13. The electrodes 11 and 13 are provided on the one surface 10A, and the electrode 12 is provided on the other surface 10B. For example, the electrodes 11, 12, and 13 can be a source electrode, a drain electrode, and a gate electrode, respectively.

[0014] The semiconductor element 20 has one surface 20A and another surface 20B opposite to the one surface 20A. The semiconductor element 20 also has a main body 25, an electrode 21, an electrode 22, and an electrode 23. The electrodes 21 and 23 are provided on the one surface 20A, and the electrode 22 is provided on the other surface 20B. For example, the electrodes 21, 22, and 23 can be a source electrode, a drain electrode, and a gate electrode, respectively.

[0015] The material of the electrodes 11, 12, 13, 21, 22, and 23 (hereinafter, these may be collectively referred to as "electrodes") may be, for example, a metal such as aluminum (Al), silver (Ag), or copper (Cu), or a metal layer or alloy containing at least one metal selected from these metals. If necessary, a surface treatment layer may be formed on the surface of the electrodes. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order). As the Au layer, Ni layer, and Pd layer, for example, a metal layer formed by electroless plating (electroless plating metal layer) may be used. The Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy.

[0016] The flexible wiring board 40 has an insulating base material 41, an insulating adhesive layer 42, and a wiring layer 45. The insulating base material 41 has one surface 41A and another surface 41B opposite to the one surface 41A. The adhesive layer 42 is provided on the one surface 41A, and the wiring layer 45 is provided on the other surface 41B. The wiring layer 45 is laminated on the other surface 41B. The wiring layer 45 has a seed layer 43 and a metal layer 44.

[0017] The flexible wiring board 80 has an insulating base material 81, an insulating adhesive layer 82, and a wiring layer 85. The insulating base material 81 has one surface 81A and another surface 81B opposite to the one surface 81A. The adhesive layer 82 is provided on the one surface 81A, and the wiring layer 85 is provided on the other surface 81B. The wiring layer 85 is laminated on the other surface 81B. The wiring layer 85 has a seed layer 83 and a metal layer 84.

[0018] The semiconductor device 1 further includes a lead terminal 110, a lead terminal 120, a lead terminal 130, a lead terminal 140, and a lead terminal 150. The lead terminals 110, 120, 130, 140, and 150 are formed of, for example, a lead frame.

[0019] The semiconductor element 10 is adhered to one surface 41A of the insulating base material 41 by an adhesive layer 42. One surface 10A of the semiconductor element 10 faces one surface 41A of the insulating base material 41. The insulating base material 41 and the adhesive layer 42 are formed with a through hole 51 through which the electrode 11 is exposed and a through hole 54 through which the electrode 13 is exposed.

[0020] The insulating substrate 41 may be, for example, a resin film. The resin film may be made of insulating resin such as polyimide resin, polyethylene resin, or epoxy resin. The insulating substrate 41 may have, for example, flexibility. Here, flexibility refers to the property of being able to bend or flex. The planar shape of the insulating substrate 41 may be any shape and any size. The planar shape of the insulating substrate 41 is, for example, rectangular. The thickness of the insulating substrate 41 may be, for example, about 50 μm to 100 μm.

[0021] For example, an epoxy-, polyimide-, or silicone-based adhesive can be used as the material of the adhesive layer 42. The thickness of the adhesive layer 42 can be, for example, about 20 μm to 40 μm.

[0022] For example, the electrode 11 and the through hole 51 are on the X1 side of the electrode 13 and the through hole 54. A plurality of pairs of the electrode 11 and the through hole 51 may be provided.

[0023] The wiring layer 45 has a wiring 61 connected to the electrode 11 through the through hole 51 and a wiring 63 connected to the electrode 13 through the through hole 54 .

[0024] The wiring 61 includes a via wiring filled in the through hole 51 and a wiring pattern formed on the other surface 41B of the insulating base material 41. The wiring 63 includes a via wiring filled in the through hole 54 and a wiring pattern formed on the other surface 41B of the insulating base material 41.

[0025] The seed layer 43 covers the other surface 41B of the insulating base material 41 and the inner surfaces of the through holes 51 and 54. The seed layer 43 is formed so as to continuously cover the other surface 41B of the insulating base material 41, the inner surfaces of the through holes 51 and 54, and the surfaces of the electrodes 11 and 13 exposed at the bottoms of the through holes 51 and 54. A metal film (sputtered film) formed by a sputtering method can be used as the seed layer 43. For example, a two-layered metal film in which a Ti layer made of titanium (Ti) and a Cu layer made of copper (Cu) are laminated in this order on the other surface 41B of the insulating base material 41 and the inner surfaces of the through holes 51 and 54 can be used as the seed layer 43 formed by the sputtering method. In this case, the thickness of the Ti layer can be, for example, about 10 nm to 300 nm, and the thickness of the Cu layer can be, for example, about 100 nm to 1000 nm. The Ti layer functions as an adhesion layer that improves adhesion between the insulating base material 41 and the electrodes, etc., and the seed layer 43. The Ti layer also functions as a metal barrier layer that suppresses copper diffusion from the Cu layer, etc., to the insulating base material 41, etc. As materials for the metal film that functions as such an adhesion layer and metal barrier layer, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), chromium (Cr), etc. can be used in addition to Ti.

[0026] The semiconductor element 20 is adhered to one surface 81A of the insulating base material 81 by an adhesive layer 82. A surface 20A of the semiconductor element 20 faces one surface 81A of the insulating base material 81. The insulating base material 81 and the adhesive layer 82 are formed with a through hole 52 through which the electrode 21 is exposed and a through hole 55 through which the electrode 23 is exposed.

[0027] The insulating base material 81 may be, for example, a resin film. The resin film may be made of insulating resin such as polyimide resin, polyethylene resin, or epoxy resin. The insulating base material 81 may have, for example, flexibility. Here, flexibility refers to the property of being able to bend or flex. The planar shape of the insulating base material 81 may be any shape and any size. The planar shape of the insulating base material 81 is, for example, rectangular. The thickness of the insulating base material 81 may be, for example, about 50 μm to 100 μm.

[0028] For example, an epoxy-, polyimide-, or silicone-based adhesive can be used as the material of the adhesive layer 82. The thickness of the adhesive layer 82 can be, for example, about 20 μm to 40 μm.

[0029] For example, the electrode 21 and the through hole 52 are on the X2 side of the electrode 23 and the through hole 55. A plurality of pairs of the electrode 21 and the through hole 52 may be provided.

[0030] The wiring layer 85 has a wiring 62 connected to the electrode 21 through the through hole 52 and a wiring 64 connected to the electrode 23 through the through hole 55 .

[0031] The wiring 62 includes a via wiring filled in the through hole 52 and a wiring pattern formed on the other surface 81B of the insulating base material 81. The wiring 64 includes a via wiring filled in the through hole 55 and a wiring pattern formed on the other surface 81B of the insulating base material 81.

[0032] The seed layer 83 covers the other surface 81B of the insulating base material 81 and the inner surfaces of the through holes 52 and 55. The seed layer 83 is formed so as to continuously cover the other surface 81B of the insulating base material 81, the inner surfaces of the through holes 52 and 55, and the surfaces of the electrodes 21 and 23 exposed at the bottoms of the through holes 52 and 55. A metal film (sputtered film) formed by a sputtering method can be used as the seed layer 83. For example, a two-layered metal film in which a Ti layer made of titanium (Ti) and a Cu layer made of copper (Cu) are laminated in this order on the other surface 81B of the insulating base material 81 and the inner surfaces of the through holes 52 and 55 can be used as the seed layer 83 formed by the sputtering method. In this case, the thickness of the Ti layer can be, for example, about 10 nm to 300 nm, and the thickness of the Cu layer can be, for example, about 100 nm to 1000 nm. The Ti layer functions as an adhesion layer that improves adhesion between the insulating base material 41 and the electrodes, etc., and the seed layer 83. The Ti layer also functions as a metal barrier layer that suppresses diffusion of copper from the Cu layer, etc., to the insulating base material 81, etc. As materials for the metal film that functions as such an adhesion layer and metal barrier layer, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), chromium (Cr), etc. can be used in addition to Ti.

[0033] For example, copper or a copper alloy can be used as the material of the metal layers 44 and 84. For example, a metal layer formed by electrolytic plating (electrolytic plated metal layer) can be used as the metal layers 44 and 84.

[0034] The semiconductor element 10 and the semiconductor element 20 overlap in the Z1-Z2 direction. The semiconductor element 20 is located on the upper side (Z1 side) of the semiconductor element 10, and a surface 10A of the semiconductor element 10 and a surface 20B of the semiconductor element 20 face each other.

[0035] The lead terminal 110 is bonded to the electrode 12 of the semiconductor element 10 by a conductive adhesive layer 71. The lead terminal 120 is bonded to the wiring 62 of the wiring layer 85 by a conductive adhesive layer 72. The lead terminal 130 is bonded to the wiring 61 of the wiring layer 45 by a conductive adhesive layer 73, and is bonded to the electrode 22 of the semiconductor element 20 by a conductive adhesive layer 74. The lead terminal 140 is bonded to the wiring 63 of the wiring layer 45 by a conductive adhesive layer 75. The lead terminal 150 is bonded to the wiring 64 of the wiring layer 85 by a conductive adhesive layer 76. The conductive adhesive layers 71 to 76 are, for example, solder layers or sintered metal layers. The conductive adhesive layers 71 to 76 may be made of a conductive paste. The semiconductor elements 10 and 20 are fixed to each other via the conductive adhesive layers 73 and 74.

[0036] The lead terminals 110 and 120 extend parallel to each other on the X2 side as viewed from the semiconductor elements 10 and 20. The distance between the lead terminals 110 and 120 is approximately the same as the sum of the thickness of the semiconductor element 10, the thickness of the flexible wiring board 40, the thickness of the semiconductor element 20, and the thickness of the flexible wiring board 80, and is, for example, 1 mm or less. The lead terminal 130 extends on the X1 side as viewed from the semiconductor elements 10 and 20.

[0037] An electrode 12 of the semiconductor element 10 is electrically connected to the lead terminal 110. An electrode 21 of the semiconductor element 20 is electrically connected to the lead terminal 120. An electrode 11 of the semiconductor element 10 and an electrode 22 of the semiconductor element 20 are electrically connected to the lead terminal 130. In addition, the lead terminal 140 is electrically connected to the electrode 13 of the semiconductor element 10, and the lead terminal 150 is electrically connected to the electrode 23 of the semiconductor element 20.

[0038] Here, a description will be given of the circuit configuration of the semiconductor device 1 according to the first embodiment. Fig. 2 is a circuit diagram showing the semiconductor device according to the first embodiment.

[0039] 2, electrode 12 of semiconductor element 10 is electrically connected to the P terminal via lead terminal 110. Electrode 21 of semiconductor element 20 is electrically connected to the N terminal via lead terminal 120. Electrode 11 of semiconductor element 10 and electrode 22 of semiconductor element 20 are electrically connected to the O terminal via lead terminal 130. The P terminal is a positive input terminal, the N terminal is a negative input terminal, and the O terminal is an output terminal. Therefore, currents flow in the opposite directions to each other through lead terminal 110 and lead terminal 120.

[0040] [Method of manufacturing semiconductor device] Next, a method for manufacturing a semiconductor device according to the first embodiment will be described. Figures 3 to 5 are cross-sectional views showing the method for manufacturing a semiconductor device according to the first embodiment. In the following description, a so-called multi-piece manufacturing method will be described in which the parts that will become the semiconductor device 1 are manufactured collectively, and then diced to manufacture a large number of semiconductor devices 1. For ease of explanation, the parts that will ultimately become the components of the semiconductor device 1 will be described with the reference numerals of the final components.

[0041] First, as shown in FIG. 3(a), a large insulating base material 41 having one surface 41A and the other surface 41B is prepared. The large insulating base material 41 has, for example, a plurality of individual regions in which semiconductor devices 1 are formed, arranged in a matrix pattern. Here, the individual regions are regions that will ultimately be cut along predetermined cutting lines to be individualized and become individual semiconductor devices 1. The number of individual regions that the large insulating base material 41 has is not particularly limited. One surface 41A of the insulating base material 41 is provided with an insulating adhesive layer 42 that covers the entire one surface 41A.

[0042] 3(b), through holes 51 and 54 are formed at required locations of the insulating base material 41 and the adhesive layer 42, penetrating the insulating base material 41 and the adhesive layer 42 in the thickness direction. 2 The through hole 51 can be formed by a laser processing method using a laser, a UV-YAG laser, or the like, or a punching method. For example, the through hole 51 is formed on the X1 side of the through hole 54.

[0043] 3(c), the semiconductor element 10 is adhered to the insulating base material 41 by the adhesive layer 42. At this time, the surface 10A of the semiconductor element 10 is opposed to one surface 41A of the insulating base material 41, and the electrodes 11 and 13 are aligned so as to overlap with the through holes 51 and 54, respectively, in a plan view.

[0044] 3(d), a wiring layer 45 including a seed layer 43 and a metal layer 44 is formed on the other surface 41B of the insulating base material 41. The wiring layer 45 can be formed by, for example, a semi-additive method.

[0045] Specifically, the seed layer 43 is formed so as to cover the entire other surface 41B of the insulating base material 41 and the entire inner surfaces of the through holes 51 and 54. The seed layer 43 can be formed by, for example, a sputtering method or an electroless plating method. For example, when the seed layer 43 is formed by a sputtering method, first, titanium is deposited by sputtering to form a Ti layer so as to cover the other surface 41B of the insulating base material 41 and the inner surfaces of the through holes 51 and 54. Then, copper is deposited by sputtering on the Ti layer to form a Cu layer. This makes it possible to form the seed layer 43 of a two-layer structure (Ti layer / Cu layer). When the seed layer 43 is formed by an electroless plating method, for example, the seed layer 43 made of a Cu layer (one-layer structure) can be formed by an electroless copper plating method.

[0046] Next, a plating resist layer (not shown) having openings in the portion where the wiring layer 45 is to be formed, i.e., the portion where the wirings 61 and 63 are to be formed, is formed on the seed layer 43. Next, a metal layer 44 made of copper or the like is formed in the openings of the plating resist layer by electrolytic plating using the seed layer 43 as a plating power supply path. Thereafter, the plating resist layer is removed. Next, the seed layer 43 is removed by wet etching using the metal layer 44 as a mask. In this manner, the wiring layer 45 including the seed layer 43 and the metal layer 44 can be formed. The wiring layer 45 has the wirings 61 and 63. The insulating base material 41, the adhesive layer 42, and the wiring layer 45 constitute a flexible wiring board 40.

[0047] Also, as shown in FIG. 4(a), a large insulating base material 81 having one surface 81A and the other surface 81B is prepared. The large insulating base material 81 has, for example, a plurality of individual regions in which semiconductor devices 1 are formed, arranged in a matrix pattern. Here, the individual regions are regions that are finally cut along predetermined cutting lines to be individualized and become individual semiconductor devices 1. The number of individual regions that the large insulating base material 81 has is not particularly limited. One surface 81A of the insulating base material 81 is provided with an insulating adhesive layer 82 that covers the entire one surface 81A.

[0048] 4(b), through holes 52 and 55 are formed in required locations of the insulating base material 81 and the adhesive layer 82, penetrating the insulating base material 81 and the adhesive layer 82 in the thickness direction. The through holes 51 and 54 can be formed by the same method as the through holes 52 and 55. For example, the through hole 52 is formed on the X2 side of the through hole 55.

[0049] 4(c), the semiconductor element 20 is adhered to the insulating base material 81 by the adhesive layer 82. At this time, the surface 20A of the semiconductor element 20 is opposed to one surface 81A of the insulating base material 81, and the electrodes 21 and 23 are aligned so as to overlap with the through holes 52 and 55, respectively, in a plan view.

[0050] 4(d), a wiring layer 85 including a seed layer 83 and a metal layer 84 is formed on the other surface 81B of the insulating base material 81. The wiring layer 85 can be formed by a method similar to that for the wiring layer 45. The wiring layer 85 has wires 62 and 64. The insulating base material 81, the adhesive layer 82, and the wiring layer 85 form a flexible wiring board 80.

[0051] 5(a), after the wiring layer 45 is formed, a conductive adhesive layer 71 is provided on the surface 10B of the semiconductor element 10, a conductive adhesive layer 73 is provided on the Z1 side surface of the wiring 61 of the wiring layer 45, and a conductive adhesive layer 75 is provided on the Z1 side surface of the wiring 63. The conductive adhesive layers 71, 73, and 75 are in an uncured state.

[0052] 5(b), after the wiring layer 85 is formed, a conductive adhesive layer 74 is provided on the surface 20B of the semiconductor element 20, a conductive adhesive layer 72 is provided on the Z1 side surface of the wiring 62 of the wiring layer 85, and a conductive adhesive layer 76 is provided on the Z1 side surface of the wiring 64. The conductive adhesive layers 72, 74, and 76 are in an uncured state.

[0053] 5(c), the lead terminal 110 is joined to the electrode 12 by a conductive adhesive layer 71, the lead terminal 130 is joined to the wiring 61 by a conductive adhesive layer 73 and is also joined to the electrode 22 by a conductive adhesive layer 74, and the lead terminal 140 is joined to the wiring 63 by a conductive adhesive layer 75. Furthermore, the lead terminal 120 is joined to the wiring 62 by a conductive adhesive layer 72, and the lead terminal 150 is joined to the wiring 64 by a conductive adhesive layer 76. During this joining, the conductive adhesive layers 71 to 76 are cured.

[0054] In this manner, the semiconductor device 1 according to the first embodiment can be manufactured.

[0055] In the semiconductor device 1 according to the first embodiment, a current flows from the P terminal to the N terminal. Therefore, in the lead terminal 110, a current flows from the X2 side to the X1 side, and in the lead terminal 120, a current flows from the X1 side to the X2 side. In this embodiment, the distance between the lead terminals 110 and 120 is approximately the same as the sum of the thickness of the semiconductor element 10, the thickness of the flexible wiring board 40, the thickness of the semiconductor element 20, and the thickness of the flexible wiring board 80. Therefore, the inductance can be significantly reduced.

[0056] Moreover, the wiring layer 45 can be formed finely and with high accuracy on the other surface 41B of the insulating base material 41 by a semi-additive method, and the wiring layer 85 can be formed finely and with high accuracy on the other surface 81B of the insulating base material 81 by a semi-additive method. The wiring layer 45 and the wiring layer 85 can also be formed by a subtractive method. Furthermore, by adhering the semiconductor element 10 to one surface 41A of the insulating base material 41 by the adhesive layer 42, the position of the semiconductor element 10 can be fixed with respect to the insulating base material 41 and the wiring layer 45, and by adhering the semiconductor element 20 to one surface 81A of the insulating base material 81 by the adhesive layer 82, the position of the semiconductor element 20 can be fixed with respect to the insulating base material 81 and the wiring layer 85. Therefore, according to this embodiment, excellent positional accuracy and connection reliability can be obtained.

[0057] As a reference example, assume that a semiconductor device (power module) is manufactured in which a semiconductor element is fixed to a metal foil (copper foil, etc.) provided on the surface of an insulating substrate (ceramic substrate, etc.). When manufacturing such a semiconductor device, solder reflow is performed to fix the semiconductor element, and the semiconductor element may be misaligned to some extent during this reflow. For this reason, a relatively large margin is required for the placement of the semiconductor element at the design stage.

[0058] On the other hand, in this embodiment, the semiconductor element 10 is bonded to the insulating base material 41 in which the through holes 51 and 54 are formed, and the wiring layer 45 is formed by the semi-additive method. Also, the semiconductor element 20 is bonded to the insulating base material 81 in which the through holes 52 and 54 are formed, and the wiring layer 85 is formed by the semi-additive method. Therefore, excellent positional accuracy and connection reliability can be obtained, and a large margin as in the reference example is not required.

[0059] Second embodiment Next, a second embodiment will be described with reference to Fig. 6, which is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0060] As shown in FIG. 6, the semiconductor device 2 according to the second embodiment has a wiring board 210 instead of the lead terminal 110, a wiring board 220 instead of the lead terminals 120 and 150, and a wiring board 230 instead of the lead terminals 130 and 140.

[0061] The wiring board 210 has an insulating layer 211 and a wiring layer 212. The wiring layer 212 is provided on the upper surface (on the surface on the Z1 side) of the insulating layer 211. The material of the insulating layer 211 may be an inorganic material, an organic material, or a composite material. The material of the wiring layer 212 is, for example, copper or a copper alloy. The wiring layer 212 is bonded to the electrode 12 of the semiconductor element 10 by a conductive adhesive layer 71.

[0062] The wiring board 220 has an insulating layer 221, a wiring layer 222, a wiring layer 223, a wiring layer 224, a via conductor 225, and a wiring layer 226. The wiring layers 222, 223, and 226 are provided on the lower surface (on the surface on the Z2 side) of the insulating layer 221, and the wiring layer 224 is provided on the upper surface (on the surface on the Z1 side) of the insulating layer 221. The via conductor 225 penetrates the insulating layer 221 and is connected to the wiring layers 222 and 224. The material of the insulating layer 221 may be an inorganic material, an organic material, or a composite material. The material of the wiring layers 222, 223, 224, and 226 and the material of the via conductor 225 are, for example, copper or a copper alloy. The wiring layer 222 is bonded to the wiring 62 of the wiring layer 85 by a conductive adhesive layer 72, and the wiring layer 223 is bonded to the wiring 64 of the wiring layer 85 by a conductive adhesive layer .

[0063] The wiring board 230 has an insulating layer 231, a wiring layer 232, a wiring layer 233, a wiring layer 234, and a via conductor 235. The wiring layer 232 is provided on the upper surface (on the surface on the Z1 side) of the insulating layer 231, and the wiring layers 233 and 234 are provided on the lower surface (on the surface on the Z2 side) of the insulating layer 231. The via conductor 235 penetrates the insulating layer 231 and is connected to the wiring layers 232 and 233. The material of the insulating layer 231 may be an inorganic material, an organic material, or a composite material. The material of the wiring layers 232, 233, and 234 and the material of the via conductor 235 are, for example, copper or a copper alloy. The wiring layer 233 is bonded to the wiring 61 of the wiring layer 45 by a conductive adhesive layer 73, and the wiring layer 232 is bonded to the electrode 22 of the semiconductor element 20 by a conductive adhesive layer 74. Moreover, the wiring layer 234 is joined to the wiring 63 of the wiring layer 45 by a conductive adhesive layer 75 .

[0064] Wiring board 210 includes a wiring layer (e.g., wiring layer 212) extending to the X2 side as viewed from semiconductor elements 10 and 20, and wiring board 220 includes a wiring layer (e.g., wiring layer 224) extending to the X2 side as viewed from semiconductor elements 10 and 20. Furthermore, wiring board 230 includes a wiring layer (e.g., wiring layer 232) extending to the X1 side as viewed from semiconductor elements 10 and 20.

[0065] The other configuration is similar to that of the first embodiment.

[0066] When manufacturing the semiconductor device 2 according to the second embodiment, the wiring boards 210, 220, and 230 are prepared in advance. Then, the wiring board 210 is bonded to the semiconductor element 10 in place of the lead terminals 110, the wiring board 230 is bonded to the semiconductor element 20 and the wiring layer 45 in place of the lead terminals 130 and 140, and the wiring board 230 is bonded to the wiring layer 85 in place of the lead terminals 120 and 150. In this manner, the semiconductor device 2 can be manufactured.

[0067] In the semiconductor device 2 according to the second embodiment, a current also flows from the P terminal to the N terminal. Therefore, in the wiring board 210, a current flows from the X2 side to the X1 side, and in the wiring board 220, a current flows from the X1 side to the X2 side. In addition, in this embodiment, the distance between the wiring board 210 and the wiring board 220 is approximately the same as the sum of the thickness of the semiconductor element 10, the thickness of the flexible wiring board 40, the thickness of the semiconductor element 20, and the thickness of the flexible wiring board 80. Therefore, similar to the first embodiment, the inductance can be significantly reduced.

[0068] Moreover, similarly to the first embodiment, the semiconductor element 10 is bonded to the insulating base material 41 in which the through holes 51 and 54 are formed, and the wiring layer 45 is formed by the semi-additive method. Moreover, the semiconductor element 20 is bonded to the insulating base material 81 in which the through holes 52 and 54 are formed, and the wiring layer 85 is formed by the semi-additive method. Therefore, excellent positional accuracy and connection reliability can be obtained.

[0069] Third embodiment Next, a third embodiment will be described with reference to Fig. 7, which is a cross-sectional view showing a semiconductor device according to the third embodiment.

[0070] 7, the semiconductor device 3 according to the third embodiment has a wiring board 230 instead of the lead terminals 130 and 140. The wiring board 230 has the same configuration as in the second embodiment.

[0071] The other configuration is similar to that of the first embodiment.

[0072] The third embodiment can also provide the same effects as the first and second embodiments.

[0073] (Fourth embodiment) Next, a fourth embodiment will be described with reference to Fig. 8, which is a cross-sectional view showing a semiconductor device according to the fourth embodiment.

[0074] 8, the semiconductor device 4 according to the fourth embodiment has lead terminals 410, 420, 431, 432, 440, and 450 instead of the lead terminals 110, 120, 130, 140, and 150. The lead terminals 410, 420, 431, 432, 440, and 450 are formed of, for example, a lead frame. Also, the semiconductor element 10 is on the Z1 side of the semiconductor element 20.

[0075] The lead terminal 410 is joined to the electrode 12 of the semiconductor element 10 by a conductive adhesive layer 71. The lead terminal 420 is joined to the wiring 62 of the wiring layer 85 by a conductive adhesive layer 72. The lead terminal 431 is joined to the wiring 61 of the wiring layer 45 by a conductive adhesive layer 73. The lead terminal 432 is joined to the electrode 22 of the semiconductor element 20 by a conductive adhesive layer 74. The lead terminal 440 is joined to the wiring 63 of the wiring layer 45 by a conductive adhesive layer 75. The lead terminal 450 is joined to the wiring 64 of the wiring layer 85 by a conductive adhesive layer 76.

[0076] The lead terminal 410 is joined to the lead terminals 420 and 450 by an insulating adhesive layer 470. The lead terminals 410, 420, and 450 are fixed to each other by the insulating adhesive layer 470. The insulating adhesive layer 470 may be made of, for example, an epoxy-based, polyimide-based, or silicone-based adhesive. The semiconductor elements 10 and 20 are fixed to each other by the insulating adhesive layer 470. The semiconductor elements 10 and 20 are fixed to each other by the conductive adhesive layers 73 and 74. The insulating adhesive layer 470 has a thickness of about 50 to 1000 μm.

[0077] The lead terminals 410 and 420 extend parallel to each other on the X2 side as viewed from the semiconductor elements 10 and 20. The distance between the lead terminals 410 and 420 is approximately the same as the thickness of the insulating adhesive layer 470. In addition, the lead terminals 431 and 432 extend on the X1 side as viewed from the semiconductor elements 10 and 20.

[0078] An electrode 12 of the semiconductor element 10 is electrically connected to the lead terminal 410. An electrode 21 of the semiconductor element 20 is electrically connected to the lead terminal 420. An electrode 11 of the semiconductor element 10 is electrically connected to the lead terminal 431. An electrode 22 of the semiconductor element 20 is electrically connected to the lead terminal 432. In addition, the lead terminal 440 is electrically connected to the electrode 13 of the semiconductor element 10, and the lead terminal 450 is electrically connected to the electrode 23 of the semiconductor element 20.

[0079] The electrode 12 of the semiconductor element 10 is electrically connected to the P terminal via the lead terminal 410. The electrode 21 of the semiconductor element 20 is electrically connected to the N terminal via the lead terminal 420. The electrode 11 of the semiconductor element 10 is electrically connected to the O terminal via the lead terminal 431, and the electrode 22 of the semiconductor element 20 is electrically connected to the O terminal via the lead terminal 432. That is, the wiring 61 of the wiring layer 45 and the electrode 22 of the semiconductor element 20 are electrically connected to each other. As described above, the P terminal is a positive input terminal, the N terminal is a negative input terminal, and the O terminal is an output terminal. Therefore, currents flow in the opposite directions to each other through the lead terminals 410 and 420.

[0080] The other configuration is similar to that of the first embodiment.

[0081] When manufacturing the semiconductor device 4 according to the fourth embodiment, the lead terminal 410 is bonded to the electrode 12 by the conductive adhesive layer 71, the lead terminal 431 is bonded to the wiring 61 by the conductive adhesive layer 73, and the lead terminal 440 is bonded to the wiring 63 by the conductive adhesive layer 75. Also, the lead terminal 420 is bonded to the wiring 62 by the conductive adhesive layer 72, the lead terminal 450 is bonded to the wiring 64 by the conductive adhesive layer 76, and the lead terminal 432 is bonded to the electrode 22 by the conductive adhesive layer 74. Thereafter, the lead terminal 410 and the lead terminals 420 and 450 are bonded to each other by the insulating adhesive layer 470. In this manner, the semiconductor device 4 can be manufactured.

[0082] The fourth embodiment can provide the same effects as the first embodiment. In addition, the distance between the lead terminals 410 and 420 can be made smaller, so that the inductance can be further reduced.

[0083] Fifth embodiment Next, a fifth embodiment will be described with reference to Fig. 9, which is a cross-sectional view showing a semiconductor device according to the fifth embodiment.

[0084] As shown in FIG. 9, the semiconductor device 5 of the fifth embodiment has a wiring board 510 instead of the lead terminals 410, 420, 450 and the insulating adhesive layer 470, has a wiring board 520 instead of the lead terminals 431 and 440, and has a wiring board 530 instead of the lead terminal 432.

[0085] The wiring board 510 has an insulating layer 511, a wiring layer 512, a wiring layer 513, and a wiring layer 514. The wiring layer 512 is provided on the Z1 side surface of the insulating layer 511, and the wiring layers 513 and 514 are provided on the Z2 side surface of the insulating layer 511. The material of the insulating layer 511 may be an inorganic material, an organic material, or a composite material. The wiring layers 512, 513, and 514 are fixed to each other by the insulating layer 511. The thickness of the insulating layer 511 is about 50 to 2000 μm. The material of the wiring layers 512, 513, and 514 is, for example, copper or a copper alloy. The wiring layer 512 is bonded to the electrode 12 of the semiconductor element 10 by a conductive adhesive layer 71. The wiring layer 513 is bonded to the wiring 62 of the wiring layer 85 by a conductive adhesive layer 72. The wiring layer 514 is bonded to the wiring 64 of the wiring layer 85 by a conductive adhesive layer 76 .

[0086] The wiring board 520 has an insulating layer 521, a wiring layer 522, a wiring layer 523, a wiring layer 524, and a via conductor 525. The wiring layers 522 and 523 are provided on the Z2 side surface of the insulating layer 521, and the wiring layer 524 is provided on the Z1 side surface of the insulating layer 521. The via conductor 525 penetrates the insulating layer 521 and is connected to the wiring layers 522 and 524. The material of the insulating layer 521 may be an inorganic material, an organic material, or a composite material. The material of the wiring layers 522, 523, and 524 and the material of the via conductor 525 are, for example, copper or a copper alloy. The wiring layer 522 is bonded to the wiring 61 of the wiring layer 45 by a conductive adhesive layer 73, and the wiring layer 523 is bonded to the wiring 63 of the wiring layer 45 by a conductive adhesive layer 75.

[0087] The wiring board 530 has an insulating layer 531 and a wiring layer 532. The wiring layer 532 is provided on the Z1 side surface of the insulating layer 531. The material of the insulating layer 531 may be an inorganic material, an organic material, or a composite material. The material of the wiring layer 532 is, for example, copper or a copper alloy. The wiring layer 532 is bonded to the electrode 22 of the semiconductor element 20 by a conductive adhesive layer 74.

[0088] The wiring board 510 includes wiring layers (e.g., wiring layers 512 and 513) extending to the X2 side as viewed from the semiconductor elements 10 and 20. The wiring board 520 includes wiring layers (e.g., wiring layers 522 and 524) extending to the X1 side as viewed from the semiconductor elements 10 and 20, and the wiring board 530 includes a wiring layer (e.g., wiring layer 532) extending to the X1 side as viewed from the semiconductor elements 10 and 20.

[0089] In the fifth embodiment, the electrode 12 of the semiconductor element 10 is electrically connected to the P terminal via the wiring layer 512. The electrode 21 of the semiconductor element 20 is electrically connected to the N terminal via the wiring layer 513. Therefore, currents flow through the wiring layers 512 and 513 in the opposite directions to each other.

[0090] The other configuration is similar to that of the fourth embodiment.

[0091] The fifth embodiment can also provide the same effects as the first embodiment. In addition, since the distance between the wiring layer 512 and the wiring layer 513 is approximately the same as the thickness of the insulating layer 511, the inductance can be further reduced, similarly to the fourth embodiment.

[0092] Sixth embodiment Next, a sixth embodiment will be described with reference to Fig. 10, which is a cross-sectional view showing a semiconductor device according to the sixth embodiment.

[0093] 10, the semiconductor device 6 according to the sixth embodiment has a wiring board 510 instead of the lead terminals 410, 420, 450 and the insulating adhesive layer 470. The wiring board 510 has the same configuration as in the fifth embodiment.

[0094] The other configuration is similar to that of the fourth embodiment.

[0095] The sixth embodiment can also provide the same effects as the fourth and fifth embodiments.

[0096] The structure of the wiring board is not limited to the above, and may be a ceramic substrate or a build-up substrate, and is not limited to a single-layer structure. For example, it may be embodied as a laminated structure in which one or more wiring layers and multiple insulating layers are laminated. The wiring layer may be provided on both the front and back surfaces.

[0097] The lead terminals 110, 120, 130, 140, 150, 410, 420, 431, 432, 440, and 450 and the wiring boards 210, 220, 230, 510, 520, and 530 are an example of a wiring member.

[0098] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0099] 1, 2, 3, 4, 5, 6 Semiconductor device 10, 20 Semiconductor element 10A, 10B, 20A, 20B side 11, 21 electrode 12, 22 electrodes 13, 23 electrodes 40, 80 Flexible wiring board 41, 81 Insulating substrate 42, 82 Adhesive layer 45, 85 wiring layer 51, 52, 54, 55 Through holes 61, 62, 63, 64 Wiring 71, 72, 73, 74, 75, 76 Conductive adhesive layer 110, 120, 130, 140, 150, 410, 420, 431, 432, 440, 450 Lead terminal 210, 220, 230, 510, 520, 530 Wiring board 211, 221, 231, 511, 521, 531 Insulating layer 212, 222, 223, 224, 226, 232, 233, 234, 512, 513, 514, 522, 523, 524, 532 wiring layer 470 Insulating adhesive layer

Claims

1. a first semiconductor element having a first surface and a second surface opposite to the first surface, a first electrode being provided on the first surface and a second electrode being provided on the second surface; a second semiconductor element having a third surface and a fourth surface opposite to the third surface, the second semiconductor element having a third electrode provided on the third surface and a fourth electrode provided on the fourth surface; a first insulating base material having a fifth surface bonded to the first surface side of the first semiconductor element and a sixth surface opposite to the fifth surface; a first wiring that penetrates the first insulating base material, is electrically connected to the first electrode, and is laminated on the sixth surface of the first insulating base material; a second insulating base material having a seventh surface bonded to the third surface side of the second semiconductor element and an eighth surface opposite to the seventh surface; a second wiring that penetrates the second insulating base material, is electrically connected to the third electrode, and is laminated on the eighth surface of the second insulating base material; a first wiring member electrically connected to the second electrode of the first semiconductor element; a second wiring member having a ninth surface facing the sixth surface of the first insulating base material and a tenth surface opposite to the ninth surface, the second wiring member being electrically connected to the first wiring on the ninth surface and electrically connected to the fourth electrode of the second semiconductor element on the tenth surface; a third wiring member electrically connected to the second wiring; having A semiconductor device in which currents flow in opposite directions through the first wiring member and the third wiring member.

2. a first conductive adhesive layer that bonds the first wiring member and the second electrode to each other; a second conductive adhesive layer that bonds the third wiring member and the second wiring to each other; The semiconductor device according to claim 1 ,

3. the first wiring member has a first lead terminal, 3. The semiconductor device according to claim 1, wherein the third wiring member has a second lead terminal.

4. the first wiring member has a first wiring substrate, The semiconductor device according to claim 1 , wherein the third wiring member includes a second wiring substrate.

5. a third conductive adhesive layer that bonds the second wiring member and the first wiring to each other; a fourth conductive adhesive layer that bonds the second wiring member and the fourth electrode to each other; The semiconductor device according to claim 1 , further comprising:

6. The semiconductor device according to claim 1 , wherein the second wiring member has a third lead terminal.

7. The semiconductor device according to claim 1 , wherein the second wiring member includes a third wiring substrate.

8. a first semiconductor element having a first surface and a second surface opposite to the first surface, a first electrode being provided on the first surface, and a second electrode being provided on the second surface; a second semiconductor element having a third surface and a fourth surface opposite to the third surface, the second semiconductor element having a third electrode provided on the third surface and a fourth electrode provided on the fourth surface; a first insulating base material having a fifth surface bonded to the first surface side of the first semiconductor element and a sixth surface opposite to the fifth surface; a first wiring that penetrates the first insulating base material, is electrically connected to the first electrode, and is laminated on the sixth surface of the first insulating base material; a second insulating base material having a seventh surface bonded to the third surface side of the second semiconductor element and an eighth surface opposite to the seventh surface; a second wiring that penetrates the second insulating base material, is electrically connected to the third electrode, and is laminated on the eighth surface of the second insulating base material; a fourth wiring member electrically connected to the second electrode of the first semiconductor element; a fifth wiring member electrically connected to the second wiring; an insulating fixing member that fixes the fourth wiring member and the fifth wiring member to each other; having A semiconductor device in which currents flow in opposite directions through the fourth wiring member and the fifth wiring member.

9. a fifth conductive adhesive layer that bonds the fourth wiring member and the second electrode to each other; a sixth conductive adhesive layer that bonds the fifth wiring member and the second wiring to each other; The semiconductor device according to claim 8 , further comprising:

10. the fourth wiring member has a fourth lead terminal, 10. The semiconductor device according to claim 8, wherein the fifth wiring member has a fifth lead terminal.

11. The semiconductor device according to claim 10 , wherein the insulating fixing member has an insulating adhesive layer that bonds the fourth lead terminal and the fifth lead terminal to each other.

12. the insulating fixing member has an insulating layer having an eleventh surface facing the second surface of the first semiconductor element and a twelfth surface opposite to the eleventh surface, the fourth wiring member has a first conductive layer provided on the eleventh surface of the insulating layer, The semiconductor device according to claim 8 , wherein the fifth wiring member includes a second conductive layer provided on the twelfth surface of the insulating layer.

13. a sixth wiring member electrically connected to the first wiring; a seventh wiring member electrically connected to the fourth electrode; The semiconductor device according to claim 8 , further comprising:

14. a seventh conductive adhesive layer that bonds the sixth wiring member and the first wiring to each other; an eighth conductive adhesive layer that bonds the seventh wiring member and the fourth electrode to each other; The semiconductor device according to claim 13 , comprising:

15. the sixth wiring member has a sixth lead terminal, 15. The semiconductor device according to claim 13, wherein the seventh wiring member has a seventh lead terminal.

16. the sixth wiring member has a fourth wiring board, The semiconductor device according to claim 13 , wherein the seventh wiring member comprises a fifth wiring board.

17. the first semiconductor element has a fifth electrode provided on the first surface, the second semiconductor element has a sixth electrode provided on the third surface, a third wiring that penetrates the first insulating base material, is electrically connected to the fifth electrode, and is laminated on the sixth surface of the first insulating base material; a fourth wiring that penetrates the second insulating base material, is electrically connected to the sixth electrode, and is laminated on the sixth surface of the second insulating base material; The semiconductor device according to claim 1 , further comprising:

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